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GET /api/1.2/patches/831211/?format=api
{ "id": 831211, "url": "http://patchwork.ozlabs.org/api/1.2/patches/831211/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/patch/1509101470-7881-11-git-send-email-Dave.Martin@arm.com/", "project": { "id": 41, "url": "http://patchwork.ozlabs.org/api/1.2/projects/41/?format=api", "name": "GNU C Library", "link_name": "glibc", "list_id": "libc-alpha.sourceware.org", "list_email": "libc-alpha@sourceware.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1509101470-7881-11-git-send-email-Dave.Martin@arm.com>", "list_archive_url": null, "date": "2017-10-27T10:50:52", "name": "[v4,10/28] arm64/sve: Low-level CPU setup", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "953ae579331b9687ff3e9b111209196569ac8a7e", "submitter": { "id": 26612, "url": "http://patchwork.ozlabs.org/api/1.2/people/26612/?format=api", "name": "Dave Martin", "email": "Dave.Martin@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/glibc/patch/1509101470-7881-11-git-send-email-Dave.Martin@arm.com/mbox/", "series": [ { "id": 10555, "url": "http://patchwork.ozlabs.org/api/1.2/series/10555/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/list/?series=10555", "date": "2017-10-27T10:50:42", "name": "ARM Scalable Vector Extension (SVE)", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/10555/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/831211/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/831211/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<libc-alpha-return-86452-incoming=patchwork.ozlabs.org@sourceware.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list libc-alpha@sourceware.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-86452-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"yULFmasI\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yNghq0j5kz9sNx\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 27 Oct 2017 21:53:30 +1100 (AEDT)", "(qmail 117557 invoked by alias); 27 Oct 2017 10:51:41 -0000", "(qmail 117468 invoked by uid 89); 27 Oct 2017 10:51:40 -0000" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\tq=dns; s=default; b=nLwj2P3+kSzmMdjuOr1UvtDeKUH/XigRKpxK9yMNH1c\n\tG5Z2Qe5MA0dMOwLM44N2BP+VY5FrNXCbM68xOEE86EiOcGKyqhrB1jN+VnMLlZga\n\t8kF8Vfy7Enzm89DFycj01+PrN9KPbzq0zp6tzA//C02zuJBz7HxoovhA7rTKj/+c\n\t=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\ts=default; bh=SsRKUE/dxO7zL963itPcE3JPHcw=; b=yULFmasIqlfvV5FGE\n\tBxwFmNEhY3ISD+pVUfw8UAFwu/y+BRtaPaLyqcz4jtU4i5izGxHfj1JPUxNF/f2V\n\t3Ie8PvGm6XufSrHw5kXorFdfRqw0ddlR4iKyC4um/J3wU799+aW1HJ+zPwOOICqQ\n\taM6b+nqlpji/4k64QCGfVUBphI=", "Mailing-List": "contact libc-alpha-help@sourceware.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<libc-alpha.sourceware.org>", "List-Unsubscribe": "<mailto:libc-alpha-unsubscribe-incoming=patchwork.ozlabs.org@sourceware.org>", "List-Subscribe": "<mailto:libc-alpha-subscribe@sourceware.org>", "List-Archive": "<http://sourceware.org/ml/libc-alpha/>", "List-Post": "<mailto:libc-alpha@sourceware.org>", "List-Help": "<mailto:libc-alpha-help@sourceware.org>,\n\t<http://sourceware.org/ml/#faqs>", "Sender": "libc-alpha-owner@sourceware.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=", "X-HELO": "foss.arm.com", "From": "Dave Martin <Dave.Martin@arm.com>", "To": "linux-arm-kernel@lists.infradead.org", "Cc": "Catalin Marinas <catalin.marinas@arm.com>, Will Deacon\n\t<will.deacon@arm.com>, \tArd Biesheuvel <ard.biesheuvel@linaro.org>,\n\t=?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= <alex.bennee@linaro.org>,\n\tSzabolcs Nagy <szabolcs.nagy@arm.com>, Okamoto Takayuki\n\t<tokamoto@jp.fujitsu.com>, \tkvmarm@lists.cs.columbia.edu,\n\tlibc-alpha@sourceware.org, \tlinux-arch@vger.kernel.org", "Subject": "[PATCH v4 10/28] arm64/sve: Low-level CPU setup", "Date": "Fri, 27 Oct 2017 11:50:52 +0100", "Message-Id": "<1509101470-7881-11-git-send-email-Dave.Martin@arm.com>", "In-Reply-To": "<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>", "References": "<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit" }, "content": "To enable the kernel to use SVE, SVE traps from EL1 to EL2 must be\ndisabled. To take maximum advantage of the hardware, the full\navailable vector length also needs to be enabled for EL1 by\nprogramming ZCR_EL2.LEN. (The kernel will program ZCR_EL1.LEN as\nrequired, but this cannot override the limit set by ZCR_EL2.)\n\nThis patch makes the appropriate changes to the EL2 early setup\ncode.\n\nSigned-off-by: Dave Martin <Dave.Martin@arm.com>\nReviewed-by: Catalin Marinas <catalin.marinas@arm.com>\nCc: Alex Bennée <alex.bennee@linaro.org>\n\n---\n\n**Dropped at v3** Reviewed-by: Alex Bennée <alex.bennee@linaro.org>\n(Due to significant changes to the logic.)\n---\n arch/arm64/kernel/head.S | 13 ++++++++++++-\n 1 file changed, 12 insertions(+), 1 deletion(-)", "diff": "diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S\nindex cfa90a4..67e86a0 100644\n--- a/arch/arm64/kernel/head.S\n+++ b/arch/arm64/kernel/head.S\n@@ -524,8 +524,19 @@ CPU_LE(\tmovk\tx0, #0x30d0, lsl #16\t)\t// Clear EE and E0E on LE systems\n \tmov\tx0, #0x33ff\n \tmsr\tcptr_el2, x0\t\t\t// Disable copro. traps to EL2\n \n+\t/* SVE register access */\n+\tmrs\tx1, id_aa64pfr0_el1\n+\tubfx\tx1, x1, #ID_AA64PFR0_SVE_SHIFT, #4\n+\tcbz\tx1, 7f\n+\n+\tbic\tx0, x0, #CPTR_EL2_TZ\t\t// Also disable SVE traps\n+\tmsr\tcptr_el2, x0\t\t\t// Disable copro. traps to EL2\n+\tisb\n+\tmov\tx1, #ZCR_ELx_LEN_MASK\t\t// SVE: Enable full vector\n+\tmsr_s\tSYS_ZCR_EL2, x1\t\t\t// length for EL1.\n+\n \t/* Hypervisor stub */\n-\tadr_l\tx0, __hyp_stub_vectors\n+7:\tadr_l\tx0, __hyp_stub_vectors\n \tmsr\tvbar_el2, x0\n \n \t/* spsr */\n", "prefixes": [ "v4", "10/28" ] }