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GET /api/1.2/patches/831062/?format=api
{ "id": 831062, "url": "http://patchwork.ozlabs.org/api/1.2/patches/831062/?format=api", "web_url": "http://patchwork.ozlabs.org/project/kvm-ppc/patch/1509079594-28977-2-git-send-email-paulus@ozlabs.org/", "project": { "id": 23, "url": "http://patchwork.ozlabs.org/api/1.2/projects/23/?format=api", "name": "KVM PowerPC development", "link_name": "kvm-ppc", "list_id": "kvm-ppc.vger.kernel.org", "list_email": "kvm-ppc@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1509079594-28977-2-git-send-email-paulus@ozlabs.org>", "list_archive_url": null, "date": "2017-10-27T04:46:29", "name": "[v2,1/6] KVM: PPC: Book3S HV: Don't rely on host's page size information", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "f32990ba673e6e18baf4e4ad3e30d02a69ad0929", "submitter": { "id": 67079, "url": "http://patchwork.ozlabs.org/api/1.2/people/67079/?format=api", "name": "Paul Mackerras", "email": "paulus@ozlabs.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/kvm-ppc/patch/1509079594-28977-2-git-send-email-paulus@ozlabs.org/mbox/", "series": [ { "id": 10490, "url": "http://patchwork.ozlabs.org/api/1.2/series/10490/?format=api", "web_url": "http://patchwork.ozlabs.org/project/kvm-ppc/list/?series=10490", "date": "2017-10-27T04:46:28", "name": "KVM: PPC: Book3S HV: Run HPT guests on radix hosts", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/10490/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/831062/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/831062/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<kvm-ppc-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=kvm-ppc-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"IFjzours\";\n\tdkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yNWYl3JQZz9t3F\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 27 Oct 2017 15:46:51 +1100 (AEDT)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751894AbdJ0Eqs (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 27 Oct 2017 00:46:48 -0400", "from ozlabs.org ([103.22.144.67]:49713 \"EHLO ozlabs.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751483AbdJ0Eqp (ORCPT <rfc822;kvm-ppc@vger.kernel.org>);\n\tFri, 27 Oct 2017 00:46:45 -0400", "from authenticated.ozlabs.org (localhost [127.0.0.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPSA id 3yNWYb64DJz9t30;\n\tFri, 27 Oct 2017 15:46:43 +1100 (AEDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; \n\tt=1509079604; bh=mE1k4CKEeiOTfs9p2iPBHpdnldwqwtKLBXHh3RS7VhA=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=IFjzoursN/nKzAjK3XTPzblhAvMwKig+ELIMo/suuEFR0urJSED1Q53XEMDxviNzH\n\tuHez+QqRVDkHNVFF7TwCaKlheCuzgThFtPcH4GRQNEW1KOPv6d2m8kfHto2ICIe/Pb\n\tlNxLTF4Qqylepz77XKNGa82kw5rn2m7DUVOgKlwaElWJFXaj0JvKkxAMvu+pb4lLgt\n\tbf1zxh2Mqbtw9KanVGv9MXtNGHK9N88RXtBnOYMcdnYuTuR6eQkqZRgPKueu4+bS8V\n\tz2HP1Zph+UrYJeuzP0ZHrjE9WBFhGSJu4hA0Ygpkx2NqOcX03dPLL1rm4lnRqnOVZS\n\tHR8GkbioQk/SQ==", "From": "Paul Mackerras <paulus@ozlabs.org>", "To": "kvm@vger.kernel.org, kvm-ppc@vger.kernel.org", "Cc": "david@gibson.dropbear.id.au", "Subject": "[PATCH v2 1/6] KVM: PPC: Book3S HV: Don't rely on host's page size\n\tinformation", "Date": "Fri, 27 Oct 2017 15:46:29 +1100", "Message-Id": "<1509079594-28977-2-git-send-email-paulus@ozlabs.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1509079594-28977-1-git-send-email-paulus@ozlabs.org>", "References": "<1509079594-28977-1-git-send-email-paulus@ozlabs.org>", "Sender": "kvm-ppc-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<kvm-ppc.vger.kernel.org>", "X-Mailing-List": "kvm-ppc@vger.kernel.org" }, "content": "This removes the dependence of KVM on the mmu_psize_defs array (which\nstores information about hardware support for various page sizes) and\nthe things derived from it, chiefly hpte_page_sizes[], hpte_page_size(),\nhpte_actual_page_size() and get_sllp_encoding(). We also no longer\nrely on the mmu_slb_size variable or the MMU_FTR_1T_SEGMENTS feature\nbit.\n\nThe reason for doing this is so we can support a HPT guest on a radix\nhost. In a radix host, the mmu_psize_defs array contains information\nabout page sizes supported by the MMU in radix mode rather than the\npage sizes supported by the MMU in HPT mode. Similarly, mmu_slb_size\nand the MMU_FTR_1T_SEGMENTS bit are not set.\n\nInstead we hard-code knowledge of the behaviour of the HPT MMU in the\nPOWER7, POWER8 and POWER9 processors (which are the only processors\nsupported by HV KVM) - specifically the encoding of the LP fields in\nthe HPT and SLB entries, and the fact that they have 32 SLB entries\nand support 1TB segments.\n\nSigned-off-by: Paul Mackerras <paulus@ozlabs.org>\n---\n arch/powerpc/include/asm/kvm_book3s_64.h | 116 +++++++++++++++++++++++++------\n arch/powerpc/kvm/book3s_64_mmu_hv.c | 13 ++--\n arch/powerpc/kvm/book3s_hv.c | 39 +++++------\n arch/powerpc/kvm/book3s_hv_rm_mmu.c | 11 +--\n 4 files changed, 126 insertions(+), 53 deletions(-)", "diff": "diff --git a/arch/powerpc/include/asm/kvm_book3s_64.h b/arch/powerpc/include/asm/kvm_book3s_64.h\nindex d55c7f8..b21936c 100644\n--- a/arch/powerpc/include/asm/kvm_book3s_64.h\n+++ b/arch/powerpc/include/asm/kvm_book3s_64.h\n@@ -107,18 +107,96 @@ static inline void __unlock_hpte(__be64 *hpte, unsigned long hpte_v)\n \thpte[0] = cpu_to_be64(hpte_v);\n }\n \n+/*\n+ * These functions encode knowledge of the POWER7/8/9 hardware\n+ * interpretations of the HPTE LP (large page size) field.\n+ */\n+static inline int kvmppc_hpte_page_shifts(unsigned long h, unsigned long l)\n+{\n+\tunsigned int lphi;\n+\n+\tif (!(h & HPTE_V_LARGE))\n+\t\treturn 12;\t/* 4kB */\n+\tlphi = (l >> 16) & 0xf;\n+\tswitch ((l >> 12) & 0xf) {\n+\tcase 0:\n+\t\treturn !lphi ? 24 : -1;\t\t/* 16MB */\n+\t\tbreak;\n+\tcase 1:\n+\t\treturn 16;\t\t\t/* 64kB */\n+\t\tbreak;\n+\tcase 3:\n+\t\treturn !lphi ? 34 : -1;\t\t/* 16GB */\n+\t\tbreak;\n+\tcase 7:\n+\t\treturn (16 << 8) + 12;\t\t/* 64kB in 4kB */\n+\t\tbreak;\n+\tcase 8:\n+\t\tif (!lphi)\n+\t\t\treturn (24 << 8) + 16;\t/* 16MB in 64kkB */\n+\t\tif (lphi == 3)\n+\t\t\treturn (24 << 8) + 12;\t/* 16MB in 4kB */\n+\t\tbreak;\n+\t}\n+\treturn -1;\n+}\n+\n+static inline int kvmppc_hpte_base_page_shift(unsigned long h, unsigned long l)\n+{\n+\treturn kvmppc_hpte_page_shifts(h, l) & 0xff;\n+}\n+\n+static inline int kvmppc_hpte_actual_page_shift(unsigned long h, unsigned long l)\n+{\n+\tint tmp = kvmppc_hpte_page_shifts(h, l);\n+\n+\tif (tmp >= 0x100)\n+\t\ttmp >>= 8;\n+\treturn tmp;\n+}\n+\n+static inline unsigned long kvmppc_actual_pgsz(unsigned long v, unsigned long r)\n+{\n+\treturn 1ul << kvmppc_hpte_actual_page_shift(v, r);\n+}\n+\n+static inline int kvmppc_pgsize_lp_encoding(int base_shift, int actual_shift)\n+{\n+\tswitch (base_shift) {\n+\tcase 12:\n+\t\tswitch (actual_shift) {\n+\t\tcase 12:\n+\t\t\treturn 0;\n+\t\tcase 16:\n+\t\t\treturn 7;\n+\t\tcase 24:\n+\t\t\treturn 0x38;\n+\t\t}\n+\t\tbreak;\n+\tcase 16:\n+\t\tswitch (actual_shift) {\n+\t\tcase 16:\n+\t\t\treturn 1;\n+\t\tcase 24:\n+\t\t\treturn 8;\n+\t\t}\n+\t\tbreak;\n+\tcase 24:\n+\t\treturn 0;\n+\t}\n+\treturn -1;\n+}\n+\n static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,\n \t\t\t\t\t unsigned long pte_index)\n {\n-\tint i, b_psize = MMU_PAGE_4K, a_psize = MMU_PAGE_4K;\n-\tunsigned int penc;\n+\tint a_pgshift, b_pgshift;\n \tunsigned long rb = 0, va_low, sllp;\n-\tunsigned int lp = (r >> LP_SHIFT) & ((1 << LP_BITS) - 1);\n \n-\tif (v & HPTE_V_LARGE) {\n-\t\ti = hpte_page_sizes[lp];\n-\t\tb_psize = i & 0xf;\n-\t\ta_psize = i >> 4;\n+\tb_pgshift = a_pgshift = kvmppc_hpte_page_shifts(v, r);\n+\tif (a_pgshift >= 0x100) {\n+\t\tb_pgshift &= 0xff;\n+\t\ta_pgshift >>= 8;\n \t}\n \n \t/*\n@@ -152,37 +230,33 @@ static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,\n \t\tva_low ^= v >> (SID_SHIFT_1T - 16);\n \tva_low &= 0x7ff;\n \n-\tswitch (b_psize) {\n-\tcase MMU_PAGE_4K:\n-\t\tsllp = get_sllp_encoding(a_psize);\n-\t\trb |= sllp << 5;\t/* AP field */\n+\tif (b_pgshift == 12) {\n+\t\tif (a_pgshift > 12) {\n+\t\t\tsllp = (a_pgshift == 16) ? 5 : 4;\n+\t\t\trb |= sllp << 5;\t/* AP field */\n+\t\t}\n \t\trb |= (va_low & 0x7ff) << 12;\t/* remaining 11 bits of AVA */\n-\t\tbreak;\n-\tdefault:\n-\t{\n+\t} else {\n \t\tint aval_shift;\n \t\t/*\n \t\t * remaining bits of AVA/LP fields\n \t\t * Also contain the rr bits of LP\n \t\t */\n-\t\trb |= (va_low << mmu_psize_defs[b_psize].shift) & 0x7ff000;\n+\t\trb |= (va_low << b_pgshift) & 0x7ff000;\n \t\t/*\n \t\t * Now clear not needed LP bits based on actual psize\n \t\t */\n-\t\trb &= ~((1ul << mmu_psize_defs[a_psize].shift) - 1);\n+\t\trb &= ~((1ul << a_pgshift) - 1);\n \t\t/*\n \t\t * AVAL field 58..77 - base_page_shift bits of va\n \t\t * we have space for 58..64 bits, Missing bits should\n \t\t * be zero filled. +1 is to take care of L bit shift\n \t\t */\n-\t\taval_shift = 64 - (77 - mmu_psize_defs[b_psize].shift) + 1;\n+\t\taval_shift = 64 - (77 - b_pgshift) + 1;\n \t\trb |= ((va_low << aval_shift) & 0xfe);\n \n \t\trb |= 1;\t\t/* L field */\n-\t\tpenc = mmu_psize_defs[b_psize].penc[a_psize];\n-\t\trb |= penc << 12;\t/* LP field */\n-\t\tbreak;\n-\t}\n+\t\trb |= r & 0xff000 & ((1ul << a_pgshift) - 1); /* LP field */\n \t}\n \trb |= (v >> HPTE_V_SSIZE_SHIFT) << 8;\t/* B field */\n \treturn rb;\ndiff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c b/arch/powerpc/kvm/book3s_64_mmu_hv.c\nindex 624b011..cc21d3c 100644\n--- a/arch/powerpc/kvm/book3s_64_mmu_hv.c\n+++ b/arch/powerpc/kvm/book3s_64_mmu_hv.c\n@@ -333,7 +333,7 @@ static unsigned long kvmppc_mmu_get_real_addr(unsigned long v, unsigned long r,\n {\n \tunsigned long ra_mask;\n \n-\tra_mask = hpte_page_size(v, r) - 1;\n+\tra_mask = kvmppc_actual_pgsz(v, r) - 1;\n \treturn (r & HPTE_R_RPN & ~ra_mask) | (ea & ra_mask);\n }\n \n@@ -504,7 +504,8 @@ int kvmppc_book3s_hv_page_fault(struct kvm_run *run, struct kvm_vcpu *vcpu,\n \t\tmmio_update = atomic64_read(&kvm->arch.mmio_update);\n \t\tif (mmio_update == vcpu->arch.pgfault_cache->mmio_update) {\n \t\t\tr = vcpu->arch.pgfault_cache->rpte;\n-\t\t\tpsize = hpte_page_size(vcpu->arch.pgfault_hpte[0], r);\n+\t\t\tpsize = kvmppc_actual_pgsz(vcpu->arch.pgfault_hpte[0],\n+\t\t\t\t\t\t r);\n \t\t\tgpa_base = r & HPTE_R_RPN & ~(psize - 1);\n \t\t\tgfn_base = gpa_base >> PAGE_SHIFT;\n \t\t\tgpa = gpa_base | (ea & (psize - 1));\n@@ -533,7 +534,7 @@ int kvmppc_book3s_hv_page_fault(struct kvm_run *run, struct kvm_vcpu *vcpu,\n \t\treturn RESUME_GUEST;\n \n \t/* Translate the logical address and get the page */\n-\tpsize = hpte_page_size(hpte[0], r);\n+\tpsize = kvmppc_actual_pgsz(hpte[0], r);\n \tgpa_base = r & HPTE_R_RPN & ~(psize - 1);\n \tgfn_base = gpa_base >> PAGE_SHIFT;\n \tgpa = gpa_base | (ea & (psize - 1));\n@@ -797,7 +798,7 @@ static void kvmppc_unmap_hpte(struct kvm *kvm, unsigned long i,\n \n \t/* Now check and modify the HPTE */\n \tptel = rev[i].guest_rpte;\n-\tpsize = hpte_page_size(be64_to_cpu(hptep[0]), ptel);\n+\tpsize = kvmppc_actual_pgsz(be64_to_cpu(hptep[0]), ptel);\n \tif ((be64_to_cpu(hptep[0]) & HPTE_V_VALID) &&\n \t hpte_rpn(ptel, psize) == gfn) {\n \t\thptep[0] |= cpu_to_be64(HPTE_V_ABSENT);\n@@ -1091,7 +1092,7 @@ static int kvm_test_clear_dirty_npages(struct kvm *kvm, unsigned long *rmapp)\n \t\t\t\trev[i].guest_rpte |= HPTE_R_C;\n \t\t\t\tnote_hpte_modification(kvm, &rev[i]);\n \t\t\t}\n-\t\t\tn = hpte_page_size(v, r);\n+\t\t\tn = kvmppc_actual_pgsz(v, r);\n \t\t\tn = (n + PAGE_SIZE - 1) >> PAGE_SHIFT;\n \t\t\tif (n > npages_dirty)\n \t\t\t\tnpages_dirty = n;\n@@ -1266,7 +1267,7 @@ static unsigned long resize_hpt_rehash_hpte(struct kvm_resize_hpt *resize,\n \tguest_rpte = rev->guest_rpte;\n \n \tret = -EIO;\n-\tapsize = hpte_page_size(vpte, guest_rpte);\n+\tapsize = kvmppc_actual_pgsz(vpte, guest_rpte);\n \tif (!apsize)\n \t\tgoto out;\n \ndiff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c\nindex 9634425..b3817df 100644\n--- a/arch/powerpc/kvm/book3s_hv.c\n+++ b/arch/powerpc/kvm/book3s_hv.c\n@@ -3300,22 +3300,21 @@ static int kvmppc_vcpu_run_hv(struct kvm_run *run, struct kvm_vcpu *vcpu)\n }\n \n static void kvmppc_add_seg_page_size(struct kvm_ppc_one_seg_page_size **sps,\n-\t\t\t\t int linux_psize)\n+\t\t\t\t int shift, int sllp)\n {\n-\tstruct mmu_psize_def *def = &mmu_psize_defs[linux_psize];\n-\n-\tif (!def->shift)\n-\t\treturn;\n-\t(*sps)->page_shift = def->shift;\n-\t(*sps)->slb_enc = def->sllp;\n-\t(*sps)->enc[0].page_shift = def->shift;\n-\t(*sps)->enc[0].pte_enc = def->penc[linux_psize];\n+\t(*sps)->page_shift = shift;\n+\t(*sps)->slb_enc = sllp;\n+\t(*sps)->enc[0].page_shift = shift;\n+\t(*sps)->enc[0].pte_enc = kvmppc_pgsize_lp_encoding(shift, shift);\n \t/*\n-\t * Add 16MB MPSS support if host supports it\n+\t * Add 16MB MPSS support (may get filtered out by userspace)\n \t */\n-\tif (linux_psize != MMU_PAGE_16M && def->penc[MMU_PAGE_16M] != -1) {\n-\t\t(*sps)->enc[1].page_shift = 24;\n-\t\t(*sps)->enc[1].pte_enc = def->penc[MMU_PAGE_16M];\n+\tif (shift != 24) {\n+\t\tint penc = kvmppc_pgsize_lp_encoding(shift, 24);\n+\t\tif (penc != -1) {\n+\t\t\t(*sps)->enc[1].page_shift = 24;\n+\t\t\t(*sps)->enc[1].pte_enc = penc;\n+\t\t}\n \t}\n \t(*sps)++;\n }\n@@ -3340,16 +3339,15 @@ static int kvm_vm_ioctl_get_smmu_info_hv(struct kvm *kvm,\n \tinfo->data_keys = 32;\n \tinfo->instr_keys = cpu_has_feature(CPU_FTR_ARCH_207S) ? 32 : 0;\n \n-\tinfo->flags = KVM_PPC_PAGE_SIZES_REAL;\n-\tif (mmu_has_feature(MMU_FTR_1T_SEGMENT))\n-\t\tinfo->flags |= KVM_PPC_1T_SEGMENTS;\n-\tinfo->slb_size = mmu_slb_size;\n+\t/* POWER7, 8 and 9 all have 1T segments and 32-entry SLB */\n+\tinfo->flags = KVM_PPC_PAGE_SIZES_REAL | KVM_PPC_1T_SEGMENTS;\n+\tinfo->slb_size = 32;\n \n \t/* We only support these sizes for now, and no muti-size segments */\n \tsps = &info->sps[0];\n-\tkvmppc_add_seg_page_size(&sps, MMU_PAGE_4K);\n-\tkvmppc_add_seg_page_size(&sps, MMU_PAGE_64K);\n-\tkvmppc_add_seg_page_size(&sps, MMU_PAGE_16M);\n+\tkvmppc_add_seg_page_size(&sps, 12, 0);\n+\tkvmppc_add_seg_page_size(&sps, 16, SLB_VSID_L | SLB_VSID_LP_01);\n+\tkvmppc_add_seg_page_size(&sps, 24, SLB_VSID_L);\n \n \treturn 0;\n }\n@@ -4352,4 +4350,3 @@ module_exit(kvmppc_book3s_exit_hv);\n MODULE_LICENSE(\"GPL\");\n MODULE_ALIAS_MISCDEV(KVM_MINOR);\n MODULE_ALIAS(\"devname:kvm\");\n-\ndiff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c b/arch/powerpc/kvm/book3s_hv_rm_mmu.c\nindex 4efe364..cf98f17 100644\n--- a/arch/powerpc/kvm/book3s_hv_rm_mmu.c\n+++ b/arch/powerpc/kvm/book3s_hv_rm_mmu.c\n@@ -129,7 +129,7 @@ static unsigned long *revmap_for_hpte(struct kvm *kvm, unsigned long hpte_v,\n \tunsigned long *rmap;\n \tunsigned long gfn;\n \n-\tgfn = hpte_rpn(hpte_gr, hpte_page_size(hpte_v, hpte_gr));\n+\tgfn = hpte_rpn(hpte_gr, kvmppc_actual_pgsz(hpte_v, hpte_gr));\n \tmemslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);\n \tif (!memslot)\n \t\treturn NULL;\n@@ -169,7 +169,8 @@ static void remove_revmap_chain(struct kvm *kvm, long pte_index,\n \t}\n \t*rmap |= rcbits << KVMPPC_RMAP_RC_SHIFT;\n \tif (rcbits & HPTE_R_C)\n-\t\tkvmppc_update_rmap_change(rmap, hpte_page_size(hpte_v, hpte_r));\n+\t\tkvmppc_update_rmap_change(rmap,\n+\t\t\t\t\t kvmppc_actual_pgsz(hpte_v, hpte_r));\n \tunlock_rmap(rmap);\n }\n \n@@ -193,7 +194,7 @@ long kvmppc_do_h_enter(struct kvm *kvm, unsigned long flags,\n \n \tif (kvm_is_radix(kvm))\n \t\treturn H_FUNCTION;\n-\tpsize = hpte_page_size(pteh, ptel);\n+\tpsize = kvmppc_actual_pgsz(pteh, ptel);\n \tif (!psize)\n \t\treturn H_PARAMETER;\n \twriting = hpte_is_writable(ptel);\n@@ -848,7 +849,7 @@ long kvmppc_h_clear_mod(struct kvm_vcpu *vcpu, unsigned long flags,\n \t\tr = be64_to_cpu(hpte[1]);\n \t\tgr |= r & (HPTE_R_R | HPTE_R_C);\n \t\tif (r & HPTE_R_C) {\n-\t\t\tunsigned long psize = hpte_page_size(v, r);\n+\t\t\tunsigned long psize = kvmppc_actual_pgsz(v, r);\n \t\t\thpte[1] = cpu_to_be64(r & ~HPTE_R_C);\n \t\t\teieio();\n \t\t\trmap = revmap_for_hpte(kvm, v, gr);\n@@ -1014,7 +1015,7 @@ long kvmppc_hv_find_lock_hpte(struct kvm *kvm, gva_t eaddr, unsigned long slb_v,\n \t\t\t * Check the HPTE again, including base page size\n \t\t\t */\n \t\t\tif ((v & valid) && (v & mask) == val &&\n-\t\t\t hpte_base_page_size(v, r) == (1ul << pshift))\n+\t\t\t kvmppc_hpte_base_page_shift(v, r) == pshift)\n \t\t\t\t/* Return with the HPTE still locked */\n \t\t\t\treturn (hash << 3) + (i >> 1);\n \n", "prefixes": [ "v2", "1/6" ] }