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GET /api/1.2/patches/831049/?format=api
{ "id": 831049, "url": "http://patchwork.ozlabs.org/api/1.2/patches/831049/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20171027040833.3644-8-aneesh.kumar@linux.vnet.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/1.2/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20171027040833.3644-8-aneesh.kumar@linux.vnet.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20171027040833.3644-8-aneesh.kumar@linux.vnet.ibm.com/", "date": "2017-10-27T04:08:24", "name": "[07/16] powerpc/mm: Add hash updatepp callback", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "1dac37b632ba6af7e02bde86cb286947165698bf", "submitter": { "id": 664, "url": "http://patchwork.ozlabs.org/api/1.2/people/664/?format=api", "name": "Aneesh Kumar K.V", "email": "aneesh.kumar@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20171027040833.3644-8-aneesh.kumar@linux.vnet.ibm.com/mbox/", "series": [ { "id": 10486, "url": "http://patchwork.ozlabs.org/api/1.2/series/10486/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=10486", "date": "2017-10-27T04:08:17", "name": "Remove hash page table slot tracking from linux PTE", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/10486/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/831049/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/831049/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yNVzJ5LXpz9t2S\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri, 27 Oct 2017 15:20:28 +1100 (AEDT)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3yNVzJ4QVPzDsc8\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri, 27 Oct 2017 15:20:28 +1100 (AEDT)", "from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3yNVkg1tcpzDrcQ\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 27 Oct 2017 15:09:31 +1100 (AEDT)", "from pps.filterd (m0098420.ppops.net [127.0.0.1])\n\tby mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv9R492qV141755\n\tfor <linuxppc-dev@lists.ozlabs.org>; Fri, 27 Oct 2017 00:09:28 -0400", "from e32.co.us.ibm.com (e32.co.us.ibm.com [32.97.110.150])\n\tby mx0b-001b2d01.pphosted.com with ESMTP id 2dustahpt4-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <linuxppc-dev@lists.ozlabs.org>; Fri, 27 Oct 2017 00:09:28 -0400", "from localhost\n\tby e32.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <linuxppc-dev@lists.ozlabs.org> from\n\t<aneesh.kumar@linux.vnet.ibm.com>; Thu, 26 Oct 2017 22:09:27 -0600", "from b03cxnp08027.gho.boulder.ibm.com (9.17.130.19)\n\tby e32.co.us.ibm.com (192.168.1.132) with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted; \n\tThu, 26 Oct 2017 22:09:24 -0600", "from b03ledav001.gho.boulder.ibm.com\n\t(b03ledav001.gho.boulder.ibm.com [9.17.130.232])\n\tby b03cxnp08027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v9R49NVH61931622; Thu, 26 Oct 2017 21:09:23 -0700", "from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id D8C0D6E179;\n\tThu, 26 Oct 2017 22:09:23 -0600 (MDT)", "from skywalker.ibmmodules.com (unknown [9.85.199.61])\n\tby b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTP id EF4716E121;\n\tThu, 26 Oct 2017 22:09:19 -0600 (MDT)" ], "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com\n\t(client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com;\n\tenvelope-from=aneesh.kumar@linux.vnet.ibm.com; receiver=<UNKNOWN>)", "From": "\"Aneesh Kumar K.V\" <aneesh.kumar@linux.vnet.ibm.com>", "To": "benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au", "Subject": "[PATCH 07/16] powerpc/mm: Add hash updatepp callback", "Date": "Fri, 27 Oct 2017 09:38:24 +0530", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20171027040833.3644-1-aneesh.kumar@linux.vnet.ibm.com>", "References": "<20171027040833.3644-1-aneesh.kumar@linux.vnet.ibm.com>", "X-TM-AS-GCONF": "00", "x-cbid": "17102704-0004-0000-0000-0000131F7218", "X-IBM-SpamModules-Scores": "", "X-IBM-SpamModules-Versions": "BY=3.00007958; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000239; SDB=6.00937034; UDB=6.00472245;\n\tIPR=6.00717297; \n\tBA=6.00005660; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009;\n\tZB=6.00000000; \n\tZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017735;\n\tXFM=3.00000015; UTC=2017-10-27 04:09:25", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17102704-0005-0000-0000-000084A29F50", "Message-Id": "<20171027040833.3644-8-aneesh.kumar@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-10-27_02:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tpriorityscore=1501\n\tmalwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0\n\tclxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0\n\tclassifier=spam adjust=0 reason=mlx scancount=1\n\tengine=8.0.1-1707230000\n\tdefinitions=main-1710270053", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "linuxppc-dev@lists.ozlabs.org,\n\t\"Aneesh Kumar K.V\" <aneesh.kumar@linux.vnet.ibm.com>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Add hash based updatepp callback and use that during hash pte fault.\n\nSigned-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>\n---\n arch/powerpc/include/asm/book3s/64/mmu-hash.h | 6 +++++\n arch/powerpc/mm/hash64_4k.c | 7 +----\n arch/powerpc/mm/hash64_64k.c | 19 +++-----------\n arch/powerpc/mm/hash_native_64.c | 37 +++++++++++++++++++++++++++\n arch/powerpc/mm/hugetlbpage-hash64.c | 9 ++-----\n arch/powerpc/platforms/ps3/htab.c | 29 +++++++++++++++++++++\n arch/powerpc/platforms/pseries/lpar.c | 31 ++++++++++++++++++++++\n 7 files changed, 110 insertions(+), 28 deletions(-)", "diff": "diff --git a/arch/powerpc/include/asm/book3s/64/mmu-hash.h b/arch/powerpc/include/asm/book3s/64/mmu-hash.h\nindex 79f141e721ee..8b1d924a2f85 100644\n--- a/arch/powerpc/include/asm/book3s/64/mmu-hash.h\n+++ b/arch/powerpc/include/asm/book3s/64/mmu-hash.h\n@@ -145,6 +145,12 @@ struct mmu_hash_ops {\n \t\t\t\t\t unsigned long vpn,\n \t\t\t\t\t int bpsize, int apsize,\n \t\t\t\t\t int ssize, unsigned long flags);\n+\tlong\t\t(*hash_updatepp)(unsigned long hash,\n+\t\t\t\t\t unsigned long newpp,\n+\t\t\t\t\t unsigned long vpn,\n+\t\t\t\t\t int bpsize, int apsize,\n+\t\t\t\t\t int ssize, unsigned long flags);\n+\n \tvoid (*hpte_updateboltedpp)(unsigned long newpp,\n \t\t\t\t\t unsigned long ea,\n \t\t\t\t\t int psize, int ssize);\ndiff --git a/arch/powerpc/mm/hash64_4k.c b/arch/powerpc/mm/hash64_4k.c\nindex 975793de0914..afb79100f0ce 100644\n--- a/arch/powerpc/mm/hash64_4k.c\n+++ b/arch/powerpc/mm/hash64_4k.c\n@@ -65,12 +65,7 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,\n \t\t * There MIGHT be an HPTE for this pte\n \t\t */\n \t\thash = hpt_hash(vpn, shift, ssize);\n-\t\tif (old_pte & H_PAGE_F_SECOND)\n-\t\t\thash = ~hash;\n-\t\tslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;\n-\t\tslot += (old_pte & H_PAGE_F_GIX) >> H_PAGE_F_GIX_SHIFT;\n-\n-\t\tif (mmu_hash_ops.hpte_updatepp(slot, rflags, vpn, MMU_PAGE_4K,\n+\t\tif (mmu_hash_ops.hash_updatepp(hash, rflags, vpn, MMU_PAGE_4K,\n \t\t\t\t\t MMU_PAGE_4K, ssize, flags) == -1)\n \t\t\told_pte &= ~_PAGE_HPTEFLAGS;\n \t}\ndiff --git a/arch/powerpc/mm/hash64_64k.c b/arch/powerpc/mm/hash64_64k.c\nindex f1eb538721fc..096fdfaf6f1c 100644\n--- a/arch/powerpc/mm/hash64_64k.c\n+++ b/arch/powerpc/mm/hash64_64k.c\n@@ -53,7 +53,7 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,\n \tunsigned long *hidxp;\n \tunsigned long hpte_group;\n \tunsigned int subpg_index;\n-\tunsigned long rflags, pa, hidx;\n+\tunsigned long rflags, pa;\n \tunsigned long old_pte, new_pte, subpg_pte;\n \tunsigned long vpn, hash, slot;\n \tunsigned long shift = mmu_psize_defs[MMU_PAGE_4K].shift;\n@@ -127,17 +127,11 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,\n \t\tint ret;\n \n \t\thash = hpt_hash(vpn, shift, ssize);\n-\t\thidx = __rpte_to_hidx(rpte, subpg_index);\n-\t\tif (hidx & _PTEIDX_SECONDARY)\n-\t\t\thash = ~hash;\n-\t\tslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;\n-\t\tslot += hidx & _PTEIDX_GROUP_IX;\n-\n-\t\tret = mmu_hash_ops.hpte_updatepp(slot, rflags, vpn,\n+\t\tret = mmu_hash_ops.hash_updatepp(hash, rflags, vpn,\n \t\t\t\t\t\t MMU_PAGE_4K, MMU_PAGE_4K,\n \t\t\t\t\t\t ssize, flags);\n \t\t/*\n-\t\t *if we failed because typically the HPTE wasn't really here\n+\t\t * if we failed because typically the HPTE wasn't really here\n \t\t * we try an insertion.\n \t\t */\n \t\tif (ret == -1)\n@@ -268,12 +262,7 @@ int __hash_page_64K(unsigned long ea, unsigned long access,\n \t\t * There MIGHT be an HPTE for this pte\n \t\t */\n \t\thash = hpt_hash(vpn, shift, ssize);\n-\t\tif (old_pte & H_PAGE_F_SECOND)\n-\t\t\thash = ~hash;\n-\t\tslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;\n-\t\tslot += (old_pte & H_PAGE_F_GIX) >> H_PAGE_F_GIX_SHIFT;\n-\n-\t\tif (mmu_hash_ops.hpte_updatepp(slot, rflags, vpn, MMU_PAGE_64K,\n+\t\tif (mmu_hash_ops.hash_updatepp(hash, rflags, vpn, MMU_PAGE_64K,\n \t\t\t\t\t MMU_PAGE_64K, ssize,\n \t\t\t\t\t flags) == -1)\n \t\t\told_pte &= ~_PAGE_HPTEFLAGS;\ndiff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c\nindex 8e2e6b92aa27..3b061844929c 100644\n--- a/arch/powerpc/mm/hash_native_64.c\n+++ b/arch/powerpc/mm/hash_native_64.c\n@@ -396,6 +396,42 @@ struct hash_pte *native_hpte_find(unsigned long hash, unsigned long vpn,\n \treturn NULL;\n }\n \n+static long native_hash_updatepp(unsigned long hash, unsigned long newpp,\n+\t\t\t\t unsigned long vpn, int bpsize,\n+\t\t\t\t int apsize, int ssize, unsigned long flags)\n+{\n+\tint ret = 0;\n+\tstruct hash_pte *hptep;\n+\tint local = 0;\n+\n+\n+\tDBG_LOW(\" update(vpn=%016lx, newpp=%lx)\", vpn, newpp);\n+\n+\thptep = native_hpte_find(hash, vpn, bpsize, ssize);\n+\tif (hptep) {\n+\t\tDBG_LOW(\" -> hit\\n\");\n+\t\t/* Update the HPTE */\n+\t\thptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &\n+\t\t\t\t\t~(HPTE_R_PPP | HPTE_R_N)) |\n+\t\t\t\t (newpp & (HPTE_R_PPP | HPTE_R_N |\n+\t\t\t\t\t\t HPTE_R_C)));\n+\t\tnative_unlock_hpte(hptep);\n+\t} else {\n+\t\tDBG_LOW(\" -> miss\\n\");\n+\t\tret = -1;\n+\t}\n+\t/*\n+\t * Ensure it is out of the tlb too if it is not a nohpte fault\n+\t */\n+\tif (!(flags & HPTE_NOHPTE_UPDATE)) {\n+\t\tif (flags & HPTE_LOCAL_UPDATE)\n+\t\t\tlocal = 1;\n+\t\ttlbie(vpn, bpsize, apsize, ssize, local);\n+\t}\n+\treturn ret;\n+}\n+\n+\n /*\n * Update the page protection bits. Intended to be used to create\n * guard pages for kernel data structures on pages which are bolted\n@@ -792,6 +828,7 @@ void __init hpte_init_native(void)\n \tmmu_hash_ops.hpte_invalidate\t= native_hpte_invalidate;\n \tmmu_hash_ops.hash_invalidate\t= native_hash_invalidate;\n \tmmu_hash_ops.hpte_updatepp\t= native_hpte_updatepp;\n+\tmmu_hash_ops.hash_updatepp\t= native_hash_updatepp;\n \tmmu_hash_ops.hpte_updateboltedpp = native_hpte_updateboltedpp;\n \tmmu_hash_ops.hpte_removebolted = native_hpte_removebolted;\n \tmmu_hash_ops.hpte_insert\t= native_hpte_insert;\ndiff --git a/arch/powerpc/mm/hugetlbpage-hash64.c b/arch/powerpc/mm/hugetlbpage-hash64.c\nindex a84bb44497f9..4eb8c9d2f452 100644\n--- a/arch/powerpc/mm/hugetlbpage-hash64.c\n+++ b/arch/powerpc/mm/hugetlbpage-hash64.c\n@@ -71,15 +71,10 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,\n \t/* Check if pte already has an hpte (case 2) */\n \tif (unlikely(old_pte & H_PAGE_HASHPTE)) {\n \t\t/* There MIGHT be an HPTE for this pte */\n-\t\tunsigned long hash, slot;\n+\t\tunsigned long hash;\n \n \t\thash = hpt_hash(vpn, shift, ssize);\n-\t\tif (old_pte & H_PAGE_F_SECOND)\n-\t\t\thash = ~hash;\n-\t\tslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;\n-\t\tslot += (old_pte & H_PAGE_F_GIX) >> H_PAGE_F_GIX_SHIFT;\n-\n-\t\tif (mmu_hash_ops.hpte_updatepp(slot, rflags, vpn, mmu_psize,\n+\t\tif (mmu_hash_ops.hash_updatepp(hash, rflags, vpn, mmu_psize,\n \t\t\t\t\t mmu_psize, ssize, flags) == -1)\n \t\t\told_pte &= ~_PAGE_HPTEFLAGS;\n \t}\ndiff --git a/arch/powerpc/platforms/ps3/htab.c b/arch/powerpc/platforms/ps3/htab.c\nindex 813c2f77f75d..4e82f7cbd124 100644\n--- a/arch/powerpc/platforms/ps3/htab.c\n+++ b/arch/powerpc/platforms/ps3/htab.c\n@@ -251,11 +251,40 @@ static void ps3_hash_invalidate(unsigned long hash, unsigned long vpn,\n \treturn;\n }\n \n+static long ps3_hash_updatepp(unsigned long hash,\n+\t\t\t unsigned long newpp, unsigned long vpn,\n+\t\t\t int psize, int apsize, int ssize,\n+\t\t\t unsigned long inv_flags)\n+{\n+\tlong slot;\n+\tunsigned long flags;\n+\tunsigned long want_v;\n+\n+\twant_v = hpte_encode_avpn(vpn, psize, ssize);\n+\tspin_lock_irqsave(&ps3_htab_lock, flags);\n+\n+\tslot = ps3_hpte_find(hash, want_v);\n+\tif (slot < 0)\n+\t\tgoto err_out;\n+\t/*\n+\t * entry found, just invalidate it\n+\t */\n+\tlv1_write_htab_entry(PS3_LPAR_VAS_ID_CURRENT, slot, 0, 0);\n+\t/*\n+\t * We just invalidate instead of updating pp. Hence\n+\t * return -1;\n+\t */\n+err_out:\n+\tspin_unlock_irqrestore(&ps3_htab_lock, flags);\n+\treturn -1;\n+}\n+\n void __init ps3_hpte_init(unsigned long htab_size)\n {\n \tmmu_hash_ops.hpte_invalidate = ps3_hpte_invalidate;\n \tmmu_hash_ops.hash_invalidate = ps3_hash_invalidate;\n \tmmu_hash_ops.hpte_updatepp = ps3_hpte_updatepp;\n+\tmmu_hash_ops.hash_updatepp = ps3_hash_updatepp;\n \tmmu_hash_ops.hpte_updateboltedpp = ps3_hpte_updateboltedpp;\n \tmmu_hash_ops.hpte_insert = ps3_hpte_insert;\n \tmmu_hash_ops.hpte_remove = ps3_hpte_remove;\ndiff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c\nindex d32469e40bbc..511a2e9ed9a0 100644\n--- a/arch/powerpc/platforms/pseries/lpar.c\n+++ b/arch/powerpc/platforms/pseries/lpar.c\n@@ -376,6 +376,36 @@ static long pSeries_lpar_hpte_find(unsigned long vpn, int psize, int ssize)\n \treturn slot;\n }\n \n+static long pSeries_lpar_hash_updatepp(unsigned long hash,\n+\t\t\t\t unsigned long newpp,\n+\t\t\t\t unsigned long vpn,\n+\t\t\t\t int psize, int apsize,\n+\t\t\t\t int ssize, unsigned long inv_flags)\n+{\n+\tlong slot;\n+\tunsigned long lpar_rc;\n+\tunsigned long flags = (newpp & 7) | H_AVPN;\n+\tunsigned long want_v;\n+\n+\twant_v = hpte_encode_avpn(vpn, psize, ssize);\n+\n+\tpr_devel(\" update: avpnv=%016lx, hash=%016lx, f=%lx, psize: %d ...\",\n+\t\t want_v, hash, flags, psize);\n+\n+\tslot = __pSeries_lpar_hpte_find(hash, want_v);\n+\tif (slot < 0)\n+\t\treturn -1;\n+\n+\tlpar_rc = plpar_pte_protect(flags, slot, want_v);\n+\tif (lpar_rc == H_NOT_FOUND) {\n+\t\tpr_devel(\"not found !\\n\");\n+\t\treturn -1;\n+\t}\n+\tpr_devel(\"ok\\n\");\n+\tBUG_ON(lpar_rc != H_SUCCESS);\n+\n+\treturn 0;\n+}\n \n static void pSeries_lpar_hpte_updateboltedpp(unsigned long newpp,\n \t\t\t\t\t unsigned long ea,\n@@ -784,6 +814,7 @@ void __init hpte_init_pseries(void)\n \tmmu_hash_ops.hpte_invalidate\t = pSeries_lpar_hpte_invalidate;\n \tmmu_hash_ops.hash_invalidate\t = pSeries_lpar_hash_invalidate;\n \tmmu_hash_ops.hpte_updatepp\t = pSeries_lpar_hpte_updatepp;\n+\tmmu_hash_ops.hash_updatepp\t = pSeries_lpar_hash_updatepp;\n \tmmu_hash_ops.hpte_updateboltedpp = pSeries_lpar_hpte_updateboltedpp;\n \tmmu_hash_ops.hpte_insert\t = pSeries_lpar_hpte_insert;\n \tmmu_hash_ops.hpte_remove\t = pSeries_lpar_hpte_remove;\n", "prefixes": [ "07/16" ] }