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GET /api/1.2/patches/831046/?format=api
{ "id": 831046, "url": "http://patchwork.ozlabs.org/api/1.2/patches/831046/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20171027040833.3644-5-aneesh.kumar@linux.vnet.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/1.2/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20171027040833.3644-5-aneesh.kumar@linux.vnet.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20171027040833.3644-5-aneesh.kumar@linux.vnet.ibm.com/", "date": "2017-10-27T04:08:21", "name": "[04/16] powerpc/mm: Add hash invalidate callback", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "db2d21bc747ca0ab6443278674c69fd610857c56", "submitter": { "id": 664, "url": "http://patchwork.ozlabs.org/api/1.2/people/664/?format=api", "name": "Aneesh Kumar K.V", "email": "aneesh.kumar@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20171027040833.3644-5-aneesh.kumar@linux.vnet.ibm.com/mbox/", "series": [ { "id": 10486, "url": "http://patchwork.ozlabs.org/api/1.2/series/10486/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=10486", "date": "2017-10-27T04:08:17", "name": "Remove hash page table slot tracking from linux PTE", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/10486/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/831046/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/831046/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yNVtd4xYhz9t0F\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri, 27 Oct 2017 15:16:25 +1100 (AEDT)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3yNVtd3tPBzDsPK\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri, 27 Oct 2017 15:16:25 +1100 (AEDT)", "from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3yNVkN5fmBzDrcR\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 27 Oct 2017 15:09:16 +1100 (AEDT)", "from pps.filterd (m0098417.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv9R49464047533\n\tfor <linuxppc-dev@lists.ozlabs.org>; Fri, 27 Oct 2017 00:09:13 -0400", "from e32.co.us.ibm.com (e32.co.us.ibm.com [32.97.110.150])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2dus55ax77-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <linuxppc-dev@lists.ozlabs.org>; Fri, 27 Oct 2017 00:09:12 -0400", "from localhost\n\tby e32.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <linuxppc-dev@lists.ozlabs.org> from\n\t<aneesh.kumar@linux.vnet.ibm.com>; Thu, 26 Oct 2017 22:09:11 -0600", "from b03cxnp08028.gho.boulder.ibm.com (9.17.130.20)\n\tby e32.co.us.ibm.com (192.168.1.132) with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted; \n\tThu, 26 Oct 2017 22:09:08 -0600", "from b03ledav001.gho.boulder.ibm.com\n\t(b03ledav001.gho.boulder.ibm.com [9.17.130.232])\n\tby b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v9R498fi31916206; Thu, 26 Oct 2017 21:09:08 -0700", "from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 23C656E177;\n\tThu, 26 Oct 2017 22:09:08 -0600 (MDT)", "from skywalker.ibmmodules.com (unknown [9.85.199.61])\n\tby b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTP id 339066E175;\n\tThu, 26 Oct 2017 22:09:03 -0600 (MDT)" ], "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com\n\t(client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com;\n\tenvelope-from=aneesh.kumar@linux.vnet.ibm.com; receiver=<UNKNOWN>)", "From": "\"Aneesh Kumar K.V\" <aneesh.kumar@linux.vnet.ibm.com>", "To": "benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au", "Subject": "[PATCH 04/16] powerpc/mm: Add hash invalidate callback", "Date": "Fri, 27 Oct 2017 09:38:21 +0530", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20171027040833.3644-1-aneesh.kumar@linux.vnet.ibm.com>", "References": "<20171027040833.3644-1-aneesh.kumar@linux.vnet.ibm.com>", "X-TM-AS-GCONF": "00", "x-cbid": "17102704-0004-0000-0000-0000131F720B", "X-IBM-SpamModules-Scores": "", "X-IBM-SpamModules-Versions": "BY=3.00007958; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000239; SDB=6.00937034; UDB=6.00472245;\n\tIPR=6.00717296; \n\tBA=6.00005660; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009;\n\tZB=6.00000000; \n\tZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017735;\n\tXFM=3.00000015; UTC=2017-10-27 04:09:09", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17102704-0005-0000-0000-000084A29F2B", "Message-Id": "<20171027040833.3644-5-aneesh.kumar@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-10-27_02:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tpriorityscore=1501\n\tmalwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0\n\tclxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0\n\tclassifier=spam adjust=0 reason=mlx scancount=1\n\tengine=8.0.1-1707230000\n\tdefinitions=main-1710270053", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "linuxppc-dev@lists.ozlabs.org,\n\t\"Aneesh Kumar K.V\" <aneesh.kumar@linux.vnet.ibm.com>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Add hash based invalidate callback and use that in flush_hash_page.\nNote: In a later patch, we will drop the slot tracking completely. At that point\nwe will also loose the __rpte_sub_valid() check in\npte_iterate_hashed_subpages(). That means we call the invalidate for all\nsubpages irrespective of whether we took a hash fault on that or not.\n\nSigned-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>\n---\n arch/powerpc/include/asm/book3s/64/mmu-hash.h | 4 ++\n arch/powerpc/mm/hash_native_64.c | 27 ++++++++++++\n arch/powerpc/mm/hash_utils_64.c | 11 ++---\n arch/powerpc/platforms/ps3/htab.c | 59 +++++++++++++++++++++++++++\n arch/powerpc/platforms/pseries/lpar.c | 26 ++++++++++++\n 5 files changed, 119 insertions(+), 8 deletions(-)", "diff": "diff --git a/arch/powerpc/include/asm/book3s/64/mmu-hash.h b/arch/powerpc/include/asm/book3s/64/mmu-hash.h\nindex 508275bb05d5..79f141e721ee 100644\n--- a/arch/powerpc/include/asm/book3s/64/mmu-hash.h\n+++ b/arch/powerpc/include/asm/book3s/64/mmu-hash.h\n@@ -136,6 +136,10 @@ struct mmu_hash_ops {\n \t\t\t\t\t unsigned long vpn,\n \t\t\t\t\t int bpsize, int apsize,\n \t\t\t\t\t int ssize, int local);\n+\tvoid (*hash_invalidate)(unsigned long hash,\n+\t\t\t\t\t unsigned long vpn,\n+\t\t\t\t\t int bpsize, int apsize,\n+\t\t\t\t\t int ssize, int local);\n \tlong\t\t(*hpte_updatepp)(unsigned long slot,\n \t\t\t\t\t unsigned long newpp,\n \t\t\t\t\t unsigned long vpn,\ndiff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c\nindex 496b1680ba24..f473a78baab7 100644\n--- a/arch/powerpc/mm/hash_native_64.c\n+++ b/arch/powerpc/mm/hash_native_64.c\n@@ -497,6 +497,32 @@ static void native_hpte_invalidate(unsigned long slot, unsigned long vpn,\n \tlocal_irq_restore(flags);\n }\n \n+static void native_hash_invalidate(unsigned long hash, unsigned long vpn,\n+\t\t\t\t int bpsize, int apsize, int ssize, int local)\n+{\n+\tunsigned long flags;\n+\tstruct hash_pte *hptep;\n+\n+\tDBG_LOW(\" invalidate(vpn=%016lx, hash: %lx)\\n\", vpn, hash);\n+\tlocal_irq_save(flags);\n+\thptep = native_hpte_find(hash, vpn, bpsize, ssize);\n+\tif (hptep) {\n+\t\t/*\n+\t\t * Invalidate the hpte. NOTE: this also unlocks it\n+\t\t */\n+\t\thptep->v = 0;\n+\t}\n+\t/*\n+\t * We need to invalidate the TLB always because hpte_remove doesn't do\n+\t * a tlb invalidate. If a hash bucket gets full, we \"evict\" a more/less\n+\t * random entry from it. When we do that we don't invalidate the TLB\n+\t * (hpte_remove) because we assume the old translation is still\n+\t * technically \"valid\".\n+\t */\n+\ttlbie(vpn, bpsize, apsize, ssize, local);\n+\tlocal_irq_restore(flags);\n+}\n+\n #ifdef CONFIG_TRANSPARENT_HUGEPAGE\n static void native_hugepage_invalidate(unsigned long vsid,\n \t\t\t\t unsigned long addr,\n@@ -776,6 +802,7 @@ static int native_register_proc_table(unsigned long base, unsigned long page_siz\n void __init hpte_init_native(void)\n {\n \tmmu_hash_ops.hpte_invalidate\t= native_hpte_invalidate;\n+\tmmu_hash_ops.hash_invalidate\t= native_hash_invalidate;\n \tmmu_hash_ops.hpte_updatepp\t= native_hpte_updatepp;\n \tmmu_hash_ops.hpte_updateboltedpp = native_hpte_updateboltedpp;\n \tmmu_hash_ops.hpte_removebolted = native_hpte_removebolted;\ndiff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c\nindex 4d4662a77c14..b197fe57547e 100644\n--- a/arch/powerpc/mm/hash_utils_64.c\n+++ b/arch/powerpc/mm/hash_utils_64.c\n@@ -1598,23 +1598,18 @@ static inline void tm_flush_hash_page(int local)\n void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,\n \t\t unsigned long flags)\n {\n-\tunsigned long hash, index, shift, hidx, slot;\n+\tunsigned long hash, index, shift;\n \tint local = flags & HPTE_LOCAL_UPDATE;\n \n \tDBG_LOW(\"flush_hash_page(vpn=%016lx)\\n\", vpn);\n \tpte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {\n \t\thash = hpt_hash(vpn, shift, ssize);\n-\t\thidx = __rpte_to_hidx(pte, index);\n-\t\tif (hidx & _PTEIDX_SECONDARY)\n-\t\t\thash = ~hash;\n-\t\tslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;\n-\t\tslot += hidx & _PTEIDX_GROUP_IX;\n-\t\tDBG_LOW(\" sub %ld: hash=%lx, hidx=%lx\\n\", index, slot, hidx);\n+\t\tDBG_LOW(\" sub %ld: hash=%lx\\n\", index, hash);\n \t\t/*\n \t\t * We use same base page size and actual psize, because we don't\n \t\t * use these functions for hugepage\n \t\t */\n-\t\tmmu_hash_ops.hpte_invalidate(slot, vpn, psize, psize,\n+\t\tmmu_hash_ops.hash_invalidate(hash, vpn, psize, psize,\n \t\t\t\t\t ssize, local);\n \t} pte_iterate_hashed_end();\n \ndiff --git a/arch/powerpc/platforms/ps3/htab.c b/arch/powerpc/platforms/ps3/htab.c\nindex cc2b281a3766..813c2f77f75d 100644\n--- a/arch/powerpc/platforms/ps3/htab.c\n+++ b/arch/powerpc/platforms/ps3/htab.c\n@@ -193,9 +193,68 @@ static void ps3_hpte_clear(void)\n \tps3_mm_vas_destroy();\n }\n \n+static long ps3_hpte_find(unsigned long hash, unsigned long want_v)\n+{\n+\tunsigned long i, j, result;\n+\tunsigned long hpte_group;\n+\tbool secondary_search = false;\n+\tu64 hpte_v_array[4], hpte_rs;\n+\n+\n+\t/* first check primary */\n+\thpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP;\n+\n+search_again:\n+\tfor (i = 0; i < HPTES_PER_GROUP; i += 4, hpte_group += 4) {\n+\n+\t\tresult = lv1_read_htab_entries(PS3_LPAR_VAS_ID_CURRENT,\n+\t\t\t\t\t hpte_group & ~0x3UL, &hpte_v_array[0],\n+\t\t\t\t\t &hpte_v_array[1], &hpte_v_array[2],\n+\t\t\t\t\t &hpte_v_array[3], &hpte_rs);\n+\t\t/* ignore failures ? */\n+\t\tif (result)\n+\t\t\tcontinue;\n+\n+\t\tfor (j = 0; j < 4; j++) {\n+\t\t\tif (HPTE_V_COMPARE(hpte_v_array[j], want_v) &&\n+\t\t\t (hpte_v_array[j] & HPTE_V_VALID)) {\n+\t\t\t\treturn hpte_group + j;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tif (!secondary_search) {\n+\t\thpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP;\n+\t\tsecondary_search = true;\n+\t\tgoto search_again;\n+\t}\n+\treturn -1;\n+}\n+\n+static void ps3_hash_invalidate(unsigned long hash, unsigned long vpn,\n+\t\t\t\tint psize, int apsize, int ssize, int local)\n+{\n+\tlong slot;\n+\tunsigned long flags;\n+\tunsigned long want_v;\n+\n+\twant_v = hpte_encode_avpn(vpn, psize, ssize);\n+\n+\tspin_lock_irqsave(&ps3_htab_lock, flags);\n+\tslot = ps3_hpte_find(hash, want_v);\n+\tif (slot < 0)\n+\t\t/* HPTE not found */\n+\t\tgoto err_out;\n+\t/* invalidate the entry */\n+\tlv1_write_htab_entry(PS3_LPAR_VAS_ID_CURRENT, slot, 0, 0);\n+err_out:\n+\tspin_unlock_irqrestore(&ps3_htab_lock, flags);\n+\treturn;\n+}\n+\n void __init ps3_hpte_init(unsigned long htab_size)\n {\n \tmmu_hash_ops.hpte_invalidate = ps3_hpte_invalidate;\n+\tmmu_hash_ops.hash_invalidate = ps3_hash_invalidate;\n \tmmu_hash_ops.hpte_updatepp = ps3_hpte_updatepp;\n \tmmu_hash_ops.hpte_updateboltedpp = ps3_hpte_updateboltedpp;\n \tmmu_hash_ops.hpte_insert = ps3_hpte_insert;\ndiff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c\nindex edab68d9f9f3..e366252e0e93 100644\n--- a/arch/powerpc/platforms/pseries/lpar.c\n+++ b/arch/powerpc/platforms/pseries/lpar.c\n@@ -419,6 +419,31 @@ static void pSeries_lpar_hpte_invalidate(unsigned long slot, unsigned long vpn,\n \tBUG_ON(lpar_rc != H_SUCCESS);\n }\n \n+static void pSeries_lpar_hash_invalidate(unsigned long hash, unsigned long vpn,\n+\t\t\t\t\t int psize, int apsize,\n+\t\t\t\t\t int ssize, int local)\n+{\n+\tlong slot;\n+\tunsigned long want_v;\n+\tunsigned long lpar_rc;\n+\tunsigned long dummy1, dummy2;\n+\n+\tpr_devel(\" inval : hash=%lx, vpn=%016lx, psize: %d, local: %d\\n\",\n+\t\t hash, vpn, psize, local);\n+\n+\twant_v = hpte_encode_avpn(vpn, psize, ssize);\n+\tslot = __pSeries_lpar_hpte_find(hash, want_v);\n+\tif (slot < 0)\n+\t\t/* HPTE not found */\n+\t\treturn;\n+\tlpar_rc = plpar_pte_remove(H_AVPN, slot, want_v, &dummy1, &dummy2);\n+\tif (lpar_rc == H_NOT_FOUND)\n+\t\treturn;\n+\n+\tBUG_ON(lpar_rc != H_SUCCESS);\n+}\n+\n+\n #ifdef CONFIG_TRANSPARENT_HUGEPAGE\n /*\n * Limit iterations holding pSeries_lpar_tlbie_lock to 3. We also need\n@@ -758,6 +783,7 @@ static int pseries_lpar_register_process_table(unsigned long base,\n void __init hpte_init_pseries(void)\n {\n \tmmu_hash_ops.hpte_invalidate\t = pSeries_lpar_hpte_invalidate;\n+\tmmu_hash_ops.hash_invalidate\t = pSeries_lpar_hash_invalidate;\n \tmmu_hash_ops.hpte_updatepp\t = pSeries_lpar_hpte_updatepp;\n \tmmu_hash_ops.hpte_updateboltedpp = pSeries_lpar_hpte_updateboltedpp;\n \tmmu_hash_ops.hpte_insert\t = pSeries_lpar_hpte_insert;\n", "prefixes": [ "04/16" ] }