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GET /api/1.2/patches/831036/?format=api
{ "id": 831036, "url": "http://patchwork.ozlabs.org/api/1.2/patches/831036/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1509073651-23730-2-git-send-email-shawnguo@kernel.org/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/1.2/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1509073651-23730-2-git-send-email-shawnguo@kernel.org>", "list_archive_url": null, "date": "2017-10-27T03:07:30", "name": "[v4,1/2] dt-bindings: add bindings doc for hi3798cv200 combphy", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "cf85a03b495fd817d08c7922532a6e934ccf71e5", "submitter": { "id": 66396, "url": "http://patchwork.ozlabs.org/api/1.2/people/66396/?format=api", "name": "Shawn Guo", "email": "shawnguo@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1509073651-23730-2-git-send-email-shawnguo@kernel.org/mbox/", "series": [ { "id": 10481, "url": "http://patchwork.ozlabs.org/api/1.2/series/10481/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=10481", "date": "2017-10-27T03:07:29", "name": "Add Combo PHY driver for HiSilicon STB SoCs", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/10481/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/831036/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/831036/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org", "mail.kernel.org;\n\tspf=none smtp.mailfrom=shawnguo@kernel.org" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yNTMd4025z9t2x\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tFri, 27 Oct 2017 14:07:57 +1100 (AEDT)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751646AbdJ0DH4 (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tThu, 26 Oct 2017 23:07:56 -0400", "from mail.kernel.org ([198.145.29.99]:41062 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751483AbdJ0DH4 (ORCPT <rfc822;devicetree@vger.kernel.org>);\n\tThu, 26 Oct 2017 23:07:56 -0400", "from localhost.localdomain (unknown [104.237.91.22])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 732E721934;\n\tFri, 27 Oct 2017 03:07:53 +0000 (UTC)" ], "DMARC-Filter": "OpenDMARC Filter v1.3.2 mail.kernel.org 732E721934", "From": "Shawn Guo <shawnguo@kernel.org>", "To": "Kishon Vijay Abraham I <kishon@ti.com>", "Cc": "Rob Herring <robh+dt@kernel.org>, Jianguo Sun <sunjianguo1@huawei.com>, \n\tJiancheng Xue <xuejiancheng@hisilicon.com>,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tShawn Guo <shawn.guo@linaro.org>", "Subject": "[PATCH v4 1/2] dt-bindings: add bindings doc for hi3798cv200 combphy", "Date": "Fri, 27 Oct 2017 11:07:30 +0800", "Message-Id": "<1509073651-23730-2-git-send-email-shawnguo@kernel.org>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1509073651-23730-1-git-send-email-shawnguo@kernel.org>", "References": "<1509073651-23730-1-git-send-email-shawnguo@kernel.org>", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "From: Jianguo Sun <sunjianguo1@huawei.com>\n\nIt adds the device tree bindings for PCIE/SATA/USB3 combo PHY found on\nHiSilicon STB SoCs.\n\nSigned-off-by: Jianguo Sun <sunjianguo1@huawei.com>\nSigned-off-by: Shawn Guo <shawn.guo@linaro.org>\n---\n .../bindings/phy/phy-hi3798cv200-combphy.txt | 57 ++++++++++++++++++++++\n 1 file changed, 57 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt", "diff": "diff --git a/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt b/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt\nnew file mode 100644\nindex 000000000000..efb6cd5eae04\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt\n@@ -0,0 +1,57 @@\n+HiSilicon STB PCIE/SATA/USB3 PHY\n+\n+Required properties:\n+- compatible: Should be \"hisilicon,hi3798cv200-combphy\"\n+- reg: Should be the address space for COMBPHY configuration and state\n+ registers in peripheral controller, e.g. PERI_COMBPHY0_CFG and\n+ PERI_COMBPHY0_STATE for COMBPHY0 Hi3798cv200 SoC.\n+- #phy-cells: Should be 1. The cell number is used to select the phy mode\n+ as defined in <dt-bindings/phy/phy.h>.\n+- clocks: The phandle to clock provider and clock specifier pair.\n+- resets: The phandle to reset controller and reset specifier pair.\n+\n+Refer to phy/phy-bindings.txt for the generic PHY binding properties\n+\n+Optional properties:\n+- hisilicon,fixed-mode: If the phy device doesn't support mode select\n+ but a fixed mode setting, the property should be present to specify\n+ the particular mode.\n+- hisilicon,mode-select-bits: If the phy device support mode select,\n+ this property should be present to specify the register bits in\n+ peripheral controller, as a 3 integers tuple:\n+ <register_offset bit_shift bit_mask>.\n+\n+Notes:\n+- Between hisilicon,fixed-mode and hisilicon,mode-select-bits, one and only\n+ one of them should be present.\n+- The device node should be a child of peripheral controller that contains\n+ COMBPHY configuration/state and PERI_CTRL register used to select PHY mode.\n+\n+Examples:\n+\n+perictrl: peripheral-controller@8a20000 {\n+\tcompatible = \"hisilicon,hi3798cv200-perictrl\", \"syscon\",\n+\t\t \"simple-mfd\";\n+\treg = <0x8a20000 0x1000>;\n+\t#address-cells = <1>;\n+\t#size-cells = <1>;\n+\tranges = <0x0 0x8a20000 0x1000>;\n+\n+\tcombphy0: phy@850 {\n+\t\tcompatible = \"hisilicon,hi3798cv200-combphy\";\n+\t\treg = <0x850 0x8>;\n+\t\t#phy-cells = <1>;\n+\t\tclocks = <&crg HISTB_COMBPHY0_CLK>;\n+\t\tresets = <&crg 0x188 4>;\n+\t\thisilicon,fixed-mode = <PHY_TYPE_USB3>;\n+\t};\n+\n+\tcombphy1: phy@858 {\n+\t\tcompatible = \"hisilicon,hi3798cv200-combphy\";\n+\t\treg = <0x858 0x8>;\n+\t\t#phy-cells = <1>;\n+\t\tclocks = <&crg HISTB_COMBPHY1_CLK>;\n+\t\tresets = <&crg 0x188 12>;\n+\t\thisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;\n+\t};\n+};\n", "prefixes": [ "v4", "1/2" ] }