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GET /api/1.2/patches/831029/?format=api
{ "id": 831029, "url": "http://patchwork.ozlabs.org/api/1.2/patches/831029/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1509072544-89012-3-git-send-email-eswierk@skyportsystems.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1509072544-89012-3-git-send-email-eswierk@skyportsystems.com>", "list_archive_url": null, "date": "2017-10-27T02:49:04", "name": "[2/2] e1000e: Add e1000-ng devices", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6b7f500541edf291119d20aa98e78a72e7fa2875", "submitter": { "id": 71296, "url": "http://patchwork.ozlabs.org/api/1.2/people/71296/?format=api", "name": "Andrew S. Rightenburg\" via qemu development", "email": "qemu-devel@nongnu.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1509072544-89012-3-git-send-email-eswierk@skyportsystems.com/mbox/", "series": [ { "id": 10475, "url": "http://patchwork.ozlabs.org/api/1.2/series/10475/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=10475", "date": "2017-10-27T02:49:02", "name": "e1000e: Reimplement e1000 as a variant of e1000e", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/10475/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/831029/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/831029/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=skyportsystems.com header.i=@skyportsystems.com\n\theader.b=\"TxketOb5\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yNSzh5Gxsz9t2h\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 27 Oct 2017 13:50:40 +1100 (AEDT)", "from localhost ([::1]:55516 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1e7ujG-0003g2-SE\n\tfor incoming@patchwork.ozlabs.org; Thu, 26 Oct 2017 22:50:38 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:46827)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <eswierk@skyportsystems.com>) id 1e7uib-0003dk-Dp\n\tfor qemu-devel@nongnu.org; Thu, 26 Oct 2017 22:49:59 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <eswierk@skyportsystems.com>) id 1e7uiY-0002no-9O\n\tfor qemu-devel@nongnu.org; Thu, 26 Oct 2017 22:49:57 -0400", "from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:44087)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <eswierk@skyportsystems.com>)\n\tid 1e7uiY-0002n7-18\n\tfor qemu-devel@nongnu.org; Thu, 26 Oct 2017 22:49:54 -0400", "by mail-pf0-x242.google.com with SMTP id x7so3921848pfa.1\n\tfor <qemu-devel@nongnu.org>; Thu, 26 Oct 2017 19:49:53 -0700 (PDT)", "from localhost.localdomain ([104.153.224.169])\n\tby smtp.gmail.com with ESMTPSA id\n\tu7sm11030522pfh.142.2017.10.26.19.49.44\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tThu, 26 Oct 2017 19:49:52 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=skyportsystems.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=0tUBOYXNuvdq49uDGepeSThnNknZIDHc/X1Ons6zfe4=;\n\tb=TxketOb5hxvSjflAaI9tZhEAZBarizfiAdxhGY9uxHwIWqh8iN22KFhaXI3inv3U8H\n\tgpHA8Rg/BBVF+JGh8XUxAUzI9StV7sLx8L7IUVsYP205un5ak5SlW8t8PHmWPKxGdXX4\n\tPtO1x/Uf7hGDe62+xMkpbpF6KGtayzH6WsSGE=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=0tUBOYXNuvdq49uDGepeSThnNknZIDHc/X1Ons6zfe4=;\n\tb=exYSK5tCs5AnhhDdTnvgkTuaxkzsk9kyAnAVj8JpiFQTf/icVcITroY4ObJ9WsJI3c\n\tfBM7uxDya4HMDxLPB+8adCSu7tI3msbhvm1/zTINZQYzNxB89I/LisMRxKLbqsA48Vxu\n\tKCDd+hQ6aTMEOkRjw+4ghEoy2gyieeXYrFnHXfOQqIJPI9qwgG9PBjIjNvWqqc/a+1jE\n\tDuZz2Owfr7SSxHbUhmq0mXqivLt2zuKrafNpaxXdNbi/k5UTE/CO5icx0zIgqO79A8Pm\n\tg/czRt9+yQH2URPIXhYINeBZnsxvzrwkcZHXNqmNGG0i1rRIV/osYIu0wCYwIRr7efOU\n\tEN1w==", "X-Gm-Message-State": "AMCzsaX0B5WGDMmcnivLqmjpM5ARHa4q1rDOQBpGdBPGVoeIij1lwRNs\n\tmGkKTxQj1VYXl5f/HSdIonAomQ==", "X-Google-Smtp-Source": "ABhQp+THjLU6zhA+8cTlCI472x8JdY1c+Lss1vwMGXxs2dDT6G/ZjMOVIr3xsTcMSaJEb5ZUT3BG1A==", "X-Received": "by 10.98.223.15 with SMTP id u15mr7335190pfg.115.1509072592906; \n\tThu, 26 Oct 2017 19:49:52 -0700 (PDT)", "To": "Ed Swierk <eswierk@skyportsystems.com>,\n\tqemu-devel@nongnu.org", "Date": "Thu, 26 Oct 2017 19:49:04 -0700", "Message-Id": "<1509072544-89012-3-git-send-email-eswierk@skyportsystems.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1509072544-89012-1-git-send-email-eswierk@skyportsystems.com>", "References": "<1509072544-89012-1-git-send-email-eswierk@skyportsystems.com>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c00::242", "Subject": "[Qemu-devel] [PATCH 2/2] e1000e: Add e1000-ng devices", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "From": "Ed Swierk via Qemu-devel <qemu-devel@nongnu.org>", "Reply-To": "Ed Swierk <eswierk@skyportsystems.com>", "Cc": "Dmitry Fleytman <dmitry@daynix.com>,\n\tLeonid Bloch <leonid.bloch@ravellosystems.com>,\n\tJason Wang <jasowang@redhat.com>, Stefan Hajnoczi <stefanha@gmail.com>,\n\tPeter Maydell <peter.maydell@linaro.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Implement e1000-compatible devices using the reworked e1000e code:\n\n- e1000-ng: Intel 82540EM\n- e1000-82544gc-ng: Intel 82544GC\n- e1000-82545em-ng: Intel 82545EM\n\nFrom a guest's perspective, these should be drop-in replacements for\nthe existing e1000 devices.\n\nAmong other deficiencies, this version does not handle migration. But\nit should work well enough to start testing e1000-ng devices with a\nvariety of guest OSes.\n\nSigned-off-by: Ed Swierk <eswierk@skyportsystems.com>\n---\n hw/net/e1000e.c | 50 +++++++++++++++++++++\n hw/net/e1000e_core.c | 120 ++++++++++++++++++++++++++++++++++++++++++++++-----\n hw/net/e1000e_core.h | 12 ++++++\n 3 files changed, 171 insertions(+), 11 deletions(-)", "diff": "diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c\nindex 100979c..5f75a41 100644\n--- a/hw/net/e1000e.c\n+++ b/hw/net/e1000e.c\n@@ -281,6 +281,17 @@ static const uint16_t e1000e_eeprom_template[64] = {\n 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0120, 0xffff, 0x0000,\n };\n \n+static const uint16_t e1000_eeprom_template[64] = {\n+ 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,\n+ 0x3000, 0x1000, 0x6403, 0 /*DevId*/, 0x8086, 0 /*DevId*/, 0x8086, 0x3040,\n+ 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,\n+ 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,\n+ 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,\n+ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+ 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,\n+};\n+\n static void e1000e_core_realize(E1000EState *s)\n {\n s->core.owner = &s->parent_obj;\n@@ -776,6 +787,45 @@ static const E1000EInfo e1000e_devices[] = {\n .eeprom_size = sizeof(e1000e_eeprom_template),\n .phy_id2 = E1000_PHY_ID2_82574x,\n },\n+ {\n+ .name = \"e1000-ng\",\n+ .desc = \"Intel 82540EM Gigabit Ethernet Controller\",\n+ .device_id = E1000_DEV_ID_82540EM,\n+ .revision = 3,\n+ .subsystem_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET,\n+ .subsystem_id = PCI_SUBDEVICE_ID_QEMU,\n+ .is_express = 0,\n+ .romfile = \"efi-e1000.rom\",\n+ .eeprom_templ = e1000_eeprom_template,\n+ .eeprom_size = sizeof(e1000_eeprom_template),\n+ .phy_id2 = E1000_PHY_ID2_8254xx_DEFAULT,\n+ },\n+ {\n+ .name = \"e1000-82544gc-ng\",\n+ .desc = \"Intel 82544GC Gigabit Ethernet Controller\",\n+ .device_id = E1000_DEV_ID_82544GC_COPPER,\n+ .revision = 3,\n+ .subsystem_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET,\n+ .subsystem_id = PCI_SUBDEVICE_ID_QEMU,\n+ .is_express = 0,\n+ .romfile = \"efi-e1000.rom\",\n+ .eeprom_templ = e1000_eeprom_template,\n+ .eeprom_size = sizeof(e1000_eeprom_template),\n+ .phy_id2 = E1000_PHY_ID2_82544x,\n+ },\n+ {\n+ .name = \"e1000-82545em-ng\",\n+ .desc = \"Intel 82545EM Gigabit Ethernet Controller\",\n+ .device_id = E1000_DEV_ID_82545EM_COPPER,\n+ .revision = 3,\n+ .subsystem_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET,\n+ .subsystem_id = PCI_SUBDEVICE_ID_QEMU,\n+ .is_express = 0,\n+ .romfile = \"efi-e1000.rom\",\n+ .eeprom_templ = e1000_eeprom_template,\n+ .eeprom_size = sizeof(e1000_eeprom_template),\n+ .phy_id2 = E1000_PHY_ID2_8254xx_DEFAULT,\n+ },\n };\n \n static void e1000e_register_types(void)\ndiff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c\nindex 959c697..02a60a1 100644\n--- a/hw/net/e1000e_core.c\n+++ b/hw/net/e1000e_core.c\n@@ -2261,6 +2261,24 @@ static const char e1000e_phy_regcap[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = {\n }\n };\n \n+static const char e1000_phy_regcap[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = {\n+ [0] = {\n+ [PHY_CTRL] = PHY_RW,\n+ [PHY_STATUS] = PHY_R,\n+ [PHY_ID1] = PHY_R,\n+ [PHY_ID2] = PHY_R,\n+ [PHY_AUTONEG_ADV] = PHY_RW,\n+ [PHY_LP_ABILITY] = PHY_R,\n+ [PHY_AUTONEG_EXP] = PHY_R,\n+ [PHY_1000T_CTRL] = PHY_RW,\n+ [PHY_1000T_STATUS] = PHY_R,\n+ [M88E1000_PHY_SPEC_CTRL] = PHY_RW,\n+ [M88E1000_PHY_SPEC_STATUS] = PHY_R,\n+ [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,\n+ [M88E1000_RX_ERR_CNTR] = PHY_R,\n+ }\n+};\n+\n static bool\n e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr,\n char cap, uint8_t *page)\n@@ -2616,6 +2634,10 @@ e1000e_mac_icr_read(E1000ECore *core, int index)\n e1000e_clear_ims_bits(core, core->mac[IAM]);\n }\n \n+ if (core->clear_icr_on_read) {\n+ core->mac[ICR] = 0;\n+ }\n+\n trace_e1000e_irq_icr_read_exit(core->mac[ICR]);\n e1000e_update_interrupt_state(core);\n return ret;\n@@ -2732,50 +2754,83 @@ e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val)\n static uint32_t\n e1000e_get_eecd(E1000ECore *core, int index)\n {\n- return e1000e_mac_readreg(core, index);\n+ uint32_t ret = E1000_EECD_PRES | E1000_EECD_GNT | core->eecd_state.old_eecd;\n+\n+ if (!core->eecd_state.reading ||\n+ ((core->eeprom[(core->eecd_state.bitnum_out >> 4) & 0x3f] >>\n+ ((core->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1) {\n+ ret |= E1000_EECD_DO;\n+ }\n+ return ret;\n }\n \n static void\n e1000e_set_eecd(E1000ECore *core, int index, uint32_t val)\n {\n- static const uint32_t ro_bits = E1000_EECD_PRES |\n- E1000_EECD_AUTO_RD |\n- E1000_EECD_SIZE_EX_MASK;\n+ uint32_t oldval = core->eecd_state.old_eecd;\n \n- core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits);\n+ core->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |\n+ E1000_EECD_DI | E1000_EECD_FWE_MASK |\n+ E1000_EECD_REQ);\n+ if (!(E1000_EECD_CS & val)) { /* CS inactive; nothing to do */\n+ return;\n+ }\n+ if (E1000_EECD_CS & (val ^ oldval)) { /* CS rise edge; reset state */\n+ core->eecd_state.val_in = 0;\n+ core->eecd_state.bitnum_in = 0;\n+ core->eecd_state.bitnum_out = 0;\n+ core->eecd_state.reading = 0;\n+ }\n+ if (!(E1000_EECD_SK & (val ^ oldval))) { /* no clock edge */\n+ return;\n+ }\n+ if (!(E1000_EECD_SK & val)) { /* falling edge */\n+ core->eecd_state.bitnum_out++;\n+ return;\n+ }\n+ core->eecd_state.val_in <<= 1;\n+ if (val & E1000_EECD_DI) {\n+ core->eecd_state.val_in |= 1;\n+ }\n+ if (++core->eecd_state.bitnum_in == 9 && !core->eecd_state.reading) {\n+ core->eecd_state.bitnum_out = ((core->eecd_state.val_in & 0x3f)\n+ << 4) - 1;\n+ core->eecd_state.reading = (((core->eecd_state.val_in >> 6) & 7) ==\n+ EEPROM_READ_OPCODE_MICROWIRE);\n+ }\n }\n \n static void\n e1000e_set_eerd(E1000ECore *core, int index, uint32_t val)\n {\n- uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;\n+ uint32_t addr = (val >> core->eerw_addr_shift) & core->eerw_addr_mask;\n uint32_t flags = 0;\n uint32_t data = 0;\n \n if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {\n data = core->eeprom[addr];\n- flags = E1000_EERW_DONE;\n+ flags = core->eerw_done;\n }\n \n core->mac[EERD] = flags |\n- (addr << E1000_EERW_ADDR_SHIFT) |\n+ (addr << core->eerw_addr_shift) |\n (data << E1000_EERW_DATA_SHIFT);\n }\n \n static void\n e1000e_set_eewr(E1000ECore *core, int index, uint32_t val)\n {\n- uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;\n+ uint32_t addr = (val >> core->eerw_addr_shift) & core->eerw_addr_mask;\n uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK;\n uint32_t flags = 0;\n \n if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {\n core->eeprom[addr] = data;\n- flags = E1000_EERW_DONE;\n+ flags = core->eerw_done;\n }\n \n core->mac[EERD] = flags |\n- (addr << E1000_EERW_ADDR_SHIFT) |\n+ (addr << core->eerw_addr_shift) |\n (data << E1000_EERW_DATA_SHIFT);\n }\n \n@@ -3352,6 +3407,36 @@ e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = {\n }\n };\n \n+static const uint16_t\n+e1000_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = {\n+ [0] = {\n+ [PHY_CTRL] = MII_CR_SPEED_SELECT_MSB |\n+ MII_CR_FULL_DUPLEX |\n+ MII_CR_AUTO_NEG_EN,\n+\n+ [PHY_STATUS] = MII_SR_EXTENDED_CAPS |\n+ MII_SR_LINK_STATUS |\n+ MII_SR_AUTONEG_CAPS |\n+ MII_SR_PREAMBLE_SUPPRESS |\n+ MII_SR_EXTENDED_STATUS |\n+ MII_SR_10T_HD_CAPS |\n+ MII_SR_10T_FD_CAPS |\n+ MII_SR_100X_HD_CAPS |\n+ MII_SR_100X_FD_CAPS,\n+\n+ [PHY_ID1] = 0x141,\n+ /* [PHY_ID2] set by e1000e_core_reset() */\n+ [PHY_AUTONEG_ADV] = 0xde1,\n+ [PHY_LP_ABILITY] = 0x1e0,\n+ [PHY_1000T_CTRL] = 0x0e00,\n+ [PHY_1000T_STATUS] = 0x3c00,\n+\n+ [M88E1000_PHY_SPEC_CTRL] = 0x360,\n+ [M88E1000_PHY_SPEC_STATUS] = 0xac00,\n+ [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60,\n+ }\n+};\n+\n static const uint32_t e1000e_mac_reg_init[] = {\n [PBA] = 0x00140014,\n [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18),\n@@ -3408,6 +3493,19 @@ e1000e_core_pci_realize(E1000ECore *core,\n case E1000_PHY_ID2_82574x:\n core->phy_regcap = &e1000e_phy_regcap;\n core->phy_reg_init = &e1000e_phy_reg_init;\n+ core->clear_icr_on_read = false;\n+ core->eerw_done = BIT(1);\n+ core->eerw_addr_shift = 2;\n+ core->eerw_addr_mask = ((1L << 14) - 1);\n+ break;\n+ case E1000_PHY_ID2_8254xx_DEFAULT:\n+ case E1000_PHY_ID2_82544x:\n+ core->phy_regcap = &e1000_phy_regcap;\n+ core->phy_reg_init = &e1000_phy_reg_init;\n+ core->clear_icr_on_read = true;\n+ core->eerw_done = BIT(4);\n+ core->eerw_addr_shift = 8;\n+ core->eerw_addr_mask = ((1L << 8) - 1);\n break;\n default:\n g_assert_not_reached();\ndiff --git a/hw/net/e1000e_core.h b/hw/net/e1000e_core.h\nindex 9ac6f32..f667631 100644\n--- a/hw/net/e1000e_core.h\n+++ b/hw/net/e1000e_core.h\n@@ -59,6 +59,7 @@ struct E1000Core {\n uint16_t phy_id2;\n const char (*phy_regcap)[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE];\n const uint16_t (*phy_reg_init)[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE];\n+ bool clear_icr_on_read;\n \n uint32_t mac[E1000E_MAC_SIZE];\n uint16_t phy[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE];\n@@ -108,6 +109,17 @@ struct E1000Core {\n \n uint8_t permanent_mac[ETH_ALEN];\n \n+ int eerw_done;\n+ int eerw_addr_shift;\n+ int eerw_addr_mask;\n+ struct {\n+ uint32_t val_in; /* shifted in from guest driver */\n+ uint16_t bitnum_in;\n+ uint16_t bitnum_out;\n+ uint16_t reading;\n+ uint32_t old_eecd;\n+ } eecd_state;\n+\n NICState *owner_nic;\n PCIDevice *owner;\n void (*owner_start_recv)(PCIDevice *d);\n", "prefixes": [ "2/2" ] }