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GET /api/1.2/patches/831028/?format=api
{ "id": 831028, "url": "http://patchwork.ozlabs.org/api/1.2/patches/831028/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1509072544-89012-2-git-send-email-eswierk@skyportsystems.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1509072544-89012-2-git-send-email-eswierk@skyportsystems.com>", "list_archive_url": null, "date": "2017-10-27T02:49:03", "name": "[1/2] e1000e: Infrastructure for e1000-ng", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8147d7b05fb56f038c2cd4bdaa682eeac82047e6", "submitter": { "id": 71296, "url": "http://patchwork.ozlabs.org/api/1.2/people/71296/?format=api", "name": "Andrew S. Rightenburg\" via qemu development", "email": "qemu-devel@nongnu.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1509072544-89012-2-git-send-email-eswierk@skyportsystems.com/mbox/", "series": [ { "id": 10475, "url": "http://patchwork.ozlabs.org/api/1.2/series/10475/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=10475", "date": "2017-10-27T02:49:02", "name": "e1000e: Reimplement e1000 as a variant of e1000e", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/10475/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/831028/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/831028/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ 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"from eggs.gnu.org ([2001:4830:134:3::10]:46765)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <eswierk@skyportsystems.com>) id 1e7uiS-0003ZX-0Y\n\tfor qemu-devel@nongnu.org; Thu, 26 Oct 2017 22:49:50 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <eswierk@skyportsystems.com>) id 1e7uiO-0002iO-PK\n\tfor qemu-devel@nongnu.org; Thu, 26 Oct 2017 22:49:48 -0400", "from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:49551)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <eswierk@skyportsystems.com>)\n\tid 1e7uiO-0002i8-G0\n\tfor qemu-devel@nongnu.org; Thu, 26 Oct 2017 22:49:44 -0400", "by mail-pf0-x242.google.com with SMTP id i5so3912848pfe.6\n\tfor <qemu-devel@nongnu.org>; Thu, 26 Oct 2017 19:49:44 -0700 (PDT)", "from localhost.localdomain ([104.153.224.169])\n\tby smtp.gmail.com with ESMTPSA id\n\tu7sm11030522pfh.142.2017.10.26.19.49.32\n\t(version=TLS1_2 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"<1509072544-89012-2-git-send-email-eswierk@skyportsystems.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1509072544-89012-1-git-send-email-eswierk@skyportsystems.com>", "References": "<1509072544-89012-1-git-send-email-eswierk@skyportsystems.com>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c00::242", "Subject": "[Qemu-devel] [PATCH 1/2] e1000e: Infrastructure for e1000-ng", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "From": "Ed Swierk via Qemu-devel <qemu-devel@nongnu.org>", "Reply-To": "Ed Swierk <eswierk@skyportsystems.com>", "Cc": "Dmitry Fleytman <dmitry@daynix.com>,\n\tLeonid Bloch <leonid.bloch@ravellosystems.com>,\n\tJason Wang <jasowang@redhat.com>, Stefan Hajnoczi <stefanha@gmail.com>,\n\tPeter Maydell <peter.maydell@linaro.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Generalize e1000e to support e1000 and other devices with a similar\nregister spec:\n\n- plain PCI instead of PCIe, skipping setup of MSI-X, AER, etc.\n- model-specific PHY ID2, register values and access permissions\n- model-specific EEPROM template and read/write methods\n\nThis is just infrastructure, no functional changes.\n\nSigned-off-by: Ed Swierk <eswierk@skyportsystems.com>\n---\n hw/net/e1000e.c | 186 ++++++++++++++++++++++++++++++++++++---------------\n hw/net/e1000e_core.c | 131 ++++++++++++++++++++----------------\n hw/net/e1000e_core.h | 13 ++--\n 3 files changed, 217 insertions(+), 113 deletions(-)", "diff": "diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c\nindex f1af279..100979c 100644\n--- a/hw/net/e1000e.c\n+++ b/hw/net/e1000e.c\n@@ -49,8 +49,13 @@\n #include \"trace.h\"\n #include \"qapi/error.h\"\n \n-#define TYPE_E1000E \"e1000e\"\n-#define E1000E(obj) OBJECT_CHECK(E1000EState, (obj), TYPE_E1000E)\n+#define TYPE_E1000E_BASE \"e1000e-base\"\n+#define E1000E(obj) \\\n+ OBJECT_CHECK(E1000EState, (obj), TYPE_E1000E_BASE)\n+#define E1000E_DEVICE_CLASS(klass) \\\n+ OBJECT_CLASS_CHECK(E1000EBaseClass, (klass), TYPE_E1000E_BASE)\n+#define E1000E_DEVICE_GET_CLASS(obj) \\\n+ OBJECT_GET_CLASS(E1000EBaseClass, (obj), TYPE_E1000E_BASE)\n \n typedef struct E1000EState {\n PCIDevice parent_obj;\n@@ -76,6 +81,28 @@ typedef struct E1000EState {\n \n } E1000EState;\n \n+typedef struct E1000EInfo {\n+ const char *name;\n+ const char *desc;\n+\n+ uint16_t device_id;\n+ uint8_t revision;\n+ uint16_t subsystem_vendor_id;\n+ uint16_t subsystem_id;\n+ int is_express;\n+ const char *romfile;\n+\n+ const uint16_t *eeprom_templ;\n+ uint32_t eeprom_size;\n+\n+ uint16_t phy_id2;\n+} E1000EInfo;\n+\n+typedef struct E1000EBaseClass {\n+ PCIDeviceClass parent_class;\n+ const E1000EInfo *info;\n+} E1000EBaseClass;\n+\n #define E1000E_MMIO_IDX 0\n #define E1000E_FLASH_IDX 1\n #define E1000E_IO_IDX 2\n@@ -416,7 +443,9 @@ static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp)\n static const uint16_t e1000e_pcie_offset = 0x0E0;\n static const uint16_t e1000e_aer_offset = 0x100;\n static const uint16_t e1000e_dsn_offset = 0x140;\n+ PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);\n E1000EState *s = E1000E(pci_dev);\n+ E1000EBaseClass *edc = E1000E_DEVICE_GET_CLASS(s);\n uint8_t *macaddr;\n int ret;\n \n@@ -427,11 +456,16 @@ static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp)\n pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10;\n pci_dev->config[PCI_INTERRUPT_PIN] = 1;\n \n- pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, s->subsys_ven);\n- pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, s->subsys);\n+ if (s->subsys_ven != (uint16_t)-1) {\n+ pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, s->subsys_ven);\n+ }\n+ if (s->subsys != (uint16_t)-1) {\n+ pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, s->subsys);\n+ }\n \n- s->subsys_ven_used = s->subsys_ven;\n- s->subsys_used = s->subsys;\n+ s->subsys_ven_used = pci_get_word(pci_dev->config\n+ + PCI_SUBSYSTEM_VENDOR_ID);\n+ s->subsys_used = pci_get_word(pci_dev->config + PCI_SUBSYSTEM_ID);\n \n /* Define IO/MMIO regions */\n memory_region_init_io(&s->mmio, OBJECT(s), &mmio_ops, s,\n@@ -453,65 +487,75 @@ static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp)\n pci_register_bar(pci_dev, E1000E_IO_IDX,\n PCI_BASE_ADDRESS_SPACE_IO, &s->io);\n \n- memory_region_init(&s->msix, OBJECT(s), \"e1000e-msix\",\n- E1000E_MSIX_SIZE);\n- pci_register_bar(pci_dev, E1000E_MSIX_IDX,\n- PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix);\n+ if (pc->is_express) {\n+ memory_region_init(&s->msix, OBJECT(s), \"e1000e-msix\",\n+ E1000E_MSIX_SIZE);\n+ pci_register_bar(pci_dev, E1000E_MSIX_IDX,\n+ PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix);\n+ }\n \n /* Create networking backend */\n qemu_macaddr_default_if_unset(&s->conf.macaddr);\n macaddr = s->conf.macaddr.a;\n \n- e1000e_init_msix(s);\n+ if (pc->is_express) {\n+ e1000e_init_msix(s);\n \n- if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) {\n- hw_error(\"Failed to initialize PCIe capability\");\n+ if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) {\n+ hw_error(\"Failed to initialize PCIe capability\");\n+ }\n+\n+ ret = msi_init(PCI_DEVICE(s), 0xD0, 1, true, false, NULL);\n+ if (ret) {\n+ trace_e1000e_msi_init_fail(ret);\n+ }\n+\n+ if (e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset,\n+ PCI_PM_CAP_DSI) < 0) {\n+ hw_error(\"Failed to initialize PM capability\");\n+ }\n+\n+ if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset,\n+ PCI_ERR_SIZEOF, NULL) < 0) {\n+ hw_error(\"Failed to initialize AER capability\");\n+ }\n+\n+ pcie_dev_ser_num_init(pci_dev, e1000e_dsn_offset,\n+ e1000e_gen_dsn(macaddr));\n }\n \n- ret = msi_init(PCI_DEVICE(s), 0xD0, 1, true, false, NULL);\n- if (ret) {\n- trace_e1000e_msi_init_fail(ret);\n- }\n-\n- if (e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset,\n- PCI_PM_CAP_DSI) < 0) {\n- hw_error(\"Failed to initialize PM capability\");\n- }\n-\n- if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset,\n- PCI_ERR_SIZEOF, NULL) < 0) {\n- hw_error(\"Failed to initialize AER capability\");\n- }\n-\n- pcie_dev_ser_num_init(pci_dev, e1000e_dsn_offset,\n- e1000e_gen_dsn(macaddr));\n-\n e1000e_init_net_peer(s, pci_dev, macaddr);\n \n /* Initialize core */\n e1000e_core_realize(s);\n \n e1000e_core_pci_realize(&s->core,\n- e1000e_eeprom_template,\n- sizeof(e1000e_eeprom_template),\n- macaddr);\n+ edc->info->eeprom_templ,\n+ edc->info->eeprom_size,\n+ macaddr,\n+ edc->info->phy_id2);\n }\n \n static void e1000e_pci_uninit(PCIDevice *pci_dev)\n {\n+ PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);\n E1000EState *s = E1000E(pci_dev);\n \n trace_e1000e_cb_pci_uninit();\n \n e1000e_core_pci_uninit(&s->core);\n \n- pcie_aer_exit(pci_dev);\n- pcie_cap_exit(pci_dev);\n+ if (pc->is_express) {\n+ pcie_aer_exit(pci_dev);\n+ pcie_cap_exit(pci_dev);\n+ }\n \n qemu_del_nic(s->nic);\n \n- e1000e_cleanup_msix(s);\n- msi_uninit(pci_dev);\n+ if (pc->is_express) {\n+ e1000e_cleanup_msix(s);\n+ msi_uninit(pci_dev);\n+ }\n }\n \n static void e1000e_qdev_reset(DeviceState *dev)\n@@ -655,10 +699,9 @@ static Property e1000e_properties[] = {\n DEFINE_NIC_PROPERTIES(E1000EState, conf),\n DEFINE_PROP_SIGNED(\"disable_vnet_hdr\", E1000EState, disable_vnet, false,\n e1000e_prop_disable_vnet, bool),\n- DEFINE_PROP_SIGNED(\"subsys_ven\", E1000EState, subsys_ven,\n- PCI_VENDOR_ID_INTEL,\n+ DEFINE_PROP_SIGNED(\"subsys_ven\", E1000EState, subsys_ven, -1,\n e1000e_prop_subsys_ven, uint16_t),\n- DEFINE_PROP_SIGNED(\"subsys\", E1000EState, subsys, 0,\n+ DEFINE_PROP_SIGNED(\"subsys\", E1000EState, subsys, -1,\n e1000e_prop_subsys, uint16_t),\n DEFINE_PROP_END_OF_LIST(),\n };\n@@ -667,21 +710,27 @@ static void e1000e_class_init(ObjectClass *class, void *data)\n {\n DeviceClass *dc = DEVICE_CLASS(class);\n PCIDeviceClass *c = PCI_DEVICE_CLASS(class);\n+ E1000EBaseClass *edc = E1000E_DEVICE_CLASS(class);\n+ const E1000EInfo *info = data;\n \n c->realize = e1000e_pci_realize;\n c->exit = e1000e_pci_uninit;\n c->vendor_id = PCI_VENDOR_ID_INTEL;\n- c->device_id = E1000_DEV_ID_82574L;\n- c->revision = 0;\n- c->romfile = \"efi-e1000e.rom\";\n+ c->device_id = info->device_id;\n+ c->revision = info->revision;\n c->class_id = PCI_CLASS_NETWORK_ETHERNET;\n- c->is_express = 1;\n+ c->subsystem_vendor_id = info->subsystem_vendor_id;\n+ c->subsystem_id = info->subsystem_id;\n+ c->is_express = info->is_express;\n+ c->romfile = info->romfile;\n \n- dc->desc = \"Intel 82574L GbE Controller\";\n+ dc->desc = info->desc;\n dc->reset = e1000e_qdev_reset;\n dc->vmsd = &e1000e_vmstate;\n dc->props = e1000e_properties;\n \n+ edc->info = info;\n+\n e1000e_prop_disable_vnet = qdev_prop_uint8;\n e1000e_prop_disable_vnet.description = \"Do not use virtio headers, \"\n \"perform SW offloads emulation \"\n@@ -704,21 +753,52 @@ static void e1000e_instance_init(Object *obj)\n DEVICE(obj), NULL);\n }\n \n-static const TypeInfo e1000e_info = {\n- .name = TYPE_E1000E,\n+static const TypeInfo e1000e_base_info = {\n+ .name = TYPE_E1000E_BASE,\n .parent = TYPE_PCI_DEVICE,\n .instance_size = sizeof(E1000EState),\n- .class_init = e1000e_class_init,\n .instance_init = e1000e_instance_init,\n- .interfaces = (InterfaceInfo[]) {\n- { INTERFACE_PCIE_DEVICE },\n- { }\n+ .class_size = sizeof(E1000EBaseClass),\n+ .abstract = true,\n+};\n+\n+static const E1000EInfo e1000e_devices[] = {\n+ {\n+ .name = \"e1000e\",\n+ .desc = \"Intel 82574L GbE Controller\",\n+ .device_id = E1000_DEV_ID_82574L,\n+ .revision = 0,\n+ .subsystem_vendor_id = PCI_VENDOR_ID_INTEL,\n+ .subsystem_id = 0,\n+ .is_express = 1,\n+ .romfile = \"efi-e1000e.rom\",\n+ .eeprom_templ = e1000e_eeprom_template,\n+ .eeprom_size = sizeof(e1000e_eeprom_template),\n+ .phy_id2 = E1000_PHY_ID2_82574x,\n },\n };\n \n static void e1000e_register_types(void)\n {\n- type_register_static(&e1000e_info);\n+ int i;\n+\n+ type_register_static(&e1000e_base_info);\n+ for (i = 0; i < ARRAY_SIZE(e1000e_devices); i++) {\n+ const E1000EInfo *info = &e1000e_devices[i];\n+ TypeInfo type_info = {};\n+\n+ type_info.name = info->name;\n+ type_info.parent = TYPE_E1000E_BASE;\n+ type_info.class_data = (void *)info;\n+ type_info.class_init = e1000e_class_init;\n+ type_info.interfaces = (InterfaceInfo[]) {\n+ { info->is_express ? INTERFACE_PCIE_DEVICE\n+ : INTERFACE_CONVENTIONAL_PCI_DEVICE },\n+ { }\n+ };\n+\n+ type_register(&type_info);\n+ }\n }\n \n type_init(e1000e_register_types)\ndiff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c\nindex 43a8d89..959c697 100644\n--- a/hw/net/e1000e_core.c\n+++ b/hw/net/e1000e_core.c\n@@ -2213,7 +2213,7 @@ e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr)\n return index + (mac_reg_access[index] & 0xfffe);\n }\n \n-static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = {\n+static const char e1000e_phy_regcap[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = {\n [0] = {\n [PHY_CTRL] = PHY_ANYPAGE | PHY_RW,\n [PHY_STATUS] = PHY_ANYPAGE | PHY_R,\n@@ -2266,14 +2266,14 @@ e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr,\n char cap, uint8_t *page)\n {\n *page =\n- (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0\n- : core->phy[0][PHY_PAGE];\n+ ((*core->phy_regcap)[0][addr] & PHY_ANYPAGE) ? 0\n+ : core->phy[0][PHY_PAGE];\n \n if (*page >= E1000E_PHY_PAGES) {\n return false;\n }\n \n- return e1000e_phy_regcap[*page][addr] & cap;\n+ return (*core->phy_regcap)[*page][addr] & cap;\n }\n \n static void\n@@ -2729,6 +2729,12 @@ e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val)\n trace_e1000e_mac_set_sw(MAC_ARG(macaddr));\n }\n \n+static uint32_t\n+e1000e_get_eecd(E1000ECore *core, int index)\n+{\n+ return e1000e_mac_readreg(core, index);\n+}\n+\n static void\n e1000e_set_eecd(E1000ECore *core, int index, uint32_t val)\n {\n@@ -3028,6 +3034,7 @@ static uint32_t (*e1000e_macreg_readops[])(E1000ECore *, int) = {\n [TARC1] = e1000e_get_tarc,\n [SWSM] = e1000e_mac_swsm_read,\n [IMS] = e1000e_mac_ims_read,\n+ [EECD] = e1000e_get_eecd,\n \n [CRCERRS ... MPC] = e1000e_mac_readreg,\n [IP6AT ... IP6AT + 3] = e1000e_mac_readreg,\n@@ -3305,56 +3312,6 @@ e1000e_vm_state_change(void *opaque, int running, RunState state)\n }\n }\n \n-void\n-e1000e_core_pci_realize(E1000ECore *core,\n- const uint16_t *eeprom_templ,\n- uint32_t eeprom_size,\n- const uint8_t *macaddr)\n-{\n- int i;\n-\n- core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,\n- e1000e_autoneg_timer, core);\n- e1000e_intrmgr_pci_realize(core);\n-\n- core->vmstate =\n- qemu_add_vm_change_state_handler(e1000e_vm_state_change, core);\n-\n- for (i = 0; i < E1000E_NUM_QUEUES; i++) {\n- net_tx_pkt_init(&core->tx[i].tx_pkt, core->owner,\n- E1000E_MAX_TX_FRAGS, core->has_vnet);\n- }\n-\n- net_rx_pkt_init(&core->rx_pkt, core->has_vnet);\n-\n- e1000x_core_prepare_eeprom(core->eeprom,\n- eeprom_templ,\n- eeprom_size,\n- PCI_DEVICE_GET_CLASS(core->owner)->device_id,\n- macaddr);\n- e1000e_update_rx_offloads(core);\n-}\n-\n-void\n-e1000e_core_pci_uninit(E1000ECore *core)\n-{\n- int i;\n-\n- timer_del(core->autoneg_timer);\n- timer_free(core->autoneg_timer);\n-\n- e1000e_intrmgr_pci_unint(core);\n-\n- qemu_del_vm_change_state_handler(core->vmstate);\n-\n- for (i = 0; i < E1000E_NUM_QUEUES; i++) {\n- net_tx_pkt_reset(core->tx[i].tx_pkt);\n- net_tx_pkt_uninit(core->tx[i].tx_pkt);\n- }\n-\n- net_rx_pkt_uninit(core->rx_pkt);\n-}\n-\n static const uint16_t\n e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = {\n [0] = {\n@@ -3373,7 +3330,7 @@ e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = {\n MII_SR_100X_FD_CAPS,\n \n [PHY_ID1] = 0x141,\n- [PHY_ID2] = E1000_PHY_ID2_82574x,\n+ /* [PHY_ID2] set by e1000e_core_reset() */\n [PHY_AUTONEG_ADV] = 0xde1,\n [PHY_LP_ABILITY] = 0x7e0,\n [PHY_AUTONEG_EXP] = BIT(2),\n@@ -3438,6 +3395,67 @@ static const uint32_t e1000e_mac_reg_init[] = {\n };\n \n void\n+e1000e_core_pci_realize(E1000ECore *core,\n+ const uint16_t *eeprom_templ,\n+ uint32_t eeprom_size,\n+ const uint8_t *macaddr,\n+ uint16_t phy_id2)\n+{\n+ int i;\n+\n+ core->phy_id2 = phy_id2;\n+ switch (phy_id2) {\n+ case E1000_PHY_ID2_82574x:\n+ core->phy_regcap = &e1000e_phy_regcap;\n+ core->phy_reg_init = &e1000e_phy_reg_init;\n+ break;\n+ default:\n+ g_assert_not_reached();\n+ }\n+\n+ core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,\n+ e1000e_autoneg_timer, core);\n+ e1000e_intrmgr_pci_realize(core);\n+\n+ core->vmstate =\n+ qemu_add_vm_change_state_handler(e1000e_vm_state_change, core);\n+\n+ for (i = 0; i < E1000E_NUM_QUEUES; i++) {\n+ net_tx_pkt_init(&core->tx[i].tx_pkt, core->owner,\n+ E1000E_MAX_TX_FRAGS, core->has_vnet);\n+ }\n+\n+ net_rx_pkt_init(&core->rx_pkt, core->has_vnet);\n+\n+ e1000x_core_prepare_eeprom(core->eeprom,\n+ eeprom_templ,\n+ eeprom_size,\n+ PCI_DEVICE_GET_CLASS(core->owner)->device_id,\n+ macaddr);\n+ e1000e_update_rx_offloads(core);\n+}\n+\n+void\n+e1000e_core_pci_uninit(E1000ECore *core)\n+{\n+ int i;\n+\n+ timer_del(core->autoneg_timer);\n+ timer_free(core->autoneg_timer);\n+\n+ e1000e_intrmgr_pci_unint(core);\n+\n+ qemu_del_vm_change_state_handler(core->vmstate);\n+\n+ for (i = 0; i < E1000E_NUM_QUEUES; i++) {\n+ net_tx_pkt_reset(core->tx[i].tx_pkt);\n+ net_tx_pkt_uninit(core->tx[i].tx_pkt);\n+ }\n+\n+ net_rx_pkt_uninit(core->rx_pkt);\n+}\n+\n+void\n e1000e_core_reset(E1000ECore *core)\n {\n int i;\n@@ -3447,7 +3465,8 @@ e1000e_core_reset(E1000ECore *core)\n e1000e_intrmgr_reset(core);\n \n memset(core->phy, 0, sizeof core->phy);\n- memmove(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init);\n+ memmove(core->phy, *core->phy_reg_init, sizeof *core->phy_reg_init);\n+ core->phy[0][PHY_ID2] = core->phy_id2;\n memset(core->mac, 0, sizeof core->mac);\n memmove(core->mac, e1000e_mac_reg_init, sizeof e1000e_mac_reg_init);\n \ndiff --git a/hw/net/e1000e_core.h b/hw/net/e1000e_core.h\nindex 1ff6978..9ac6f32 100644\n--- a/hw/net/e1000e_core.h\n+++ b/hw/net/e1000e_core.h\n@@ -56,6 +56,10 @@ typedef struct E1000IntrDelayTimer_st {\n } E1000IntrDelayTimer;\n \n struct E1000Core {\n+ uint16_t phy_id2;\n+ const char (*phy_regcap)[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE];\n+ const uint16_t (*phy_reg_init)[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE];\n+\n uint32_t mac[E1000E_MAC_SIZE];\n uint16_t phy[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE];\n uint16_t eeprom[E1000E_EEPROM_SIZE];\n@@ -116,10 +120,11 @@ uint64_t\n e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size);\n \n void\n-e1000e_core_pci_realize(E1000ECore *regs,\n- const uint16_t *eeprom_templ,\n- uint32_t eeprom_size,\n- const uint8_t *macaddr);\n+e1000e_core_pci_realize(E1000ECore *regs,\n+ const uint16_t *eeprom_templ,\n+ uint32_t eeprom_size,\n+ const uint8_t *macaddr,\n+ uint16_t phy_id2);\n \n void\n e1000e_core_reset(E1000ECore *core);\n", "prefixes": [ "1/2" ] }