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GET /api/1.2/patches/815544/?format=api
{ "id": 815544, "url": "http://patchwork.ozlabs.org/api/1.2/patches/815544/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/E1duIrT-0008Jm-7r@debutante/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/1.2/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<E1duIrT-0008Jm-7r@debutante>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/E1duIrT-0008Jm-7r@debutante/", "date": "2017-09-19T13:46:51", "name": "Applied \"ASoC: fsl_ssi: Caculate bit clock rate using slot number and width\" to the asoc tree", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "48eaa6b6c74e4b8ac2bdcea3d15fe01f86487189", "submitter": { "id": 24878, "url": "http://patchwork.ozlabs.org/api/1.2/people/24878/?format=api", "name": "Mark Brown", "email": "broonie@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/E1duIrT-0008Jm-7r@debutante/mbox/", "series": [ { "id": 3887, "url": "http://patchwork.ozlabs.org/api/1.2/series/3887/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=3887", "date": "2017-09-19T13:46:51", "name": "Applied \"ASoC: fsl_ssi: Caculate bit clock rate using slot number and width\" to the asoc tree", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/3887/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/815544/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/815544/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxPSv066cz9s7B\n\tfor <patchwork-incoming@ozlabs.org>;\n\tTue, 19 Sep 2017 23:52:31 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xxPSt5hp0zDqZC\n\tfor <patchwork-incoming@ozlabs.org>;\n\tTue, 19 Sep 2017 23:52:30 +1000 (AEST)", "from heliosphere.sirena.org.uk (heliosphere.sirena.org.uk\n\t[IPv6:2a01:7e01::f03c:91ff:fed4:a3b6])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xxPLc1jPZzDqNh\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tTue, 19 Sep 2017 23:47:02 +1000 (AEST)", "from debutante.sirena.org.uk ([2001:470:1f1d:6b5::3]\n\thelo=debutante) by heliosphere.sirena.org.uk with esmtpsa\n\t(TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89)\n\t(envelope-from <broonie@sirena.co.uk>)\n\tid 1duIrT-0001PD-Le; Tue, 19 Sep 2017 13:46:51 +0000", "from broonie by debutante with local (Exim 4.89)\n\t(envelope-from <broonie@sirena.co.uk>)\n\tid 1duIrT-0008Jm-7r; Tue, 19 Sep 2017 14:46:51 +0100" ], "Authentication-Results": [ "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=sirena.org.uk header.i=@sirena.org.uk\n\theader.b=\"Z3MWWmz4\"; dkim-atps=neutral", "lists.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=sirena.org.uk header.i=@sirena.org.uk\n\theader.b=\"Z3MWWmz4\"; dkim-atps=neutral", "ozlabs.org;\n\tspf=neutral (mailfrom) smtp.mailfrom=sirena.co.uk\n\t(client-ip=2a01:7e01::f03c:91ff:fed4:a3b6;\n\thelo=heliosphere.sirena.org.uk; \n\tenvelope-from=broonie@sirena.co.uk; receiver=<UNKNOWN>)", "lists.ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=sirena.org.uk header.i=@sirena.org.uk\n\theader.b=\"Z3MWWmz4\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=sirena.org.uk; s=20170815-heliosphere;\n\th=Date:Message-Id:In-Reply-To:\n\tSubject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type:\n\tContent-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References:\n\tList-Id:List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:\n\tList-Archive; bh=H9Nf1I5xLxc1ZVivW4cmRcT6t92H2je26/GTLx6P3K8=;\n\tb=Z3MWWmz4T3KZ\n\t/5TsrcGh8m3rX0flD6KyxLPr9c1TKn+xseROYBJ0ji8AaUHDKDcr7fgqL+MJ7dsK8UUHx9MzWDEdJ\n\t8IrEb+Fb+1rm5jOmUg7JLzMJbsyCXuF9DRunmRtsOJPoiCdr2o8TM9V6V1vh3aE4C+feJAUF/ua9L\n\tYpc4s=;", "From": "Mark Brown <broonie@kernel.org>", "To": "Nicolin Chen <nicoleotsuka@gmail.com>", "Subject": "Applied \"ASoC: fsl_ssi: Caculate bit clock rate using slot number\n\tand width\" to the asoc tree", "In-Reply-To": "<1505358429-18314-1-git-send-email-nicoleotsuka@gmail.com>", "Message-Id": "<E1duIrT-0008Jm-7r@debutante>", "Date": "Tue, 19 Sep 2017 14:46:51 +0100", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "alsa-devel@alsa-project.org, max.krummenacher@toradex.com,\n\tlgirdwood@gmail.com, linux-kernel@vger.kernel.org,\n\tlinuxppc-dev@lists.ozlabs.org, tiwai@suse.com, caleb@crome.org,\n\ttimur@tabi.org, \n\tbroonie@kernel.org, arnaud.mouiche@invoxia.com, lukma@denx.de,\n\tfabio.estevam@nxp.com, mail@maciej.szmigiero.name", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "The patch\n\n ASoC: fsl_ssi: Caculate bit clock rate using slot number and width\n\nhas been applied to the asoc tree at\n\n git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git \n\nAll being well this means that it will be integrated into the linux-next\ntree (usually sometime in the next 24 hours) and sent to Linus during\nthe next merge window (or sooner if it is a bug fix), however if\nproblems are discovered then the patch may be dropped or reverted. \n\nYou may get further e-mails resulting from automated or manual testing\nand review of the tree, please engage with people reporting problems and\nsend followup patches addressing any issues that are reported if needed.\n\nIf any updates are required or you are submitting further changes they\nshould be sent as incremental updates against current git, existing\npatches will not be replaced.\n\nPlease add any relevant lists and maintainers to the CCs when replying\nto this mail.\n\nThanks,\nMark\n\nFrom b0a7043d5c2ccdd306959f295bf1a62be025cbf5 Mon Sep 17 00:00:00 2001\nFrom: Nicolin Chen <nicoleotsuka@gmail.com>\nDate: Wed, 13 Sep 2017 20:07:09 -0700\nSubject: [PATCH] ASoC: fsl_ssi: Caculate bit clock rate using slot number and\n width\n\nThe set_sysclk() now is used to override the output bit clock rate.\nBut this is not a common way to implement a set_dai_sysclk(). And\nthis creates a problem when a general machine driver (simple-card\nfor example) tries to do set_dai_sysclk() by passing an input clock\nrate for the baud clock instead of setting the bit clock rate as\nfsl_ssi driver expected.\n\nSo this patch solves this problem by firstly removing set_sysclk()\nsince the hw_params() can calculate the bit clock rate. Secondly,\nin order not to break those TDM use cases which previously might\nhave been using set_sysclk() to override the bit clock rate, this\npatch changes the driver to calculate the bit clock rate using the\nslot number and the slot width from the via set_tdm_slot().\n\nThe patch also removes an obsolete comment of the dir parameter.\n\nSigned-off-by: Nicolin Chen <nicoleotsuka@gmail.com>\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n sound/soc/fsl/fsl_ssi.c | 46 ++++++++++++++++++++++++++--------------------\n 1 file changed, 26 insertions(+), 20 deletions(-)", "diff": "diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c\nindex 64598d1183f8..f2f51e06e22c 100644\n--- a/sound/soc/fsl/fsl_ssi.c\n+++ b/sound/soc/fsl/fsl_ssi.c\n@@ -197,12 +197,13 @@ struct fsl_ssi_soc_data {\n * @use_dma: DMA is used or FIQ with stream filter\n * @use_dual_fifo: DMA with support for both FIFOs used\n * @fifo_deph: Depth of the SSI FIFOs\n+ * @slot_width: width of each DAI slot\n+ * @slots: number of slots\n * @rxtx_reg_val: Specific register settings for receive/transmit configuration\n *\n * @clk: SSI clock\n * @baudclk: SSI baud clock for master mode\n * @baudclk_streams: Active streams that are using baudclk\n- * @bitclk_freq: bitclock frequency set by .set_dai_sysclk\n *\n * @dma_params_tx: DMA transmit parameters\n * @dma_params_rx: DMA receive parameters\n@@ -233,12 +234,13 @@ struct fsl_ssi_private {\n \tbool use_dual_fifo;\n \tbool has_ipg_clk_name;\n \tunsigned int fifo_depth;\n+\tunsigned int slot_width;\n+\tunsigned int slots;\n \tstruct fsl_ssi_rxtx_reg_val rxtx_reg_val;\n \n \tstruct clk *clk;\n \tstruct clk *baudclk;\n \tunsigned int baudclk_streams;\n-\tunsigned int bitclk_freq;\n \n \t/* regcache for volatile regs */\n \tu32 regcache_sfcsr;\n@@ -700,8 +702,8 @@ static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,\n * Note: This function can be only called when using SSI as DAI master\n *\n * Quick instruction for parameters:\n- * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels\n- * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.\n+ * freq: Output BCLK frequency = samplerate * slots * slot_width\n+ * (In 2-channel I2S Master mode, slot_width is fixed 32)\n */\n static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,\n \t\tstruct snd_soc_dai *cpu_dai,\n@@ -712,15 +714,21 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,\n \tint synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;\n \tu32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;\n \tunsigned long clkrate, baudrate, tmprate;\n+\tunsigned int slots = params_channels(hw_params);\n+\tunsigned int slot_width = 32;\n \tu64 sub, savesub = 100000;\n \tunsigned int freq;\n \tbool baudclk_is_used;\n \n-\t/* Prefer the explicitly set bitclock frequency */\n-\tif (ssi_private->bitclk_freq)\n-\t\tfreq = ssi_private->bitclk_freq;\n-\telse\n-\t\tfreq = params_channels(hw_params) * 32 * params_rate(hw_params);\n+\t/* Override slots and slot_width if being specifically set... */\n+\tif (ssi_private->slots)\n+\t\tslots = ssi_private->slots;\n+\t/* ...but keep 32 bits if slots is 2 -- I2S Master mode */\n+\tif (ssi_private->slot_width && slots != 2)\n+\t\tslot_width = ssi_private->slot_width;\n+\n+\t/* Generate bit clock based on the slot number and slot width */\n+\tfreq = slots * slot_width * params_rate(hw_params);\n \n \t/* Don't apply it to any non-baudclk circumstance */\n \tif (IS_ERR(ssi_private->baudclk))\n@@ -805,16 +813,6 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,\n \treturn 0;\n }\n \n-static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,\n-\t\tint clk_id, unsigned int freq, int dir)\n-{\n-\tstruct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);\n-\n-\tssi_private->bitclk_freq = freq;\n-\n-\treturn 0;\n-}\n-\n /**\n * fsl_ssi_hw_params - program the sample size\n *\n@@ -1095,6 +1093,12 @@ static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,\n \tstruct regmap *regs = ssi_private->regs;\n \tu32 val;\n \n+\t/* The word length should be 8, 10, 12, 16, 18, 20, 22 or 24 */\n+\tif (slot_width & 1 || slot_width < 8 || slot_width > 24) {\n+\t\tdev_err(cpu_dai->dev, \"invalid slot width: %d\\n\", slot_width);\n+\t\treturn -EINVAL;\n+\t}\n+\n \t/* The slot number should be >= 2 if using Network mode or I2S mode */\n \tregmap_read(regs, CCSR_SSI_SCR, &val);\n \tval &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET;\n@@ -1121,6 +1125,9 @@ static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,\n \n \tregmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val);\n \n+\tssi_private->slot_width = slot_width;\n+\tssi_private->slots = slots;\n+\n \treturn 0;\n }\n \n@@ -1191,7 +1198,6 @@ static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {\n \t.hw_params\t= fsl_ssi_hw_params,\n \t.hw_free\t= fsl_ssi_hw_free,\n \t.set_fmt\t= fsl_ssi_set_dai_fmt,\n-\t.set_sysclk\t= fsl_ssi_set_dai_sysclk,\n \t.set_tdm_slot\t= fsl_ssi_set_dai_tdm_slot,\n \t.trigger\t= fsl_ssi_trigger,\n };\n", "prefixes": [] }