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{
    "id": 814913,
    "url": "http://patchwork.ozlabs.org/api/1.2/patches/814913/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/20170918130408.23114-2-antoine.tenart@free-electrons.com/",
    "project": {
        "id": 7,
        "url": "http://patchwork.ozlabs.org/api/1.2/projects/7/?format=api",
        "name": "Linux network development",
        "link_name": "netdev",
        "list_id": "netdev.vger.kernel.org",
        "list_email": "netdev@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170918130408.23114-2-antoine.tenart@free-electrons.com>",
    "list_archive_url": null,
    "date": "2017-09-18T13:04:06",
    "name": "[net,1/3] net: mvpp2: fix the dma_mask and coherent_dma_mask settings for PPv2.2",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "61a03917e5c46149fab70a4f15c10b0b4eb9d830",
    "submitter": {
        "id": 61603,
        "url": "http://patchwork.ozlabs.org/api/1.2/people/61603/?format=api",
        "name": "Antoine Tenart",
        "email": "antoine.tenart@free-electrons.com"
    },
    "delegate": {
        "id": 34,
        "url": "http://patchwork.ozlabs.org/api/1.2/users/34/?format=api",
        "username": "davem",
        "first_name": "David",
        "last_name": "Miller",
        "email": "davem@davemloft.net"
    },
    "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/20170918130408.23114-2-antoine.tenart@free-electrons.com/mbox/",
    "series": [
        {
            "id": 3642,
            "url": "http://patchwork.ozlabs.org/api/1.2/series/3642/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/netdev/list/?series=3642",
            "date": "2017-09-18T13:04:06",
            "name": "net: mvpp2: various fixes",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/3642/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/814913/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/814913/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<netdev-owner@vger.kernel.org>",
        "X-Original-To": "patchwork-incoming@ozlabs.org",
        "Delivered-To": "patchwork-incoming@ozlabs.org",
        "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)",
        "Received": [
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            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S932574AbdIRNFE (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tMon, 18 Sep 2017 09:05:04 -0400",
            "from mail.free-electrons.com ([62.4.15.54]:35877 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751550AbdIRNFD (ORCPT\n\t<rfc822;netdev@vger.kernel.org>); Mon, 18 Sep 2017 09:05:03 -0400",
            "by mail.free-electrons.com (Postfix, from userid 110)\n\tid 9E7A620E3E; Mon, 18 Sep 2017 15:05:01 +0200 (CEST)",
            "from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 6F03720985;\n\tMon, 18 Sep 2017 15:05:01 +0200 (CEST)"
        ],
        "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com",
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        "X-Spam-Status": "No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0",
        "From": "Antoine Tenart <antoine.tenart@free-electrons.com>",
        "To": "davem@davemloft.net",
        "Cc": "Antoine Tenart <antoine.tenart@free-electrons.com>, andrew@lunn.ch,\n\tgregory.clement@free-electrons.com, thomas.petazzoni@free-electrons.com,\n\tmiquel.raynal@free-electrons.com, nadavh@marvell.com,\n\tlinux@armlinux.org.uk, linux-kernel@vger.kernel.org,\n\tmw@semihalf.com, stefanc@marvell.com, netdev@vger.kernel.org",
        "Subject": "[PATCH net 1/3] net: mvpp2: fix the dma_mask and coherent_dma_mask\n\tsettings for PPv2.2",
        "Date": "Mon, 18 Sep 2017 15:04:06 +0200",
        "Message-Id": "<20170918130408.23114-2-antoine.tenart@free-electrons.com>",
        "X-Mailer": "git-send-email 2.13.5",
        "In-Reply-To": "<20170918130408.23114-1-antoine.tenart@free-electrons.com>",
        "References": "<20170918130408.23114-1-antoine.tenart@free-electrons.com>",
        "Sender": "netdev-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<netdev.vger.kernel.org>",
        "X-Mailing-List": "netdev@vger.kernel.org"
    },
    "content": "The dev->dma_mask usually points to dev->coherent_dma_mask. This is an\nissue as setting both of them will override the other. This is\nproblematic here as the PPv2 driver uses a 32-bit-mask for coherent\naccesses (txq, rxq, bm) and a 40-bit mask for all other accesses due to\nan hardware limitation.\n\nThis can lead to a memory remap for all dma_map_single() calls when\ndealing with memory above 4GB.\n\nFixes: 2067e0a13cfe (\"net: mvpp2: set dma mask and coherent dma mask on PPv2.2\")\nReported-by: Stefan Chulski <stefanc@marvell.com>\nSigned-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>\n---\n drivers/net/ethernet/marvell/mvpp2.c | 16 ++++++++++++++++\n 1 file changed, 16 insertions(+)",
    "diff": "diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c\nindex dd0ee2691c86..7024d4dbb461 100644\n--- a/drivers/net/ethernet/marvell/mvpp2.c\n+++ b/drivers/net/ethernet/marvell/mvpp2.c\n@@ -7969,9 +7969,25 @@ static int mvpp2_probe(struct platform_device *pdev)\n \tpriv->tclk = clk_get_rate(priv->pp_clk);\n \n \tif (priv->hw_version == MVPP22) {\n+\t\t/* If dma_mask points to coherent_dma_mask, setting both will\n+\t\t * override the value of the other. This is problematic as the\n+\t\t * PPv2 driver uses a 32-bit-mask for coherent accesses (txq,\n+\t\t * rxq, bm) and a 40-bit mask for all other accesses.\n+\t\t */\n+\t\tif (pdev->dev.dma_mask == &pdev->dev.coherent_dma_mask) {\n+\t\t\tpdev->dev.dma_mask = devm_kzalloc(&pdev->dev,\n+\t\t\t\t\t\t\t  sizeof(*pdev->dev.dma_mask),\n+\t\t\t\t\t\t\t  GFP_KERNEL);\n+\t\t\tif (!pdev->dev.dma_mask) {\n+\t\t\t\terr = -ENOMEM;\n+\t\t\t\tgoto err_mg_clk;\n+\t\t\t}\n+\t\t}\n+\n \t\terr = dma_set_mask(&pdev->dev, DMA_BIT_MASK(40));\n \t\tif (err)\n \t\t\tgoto err_mg_clk;\n+\n \t\t/* Sadly, the BM pools all share the same register to\n \t\t * store the high 32 bits of their address. So they\n \t\t * must all have the same high 32 bits, which forces\n",
    "prefixes": [
        "net",
        "1/3"
    ]
}