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{
    "id": 814384,
    "url": "http://patchwork.ozlabs.org/api/1.2/patches/814384/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170915191359.28712-5-marek.vasut+renesas@gmail.com/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170915191359.28712-5-marek.vasut+renesas@gmail.com>",
    "list_archive_url": null,
    "date": "2017-09-15T19:13:59",
    "name": "[U-Boot,5/5] ARM: rmobile: Zap Gen3 PFC tables",
    "commit_ref": null,
    "pull_url": null,
    "state": "rejected",
    "archived": false,
    "hash": "577b441e4f2f0b4f016a2e126ac1f5439631b95d",
    "submitter": {
        "id": 1124,
        "url": "http://patchwork.ozlabs.org/api/1.2/people/1124/?format=api",
        "name": "Marek Vasut",
        "email": "marek.vasut@gmail.com"
    },
    "delegate": {
        "id": 1750,
        "url": "http://patchwork.ozlabs.org/api/1.2/users/1750/?format=api",
        "username": "iwamatsu",
        "first_name": "Nobuhiro",
        "last_name": "Iwamatsu",
        "email": "iwamatsu@nigauri.org"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170915191359.28712-5-marek.vasut+renesas@gmail.com/mbox/",
    "series": [
        {
            "id": 3365,
            "url": "http://patchwork.ozlabs.org/api/1.2/series/3365/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=3365",
            "date": "2017-09-15T19:13:58",
            "name": "[U-Boot,1/5] pinctrl: rmobile: Add Renesas RCar pincontrol driver",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/3365/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/814384/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/814384/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Marek Vasut <marek.vasut@gmail.com>",
        "X-Google-Original-From": "Marek Vasut <marek.vasut+renesas@gmail.com>",
        "To": "u-boot@lists.denx.de",
        "Date": "Fri, 15 Sep 2017 21:13:59 +0200",
        "Message-Id": "<20170915191359.28712-5-marek.vasut+renesas@gmail.com>",
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        "X-Mailman-Approved-At": "Fri, 15 Sep 2017 19:22:46 +0000",
        "Cc": "Marek Vasut <marek.vasut+renesas@gmail.com>",
        "Subject": "[U-Boot] [PATCH 5/5] ARM: rmobile: Zap Gen3 PFC tables",
        "X-BeenThere": "u-boot@lists.denx.de",
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        "List-Id": "U-Boot discussion <u-boot.lists.denx.de>",
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    },
    "content": "These old PFC tables are no longer needed as there is now a proper\nPFC pinmux driver in drivers/pinctrl/renesas . Remove them .\n\nSigned-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>\nCc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>\n---\n arch/arm/mach-rmobile/Makefile                    |    4 +-\n arch/arm/mach-rmobile/include/mach/gpio.h         |    6 -\n arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h | 1016 ----\n arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h | 1084 -----\n arch/arm/mach-rmobile/pfc-r8a7795.c               | 5005 --------------------\n arch/arm/mach-rmobile/pfc-r8a7796.c               | 5253 ---------------------\n 6 files changed, 2 insertions(+), 12366 deletions(-)\n delete mode 100644 arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h\n delete mode 100644 arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h\n delete mode 100644 arch/arm/mach-rmobile/pfc-r8a7795.c\n delete mode 100644 arch/arm/mach-rmobile/pfc-r8a7796.c",
    "diff": "diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile\nindex 2aea527bae..8aa2b4f82a 100644\n--- a/arch/arm/mach-rmobile/Makefile\n+++ b/arch/arm/mach-rmobile/Makefile\n@@ -16,7 +16,7 @@ obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o\n obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o\n obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o\n obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o\n-obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7795.o memmap-r8a7795.o\n-obj-$(CONFIG_R8A7796) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7796.o memmap-r8a7796.o\n+obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-r8a7795.o\n+obj-$(CONFIG_R8A7796) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-r8a7796.o\n obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o\n obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o\ndiff --git a/arch/arm/mach-rmobile/include/mach/gpio.h b/arch/arm/mach-rmobile/include/mach/gpio.h\nindex 02b29364c5..448d189e92 100644\n--- a/arch/arm/mach-rmobile/include/mach/gpio.h\n+++ b/arch/arm/mach-rmobile/include/mach/gpio.h\n@@ -22,12 +22,6 @@ void r8a7793_pinmux_init(void);\n #elif defined(CONFIG_R8A7794)\n #include \"r8a7794-gpio.h\"\n void r8a7794_pinmux_init(void);\n-#elif defined(CONFIG_R8A7795)\n-#include \"r8a7795-gpio.h\"\n-void r8a7795_pinmux_init(void);\n-#elif defined(CONFIG_R8A7796)\n-#include \"r8a7796-gpio.h\"\n-void r8a7796_pinmux_init(void);\n #endif\n \n #endif /* __ASM_ARCH_GPIO_H */\ndiff --git a/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h\ndeleted file mode 100644\nindex 554063ab8f..0000000000\n--- a/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h\n+++ /dev/null\n@@ -1,1016 +0,0 @@\n-/*\n- * arch/arm/include/asm/arch-rcar_gen3/r8a7795-gpio.h\n- *\tThis file defines pin function control of gpio.\n- *\n- * Copyright (C) 2015-2016 Renesas Electronics Corporation\n- *\n- * SPDX-License-Identifier:\tGPL-2.0+\n- */\n-#ifndef __ASM_R8A7795_GPIO_H__\n-#define __ASM_R8A7795_GPIO_H__\n-\n-/* Pin Function Controller:\n- * GPIO_FN_xx - GPIO used to select pin function\n- * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU\n- */\n-\n-/* V2(ES2.0) */\n-enum {\n-\tGPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,\n-\tGPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,\n-\tGPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,\n-\tGPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,\n-\n-\tGPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,\n-\tGPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,\n-\tGPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,\n-\tGPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,\n-\tGPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,\n-\tGPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,\n-\tGPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,\n-\tGPIO_GP_1_28,\n-\n-\tGPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,\n-\tGPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,\n-\tGPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,\n-\tGPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14,\n-\n-\tGPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,\n-\tGPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,\n-\tGPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,\n-\tGPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,\n-\n-\tGPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,\n-\tGPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,\n-\tGPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,\n-\tGPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,\n-\tGPIO_GP_4_16, GPIO_GP_4_17,\n-\n-\tGPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,\n-\tGPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,\n-\tGPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,\n-\tGPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,\n-\tGPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,\n-\tGPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,\n-\tGPIO_GP_5_24, GPIO_GP_5_25,\n-\n-\tGPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,\n-\tGPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,\n-\tGPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,\n-\tGPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,\n-\tGPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19,\n-\tGPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23,\n-\tGPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27,\n-\tGPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31,\n-\n-\tGPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3,\n-\n-\t/* GPSR0 */\n-\tGPIO_GFN_D15,\n-\tGPIO_GFN_D14,\n-\tGPIO_GFN_D13,\n-\tGPIO_GFN_D12,\n-\tGPIO_GFN_D11,\n-\tGPIO_GFN_D10,\n-\tGPIO_GFN_D9,\n-\tGPIO_GFN_D8,\n-\tGPIO_GFN_D7,\n-\tGPIO_GFN_D6,\n-\tGPIO_GFN_D5,\n-\tGPIO_GFN_D4,\n-\tGPIO_GFN_D3,\n-\tGPIO_GFN_D2,\n-\tGPIO_GFN_D1,\n-\tGPIO_GFN_D0,\n-\n-\t/* GPSR1 */\n-\tGPIO_GFN_CLKOUT,\n-\tGPIO_GFN_EX_WAIT0_A,\n-\tGPIO_GFN_WE1x,\n-\tGPIO_GFN_WE0x,\n-\tGPIO_GFN_RD_WRx,\n-\tGPIO_GFN_RDx,\n-\tGPIO_GFN_BSx,\n-\tGPIO_GFN_CS1x_A26,\n-\tGPIO_GFN_CS0x,\n-\tGPIO_GFN_A19,\n-\tGPIO_GFN_A18,\n-\tGPIO_GFN_A17,\n-\tGPIO_GFN_A16,\n-\tGPIO_GFN_A15,\n-\tGPIO_GFN_A14,\n-\tGPIO_GFN_A13,\n-\tGPIO_GFN_A12,\n-\tGPIO_GFN_A11,\n-\tGPIO_GFN_A10,\n-\tGPIO_GFN_A9,\n-\tGPIO_GFN_A8,\n-\tGPIO_GFN_A7,\n-\tGPIO_GFN_A6,\n-\tGPIO_GFN_A5,\n-\tGPIO_GFN_A4,\n-\tGPIO_GFN_A3,\n-\tGPIO_GFN_A2,\n-\tGPIO_GFN_A1,\n-\tGPIO_GFN_A0,\n-\n-\t/* GPSR2 */\n-\tGPIO_GFN_AVB_AVTP_CAPTURE_A,\n-\tGPIO_GFN_AVB_AVTP_MATCH_A,\n-\tGPIO_GFN_AVB_LINK,\n-\tGPIO_GFN_AVB_PHY_INT,\n-\tGPIO_GFN_AVB_MAGIC,\n-\tGPIO_GFN_AVB_MDC,\n-\tGPIO_GFN_PWM2_A,\n-\tGPIO_GFN_PWM1_A,\n-\tGPIO_GFN_PWM0,\n-\tGPIO_GFN_IRQ5,\n-\tGPIO_GFN_IRQ4,\n-\tGPIO_GFN_IRQ3,\n-\tGPIO_GFN_IRQ2,\n-\tGPIO_GFN_IRQ1,\n-\tGPIO_GFN_IRQ0,\n-\n-\t/* GPSR3 */\n-\tGPIO_GFN_SD1_WP,\n-\tGPIO_GFN_SD1_CD,\n-\tGPIO_GFN_SD0_WP,\n-\tGPIO_GFN_SD0_CD,\n-\tGPIO_GFN_SD1_DAT3,\n-\tGPIO_GFN_SD1_DAT2,\n-\tGPIO_GFN_SD1_DAT1,\n-\tGPIO_GFN_SD1_DAT0,\n-\tGPIO_GFN_SD1_CMD,\n-\tGPIO_GFN_SD1_CLK,\n-\tGPIO_GFN_SD0_DAT3,\n-\tGPIO_GFN_SD0_DAT2,\n-\tGPIO_GFN_SD0_DAT1,\n-\tGPIO_GFN_SD0_DAT0,\n-\tGPIO_GFN_SD0_CMD,\n-\tGPIO_GFN_SD0_CLK,\n-\n-\t/* GPSR4 */\n-\tGPIO_GFN_SD3_DS,\n-\tGPIO_GFN_SD3_DAT7,\n-\tGPIO_GFN_SD3_DAT6,\n-\tGPIO_GFN_SD3_DAT5,\n-\tGPIO_GFN_SD3_DAT4,\n-\tGPIO_GFN_SD3_DAT3,\n-\tGPIO_GFN_SD3_DAT2,\n-\tGPIO_GFN_SD3_DAT1,\n-\tGPIO_GFN_SD3_DAT0,\n-\tGPIO_GFN_SD3_CMD,\n-\tGPIO_GFN_SD3_CLK,\n-\tGPIO_GFN_SD2_DS,\n-\tGPIO_GFN_SD2_DAT3,\n-\tGPIO_GFN_SD2_DAT2,\n-\tGPIO_GFN_SD2_DAT1,\n-\tGPIO_GFN_SD2_DAT0,\n-\tGPIO_GFN_SD2_CMD,\n-\tGPIO_GFN_SD2_CLK,\n-\n-\t/* GPSR5 */\n-\tGPIO_GFN_MLB_DAT,\n-\tGPIO_GFN_MLB_SIG,\n-\tGPIO_GFN_MLB_CLK,\n-\tGPIO_FN_MSIOF0_RXD,\n-\tGPIO_GFN_MSIOF0_SS2,\n-\tGPIO_FN_MSIOF0_TXD,\n-\tGPIO_GFN_MSIOF0_SS1,\n-\tGPIO_GFN_MSIOF0_SYNC,\n-\tGPIO_FN_MSIOF0_SCK,\n-\tGPIO_GFN_HRTS0x,\n-\tGPIO_GFN_HCTS0x,\n-\tGPIO_GFN_HTX0,\n-\tGPIO_GFN_HRX0,\n-\tGPIO_GFN_HSCK0,\n-\tGPIO_GFN_RX2_A,\n-\tGPIO_GFN_TX2_A,\n-\tGPIO_GFN_SCK2,\n-\tGPIO_GFN_RTS1x_TANS,\n-\tGPIO_GFN_CTS1x,\n-\tGPIO_GFN_TX1_A,\n-\tGPIO_GFN_RX1_A,\n-\tGPIO_GFN_RTS0x_TANS,\n-\tGPIO_GFN_CTS0x,\n-\tGPIO_GFN_TX0,\n-\tGPIO_GFN_RX0,\n-\tGPIO_GFN_SCK0,\n-\n-\t/* GPSR6 */\n-\tGPIO_GFN_USB3_OVC,\n-\tGPIO_GFN_USB3_PWEN,\n-\tGPIO_GFN_USB30_OVC,\n-\tGPIO_GFN_USB30_PWEN,\n-\tGPIO_GFN_USB1_OVC,\n-\tGPIO_GFN_USB1_PWEN,\n-\tGPIO_GFN_USB0_OVC,\n-\tGPIO_GFN_USB0_PWEN,\n-\tGPIO_GFN_AUDIO_CLKB_B,\n-\tGPIO_GFN_AUDIO_CLKA_A,\n-\tGPIO_GFN_SSI_SDATA9_A,\n-\tGPIO_GFN_SSI_SDATA8,\n-\tGPIO_GFN_SSI_SDATA7,\n-\tGPIO_GFN_SSI_WS78,\n-\tGPIO_GFN_SSI_SCK78,\n-\tGPIO_GFN_SSI_SDATA6,\n-\tGPIO_GFN_SSI_WS6,\n-\tGPIO_GFN_SSI_SCK6,\n-\tGPIO_FN_SSI_SDATA5,\n-\tGPIO_FN_SSI_WS5,\n-\tGPIO_FN_SSI_SCK5,\n-\tGPIO_GFN_SSI_SDATA4,\n-\tGPIO_GFN_SSI_WS4,\n-\tGPIO_GFN_SSI_SCK4,\n-\tGPIO_GFN_SSI_SDATA3,\n-\tGPIO_GFN_SSI_WS34,\n-\tGPIO_GFN_SSI_SCK34,\n-\tGPIO_GFN_SSI_SDATA2_A,\n-\tGPIO_GFN_SSI_SDATA1_A,\n-\tGPIO_GFN_SSI_SDATA0,\n-\tGPIO_GFN_SSI_WS01239,\n-\tGPIO_GFN_SSI_SCK01239,\n-\n-\t/* GPSR7 */\n-\tGPIO_FN_HDMI1_CEC,\n-\tGPIO_FN_HDMI0_CEC,\n-\tGPIO_FN_AVS2,\n-\tGPIO_FN_AVS1,\n-\n-\t/* IPSR0 */\n-\tGPIO_IFN_AVB_MDC,\n-\tGPIO_FN_MSIOF2_SS2_C,\n-\tGPIO_IFN_AVB_MAGIC,\n-\tGPIO_FN_MSIOF2_SS1_C,\n-\tGPIO_FN_SCK4_A,\n-\tGPIO_IFN_AVB_PHY_INT,\n-\tGPIO_FN_MSIOF2_SYNC_C,\n-\tGPIO_FN_RX4_A,\n-\tGPIO_IFN_AVB_LINK,\n-\tGPIO_FN_MSIOF2_SCK_C,\n-\tGPIO_FN_TX4_A,\n-\tGPIO_IFN_AVB_AVTP_MATCH_A,\n-\tGPIO_FN_MSIOF2_RXD_C,\n-\tGPIO_FN_CTS4x_A,\n-\tGPIO_FN_FSCLKST2x_A,\n-\tGPIO_IFN_AVB_AVTP_CAPTURE_A,\n-\tGPIO_FN_MSIOF2_TXD_C,\n-\tGPIO_FN_RTS4x_TANS_A,\n-\tGPIO_IFN_IRQ0,\n-\tGPIO_FN_QPOLB,\n-\tGPIO_FN_DU_CDE,\n-\tGPIO_FN_VI4_DATA0_B,\n-\tGPIO_FN_CAN0_TX_B,\n-\tGPIO_FN_CANFD0_TX_B,\n-\tGPIO_FN_MSIOF3_SS2_E,\n-\tGPIO_IFN_IRQ1,\n-\tGPIO_FN_QPOLA,\n-\tGPIO_FN_DU_DISP,\n-\tGPIO_FN_VI4_DATA1_B,\n-\tGPIO_FN_CAN0_RX_B,\n-\tGPIO_FN_CANFD0_RX_B,\n-\tGPIO_FN_MSIOF3_SS1_E,\n-\n-\t/* IPSR1 */\n-\tGPIO_IFN_IRQ2,\n-\tGPIO_FN_QCPV_QDE,\n-\tGPIO_FN_DU_EXODDF_DU_ODDF_DISP_CDE,\n-\tGPIO_FN_VI4_DATA2_B,\n-\tGPIO_FN_MSIOF3_SYNC_E,\n-\tGPIO_FN_PWM3_B,\n-\tGPIO_IFN_IRQ3,\n-\tGPIO_FN_QSTVB_QVE,\n-\tGPIO_FN_A25,\n-\tGPIO_FN_DU_DOTCLKOUT1,\n-\tGPIO_FN_VI4_DATA3_B,\n-\tGPIO_FN_MSIOF3_SCK_E,\n-\tGPIO_FN_PWM4_B,\n-\tGPIO_IFN_IRQ4,\n-\tGPIO_FN_QSTH_QHS,\n-\tGPIO_FN_A24,\n-\tGPIO_FN_DU_EXHSYNC_DU_HSYNC,\n-\tGPIO_FN_VI4_DATA4_B,\n-\tGPIO_FN_MSIOF3_RXD_E,\n-\tGPIO_FN_PWM5_B,\n-\tGPIO_IFN_IRQ5,\n-\tGPIO_FN_QSTB_QHE,\n-\tGPIO_FN_A23,\n-\tGPIO_FN_DU_EXVSYNC_DU_VSYNC,\n-\tGPIO_FN_VI4_DATA5_B,\n-\tGPIO_FN_FSCLKST2x_B,\n-\tGPIO_FN_MSIOF3_TXD_E,\n-\tGPIO_FN_PWM6_B,\n-\tGPIO_IFN_PWM0,\n-\tGPIO_FN_AVB_AVTP_PPS,\n-\tGPIO_FN_VI4_DATA6_B,\n-\tGPIO_FN_IECLK_B,\n-\tGPIO_IFN_PWM1_A,\n-\tGPIO_FN_HRX3_D,\n-\tGPIO_FN_VI4_DATA7_B,\n-\tGPIO_FN_IERX_B,\n-\tGPIO_IFN_PWM2_A,\n-\tGPIO_FN_HTX3_D,\n-\tGPIO_FN_IETX_B,\n-\tGPIO_IFN_A0,\n-\tGPIO_FN_LCDOUT16,\n-\tGPIO_FN_MSIOF3_SYNC_B,\n-\tGPIO_FN_VI4_DATA8,\n-\tGPIO_FN_DU_DB0,\n-\tGPIO_FN_PWM3_A,\n-\n-\t/* IPSR2 */\n-\tGPIO_IFN_A1,\n-\tGPIO_FN_LCDOUT17,\n-\tGPIO_FN_MSIOF3_TXD_B,\n-\tGPIO_FN_VI4_DATA9,\n-\tGPIO_FN_DU_DB1,\n-\tGPIO_FN_PWM4_A,\n-\tGPIO_IFN_A2,\n-\tGPIO_FN_LCDOUT18,\n-\tGPIO_FN_MSIOF3_SCK_B,\n-\tGPIO_FN_VI4_DATA10,\n-\tGPIO_FN_DU_DB2,\n-\tGPIO_FN_PWM5_A,\n-\tGPIO_IFN_A3,\n-\tGPIO_FN_LCDOUT19,\n-\tGPIO_FN_MSIOF3_RXD_B,\n-\tGPIO_FN_VI4_DATA11,\n-\tGPIO_FN_DU_DB3,\n-\tGPIO_FN_PWM6_A,\n-\tGPIO_IFN_A4,\n-\tGPIO_FN_LCDOUT20,\n-\tGPIO_FN_MSIOF3_SS1_B,\n-\tGPIO_FN_VI4_DATA12,\n-\tGPIO_FN_VI5_DATA12,\n-\tGPIO_FN_DU_DB4,\n-\tGPIO_IFN_A5,\n-\tGPIO_FN_LCDOUT21,\n-\tGPIO_FN_MSIOF3_SS2_B,\n-\tGPIO_FN_SCK4_B,\n-\tGPIO_FN_VI4_DATA13,\n-\tGPIO_FN_VI5_DATA13,\n-\tGPIO_FN_DU_DB5,\n-\tGPIO_IFN_A6,\n-\tGPIO_FN_LCDOUT22,\n-\tGPIO_FN_MSIOF2_SS1_A,\n-\tGPIO_FN_RX4_B,\n-\tGPIO_FN_VI4_DATA14,\n-\tGPIO_FN_VI5_DATA14,\n-\tGPIO_FN_DU_DB6,\n-\tGPIO_IFN_A7,\n-\tGPIO_FN_LCDOUT23,\n-\tGPIO_FN_MSIOF2_SS2_A,\n-\tGPIO_FN_TX4_B,\n-\tGPIO_FN_VI4_DATA15,\n-\tGPIO_FN_V15_DATA15,\n-\tGPIO_FN_DU_DB7,\n-\tGPIO_IFN_A8,\n-\tGPIO_FN_RX3_B,\n-\tGPIO_FN_MSIOF2_SYNC_A,\n-\tGPIO_FN_HRX4_B,\n-\tGPIO_FN_SDA6_A,\n-\tGPIO_FN_AVB_AVTP_MATCH_B,\n-\tGPIO_FN_PWM1_B,\n-\n-\t/* IPSR3 */\n-\tGPIO_IFN_A9,\n-\tGPIO_FN_MSIOF2_SCK_A,\n-\tGPIO_FN_CTS4x_B,\n-\tGPIO_FN_VI5_VSYNCx,\n-\tGPIO_IFN_A10,\n-\tGPIO_FN_MSIOF2_RXD_A,\n-\tGPIO_FN_RTS4n_TANS_B,\n-\tGPIO_FN_VI5_HSYNCx,\n-\tGPIO_IFN_A11,\n-\tGPIO_FN_TX3_B,\n-\tGPIO_FN_MSIOF2_TXD_A,\n-\tGPIO_FN_HTX4_B,\n-\tGPIO_FN_HSCK4,\n-\tGPIO_FN_VI5_FIELD,\n-\tGPIO_FN_SCL6_A,\n-\tGPIO_FN_AVB_AVTP_CAPTURE_B,\n-\tGPIO_FN_PWM2_B,\n-\tGPIO_IFN_A12,\n-\tGPIO_FN_LCDOUT12,\n-\tGPIO_FN_MSIOF3_SCK_C,\n-\tGPIO_FN_HRX4_A,\n-\tGPIO_FN_VI5_DATA8,\n-\tGPIO_FN_DU_DG4,\n-\tGPIO_IFN_A13,\n-\tGPIO_FN_LCDOUT13,\n-\tGPIO_FN_MSIOF3_SYNC_C,\n-\tGPIO_FN_HTX4_A,\n-\tGPIO_FN_VI5_DATA9,\n-\tGPIO_FN_DU_DG5,\n-\tGPIO_IFN_A14,\n-\tGPIO_FN_LCDOUT14,\n-\tGPIO_FN_MSIOF3_RXD_C,\n-\tGPIO_FN_HCTS4x,\n-\tGPIO_FN_VI5_DATA10,\n-\tGPIO_FN_DU_DG6,\n-\tGPIO_IFN_A15,\n-\tGPIO_FN_LCDOUT15,\n-\tGPIO_FN_MSIOF3_TXD_C,\n-\tGPIO_FN_HRTS4x,\n-\tGPIO_FN_VI5_DATA11,\n-\tGPIO_FN_DU_DG7,\n-\tGPIO_IFN_A16,\n-\tGPIO_FN_LCDOUT8,\n-\tGPIO_FN_VI4_FIELD,\n-\tGPIO_FN_DU_DG0,\n-\n-\t/* IPSR4 */\n-\tGPIO_IFN_A17,\n-\tGPIO_FN_LCDOUT9,\n-\tGPIO_FN_VI4_VSYNCx,\n-\tGPIO_FN_DU_DG1,\n-\tGPIO_IFN_A18,\n-\tGPIO_FN_LCDOUT10,\n-\tGPIO_FN_VI4_HSYNCx,\n-\tGPIO_FN_DU_DG2,\n-\tGPIO_IFN_A19,\n-\tGPIO_FN_LCDOUT11,\n-\tGPIO_FN_VI4_CLKENB,\n-\tGPIO_FN_DU_DG3,\n-\tGPIO_IFN_CS0x,\n-\tGPIO_FN_VI5_CLKENB,\n-\tGPIO_IFN_CS1x_A26,\n-\tGPIO_FN_VI5_CLK,\n-\tGPIO_FN_EX_WAIT0_B,\n-\tGPIO_IFN_BSx,\n-\tGPIO_FN_QSTVA_QVS,\n-\tGPIO_FN_MSIOF3_SCK_D,\n-\tGPIO_FN_SCK3,\n-\tGPIO_FN_HSCK3,\n-\tGPIO_FN_CAN1_TX,\n-\tGPIO_FN_CANFD1_TX,\n-\tGPIO_FN_IETX_A,\n-\tGPIO_IFN_RDx,\n-\tGPIO_FN_MSIOF3_SYNC_D,\n-\tGPIO_FN_RX3_A,\n-\tGPIO_FN_HRX3_A,\n-\tGPIO_FN_CAN0_TX_A,\n-\tGPIO_FN_CANFD0_TX_A,\n-\tGPIO_IFN_RD_WRx,\n-\tGPIO_FN_MSIOF3_RXD_D,\n-\tGPIO_FN_TX3_A,\n-\tGPIO_FN_HTX3_A,\n-\tGPIO_FN_CAN0_RX_A,\n-\tGPIO_FN_CANFD0_RX_A,\n-\n-\t/* IPSR5 */\n-\tGPIO_IFN_WE0x,\n-\tGPIO_FN_MSIIOF3_TXD_D,\n-\tGPIO_FN_CTS3x,\n-\tGPIO_FN_HCTS3x,\n-\tGPIO_FN_SCL6_B,\n-\tGPIO_FN_CAN_CLK,\n-\tGPIO_FN_IECLK_A,\n-\tGPIO_IFN_WE1x,\n-\tGPIO_FN_MSIOF3_SS1_D,\n-\tGPIO_FN_RTS3x_TANS,\n-\tGPIO_FN_HRTS3x,\n-\tGPIO_FN_SDA6_B,\n-\tGPIO_FN_CAN1_RX,\n-\tGPIO_FN_CANFD1_RX,\n-\tGPIO_FN_IERX_A,\n-\tGPIO_IFN_EX_WAIT0_A,\n-\tGPIO_FN_QCLK,\n-\tGPIO_FN_VI4_CLK,\n-\tGPIO_FN_DU_DOTCLKOUT0,\n-\tGPIO_IFN_D0,\n-\tGPIO_FN_MSIOF2_SS1_B,\n-\tGPIO_FN_MSIOF3_SCK_A,\n-\tGPIO_FN_VI4_DATA16,\n-\tGPIO_FN_VI5_DATA0,\n-\tGPIO_IFN_D1,\n-\tGPIO_FN_MSIOF2_SS2_B,\n-\tGPIO_FN_MSIOF3_SYNC_A,\n-\tGPIO_FN_VI4_DATA17,\n-\tGPIO_FN_VI5_DATA1,\n-\tGPIO_IFN_D2,\n-\tGPIO_FN_MSIOF3_RXD_A,\n-\tGPIO_FN_VI4_DATA18,\n-\tGPIO_FN_VI5_DATA2,\n-\tGPIO_IFN_D3,\n-\tGPIO_FN_MSIOF3_TXD_A,\n-\tGPIO_FN_VI4_DATA19,\n-\tGPIO_FN_VI5_DATA3,\n-\tGPIO_IFN_D4,\n-\tGPIO_FN_MSIOF2_SCK_B,\n-\tGPIO_FN_VI4_DATA20,\n-\tGPIO_FN_VI5_DATA4,\n-\n-\t/* IPSR6 */\n-\tGPIO_IFN_D5,\n-\tGPIO_FN_MSIOF2_SYNC_B,\n-\tGPIO_FN_VI4_DATA21,\n-\tGPIO_FN_VI5_DATA5,\n-\tGPIO_IFN_D6,\n-\tGPIO_FN_MSIOF2_RXD_B,\n-\tGPIO_FN_VI4_DATA22,\n-\tGPIO_FN_VI5_DATA6,\n-\tGPIO_IFN_D7,\n-\tGPIO_FN_MSIOF2_TXD_B,\n-\tGPIO_FN_VI4_DATA23,\n-\tGPIO_FN_VI5_DATA7,\n-\tGPIO_IFN_D8,\n-\tGPIO_FN_LCDOUT0,\n-\tGPIO_FN_MSIOF2_SCK_D,\n-\tGPIO_FN_SCK4_C,\n-\tGPIO_FN_VI4_DATA0_A,\n-\tGPIO_FN_DU_DR0,\n-\tGPIO_IFN_D9,\n-\tGPIO_FN_LCDOUT1,\n-\tGPIO_FN_MSIOF2_SYNC_D,\n-\tGPIO_FN_VI4_DATA1_A,\n-\tGPIO_FN_DU_DR1,\n-\tGPIO_IFN_D10,\n-\tGPIO_FN_LCDOUT2,\n-\tGPIO_FN_MSIOF2_RXD_D,\n-\tGPIO_FN_HRX3_B,\n-\tGPIO_FN_VI4_DATA2_A,\n-\tGPIO_FN_CTS4x_C,\n-\tGPIO_FN_DU_DR2,\n-\tGPIO_IFN_D11,\n-\tGPIO_FN_LCDOUT3,\n-\tGPIO_FN_MSIOF2_TXD_D,\n-\tGPIO_FN_HTX3_B,\n-\tGPIO_FN_VI4_DATA3_A,\n-\tGPIO_FN_RTS4x_TANS_C,\n-\tGPIO_FN_DU_DR3,\n-\tGPIO_IFN_D12,\n-\tGPIO_FN_LCDOUT4,\n-\tGPIO_FN_MSIOF2_SS1_D,\n-\tGPIO_FN_RX4_C,\n-\tGPIO_FN_VI4_DATA4_A,\n-\tGPIO_FN_DU_DR4,\n-\n-\t/* IPSR7 */\n-\tGPIO_IFN_D13,\n-\tGPIO_FN_LCDOUT5,\n-\tGPIO_FN_MSIOF2_SS2_D,\n-\tGPIO_FN_TX4_C,\n-\tGPIO_FN_VI4_DATA5_A,\n-\tGPIO_FN_DU_DR5,\n-\tGPIO_IFN_D14,\n-\tGPIO_FN_LCDOUT6,\n-\tGPIO_FN_MSIOF3_SS1_A,\n-\tGPIO_FN_HRX3_C,\n-\tGPIO_FN_VI4_DATA6_A,\n-\tGPIO_FN_DU_DR6,\n-\tGPIO_FN_SCL6_C,\n-\tGPIO_IFN_D15,\n-\tGPIO_FN_LCDOUT7,\n-\tGPIO_FN_MSIOF3_SS2_A,\n-\tGPIO_FN_HTX3_C,\n-\tGPIO_FN_VI4_DATA7_A,\n-\tGPIO_FN_DU_DR7,\n-\tGPIO_FN_SDA6_C,\n-\tGPIO_FN_FSCLKST,\n-\tGPIO_IFN_SD0_CLK,\n-\tGPIO_FN_MSIOF1_SCK_E,\n-\tGPIO_FN_STP_OPWM_0_B,\n-\tGPIO_IFN_SD0_CMD,\n-\tGPIO_FN_MSIOF1_SYNC_E,\n-\tGPIO_FN_STP_IVCXO27_0_B,\n-\tGPIO_IFN_SD0_DAT0,\n-\tGPIO_FN_MSIOF1_RXD_E,\n-\tGPIO_FN_TS_SCK0_B,\n-\tGPIO_FN_STP_ISCLK_0_B,\n-\tGPIO_IFN_SD0_DAT1,\n-\tGPIO_FN_MSIOF1_TXD_E,\n-\tGPIO_FN_TS_SPSYNC0_B,\n-\tGPIO_FN_STP_ISSYNC_0_B,\n-\n-\t/* IPSR8 */\n-\tGPIO_IFN_SD0_DAT2,\n-\tGPIO_FN_MSIOF1_SS1_E,\n-\tGPIO_FN_TS_SDAT0_B,\n-\tGPIO_FN_STP_ISD_0_B,\n-\tGPIO_IFN_SD0_DAT3,\n-\tGPIO_FN_MSIOF1_SS2_E,\n-\tGPIO_FN_TS_SDEN0_B,\n-\tGPIO_FN_STP_ISEN_0_B,\n-\tGPIO_IFN_SD1_CLK,\n-\tGPIO_FN_MSIOF1_SCK_G,\n-\tGPIO_FN_SIM0_CLK_A,\n-\tGPIO_IFN_SD1_CMD,\n-\tGPIO_FN_MSIOF1_SYNC_G,\n-\tGPIO_FN_NFCEx_B,\n-\tGPIO_FN_SIM0_D_A,\n-\tGPIO_FN_STP_IVCXO27_1_B,\n-\tGPIO_IFN_SD1_DAT0,\n-\tGPIO_FN_SD2_DAT4,\n-\tGPIO_FN_MSIOF1_RXD_G,\n-\tGPIO_FN_NFWPx_B,\n-\tGPIO_FN_TS_SCK1_B,\n-\tGPIO_FN_STP_ISCLK_1_B,\n-\tGPIO_IFN_SD1_DAT1,\n-\tGPIO_FN_SD2_DAT5,\n-\tGPIO_FN_MSIOF1_TXD_G,\n-\tGPIO_FN_NFDATA14_B,\n-\tGPIO_FN_TS_SPSYNC1_B,\n-\tGPIO_FN_STP_ISSYNC_1_B,\n-\tGPIO_IFN_SD1_DAT2,\n-\tGPIO_FN_SD2_DAT6,\n-\tGPIO_FN_MSIOF1_SS1_G,\n-\tGPIO_FN_NFDATA15_B,\n-\tGPIO_FN_TS_SDAT1_B,\n-\tGPIO_FN_STP_IOD_1_B,\n-\tGPIO_IFN_SD1_DAT3,\n-\tGPIO_FN_SD2_DAT7,\n-\tGPIO_FN_MSIOF1_SS2_G,\n-\tGPIO_FN_NFRBx_B,\n-\tGPIO_FN_TS_SDEN1_B,\n-\tGPIO_FN_STP_ISEN_1_B,\n-\n-\t/* IPSR9 */\n-\tGPIO_IFN_SD2_CLK,\n-\tGPIO_FN_NFDATA8,\n-\tGPIO_IFN_SD2_CMD,\n-\tGPIO_FN_NFDATA9,\n-\tGPIO_IFN_SD2_DAT0,\n-\tGPIO_FN_NFDATA10,\n-\tGPIO_IFN_SD2_DAT1,\n-\tGPIO_FN_NFDATA11,\n-\tGPIO_IFN_SD2_DAT2,\n-\tGPIO_FN_NFDATA12,\n-\tGPIO_IFN_SD2_DAT3,\n-\tGPIO_FN_NFDATA13,\n-\tGPIO_IFN_SD2_DS,\n-\tGPIO_FN_NFALE,\n-\tGPIO_FN_SATA_DEVSLP_B,\n-\tGPIO_IFN_SD3_CLK,\n-\tGPIO_FN_NFWEx,\n-\n-\t/* IPSR10 */\n-\tGPIO_IFN_SD3_CMD,\n-\tGPIO_FN_NFREx,\n-\tGPIO_IFN_SD3_DAT0,\n-\tGPIO_FN_NFDATA0,\n-\tGPIO_IFN_SD3_DAT1,\n-\tGPIO_FN_NFDATA1,\n-\tGPIO_IFN_SD3_DAT2,\n-\tGPIO_FN_NFDATA2,\n-\tGPIO_IFN_SD3_DAT3,\n-\tGPIO_FN_NFDATA3,\n-\tGPIO_IFN_SD3_DAT4,\n-\tGPIO_FN_SD2_CD_A,\n-\tGPIO_FN_NFDATA4,\n-\tGPIO_IFN_SD3_DAT5,\n-\tGPIO_FN_SD2_WP_A,\n-\tGPIO_FN_NFDATA5,\n-\tGPIO_IFN_SD3_DAT6,\n-\tGPIO_FN_SD3_CD,\n-\tGPIO_FN_NFDATA6,\n-\n-\t/* IPSR11 */\n-\tGPIO_IFN_SD3_DAT7,\n-\tGPIO_FN_SD3_WP,\n-\tGPIO_FN_NFDATA7,\n-\tGPIO_IFN_SD3_DS,\n-\tGPIO_FN_NFCLE,\n-\tGPIO_IFN_SD0_CD,\n-\tGPIO_FN_NFDATA14_A,\n-\tGPIO_FN_SCL2_B,\n-\tGPIO_FN_SIM0_RST_A,\n-\tGPIO_IFN_SD0_WP,\n-\tGPIO_FN_NFDATA15_A,\n-\tGPIO_FN_SDA2_B,\n-\tGPIO_IFN_SD1_CD,\n-\tGPIO_FN_NFRBx_A,\n-\tGPIO_FN_SIM0_CLK_B,\n-\tGPIO_IFN_SD1_WP,\n-\tGPIO_FN_NFCEx_A,\n-\tGPIO_FN_SIM0_D_B,\n-\tGPIO_IFN_SCK0,\n-\tGPIO_FN_HSCK1_B,\n-\tGPIO_FN_MSIOF1_SS2_B,\n-\tGPIO_FN_AUDIO_CLKC_B,\n-\tGPIO_FN_SDA2_A,\n-\tGPIO_FN_SIM0_RST_B,\n-\tGPIO_FN_STP_OPWM_0_C,\n-\tGPIO_FN_RIF0_CLK_B,\n-\tGPIO_FN_ADICHS2,\n-\tGPIO_FN_SCK5_B,\n-\tGPIO_IFN_RX0,\n-\tGPIO_FN_HRX1_B,\n-\tGPIO_FN_TS_SCK0_C,\n-\tGPIO_FN_STP_ISCLK_0_C,\n-\tGPIO_FN_RIF0_D0_B,\n-\n-\t/* IPSR12 */\n-\tGPIO_IFN_TX0,\n-\tGPIO_FN_HTX1_B,\n-\tGPIO_FN_TS_SPSYNC0_C,\n-\tGPIO_FN_STP_ISSYNC_0_C,\n-\tGPIO_FN_RIF0_D1_B,\n-\tGPIO_IFN_CTS0x,\n-\tGPIO_FN_HCTS1x_B,\n-\tGPIO_FN_MSIOF1_SYNC_B,\n-\tGPIO_FN_TS_SPSYNC1_C,\n-\tGPIO_FN_STP_ISSYNC_1_C,\n-\tGPIO_FN_RIF1_SYNC_B,\n-\tGPIO_FN_AUDIO_CLKOUT_C,\n-\tGPIO_FN_ADICS_SAMP,\n-\tGPIO_IFN_RTS0x_TANS,\n-\tGPIO_FN_HRTS1x_B,\n-\tGPIO_FN_MSIOF1_SS1_B,\n-\tGPIO_FN_AUDIO_CLKA_B,\n-\tGPIO_FN_SCL2_A,\n-\tGPIO_FN_STP_IVCXO27_1_C,\n-\tGPIO_FN_RIF0_SYNC_B,\n-\tGPIO_FN_ADICHS1,\n-\tGPIO_IFN_RX1_A,\n-\tGPIO_FN_HRX1_A,\n-\tGPIO_FN_TS_SDAT0_C,\n-\tGPIO_FN_STP_ISD_0_C,\n-\tGPIO_FN_RIF1_CLK_C,\n-\tGPIO_IFN_TX1_A,\n-\tGPIO_FN_HTX1_A,\n-\tGPIO_FN_TS_SDEN0_C,\n-\tGPIO_FN_STP_ISEN_0_C,\n-\tGPIO_FN_RIF1_D0_C,\n-\tGPIO_IFN_CTS1x,\n-\tGPIO_FN_HCTS1x_A,\n-\tGPIO_FN_MSIOF1_RXD_B,\n-\tGPIO_FN_TS_SDEN1_C,\n-\tGPIO_FN_STP_ISEN_1_C,\n-\tGPIO_FN_RIF1_D0_B,\n-\tGPIO_FN_ADIDATA,\n-\tGPIO_IFN_RTS1x_TANS,\n-\tGPIO_FN_HRTS1x_A,\n-\tGPIO_FN_MSIOF1_TXD_B,\n-\tGPIO_FN_TS_SDAT1_C,\n-\tGPIO_FN_STP_ISD_1_C,\n-\tGPIO_FN_RIF1_D1_B,\n-\tGPIO_FN_ADICHS0,\n-\tGPIO_IFN_SCK2,\n-\tGPIO_FN_SCIF_CLK_B,\n-\tGPIO_FN_MSIOF1_SCK_B,\n-\tGPIO_FN_TS_SCK1_C,\n-\tGPIO_FN_STP_ISCLK_1_C,\n-\tGPIO_FN_RIF1_CLK_B,\n-\tGPIO_FN_ADICLK,\n-\n-\t/* IPSR13 */\n-\tGPIO_IFN_TX2_A,\n-\tGPIO_FN_SD2_CD_B,\n-\tGPIO_FN_SCL1_A,\n-\tGPIO_FN_FMCLK_A,\n-\tGPIO_FN_RIF1_D1_C,\n-\tGPIO_FN_FSO_CFE_0x,\n-\tGPIO_IFN_RX2_A,\n-\tGPIO_FN_SD2_WP_B,\n-\tGPIO_FN_SDA1_A,\n-\tGPIO_FN_FMIN_A,\n-\tGPIO_FN_RIF1_SYNC_C,\n-\tGPIO_FN_FSO_CFE_1x,\n-\tGPIO_IFN_HSCK0,\n-\tGPIO_FN_MSIOF1_SCK_D,\n-\tGPIO_FN_AUDIO_CLKB_A,\n-\tGPIO_FN_SSI_SDATA1_B,\n-\tGPIO_FN_TS_SCK0_D,\n-\tGPIO_FN_STP_ISCLK_0_D,\n-\tGPIO_FN_RIF0_CLK_C,\n-\tGPIO_FN_RX5_B,\n-\tGPIO_IFN_HRX0,\n-\tGPIO_FN_MSIOF1_RXD_D,\n-\tGPIO_FN_SSI_SDATA2_B,\n-\tGPIO_FN_TS_SDEN0_D,\n-\tGPIO_FN_STP_ISEN_0_D,\n-\tGPIO_FN_RIF0_D0_C,\n-\tGPIO_IFN_HTX0,\n-\tGPIO_FN_MSIOF1_TXD_D,\n-\tGPIO_FN_SSI_SDATA9_B,\n-\tGPIO_FN_TS_SDAT0_D,\n-\tGPIO_FN_STP_ISD_0_D,\n-\tGPIO_FN_RIF0_D1_C,\n-\tGPIO_IFN_HCTS0x,\n-\tGPIO_FN_RX2_B,\n-\tGPIO_FN_MSIOF1_SYNC_D,\n-\tGPIO_FN_SSI_SCK9_A,\n-\tGPIO_FN_TS_SPSYNC0_D,\n-\tGPIO_FN_STP_ISSYNC_0_D,\n-\tGPIO_FN_RIF0_SYNC_C,\n-\tGPIO_FN_AUDIO_CLKOUT1_A,\n-\tGPIO_IFN_HRTS0x,\n-\tGPIO_FN_TX2_B,\n-\tGPIO_FN_MSIOF1_SS1_D,\n-\tGPIO_FN_SSI_WS9_A,\n-\tGPIO_FN_STP_IVCXO27_0_D,\n-\tGPIO_FN_BPFCLK_A,\n-\tGPIO_FN_AUDIO_CLKOUT2_A,\n-\tGPIO_IFN_MSIOF0_SYNC,\n-\tGPIO_FN_AUDIO_CLKOUT_A,\n-\tGPIO_FN_TX5_B,\n-\tGPIO_FN_BPFCLK_D,\n-\n-\t/* IPSR14 */\n-\tGPIO_IFN_MSIOF0_SS1,\n-\tGPIO_FN_RX5_A,\n-\tGPIO_FN_NFWPx_A,\n-\tGPIO_FN_AUDIO_CLKA_C,\n-\tGPIO_FN_SSI_SCK2_A,\n-\tGPIO_FN_STP_IVCXO27_0_C,\n-\tGPIO_FN_AUDIO_CLKOUT3_A,\n-\tGPIO_FN_TCLK1_B,\n-\tGPIO_IFN_MSIOF0_SS2,\n-\tGPIO_FN_TX5_A,\n-\tGPIO_FN_MSIOF1_SS2_D,\n-\tGPIO_FN_AUDIO_CLKC_A,\n-\tGPIO_FN_SSI_WS2_A,\n-\tGPIO_FN_STP_OPWM_0_D,\n-\tGPIO_FN_AUDIO_CLKOUT_D,\n-\tGPIO_FN_SPEEDIN_B,\n-\tGPIO_IFN_MLB_CLK,\n-\tGPIO_FN_MSIOF1_SCK_F,\n-\tGPIO_FN_SCL1_B,\n-\tGPIO_IFN_MLB_SIG,\n-\tGPIO_FN_RX1_B,\n-\tGPIO_FN_MSIOF1_SYNC_F,\n-\tGPIO_FN_SDA1_B,\n-\tGPIO_IFN_MLB_DAT,\n-\tGPIO_FN_TX1_B,\n-\tGPIO_FN_MSIOF1_RXD_F,\n-\tGPIO_IFN_SSI_SCK01239,\n-\tGPIO_FN_MSIOF1_TXD_F,\n-\tGPIO_FN_MOUT0,\n-\tGPIO_IFN_SSI_WS01239,\n-\tGPIO_FN_MSIOF1_SS1_F,\n-\tGPIO_FN_MOUT1,\n-\tGPIO_IFN_SSI_SDATA0,\n-\tGPIO_FN_MSIOF1_SS2_F,\n-\tGPIO_FN_MOUT2,\n-\n-\t/* IPSR15 */\n-\tGPIO_IFN_SSI_SDATA1_A,\n-\tGPIO_FN_MOUT5,\n-\tGPIO_IFN_SSI_SDATA2_A,\n-\tGPIO_FN_SSI_SCK1_B,\n-\tGPIO_FN_MOUT6,\n-\tGPIO_IFN_SSI_SCK34,\n-\tGPIO_FN_MSIOF1_SS1_A,\n-\tGPIO_FN_STP_OPWM_0_A,\n-\tGPIO_IFN_SSI_WS34,\n-\tGPIO_FN_HCTS2x_A,\n-\tGPIO_FN_MSIOF1_SS2_A,\n-\tGPIO_FN_STP_IVCXO27_0_A,\n-\tGPIO_IFN_SSI_SDATA3,\n-\tGPIO_FN_HRTS2x_A,\n-\tGPIO_FN_MSIOF1_TXD_A,\n-\tGPIO_FN_TS_SCK0_A,\n-\tGPIO_FN_STP_ISCLK_0_A,\n-\tGPIO_FN_RIF0_D1_A,\n-\tGPIO_FN_RIF2_D0_A,\n-\tGPIO_IFN_SSI_SCK4,\n-\tGPIO_FN_HRX2_A,\n-\tGPIO_FN_MSIOF1_SCK_A,\n-\tGPIO_FN_TS_SDAT0_A,\n-\tGPIO_FN_STP_ISD_0_A,\n-\tGPIO_FN_RIF0_CLK_A,\n-\tGPIO_FN_RIF2_CLK_A,\n-\tGPIO_IFN_SSI_WS4,\n-\tGPIO_FN_HTX2_A,\n-\tGPIO_FN_MSIOF1_SYNC_A,\n-\tGPIO_FN_TS_SDEN0_A,\n-\tGPIO_FN_STP_ISEN_0_A,\n-\tGPIO_FN_RIF0_SYNC_A,\n-\tGPIO_FN_RIF2_SYNC_A,\n-\tGPIO_IFN_SSI_SDATA4,\n-\tGPIO_FN_HSCK2_A,\n-\tGPIO_FN_MSIOF1_RXD_A,\n-\tGPIO_FN_TS_SPSYNC0_A,\n-\tGPIO_FN_STP_ISSYNC_0_A,\n-\tGPIO_FN_RIF0_D0_A,\n-\tGPIO_FN_RIF2_D1_A,\n-\n-\t/* IPSR16 */\n-\tGPIO_IFN_SSI_SCK6,\n-\tGPIO_FN_SIM0_RST_D,\n-\tGPIO_IFN_SSI_WS6,\n-\tGPIO_FN_SIM0_D_D,\n-\tGPIO_IFN_SSI_SDATA6,\n-\tGPIO_FN_SIM0_CLK_D,\n-\tGPIO_FN_SATA_DEVSLP_A,\n-\tGPIO_IFN_SSI_SCK78,\n-\tGPIO_FN_HRX2_B,\n-\tGPIO_FN_MSIOF1_SCK_C,\n-\tGPIO_FN_TS_SCK1_A,\n-\tGPIO_FN_STP_ISCLK_1_A,\n-\tGPIO_FN_RIF1_CLK_A,\n-\tGPIO_FN_RIF3_CLK_A,\n-\tGPIO_IFN_SSI_WS78,\n-\tGPIO_FN_HTX2_B,\n-\tGPIO_FN_MSIOF1_SYNC_C,\n-\tGPIO_FN_TS_SDAT1_A,\n-\tGPIO_FN_STP_ISD_1_A,\n-\tGPIO_FN_RIF1_SYNC_A,\n-\tGPIO_FN_RIF3_SYNC_A,\n-\tGPIO_IFN_SSI_SDATA7,\n-\tGPIO_FN_HCTS2x_B,\n-\tGPIO_FN_MSIOF1_RXD_C,\n-\tGPIO_FN_TS_SDEN1_A,\n-\tGPIO_FN_STP_ISEN_1_A,\n-\tGPIO_FN_RIF1_D0_A,\n-\tGPIO_FN_RIF3_D0_A,\n-\tGPIO_FN_TCLK2_A,\n-\tGPIO_IFN_SSI_SDATA8,\n-\tGPIO_FN_HRTS2x_B,\n-\tGPIO_FN_MSIOF1_TXD_C,\n-\tGPIO_FN_TS_SPSYNC1_A,\n-\tGPIO_FN_STP_ISSYNC_1_A,\n-\tGPIO_FN_RIF1_D1_A,\n-\tGPIO_FN_RIF3_D1_A,\n-\tGPIO_IFN_SSI_SDATA9_A,\n-\tGPIO_FN_HSCK2_B,\n-\tGPIO_FN_MSIOF1_SS1_C,\n-\tGPIO_FN_HSCK1_A,\n-\tGPIO_FN_SSI_WS1_B,\n-\tGPIO_FN_SCK1,\n-\tGPIO_FN_STP_IVCXO27_1_A,\n-\tGPIO_FN_SCK5_A,\n-\n-\t/* IPSR17 */\n-\tGPIO_IFN_AUDIO_CLKA_A,\n-\tGPIO_FN_CC5_OSCOUT,\n-\tGPIO_IFN_AUDIO_CLKB_B,\n-\tGPIO_FN_SCIF_CLK_A,\n-\tGPIO_FN_STP_IVCXO27_1_D,\n-\tGPIO_FN_REMOCON_A,\n-\tGPIO_FN_TCLK1_A,\n-\tGPIO_IFN_USB0_PWEN,\n-\tGPIO_FN_SIM0_RST_C,\n-\tGPIO_FN_TS_SCK1_D,\n-\tGPIO_FN_STP_ISCLK_1_D,\n-\tGPIO_FN_BPFCLK_B,\n-\tGPIO_FN_RIF3_CLK_B,\n-\tGPIO_FN_HSCK2_C,\n-\tGPIO_IFN_USB0_OVC,\n-\tGPIO_FN_SIM0_D_C,\n-\tGPIO_FN_TS_SDAT1_D,\n-\tGPIO_FN_STP_ISD_1_D,\n-\tGPIO_FN_RIF3_SYNC_B,\n-\tGPIO_FN_HRX2_C,\n-\tGPIO_IFN_USB1_PWEN,\n-\tGPIO_FN_SIM0_CLK_C,\n-\tGPIO_FN_SSI_SCK1_A,\n-\tGPIO_FN_TS_SCK0_E,\n-\tGPIO_FN_STP_ISCLK_0_E,\n-\tGPIO_FN_FMCLK_B,\n-\tGPIO_FN_RIF2_CLK_B,\n-\tGPIO_FN_SPEEDIN_A,\n-\tGPIO_FN_HTX2_C,\n-\tGPIO_IFN_USB1_OVC,\n-\tGPIO_FN_MSIOF1_SS2_C,\n-\tGPIO_FN_SSI_WS1_A,\n-\tGPIO_FN_TS_SDAT0_E,\n-\tGPIO_FN_STP_ISD_0_E,\n-\tGPIO_FN_FMIN_B,\n-\tGPIO_FN_RIF2_SYNC_B,\n-\tGPIO_FN_REMOCON_B,\n-\tGPIO_FN_HCTS2x_C,\n-\tGPIO_IFN_USB30_PWEN,\n-\tGPIO_FN_AUDIO_CLKOUT_B,\n-\tGPIO_FN_SSI_SCK2_B,\n-\tGPIO_FN_TS_SDEN1_D,\n-\tGPIO_FN_STP_ISEN_1_D,\n-\tGPIO_FN_STP_OPWM_0_E,\n-\tGPIO_FN_RIF3_D0_B,\n-\tGPIO_FN_TCLK2_B,\n-\tGPIO_FN_TPU0TO0,\n-\tGPIO_FN_BPFCLK_C,\n-\tGPIO_FN_HRTS2x_C,\n-\tGPIO_IFN_USB30_OVC,\n-\tGPIO_FN_AUDIO_CLKOUT1_B,\n-\tGPIO_FN_SSI_WS2_B,\n-\tGPIO_FN_TS_SPSYNC1_D,\n-\tGPIO_FN_STP_ISSYNC_1_D,\n-\tGPIO_FN_STP_IVCXO27_0_E,\n-\tGPIO_FN_RIF3_D1_B,\n-\tGPIO_FN_FSO_TOEx,\n-\tGPIO_FN_TPU0TO1,\n-\n-\t/* IPSR18 */\n-\tGPIO_IFN_USB3_PWEN,\n-\tGPIO_FN_AUDIO_CLKOUT2_B,\n-\tGPIO_FN_SSI_SCK9_B,\n-\tGPIO_FN_TS_SDEN0_E,\n-\tGPIO_FN_STP_ISEN_0_E,\n-\tGPIO_FN_RIF2_D0_B,\n-\tGPIO_FN_TPU0TO2,\n-\tGPIO_FN_FMCLK_C,\n-\tGPIO_FN_FMCLK_D,\n-\tGPIO_IFN_USB3_OVC,\n-\tGPIO_FN_AUDIO_CLKOUT3_B,\n-\tGPIO_FN_SSI_WS9_B,\n-\tGPIO_FN_TS_SPSYNC0_E,\n-\tGPIO_FN_STP_ISSYNC_0_E,\n-\tGPIO_FN_RIF2_D1_B,\n-\tGPIO_FN_TPU0TO3,\n-\tGPIO_FN_FMIN_C,\n-\tGPIO_FN_FMIN_D,\n-};\n-\n-#endif /* __ASM_R8A7795_GPIO_H__ */\ndiff --git a/arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h\ndeleted file mode 100644\nindex 2359e36a14..0000000000\n--- a/arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h\n+++ /dev/null\n@@ -1,1084 +0,0 @@\n-/*\n- * arch/arm/include/asm/arch-rcar_gen3/r8a7796-gpio.h\n- *\tThis file defines pin function control of gpio.\n- *\n- * Copyright (C) 2016 Renesas Electronics Corporation\n- *\n- * SPDX-License-Identifier:\tGPL-2.0+\n- */\n-#ifndef __ASM_R8A7796_GPIO_H__\n-#define __ASM_R8A7796_GPIO_H__\n-\n-/* Pin Function Controller:\n- * GPIO_FN_xx - GPIO used to select pin function\n- * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU\n- */\n-enum {\n-\tGPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,\n-\tGPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,\n-\tGPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,\n-\tGPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,\n-\n-\tGPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,\n-\tGPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,\n-\tGPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,\n-\tGPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,\n-\tGPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,\n-\tGPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,\n-\tGPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,\n-\tGPIO_GP_1_28,\n-\n-\tGPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,\n-\tGPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,\n-\tGPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,\n-\tGPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14,\n-\n-\tGPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,\n-\tGPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,\n-\tGPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,\n-\tGPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,\n-\n-\tGPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,\n-\tGPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,\n-\tGPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,\n-\tGPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,\n-\tGPIO_GP_4_16, GPIO_GP_4_17,\n-\n-\tGPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,\n-\tGPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,\n-\tGPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,\n-\tGPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,\n-\tGPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,\n-\tGPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,\n-\tGPIO_GP_5_24, GPIO_GP_5_25,\n-\n-\tGPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,\n-\tGPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,\n-\tGPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,\n-\tGPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,\n-\tGPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19,\n-\tGPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23,\n-\tGPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27,\n-\tGPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31,\n-\n-\tGPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3,\n-\n-\t/* GPSR0 */\n-\tGPIO_GFN_D15,\n-\tGPIO_GFN_D14,\n-\tGPIO_GFN_D13,\n-\tGPIO_GFN_D12,\n-\tGPIO_GFN_D11,\n-\tGPIO_GFN_D10,\n-\tGPIO_GFN_D9,\n-\tGPIO_GFN_D8,\n-\tGPIO_GFN_D7,\n-\tGPIO_GFN_D6,\n-\tGPIO_GFN_D5,\n-\tGPIO_GFN_D4,\n-\tGPIO_GFN_D3,\n-\tGPIO_GFN_D2,\n-\tGPIO_GFN_D1,\n-\tGPIO_GFN_D0,\n-\n-\t/* GPSR1 */\n-\tGPIO_GFN_CLKOUT,\n-\tGPIO_GFN_EX_WAIT0_A,\n-\tGPIO_GFN_WE1x,\n-\tGPIO_GFN_WE0x,\n-\tGPIO_GFN_RD_WRx,\n-\tGPIO_GFN_RDx,\n-\tGPIO_GFN_BSx,\n-\tGPIO_GFN_CS1x_A26,\n-\tGPIO_GFN_CS0x,\n-\tGPIO_GFN_A19,\n-\tGPIO_GFN_A18,\n-\tGPIO_GFN_A17,\n-\tGPIO_GFN_A16,\n-\tGPIO_GFN_A15,\n-\tGPIO_GFN_A14,\n-\tGPIO_GFN_A13,\n-\tGPIO_GFN_A12,\n-\tGPIO_GFN_A11,\n-\tGPIO_GFN_A10,\n-\tGPIO_GFN_A9,\n-\tGPIO_GFN_A8,\n-\tGPIO_GFN_A7,\n-\tGPIO_GFN_A6,\n-\tGPIO_GFN_A5,\n-\tGPIO_GFN_A4,\n-\tGPIO_GFN_A3,\n-\tGPIO_GFN_A2,\n-\tGPIO_GFN_A1,\n-\tGPIO_GFN_A0,\n-\n-\t/* GPSR2 */\n-\tGPIO_GFN_AVB_AVTP_CAPTURE_A,\n-\tGPIO_GFN_AVB_AVTP_MATCH_A,\n-\tGPIO_GFN_AVB_LINK,\n-\tGPIO_GFN_AVB_PHY_INT,\n-\tGPIO_GFN_AVB_MAGIC,\n-\tGPIO_GFN_AVB_MDC,\n-\tGPIO_GFN_PWM2_A,\n-\tGPIO_GFN_PWM1_A,\n-\tGPIO_GFN_PWM0,\n-\tGPIO_GFN_IRQ5,\n-\tGPIO_GFN_IRQ4,\n-\tGPIO_GFN_IRQ3,\n-\tGPIO_GFN_IRQ2,\n-\tGPIO_GFN_IRQ1,\n-\tGPIO_GFN_IRQ0,\n-\n-\t/* GPSR3 */\n-\tGPIO_GFN_SD1_WP,\n-\tGPIO_GFN_SD1_CD,\n-\tGPIO_GFN_SD0_WP,\n-\tGPIO_GFN_SD0_CD,\n-\tGPIO_GFN_SD1_DAT3,\n-\tGPIO_GFN_SD1_DAT2,\n-\tGPIO_GFN_SD1_DAT1,\n-\tGPIO_GFN_SD1_DAT0,\n-\tGPIO_GFN_SD1_CMD,\n-\tGPIO_GFN_SD1_CLK,\n-\tGPIO_GFN_SD0_DAT3,\n-\tGPIO_GFN_SD0_DAT2,\n-\tGPIO_GFN_SD0_DAT1,\n-\tGPIO_GFN_SD0_DAT0,\n-\tGPIO_GFN_SD0_CMD,\n-\tGPIO_GFN_SD0_CLK,\n-\n-\t/* GPSR4 */\n-\tGPIO_GFN_SD3_DS,\n-\tGPIO_GFN_SD3_DAT7,\n-\tGPIO_GFN_SD3_DAT6,\n-\tGPIO_GFN_SD3_DAT5,\n-\tGPIO_GFN_SD3_DAT4,\n-\tGPIO_FN_SD3_DAT3,\n-\tGPIO_FN_SD3_DAT2,\n-\tGPIO_FN_SD3_DAT1,\n-\tGPIO_FN_SD3_DAT0,\n-\tGPIO_FN_SD3_CMD,\n-\tGPIO_FN_SD3_CLK,\n-\tGPIO_GFN_SD2_DS,\n-\tGPIO_GFN_SD2_DAT3,\n-\tGPIO_GFN_SD2_DAT2,\n-\tGPIO_GFN_SD2_DAT1,\n-\tGPIO_GFN_SD2_DAT0,\n-\tGPIO_FN_SD2_CMD,\n-\tGPIO_GFN_SD2_CLK,\n-\n-\t/* GPSR5 */\n-\tGPIO_GFN_MLB_DAT,\n-\tGPIO_GFN_MLB_SIG,\n-\tGPIO_GFN_MLB_CLK,\n-\tGPIO_FN_MSIOF0_RXD,\n-\tGPIO_GFN_MSIOF0_SS2,\n-\tGPIO_FN_MSIOF0_TXD,\n-\tGPIO_GFN_MSIOF0_SS1,\n-\tGPIO_GFN_MSIOF0_SYNC,\n-\tGPIO_FN_MSIOF0_SCK,\n-\tGPIO_GFN_HRTS0x,\n-\tGPIO_GFN_HCTS0x,\n-\tGPIO_GFN_HTX0,\n-\tGPIO_GFN_HRX0,\n-\tGPIO_GFN_HSCK0,\n-\tGPIO_GFN_RX2_A,\n-\tGPIO_GFN_TX2_A,\n-\tGPIO_GFN_SCK2,\n-\tGPIO_GFN_RTS1x_TANS,\n-\tGPIO_GFN_CTS1x,\n-\tGPIO_GFN_TX1_A,\n-\tGPIO_GFN_RX1_A,\n-\tGPIO_GFN_RTS0x_TANS,\n-\tGPIO_GFN_CTS0x,\n-\tGPIO_GFN_TX0,\n-\tGPIO_GFN_RX0,\n-\tGPIO_GFN_SCK0,\n-\n-\t/* GPSR6 */\n-\tGPIO_GFN_GP6_31,\n-\tGPIO_GFN_GP6_30,\n-\tGPIO_GFN_USB30_OVC,\n-\tGPIO_GFN_USB30_PWEN,\n-\tGPIO_GFN_USB1_OVC,\n-\tGPIO_GFN_USB1_PWEN,\n-\tGPIO_GFN_USB0_OVC,\n-\tGPIO_GFN_USB0_PWEN,\n-\tGPIO_GFN_AUDIO_CLKB_B,\n-\tGPIO_GFN_AUDIO_CLKA_A,\n-\tGPIO_GFN_SSI_SDATA9_A,\n-\tGPIO_GFN_SSI_SDATA8,\n-\tGPIO_GFN_SSI_SDATA7,\n-\tGPIO_GFN_SSI_WS78,\n-\tGPIO_GFN_SSI_SCK78,\n-\tGPIO_GFN_SSI_SDATA6,\n-\tGPIO_GFN_SSI_WS6,\n-\tGPIO_GFN_SSI_SCK6,\n-\tGPIO_FN_SSI_SDATA5,\n-\tGPIO_FN_SSI_WS5,\n-\tGPIO_FN_SSI_SCK5,\n-\tGPIO_GFN_SSI_SDATA4,\n-\tGPIO_GFN_SSI_WS4,\n-\tGPIO_GFN_SSI_SCK4,\n-\tGPIO_GFN_SSI_SDATA3,\n-\tGPIO_GFN_SSI_WS34,\n-\tGPIO_GFN_SSI_SCK34,\n-\tGPIO_GFN_SSI_SDATA2_A,\n-\tGPIO_GFN_SSI_SDATA1_A,\n-\tGPIO_GFN_SSI_SDATA0,\n-\tGPIO_GFN_SSI_WS01239,\n-\tGPIO_GFN_SSI_SCK01239,\n-\n-\t/* GPSR7 */\n-\tGPIO_FN_HDMI1_CEC,\n-\tGPIO_FN_HDMI0_CEC,\n-\tGPIO_FN_AVS2,\n-\tGPIO_FN_AVS1,\n-\n-\t/* IPSR0 */\n-\tGPIO_IFN_AVB_MDC,\n-\tGPIO_FN_MSIOF2_SS2_C,\n-\tGPIO_IFN_AVB_MAGIC,\n-\tGPIO_FN_MSIOF2_SS1_C,\n-\tGPIO_FN_SCK4_A,\n-\tGPIO_IFN_AVB_PHY_INT,\n-\tGPIO_FN_MSIOF2_SYNC_C,\n-\tGPIO_FN_RX4_A,\n-\tGPIO_IFN_AVB_LINK,\n-\tGPIO_FN_MSIOF2_SCK_C,\n-\tGPIO_FN_TX4_A,\n-\tGPIO_IFN_AVB_AVTP_MATCH_A,\n-\tGPIO_FN_MSIOF2_RXD_C,\n-\tGPIO_FN_CTS4x_A,\n-\tGPIO_IFN_AVB_AVTP_CAPTURE_A,\n-\tGPIO_FN_MSIOF2_TXD_C,\n-\tGPIO_FN_RTS4x_TANS_A,\n-\tGPIO_IFN_IRQ0,\n-\tGPIO_FN_QPOLB,\n-\tGPIO_FN_DU_CDE,\n-\tGPIO_FN_VI4_DATA0_B,\n-\tGPIO_FN_CAN0_TX_B,\n-\tGPIO_FN_CANFD0_TX_B,\n-\tGPIO_FN_MSIOF3_SS2_E,\n-\tGPIO_IFN_IRQ1,\n-\tGPIO_FN_QPOLA,\n-\tGPIO_FN_DU_DISP,\n-\tGPIO_FN_VI4_DATA1_B,\n-\tGPIO_FN_CAN0_RX_B,\n-\tGPIO_FN_CANFD0_RX_B,\n-\tGPIO_FN_MSIOF3_SS1_E,\n-\n-\t/* IPSR1 */\n-\tGPIO_IFN_IRQ2,\n-\tGPIO_FN_QCPV_QDE,\n-\tGPIO_FN_DU_EXODDF_DU_ODDF_DISP_CDE,\n-\tGPIO_FN_VI4_DATA2_B,\n-\tGPIO_FN_MSIOF3_SYNC_E,\n-\tGPIO_FN_PWM3_B,\n-\tGPIO_IFN_IRQ3,\n-\tGPIO_FN_QSTVB_QVE,\n-\tGPIO_FN_DU_DOTCLKOUT1,\n-\tGPIO_FN_VI4_DATA3_B,\n-\tGPIO_FN_MSIOF3_SCK_E,\n-\tGPIO_FN_PWM4_B,\n-\tGPIO_IFN_IRQ4,\n-\tGPIO_FN_QSTH_QHS,\n-\tGPIO_FN_DU_EXHSYNC_DU_HSYNC,\n-\tGPIO_FN_VI4_DATA4_B,\n-\tGPIO_FN_MSIOF3_RXD_E,\n-\tGPIO_FN_PWM5_B,\n-\tGPIO_IFN_IRQ5,\n-\tGPIO_FN_QSTB_QHE,\n-\tGPIO_FN_DU_EXVSYNC_DU_VSYNC,\n-\tGPIO_FN_VI4_DATA5_B,\n-\tGPIO_FN_MSIOF3_TXD_E,\n-\tGPIO_FN_PWM6_B,\n-\tGPIO_IFN_PWM0,\n-\tGPIO_FN_AVB_AVTP_PPS,\n-\tGPIO_FN_VI4_DATA6_B,\n-\tGPIO_FN_IECLK_B,\n-\tGPIO_IFN_PWM1_A,\n-\tGPIO_FN_HRX3_D,\n-\tGPIO_FN_VI4_DATA7_B,\n-\tGPIO_FN_IERX_B,\n-\tGPIO_IFN_PWM2_A,\n-\tGPIO_FN_PWMFSW0,\n-\tGPIO_FN_HTX3_D,\n-\tGPIO_FN_IETX_B,\n-\tGPIO_IFN_A0,\n-\tGPIO_FN_LCDOUT16,\n-\tGPIO_FN_MSIOF3_SYNC_B,\n-\tGPIO_FN_VI4_DATA8,\n-\tGPIO_FN_DU_DB0,\n-\tGPIO_FN_PWM3_A,\n-\n-\t/* IPSR2 */\n-\tGPIO_IFN_A1,\n-\tGPIO_FN_LCDOUT17,\n-\tGPIO_FN_MSIOF3_TXD_B,\n-\tGPIO_FN_VI4_DATA9,\n-\tGPIO_FN_DU_DB1,\n-\tGPIO_FN_PWM4_A,\n-\tGPIO_IFN_A2,\n-\tGPIO_FN_LCDOUT18,\n-\tGPIO_FN_MSIOF3_SCK_B,\n-\tGPIO_FN_VI4_DATA10,\n-\tGPIO_FN_DU_DB2,\n-\tGPIO_FN_PWM5_A,\n-\tGPIO_IFN_A3,\n-\tGPIO_FN_LCDOUT19,\n-\tGPIO_FN_MSIOF3_RXD_B,\n-\tGPIO_FN_VI4_DATA11,\n-\tGPIO_FN_DU_DB3,\n-\tGPIO_FN_PWM6_A,\n-\tGPIO_IFN_A4,\n-\tGPIO_FN_LCDOUT20,\n-\tGPIO_FN_MSIOF3_SS1_B,\n-\tGPIO_FN_VI4_DATA12,\n-\tGPIO_FN_VI5_DATA12,\n-\tGPIO_FN_DU_DB4,\n-\tGPIO_IFN_A5,\n-\tGPIO_FN_LCDOUT21,\n-\tGPIO_FN_MSIOF3_SS2_B,\n-\tGPIO_FN_SCK4_B,\n-\tGPIO_FN_VI4_DATA13,\n-\tGPIO_FN_VI5_DATA13,\n-\tGPIO_FN_DU_DB5,\n-\tGPIO_IFN_A6,\n-\tGPIO_FN_LCDOUT22,\n-\tGPIO_FN_MSIOF2_SS1_A,\n-\tGPIO_FN_RX4_B,\n-\tGPIO_FN_VI4_DATA14,\n-\tGPIO_FN_VI5_DATA14,\n-\tGPIO_FN_DU_DB6,\n-\tGPIO_IFN_A7,\n-\tGPIO_FN_LCDOUT23,\n-\tGPIO_FN_MSIOF2_SS2_A,\n-\tGPIO_FN_TX4_B,\n-\tGPIO_FN_VI4_DATA15,\n-\tGPIO_FN_V15_DATA15,\n-\tGPIO_FN_DU_DB7,\n-\tGPIO_IFN_A8,\n-\tGPIO_FN_RX3_B,\n-\tGPIO_FN_MSIOF2_SYNC_A,\n-\tGPIO_FN_HRX4_B,\n-\tGPIO_FN_SDA6_A,\n-\tGPIO_FN_AVB_AVTP_MATCH_B,\n-\tGPIO_FN_PWM1_B,\n-\n-\t/* IPSR3 */\n-\tGPIO_IFN_A9,\n-\tGPIO_FN_MSIOF2_SCK_A,\n-\tGPIO_FN_CTS4x_B,\n-\tGPIO_FN_VI5_VSYNCx,\n-\tGPIO_IFN_A10,\n-\tGPIO_FN_MSIOF2_RXD_A,\n-\tGPIO_FN_RTS4n_TANS_B,\n-\tGPIO_FN_VI5_HSYNCx,\n-\tGPIO_IFN_A11,\n-\tGPIO_FN_TX3_B,\n-\tGPIO_FN_MSIOF2_TXD_A,\n-\tGPIO_FN_HTX4_B,\n-\tGPIO_FN_HSCK4,\n-\tGPIO_FN_VI5_FIELD,\n-\tGPIO_FN_SCL6_A,\n-\tGPIO_FN_AVB_AVTP_CAPTURE_B,\n-\tGPIO_FN_PWM2_B,\n-\tGPIO_FN_SPV_EVEN,\n-\tGPIO_IFN_A12,\n-\tGPIO_FN_LCDOUT12,\n-\tGPIO_FN_MSIOF3_SCK_C,\n-\tGPIO_FN_HRX4_A,\n-\tGPIO_FN_VI5_DATA8,\n-\tGPIO_FN_DU_DG4,\n-\tGPIO_IFN_A13,\n-\tGPIO_FN_LCDOUT13,\n-\tGPIO_FN_MSIOF3_SYNC_C,\n-\tGPIO_FN_HTX4_A,\n-\tGPIO_FN_VI5_DATA9,\n-\tGPIO_FN_DU_DG5,\n-\tGPIO_IFN_A14,\n-\tGPIO_FN_LCDOUT14,\n-\tGPIO_FN_MSIOF3_RXD_C,\n-\tGPIO_FN_HCTS4x,\n-\tGPIO_FN_VI5_DATA10,\n-\tGPIO_FN_DU_DG6,\n-\tGPIO_IFN_A15,\n-\tGPIO_FN_LCDOUT15,\n-\tGPIO_FN_MSIOF3_TXD_C,\n-\tGPIO_FN_HRTS4x,\n-\tGPIO_FN_VI5_DATA11,\n-\tGPIO_FN_DU_DG7,\n-\tGPIO_IFN_A16,\n-\tGPIO_FN_LCDOUT8,\n-\tGPIO_FN_VI4_FIELD,\n-\tGPIO_FN_DU_DG0,\n-\n-\t/* IPSR4 */\n-\tGPIO_IFN_A17,\n-\tGPIO_FN_LCDOUT9,\n-\tGPIO_FN_VI4_VSYNCx,\n-\tGPIO_FN_DU_DG1,\n-\tGPIO_IFN_A18,\n-\tGPIO_FN_LCDOUT10,\n-\tGPIO_FN_VI4_HSYNCx,\n-\tGPIO_FN_DU_DG2,\n-\tGPIO_IFN_A19,\n-\tGPIO_FN_LCDOUT11,\n-\tGPIO_FN_VI4_CLKENB,\n-\tGPIO_FN_DU_DG3,\n-\tGPIO_IFN_CS0x,\n-\tGPIO_FN_VI5_CLKENB,\n-\tGPIO_IFN_CS1x_A26,\n-\tGPIO_FN_VI5_CLK,\n-\tGPIO_FN_EX_WAIT0_B,\n-\tGPIO_IFN_BSx,\n-\tGPIO_FN_QSTVA_QVS,\n-\tGPIO_FN_MSIOF3_SCK_D,\n-\tGPIO_FN_SCK3,\n-\tGPIO_FN_HSCK3,\n-\tGPIO_FN_CAN1_TX,\n-\tGPIO_FN_CANFD1_TX,\n-\tGPIO_FN_IETX_A,\n-\tGPIO_IFN_RDx,\n-\tGPIO_FN_MSIOF3_SYNC_D,\n-\tGPIO_FN_RX3_A,\n-\tGPIO_FN_HRX3_A,\n-\tGPIO_FN_CAN0_TX_A,\n-\tGPIO_FN_CANFD0_TX_A,\n-\tGPIO_IFN_RD_WRx,\n-\tGPIO_FN_MSIOF3_RXD_D,\n-\tGPIO_FN_TX3_A,\n-\tGPIO_FN_HTX3_A,\n-\tGPIO_FN_CAN0_RX_A,\n-\tGPIO_FN_CANFD0_RX_A,\n-\n-\t/* IPSR5 */\n-\tGPIO_IFN_WE0x,\n-\tGPIO_FN_MSIIOF3_TXD_D,\n-\tGPIO_FN_CTS3x,\n-\tGPIO_FN_HCTS3x,\n-\tGPIO_FN_SCL6_B,\n-\tGPIO_FN_CAN_CLK,\n-\tGPIO_FN_IECLK_A,\n-\tGPIO_IFN_WE1x,\n-\tGPIO_FN_MSIOF3_SS1_D,\n-\tGPIO_FN_RTS3x_TANS,\n-\tGPIO_FN_HRTS3x,\n-\tGPIO_FN_SDA6_B,\n-\tGPIO_FN_CAN1_RX,\n-\tGPIO_FN_CANFD1_RX,\n-\tGPIO_FN_IERX_A,\n-\tGPIO_IFN_EX_WAIT0_A,\n-\tGPIO_FN_QCLK,\n-\tGPIO_FN_VI4_CLK,\n-\tGPIO_FN_DU_DOTCLKOUT0,\n-\tGPIO_IFN_D0,\n-\tGPIO_FN_MSIOF2_SS1_B,\n-\tGPIO_FN_MSIOF3_SCK_A,\n-\tGPIO_FN_VI4_DATA16,\n-\tGPIO_FN_VI5_DATA0,\n-\tGPIO_IFN_D1,\n-\tGPIO_FN_MSIOF2_SS2_B,\n-\tGPIO_FN_MSIOF3_SYNC_A,\n-\tGPIO_FN_VI4_DATA17,\n-\tGPIO_FN_VI5_DATA1,\n-\tGPIO_IFN_D2,\n-\tGPIO_FN_MSIOF3_RXD_A,\n-\tGPIO_FN_VI4_DATA18,\n-\tGPIO_FN_VI5_DATA2,\n-\tGPIO_IFN_D3,\n-\tGPIO_FN_MSIOF3_TXD_A,\n-\tGPIO_FN_VI4_DATA19,\n-\tGPIO_FN_VI5_DATA3,\n-\tGPIO_IFN_D4,\n-\tGPIO_FN_MSIOF2_SCK_B,\n-\tGPIO_FN_VI4_DATA20,\n-\tGPIO_FN_VI5_DATA4,\n-\n-\t/* IPSR6 */\n-\tGPIO_IFN_D5,\n-\tGPIO_FN_MSIOF2_SYNC_B,\n-\tGPIO_FN_VI4_DATA21,\n-\tGPIO_FN_VI5_DATA5,\n-\tGPIO_IFN_D6,\n-\tGPIO_FN_MSIOF2_RXD_B,\n-\tGPIO_FN_VI4_DATA22,\n-\tGPIO_FN_VI5_DATA6,\n-\tGPIO_IFN_D7,\n-\tGPIO_FN_MSIOF2_TXD_B,\n-\tGPIO_FN_VI4_DATA23,\n-\tGPIO_FN_VI5_DATA7,\n-\tGPIO_IFN_D8,\n-\tGPIO_FN_LCDOUT0,\n-\tGPIO_FN_MSIOF2_SCK_D,\n-\tGPIO_FN_SCK4_C,\n-\tGPIO_FN_VI4_DATA0_A,\n-\tGPIO_FN_DU_DR0,\n-\tGPIO_IFN_D9,\n-\tGPIO_FN_LCDOUT1,\n-\tGPIO_FN_MSIOF2_SYNC_D,\n-\tGPIO_FN_VI4_DATA1_A,\n-\tGPIO_FN_DU_DR1,\n-\tGPIO_IFN_D10,\n-\tGPIO_FN_LCDOUT2,\n-\tGPIO_FN_MSIOF2_RXD_D,\n-\tGPIO_FN_HRX3_B,\n-\tGPIO_FN_VI4_DATA2_A,\n-\tGPIO_FN_CTS4x_C,\n-\tGPIO_FN_DU_DR2,\n-\tGPIO_IFN_D11,\n-\tGPIO_FN_LCDOUT3,\n-\tGPIO_FN_MSIOF2_TXD_D,\n-\tGPIO_FN_HTX3_B,\n-\tGPIO_FN_VI4_DATA3_A,\n-\tGPIO_FN_RTS4x_TANS_C,\n-\tGPIO_FN_DU_DR3,\n-\tGPIO_IFN_D12,\n-\tGPIO_FN_LCDOUT4,\n-\tGPIO_FN_MSIOF2_SS1_D,\n-\tGPIO_FN_RX4_C,\n-\tGPIO_FN_VI4_DATA4_A,\n-\tGPIO_FN_DU_DR4,\n-\n-\t/* IPSR7 */\n-\tGPIO_IFN_D13,\n-\tGPIO_FN_LCDOUT5,\n-\tGPIO_FN_MSIOF2_SS2_D,\n-\tGPIO_FN_TX4_C,\n-\tGPIO_FN_VI4_DATA5_A,\n-\tGPIO_FN_DU_DR5,\n-\tGPIO_IFN_D14,\n-\tGPIO_FN_LCDOUT6,\n-\tGPIO_FN_MSIOF3_SS1_A,\n-\tGPIO_FN_HRX3_C,\n-\tGPIO_FN_VI4_DATA6_A,\n-\tGPIO_FN_DU_DR6,\n-\tGPIO_FN_SCL6_C,\n-\tGPIO_IFN_D15,\n-\tGPIO_FN_LCDOUT7,\n-\tGPIO_FN_MSIOF3_SS2_A,\n-\tGPIO_FN_HTX3_C,\n-\tGPIO_FN_VI4_DATA7_A,\n-\tGPIO_FN_DU_DR7,\n-\tGPIO_FN_SDA6_C,\n-\tGPIO_FN_FSCLKST,\n-\tGPIO_IFN_SD0_CLK,\n-\tGPIO_FN_MSIOF1_SCK_E,\n-\tGPIO_FN_STP_OPWM_0_B,\n-\tGPIO_IFN_SD0_CMD,\n-\tGPIO_FN_MSIOF1_SYNC_E,\n-\tGPIO_FN_STP_IVCXO27_0_B,\n-\tGPIO_IFN_SD0_DAT0,\n-\tGPIO_FN_MSIOF1_RXD_E,\n-\tGPIO_FN_TS_SCK0_B,\n-\tGPIO_FN_STP_ISCLK_0_B,\n-\tGPIO_IFN_SD0_DAT1,\n-\tGPIO_FN_MSIOF1_TXD_E,\n-\tGPIO_FN_TS_SPSYNC0_B,\n-\tGPIO_FN_STP_ISSYNC_0_B,\n-\n-\t/* IPSR8 */\n-\tGPIO_IFN_SD0_DAT2,\n-\tGPIO_FN_MSIOF1_SS1_E,\n-\tGPIO_FN_TS_SDAT0_B,\n-\tGPIO_FN_STP_ISD_0_B,\n-\n-\tGPIO_IFN_SD0_DAT3,\n-\tGPIO_FN_MSIOF1_SS2_E,\n-\tGPIO_FN_TS_SDEN0_B,\n-\tGPIO_FN_STP_ISEN_0_B,\n-\n-\tGPIO_IFN_SD1_CLK,\n-\tGPIO_FN_MSIOF1_SCK_G,\n-\tGPIO_FN_SIM0_CLK_A,\n-\n-\tGPIO_IFN_SD1_CMD,\n-\tGPIO_FN_MSIOF1_SYNC_G,\n-\tGPIO_FN_NFCEx_B,\n-\tGPIO_FN_SIM0_D_A,\n-\tGPIO_FN_STP_IVCXO27_1_B,\n-\n-\tGPIO_IFN_SD1_DAT0,\n-\tGPIO_FN_SD2_DAT4,\n-\tGPIO_FN_MSIOF1_RXD_G,\n-\tGPIO_FN_NFWPx_B,\n-\tGPIO_FN_TS_SCK1_B,\n-\tGPIO_FN_STP_ISCLK_1_B,\n-\n-\tGPIO_IFN_SD1_DAT1,\n-\tGPIO_FN_SD2_DAT5,\n-\tGPIO_FN_MSIOF1_TXD_G,\n-\tGPIO_FN_NFDATA14_B,\n-\tGPIO_FN_TS_SPSYNC1_B,\n-\tGPIO_FN_STP_ISSYNC_1_B,\n-\n-\tGPIO_IFN_SD1_DAT2,\n-\tGPIO_FN_SD2_DAT6,\n-\tGPIO_FN_MSIOF1_SS1_G,\n-\tGPIO_FN_NFDATA15_B,\n-\tGPIO_FN_TS_SDAT1_B,\n-\tGPIO_FN_STP_IOD_1_B,\n-\n-\tGPIO_IFN_SD1_DAT3,\n-\tGPIO_FN_SD2_DAT7,\n-\tGPIO_FN_MSIOF1_SS2_G,\n-\tGPIO_FN_NFRBx_B,\n-\tGPIO_FN_TS_SDEN1_B,\n-\tGPIO_FN_STP_ISEN_1_B,\n-\n-\t/* IPSR9 */\n-\tGPIO_IFN_SD2_CLK,\n-\tGPIO_FN_NFDATA8,\n-\n-\tGPIO_IFN_SD2_CMD,\n-\tGPIO_FN_NFDATA9,\n-\n-\tGPIO_IFN_SD2_DAT0,\n-\tGPIO_FN_NFDATA10,\n-\n-\tGPIO_IFN_SD2_DAT1,\n-\tGPIO_FN_NFDATA11,\n-\n-\tGPIO_IFN_SD2_DAT2,\n-\tGPIO_FN_NFDATA12,\n-\n-\tGPIO_IFN_SD2_DAT3,\n-\tGPIO_FN_NFDATA13,\n-\n-\tGPIO_IFN_SD2_DS,\n-\tGPIO_FN_NFALE,\n-\n-\tGPIO_IFN_SD3_CLK,\n-\tGPIO_FN_NFWEx,\n-\n-\t/* IPSR10 */\n-\tGPIO_IFN_SD3_CMD,\n-\tGPIO_FN_NFREx,\n-\n-\tGPIO_IFN_SD3_DAT0,\n-\tGPIO_FN_NFDATA0,\n-\n-\tGPIO_IFN_SD3_DAT1,\n-\tGPIO_FN_NFDATA1,\n-\n-\tGPIO_IFN_SD3_DAT2,\n-\tGPIO_FN_NFDATA2,\n-\n-\tGPIO_IFN_SD3_DAT3,\n-\tGPIO_FN_NFDATA3,\n-\n-\tGPIO_IFN_SD3_DAT4,\n-\tGPIO_FN_SD2_CD_A,\n-\tGPIO_FN_NFDATA4,\n-\n-\tGPIO_IFN_SD3_DAT5,\n-\tGPIO_FN_SD2_WP_A,\n-\tGPIO_FN_NFDATA5,\n-\n-\tGPIO_IFN_SD3_DAT6,\n-\tGPIO_FN_SD3_CD,\n-\tGPIO_FN_NFDATA6,\n-\n-\t/* IPSR11 */\n-\tGPIO_IFN_SD3_DAT7,\n-\tGPIO_FN_SD3_WP,\n-\tGPIO_FN_NFDATA7,\n-\n-\tGPIO_IFN_SD3_DS,\n-\tGPIO_FN_NFCLE,\n-\n-\tGPIO_IFN_SD0_CD,\n-\tGPIO_FN_NFDATA14_A,\n-\tGPIO_FN_SCL2_B,\n-\tGPIO_FN_SIM0_RST_A,\n-\n-\tGPIO_IFN_SD0_WP,\n-\tGPIO_FN_NFDATA15_A,\n-\tGPIO_FN_SDA2_B,\n-\n-\tGPIO_IFN_SD1_CD,\n-\tGPIO_FN_NFRBx_A,\n-\tGPIO_FN_SIM0_CLK_B,\n-\n-\tGPIO_IFN_SD1_WP,\n-\tGPIO_FN_NFCEx_A,\n-\tGPIO_FN_SIM0_D_B,\n-\n-\tGPIO_IFN_SCK0,\n-\tGPIO_FN_HSCK1_B,\n-\tGPIO_FN_MSIOF1_SS2_B,\n-\tGPIO_FN_AUDIO_CLKC_B,\n-\tGPIO_FN_SDA2_A,\n-\tGPIO_FN_SIM0_RST_B,\n-\tGPIO_FN_STP_OPWM_0_C,\n-\tGPIO_FN_RIF0_CLK_B,\n-\tGPIO_FN_ADICHS2,\n-\tGPIO_FN_SCK5_B,\n-\n-\tGPIO_IFN_RX0,\n-\tGPIO_FN_HRX1_B,\n-\tGPIO_FN_TS_SCK0_C,\n-\tGPIO_FN_STP_ISCLK_0_C,\n-\tGPIO_FN_RIF0_D0_B,\n-\n-\t/* IPSR12 */\n-\tGPIO_IFN_TX0,\n-\tGPIO_FN_HTX1_B,\n-\tGPIO_FN_TS_SPSYNC0_C,\n-\tGPIO_FN_STP_ISSYNC_0_C,\n-\tGPIO_FN_RIF0_D1_B,\n-\n-\tGPIO_IFN_CTS0x,\n-\tGPIO_FN_HCTS1x_B,\n-\tGPIO_FN_MSIOF1_SYNC_B,\n-\tGPIO_FN_TS_SPSYNC1_C,\n-\tGPIO_FN_STP_ISSYNC_1_C,\n-\tGPIO_FN_RIF1_SYNC_B,\n-\tGPIO_FN_AUDIO_CLKOUT_C,\n-\tGPIO_FN_ADICS_SAMP,\n-\n-\tGPIO_IFN_RTS0x_TANS,\n-\tGPIO_FN_HRTS1x_B,\n-\tGPIO_FN_MSIOF1_SS1_B,\n-\tGPIO_FN_AUDIO_CLKA_B,\n-\tGPIO_FN_SCL2_A,\n-\tGPIO_FN_STP_IVCXO27_1_C,\n-\tGPIO_FN_RIF0_SYNC_B,\n-\tGPIO_FN_ADICHS1,\n-\n-\tGPIO_IFN_RX1_A,\n-\tGPIO_FN_HRX1_A,\n-\tGPIO_FN_TS_SDAT0_C,\n-\tGPIO_FN_STP_ISD_0_C,\n-\tGPIO_FN_RIF1_CLK_C,\n-\n-\tGPIO_IFN_TX1_A,\n-\tGPIO_FN_HTX1_A,\n-\tGPIO_FN_TS_SDEN0_C,\n-\tGPIO_FN_STP_ISEN_0_C,\n-\tGPIO_FN_RIF1_D0_C,\n-\n-\tGPIO_IFN_CTS1x,\n-\tGPIO_FN_HCTS1x_A,\n-\tGPIO_FN_MSIOF1_RXD_B,\n-\tGPIO_FN_TS_SDEN1_C,\n-\tGPIO_FN_STP_ISEN_1_C,\n-\tGPIO_FN_RIF1_D0_B,\n-\tGPIO_FN_ADIDATA,\n-\n-\tGPIO_IFN_RTS1x_TANS,\n-\tGPIO_FN_HRTS1x_A,\n-\tGPIO_FN_MSIOF1_TXD_B,\n-\tGPIO_FN_TS_SDAT1_C,\n-\tGPIO_FN_STP_ISD_1_C,\n-\tGPIO_FN_RIF1_D1_B,\n-\tGPIO_FN_ADICHS0,\n-\n-\tGPIO_IFN_SCK2,\n-\tGPIO_FN_SCIF_CLK_B,\n-\tGPIO_FN_MSIOF1_SCK_B,\n-\tGPIO_FN_TS_SCK1_C,\n-\tGPIO_FN_STP_ISCLK_1_C,\n-\tGPIO_FN_RIF1_CLK_B,\n-\tGPIO_FN_ADICLK,\n-\n-\t/* IPSR13 */\n-\tGPIO_IFN_TX2_A,\n-\tGPIO_FN_SD2_CD_B,\n-\tGPIO_FN_SCL1_A,\n-\tGPIO_FN_FMCLK_A,\n-\tGPIO_FN_RIF1_D1_C,\n-\tGPIO_FN_FSO_CFE_0_B,\n-\n-\tGPIO_IFN_RX2_A,\n-\tGPIO_FN_SD2_WP_B,\n-\tGPIO_FN_SDA1_A,\n-\tGPIO_FN_FMIN_A,\n-\tGPIO_FN_RIF1_SYNC_C,\n-\tGPIO_FN_FSO_CEF_1_B,\n-\n-\tGPIO_IFN_HSCK0,\n-\tGPIO_FN_MSIOF1_SCK_D,\n-\tGPIO_FN_AUDIO_CLKB_A,\n-\tGPIO_FN_SSI_SDATA1_B,\n-\tGPIO_FN_TS_SCK0_D,\n-\tGPIO_FN_STP_ISCLK_0_D,\n-\tGPIO_FN_RIF0_CLK_C,\n-\tGPIO_FN_RX5_B,\n-\n-\tGPIO_IFN_HRX0,\n-\tGPIO_FN_MSIOF1_RXD_D,\n-\tGPIO_FN_SS1_SDATA2_B,\n-\tGPIO_FN_TS_SDEN0_D,\n-\tGPIO_FN_STP_ISEN_0_D,\n-\tGPIO_FN_RIF0_D0_C,\n-\n-\tGPIO_IFN_HTX0,\n-\tGPIO_FN_MSIOF1_TXD_D,\n-\tGPIO_FN_SSI_SDATA9_B,\n-\tGPIO_FN_TS_SDAT0_D,\n-\tGPIO_FN_STP_ISD_0_D,\n-\tGPIO_FN_RIF0_D1_C,\n-\n-\tGPIO_IFN_HCTS0x,\n-\tGPIO_FN_RX2_B,\n-\tGPIO_FN_MSIOF1_SYNC_D,\n-\tGPIO_FN_SSI_SCK9_A,\n-\tGPIO_FN_TS_SPSYNC0_D,\n-\tGPIO_FN_STP_ISSYNC_0_D,\n-\tGPIO_FN_RIF0_SYNC_C,\n-\tGPIO_FN_AUDIO_CLKOUT1_A,\n-\n-\tGPIO_IFN_HRTS0x,\n-\tGPIO_FN_TX2_B,\n-\tGPIO_FN_MSIOF1_SS1_D,\n-\tGPIO_FN_SSI_WS9_A,\n-\tGPIO_FN_STP_IVCXO27_0_D,\n-\tGPIO_FN_BPFCLK_A,\n-\tGPIO_FN_AUDIO_CLKOUT2_A,\n-\n-\tGPIO_IFN_MSIOF0_SYNC,\n-\tGPIO_FN_AUDIO_CLKOUT_A,\n-\tGPIO_FN_TX5_B,\n-\tGPIO_FN_BPFCLK_D,\n-\n-\t/* IPSR14 */\n-\tGPIO_IFN_MSIOF0_SS1,\n-\tGPIO_FN_RX5_A,\n-\tGPIO_FN_NFWPx_A,\n-\tGPIO_FN_AUDIO_CLKA_C,\n-\tGPIO_FN_SSI_SCK2_A,\n-\tGPIO_FN_STP_IVCXO27_0_C,\n-\tGPIO_FN_AUDIO_CLKOUT3_A,\n-\tGPIO_FN_TCLK1_B,\n-\n-\tGPIO_IFN_MSIOF0_SS2,\n-\tGPIO_FN_TX5_A,\n-\tGPIO_FN_MSIOF1_SS2_D,\n-\tGPIO_FN_AUDIO_CLKC_A,\n-\tGPIO_FN_SSI_WS2_A,\n-\tGPIO_FN_STP_OPWM_0_D,\n-\tGPIO_FN_AUDIO_CLKOUT_D,\n-\tGPIO_FN_SPEEDIN_B,\n-\n-\tGPIO_IFN_MLB_CLK,\n-\tGPIO_FN_MSIOF1_SCK_F,\n-\tGPIO_FN_SCL1_B,\n-\n-\tGPIO_IFN_MLB_SIG,\n-\tGPIO_FN_RX1_B,\n-\tGPIO_FN_MSIOF1_SYNC_F,\n-\tGPIO_FN_SDA1_B,\n-\n-\tGPIO_IFN_MLB_DAT,\n-\tGPIO_FN_TX1_B,\n-\tGPIO_FN_MSIOF1_RXD_F,\n-\n-\tGPIO_IFN_SSI_SCK0129,\n-\tGPIO_FN_MSIOF1_TXD_F,\n-\tGPIO_FN_MOUT0,\n-\n-\tGPIO_IFN_SSI_WS0129,\n-\tGPIO_FN_MSIOF1_SS1_F,\n-\tGPIO_FN_MOUT1,\n-\n-\tGPIO_IFN_SSI_SDATA0,\n-\tGPIO_FN_MSIOF1_SS2_F,\n-\tGPIO_FN_MOUT2,\n-\n-\t/* IPSR15 */\n-\tGPIO_IFN_SSI_SDATA1_A,\n-\tGPIO_FN_MOUT5,\n-\n-\tGPIO_IFN_SSI_SDATA2_A,\n-\tGPIO_FN_SSI_SCK1_B,\n-\tGPIO_FN_MOUT6,\n-\n-\tGPIO_IFN_SSI_SCK34,\n-\tGPIO_FN_MSIOF1_SS1_A,\n-\tGPIO_FN_STP_OPWM_0_A,\n-\n-\tGPIO_IFN_SSI_WS34,\n-\tGPIO_FN_HCTS2x_A,\n-\tGPIO_FN_MSIOF1_SS2_A,\n-\tGPIO_FN_STP_IVCXO27_0_A,\n-\n-\tGPIO_IFN_SSI_SDATA3,\n-\tGPIO_FN_HRTS2x_A,\n-\tGPIO_FN_MSIOF1_TXD_A,\n-\tGPIO_FN_TS_SCK0_A,\n-\tGPIO_FN_STP_ISCLK_0_A,\n-\tGPIO_FN_RIF0_D1_A,\n-\tGPIO_FN_RIF2_D0_A,\n-\n-\tGPIO_IFN_SSI_SCK4,\n-\tGPIO_FN_HRX2_A,\n-\tGPIO_FN_MSIOF1_SCK_A,\n-\tGPIO_FN_TS_SDAT0_A,\n-\tGPIO_FN_STP_ISD_0_A,\n-\tGPIO_FN_RIF0_CLK_A,\n-\tGPIO_FN_RIF2_CLK_A,\n-\n-\tGPIO_IFN_SSI_WS4,\n-\tGPIO_FN_HTX2_A,\n-\tGPIO_FN_MSIOF1_SYNC_A,\n-\tGPIO_FN_TS_SDEN0_A,\n-\tGPIO_FN_STP_ISEN_0_A,\n-\tGPIO_FN_RIF0_SYNC_A,\n-\tGPIO_FN_RIF2_SYNC_A,\n-\n-\tGPIO_IFN_SSI_SDATA4,\n-\tGPIO_FN_HSCK2_A,\n-\tGPIO_FN_MSIOF1_RXD_A,\n-\tGPIO_FN_TS_SPSYNC0_A,\n-\tGPIO_FN_STP_ISSYNC_0_A,\n-\tGPIO_FN_RIF0_D0_A,\n-\tGPIO_FN_RIF2_D1_A,\n-\n-\t/* IPSR16 */\n-\tGPIO_IFN_SSI_SCK6,\n-\tGPIO_FN_SIM0_RST_D,\n-\tGPIO_FN_FSO_TOE_A,\n-\n-\tGPIO_IFN_SSI_WS6,\n-\tGPIO_FN_SIM0_D_D,\n-\n-\tGPIO_IFN_SSI_SDATA6,\n-\tGPIO_FN_SIM0_CLK_D,\n-\n-\tGPIO_IFN_SSI_SCK78,\n-\tGPIO_FN_HRX2_B,\n-\tGPIO_FN_MSIOF1_SCK_C,\n-\tGPIO_FN_TS_SCK1_A,\n-\tGPIO_FN_STP_ISCLK_1_A,\n-\tGPIO_FN_RIF1_CLK_A,\n-\tGPIO_FN_RIF3_CLK_A,\n-\n-\tGPIO_IFN_SSI_WS78,\n-\tGPIO_FN_HTX2_B,\n-\tGPIO_FN_MSIOF1_SYNC_C,\n-\tGPIO_FN_TS_SDAT1_A,\n-\tGPIO_FN_STP_ISD_1_A,\n-\tGPIO_FN_RIF1_SYNC_A,\n-\tGPIO_FN_RIF3_SYNC_A,\n-\n-\tGPIO_IFN_SSI_SDATA7,\n-\tGPIO_FN_HCTS2x_B,\n-\tGPIO_FN_MSIOF1_RXD_C,\n-\tGPIO_FN_TS_SDEN1_A,\n-\tGPIO_FN_STP_IEN_1_A,\n-\tGPIO_FN_RIF1_D0_A,\n-\tGPIO_FN_RIF3_D0_A,\n-\tGPIO_FN_TCLK2_A,\n-\n-\tGPIO_IFN_SSI_SDATA8,\n-\tGPIO_FN_HRTS2x_B,\n-\tGPIO_FN_MSIOF1_TXD_C,\n-\tGPIO_FN_TS_SPSYNC1_A,\n-\tGPIO_FN_STP_ISSYNC_1_A,\n-\tGPIO_FN_RIF1_D1_A,\n-\tGPIO_FN_EIF3_D1_A,\n-\n-\tGPIO_IFN_SSI_SDATA9_A,\n-\tGPIO_FN_HSCK2_B,\n-\tGPIO_FN_MSIOF1_SS1_C,\n-\tGPIO_FN_HSCK1_A,\n-\tGPIO_FN_SSI_WS1_B,\n-\tGPIO_FN_SCK1,\n-\tGPIO_FN_STP_IVCXO27_1_A,\n-\tGPIO_FN_SCK5,\n-\n-\t/* IPSR17 */\n-\tGPIO_IFN_AUDIO_CLKA_A,\n-\tGPIO_FN_CC5_OSCOUT,\n-\n-\tGPIO_IFN_AUDIO_CLKB_B,\n-\tGPIO_FN_SCIF_CLK_A,\n-\tGPIO_FN_STP_IVCXO27_1_D,\n-\tGPIO_FN_REMOCON_A,\n-\tGPIO_FN_TCLK1_A,\n-\n-\tGPIO_IFN_USB0_PWEN,\n-\tGPIO_FN_SIM0_RST_C,\n-\tGPIO_FN_TS_SCK1_D,\n-\tGPIO_FN_STP_ISCLK_1_D,\n-\tGPIO_FN_BPFCLK_B,\n-\tGPIO_FN_RIF3_CLK_B,\n-\tGPIO_FN_FSO_CFE_1_A,\n-\tGPIO_FN_HSCK2_C,\n-\n-\tGPIO_IFN_USB0_OVC,\n-\tGPIO_FN_SIM0_D_C,\n-\tGPIO_FN_TS_SDAT1_D,\n-\tGPIO_FN_STP_ISD_1_D,\n-\tGPIO_FN_RIF3_SYNC_B,\n-\tGPIO_FN_HRX2_C,\n-\n-\tGPIO_IFN_USB1_PWEN,\n-\tGPIO_FN_SIM0_CLK_C,\n-\tGPIO_FN_SSI_SCK1_A,\n-\tGPIO_FN_TS_SCK0_E,\n-\tGPIO_FN_STP_ISCLK_0_E,\n-\tGPIO_FN_FMCLK_B,\n-\tGPIO_FN_RIF2_CLK_B,\n-\tGPIO_FN_SPEEDIN_A,\n-\tGPIO_FN_HTX2_C,\n-\n-\tGPIO_IFN_USB1_OVC,\n-\tGPIO_FN_MSIOF1_SS2_C,\n-\tGPIO_FN_SSI_WS1_A,\n-\tGPIO_FN_TS_SDAT0_E,\n-\tGPIO_FN_STP_ISD_0_E,\n-\tGPIO_FN_FMIN_B,\n-\tGPIO_FN_RIF2_SYNC_B,\n-\tGPIO_FN_REMOCON_B,\n-\tGPIO_FN_HCTS2x_C,\n-\n-\tGPIO_IFN_USB30_PWEN,\n-\tGPIO_FN_AUDIO_CLKOUT_B,\n-\tGPIO_FN_SSI_SCK2_B,\n-\tGPIO_FN_TS_SDEN1_D,\n-\tGPIO_FN_STP_ISEN_1_D,\n-\tGPIO_FN_STP_OPWM_0_E,\n-\tGPIO_FN_RIF3_D0_B,\n-\tGPIO_FN_TCLK2_B,\n-\tGPIO_FN_TPU0TO0,\n-\tGPIO_FN_BPFCLK_C,\n-\tGPIO_FN_HRTS2x_C,\n-\n-\tGPIO_IFN_USB30_OVC,\n-\tGPIO_FN_AUDIO_CLKOUT1_B,\n-\tGPIO_FN_SSI_WS2_B,\n-\tGPIO_FN_TS_SPSYNC1_D,\n-\tGPIO_FN_STP_ISSYNC_1_D,\n-\tGPIO_FN_STP_IVCXO27_0_E,\n-\tGPIO_FN_RIF3_D1_B,\n-\tGPIO_FN_FSO_TOE_B,\n-\tGPIO_FN_TPU0TO1,\n-\n-\t/* IPSR18 */\n-\tGPIO_IFN_GP6_30,\n-\tGPIO_FN_AUDIO_CLKOUT2_B,\n-\tGPIO_FN_SSI_SCK9_B,\n-\tGPIO_FN_TS_SDEN0_E,\n-\tGPIO_FN_STP_ISEN_0_E,\n-\tGPIO_FN_RIF2_D0_B,\n-\tGPIO_FN_FSO_CFE_0_A,\n-\tGPIO_FN_TPU0TO2,\n-\tGPIO_FN_FMCLK_C,\n-\tGPIO_FN_FMCLK_D,\n-\n-\tGPIO_IFN_GP6_31,\n-\tGPIO_FN_AUDIO_CLKOUT3_B,\n-\tGPIO_FN_SSI_WS9_B,\n-\tGPIO_FN_TS_SPSYNC0_E,\n-\tGPIO_FN_STP_ISSYNC_0_E,\n-\tGPIO_FN_RIF2_D1_B,\n-\tGPIO_FN_TPU0TO3,\n-\tGPIO_FN_FMIN_C,\n-\tGPIO_FN_FMIN_D,\n-\n-};\n-\n-#endif /* __ASM_R8A7796_GPIO_H__ */\ndiff --git a/arch/arm/mach-rmobile/pfc-r8a7795.c b/arch/arm/mach-rmobile/pfc-r8a7795.c\ndeleted file mode 100644\nindex 93aaf31ed9..0000000000\n--- a/arch/arm/mach-rmobile/pfc-r8a7795.c\n+++ /dev/null\n@@ -1,5005 +0,0 @@\n-/*\n- * arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7795.c\n- *     This file is r8a7795 processor support - PFC hardware block.\n- *\n- * Copyright (C) 2015-2016 Renesas Electronics Corporation\n- *\n- * SPDX-License-Identifier:\tGPL-2.0+\n- */\n-\n-#include <common.h>\n-#include <sh_pfc.h>\n-#include <asm/gpio.h>\n-\n-#define CPU_32_PORT(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),\t\\\n-\tPORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx),\t\\\n-\tPORT_1(fn, pfx##31, sfx)\n-\n-#define CPU_32_PORT1(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),\t\\\n-\tPORT_10(fn, pfx##2, sfx)\n-\n-#define CPU_32_PORT2(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),\t\\\n-\tPORT_10(fn, pfx##2, sfx)\n-\n-#define CPU_32_PORT_29(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_10(fn, pfx, sfx),\t\t\t\t\t\\\n-\tPORT_10(fn, pfx##1, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##20, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##21, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##22, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##23, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##24, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##25, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##26, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##27, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##28, sfx)\n-\n-#define CPU_32_PORT_28(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_10(fn, pfx, sfx),\t\t\t\t\t\\\n-\tPORT_10(fn, pfx##1, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##20, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##21, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##22, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##23, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##24, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##25, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##26, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##27, sfx)\n-\n-#define CPU_32_PORT_26(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_10(fn, pfx, sfx),\t\t\t\t\t\\\n-\tPORT_10(fn, pfx##1, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##20, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##21, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##22, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##23, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##24, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##25, sfx)\n-\n-#define CPU_32_PORT_18(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_10(fn, pfx, sfx),\t\t\t\t\t\\\n-\tPORT_1(fn, pfx##10, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##11, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##12, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##13, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##14, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##15, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##16, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##17, sfx)\n-\n-#define CPU_32_PORT_16(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_10(fn, pfx, sfx),\t\t\t\t\t\\\n-\tPORT_1(fn, pfx##10, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##11, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##12, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##13, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##14, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##15, sfx)\n-\n-#define CPU_32_PORT_15(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_10(fn, pfx, sfx),\t\t\t\t\t\\\n-\tPORT_1(fn, pfx##10, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##11, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##12, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##13, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##14, sfx)\n-\n-#define CPU_32_PORT_4(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_1(fn, pfx##0, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##1, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##2, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##3, sfx)\n-\n-\n-/* --gen3-- */\n-/* GP_0_0_DATA -> GP_7_4_DATA */\n-/* except for GP0[16] - [31],\n-\t\tGP1[28] - [31],\n-\t\tGP2[15] - [31],\n-\t\tGP3[16] - [31],\n-\t\tGP4[18] - [31],\n-\t\tGP5[26] - [31],\n-\t\tGP7[4] - [31] */\n-\n-#define ES_CPU_ALL_PORT(fn, pfx, sfx)\t\t\\\n-\tCPU_32_PORT_16(fn, pfx##_0_, sfx),\t\\\n-\tCPU_32_PORT_28(fn, pfx##_1_, sfx),\t\\\n-\tCPU_32_PORT_15(fn, pfx##_2_, sfx),\t\\\n-\tCPU_32_PORT_16(fn, pfx##_3_, sfx),\t\\\n-\tCPU_32_PORT_18(fn, pfx##_4_, sfx),\t\\\n-\tCPU_32_PORT_26(fn, pfx##_5_, sfx),\t\\\n-\tCPU_32_PORT(fn, pfx##_6_, sfx),\t\t\\\n-\tCPU_32_PORT_4(fn, pfx##_7_, sfx)\n-\n-#define CPU_ALL_PORT(fn, pfx, sfx)\t\t\\\n-\tCPU_32_PORT_16(fn, pfx##_0_, sfx),\t\\\n-\tCPU_32_PORT_29(fn, pfx##_1_, sfx),\t\\\n-\tCPU_32_PORT_15(fn, pfx##_2_, sfx),\t\\\n-\tCPU_32_PORT_16(fn, pfx##_3_, sfx),\t\\\n-\tCPU_32_PORT_18(fn, pfx##_4_, sfx),\t\\\n-\tCPU_32_PORT_26(fn, pfx##_5_, sfx),\t\\\n-\tCPU_32_PORT(fn, pfx##_6_, sfx),\t\t\\\n-\tCPU_32_PORT_4(fn, pfx##_7_, sfx)\n-\n-#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)\n-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN,\t\\\n-\t\t\t\t       GP##pfx##_IN, GP##pfx##_OUT)\n-\n-#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT\n-#define _GP_INDT(pfx, sfx) GP##pfx##_DATA\n-\n-#define GP_ALL(str)\tCPU_ALL_PORT(_PORT_ALL, GP, str)\n-#define PINMUX_GPIO_GP_ALL()\tCPU_ALL_PORT(_GP_GPIO, , unused)\n-#define PINMUX_DATA_GP_ALL()\tCPU_ALL_PORT(_GP_DATA, , unused)\n-\n-\n-#define PORT_10_REV(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx),\t\\\n-\tPORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx),\t\\\n-\tPORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx),\t\\\n-\tPORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx),\t\\\n-\tPORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)\n-\n-#define CPU_32_PORT_REV(fn, pfx, sfx)\t\t\t\t\t\\\n-\tPORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx),\t\t\\\n-\tPORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx),\t\\\n-\tPORT_10_REV(fn, pfx, sfx)\n-\n-#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)\n-#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)\n-\n-#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)\n-#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \\\n-\t\t\t\t\t\t\t  FN_##ipsr, FN_##fn)\n-\n-enum {\n-\tPINMUX_RESERVED = 0,\n-\n-\tPINMUX_DATA_BEGIN,\n-\tGP_ALL(DATA),\n-\tPINMUX_DATA_END,\n-\n-\tPINMUX_INPUT_BEGIN,\n-\tGP_ALL(IN),\n-\tPINMUX_INPUT_END,\n-\n-\tPINMUX_OUTPUT_BEGIN,\n-\tGP_ALL(OUT),\n-\tPINMUX_OUTPUT_END,\n-\n-\tPINMUX_FUNCTION_BEGIN,\n-\tGP_ALL(FN),\n-\n-\t/* GPSR0 */\n-\tGFN_D15,\n-\tGFN_D14,\n-\tGFN_D13,\n-\tGFN_D12,\n-\tGFN_D11,\n-\tGFN_D10,\n-\tGFN_D9,\n-\tGFN_D8,\n-\tGFN_D7,\n-\tGFN_D6,\n-\tGFN_D5,\n-\tGFN_D4,\n-\tGFN_D3,\n-\tGFN_D2,\n-\tGFN_D1,\n-\tGFN_D0,\n-\n-\t/* GPSR1 */\n-\tGFN_CLKOUT,\n-\tGFN_EX_WAIT0_A,\n-\tGFN_WE1x,\n-\tGFN_WE0x,\n-\tGFN_RD_WRx,\n-\tGFN_RDx,\n-\tGFN_BSx,\n-\tGFN_CS1x_A26,\n-\tGFN_CS0x,\n-\tGFN_A19,\n-\tGFN_A18,\n-\tGFN_A17,\n-\tGFN_A16,\n-\tGFN_A15,\n-\tGFN_A14,\n-\tGFN_A13,\n-\tGFN_A12,\n-\tGFN_A11,\n-\tGFN_A10,\n-\tGFN_A9,\n-\tGFN_A8,\n-\tGFN_A7,\n-\tGFN_A6,\n-\tGFN_A5,\n-\tGFN_A4,\n-\tGFN_A3,\n-\tGFN_A2,\n-\tGFN_A1,\n-\tGFN_A0,\n-\n-\t/* GPSR2 */\n-\tGFN_AVB_AVTP_CAPTURE_A,\n-\tGFN_AVB_AVTP_MATCH_A,\n-\tGFN_AVB_LINK,\n-\tGFN_AVB_PHY_INT,\n-\tGFN_AVB_MAGIC,\n-\tGFN_AVB_MDC,\n-\tGFN_PWM2_A,\n-\tGFN_PWM1_A,\n-\tGFN_PWM0,\n-\tGFN_IRQ5,\n-\tGFN_IRQ4,\n-\tGFN_IRQ3,\n-\tGFN_IRQ2,\n-\tGFN_IRQ1,\n-\tGFN_IRQ0,\n-\n-\t/* GPSR3 */\n-\tGFN_SD1_WP,\n-\tGFN_SD1_CD,\n-\tGFN_SD0_WP,\n-\tGFN_SD0_CD,\n-\tGFN_SD1_DAT3,\n-\tGFN_SD1_DAT2,\n-\tGFN_SD1_DAT1,\n-\tGFN_SD1_DAT0,\n-\tGFN_SD1_CMD,\n-\tGFN_SD1_CLK,\n-\tGFN_SD0_DAT3,\n-\tGFN_SD0_DAT2,\n-\tGFN_SD0_DAT1,\n-\tGFN_SD0_DAT0,\n-\tGFN_SD0_CMD,\n-\tGFN_SD0_CLK,\n-\n-\t/* GPSR4 */\n-\tGFN_SD3_DS,\n-\tGFN_SD3_DAT7,\n-\tGFN_SD3_DAT6,\n-\tGFN_SD3_DAT5,\n-\tGFN_SD3_DAT4,\n-\tGFN_SD3_DAT3,\n-\tGFN_SD3_DAT2,\n-\tGFN_SD3_DAT1,\n-\tGFN_SD3_DAT0,\n-\tGFN_SD3_CMD,\n-\tGFN_SD3_CLK,\n-\tGFN_SD2_DS,\n-\tGFN_SD2_DAT3,\n-\tGFN_SD2_DAT2,\n-\tGFN_SD2_DAT1,\n-\tGFN_SD2_DAT0,\n-\tGFN_SD2_CMD,\n-\tGFN_SD2_CLK,\n-\n-\t/* GPSR5 */\n-\tGFN_MLB_DAT,\n-\tGFN_MLB_SIG,\n-\tGFN_MLB_CLK,\n-\tFN_MSIOF0_RXD,\n-\tGFN_MSIOF0_SS2,\n-\tFN_MSIOF0_TXD,\n-\tGFN_MSIOF0_SS1,\n-\tGFN_MSIOF0_SYNC,\n-\tFN_MSIOF0_SCK,\n-\tGFN_HRTS0x,\n-\tGFN_HCTS0x,\n-\tGFN_HTX0,\n-\tGFN_HRX0,\n-\tGFN_HSCK0,\n-\tGFN_RX2_A,\n-\tGFN_TX2_A,\n-\tGFN_SCK2,\n-\tGFN_RTS1x_TANS,\n-\tGFN_CTS1x,\n-\tGFN_TX1_A,\n-\tGFN_RX1_A,\n-\tGFN_RTS0x_TANS,\n-\tGFN_CTS0x,\n-\tGFN_TX0,\n-\tGFN_RX0,\n-\tGFN_SCK0,\n-\n-\t/* GPSR6 */\n-\tGFN_USB3_OVC,\n-\tGFN_USB3_PWEN,\n-\tGFN_USB30_OVC,\n-\tGFN_USB30_PWEN,\n-\tGFN_USB1_OVC,\n-\tGFN_USB1_PWEN,\n-\tGFN_USB0_OVC,\n-\tGFN_USB0_PWEN,\n-\tGFN_AUDIO_CLKB_B,\n-\tGFN_AUDIO_CLKA_A,\n-\tGFN_SSI_SDATA9_A,\n-\tGFN_SSI_SDATA8,\n-\tGFN_SSI_SDATA7,\n-\tGFN_SSI_WS78,\n-\tGFN_SSI_SCK78,\n-\tGFN_SSI_SDATA6,\n-\tGFN_SSI_WS6,\n-\tGFN_SSI_SCK6,\n-\tFN_SSI_SDATA5,\n-\tFN_SSI_WS5,\n-\tFN_SSI_SCK5,\n-\tGFN_SSI_SDATA4,\n-\tGFN_SSI_WS4,\n-\tGFN_SSI_SCK4,\n-\tGFN_SSI_SDATA3,\n-\tGFN_SSI_WS34,\n-\tGFN_SSI_SCK34,\n-\tGFN_SSI_SDATA2_A,\n-\tGFN_SSI_SDATA1_A,\n-\tGFN_SSI_SDATA0,\n-\tGFN_SSI_WS01239,\n-\tGFN_SSI_SCK01239,\n-\n-\t/* GPSR7 */\n-\tFN_HDMI1_CEC,\n-\tFN_HDMI0_CEC,\n-\tFN_AVS2,\n-\tFN_AVS1,\n-\n-\t/* IPSR0 */\n-\tIFN_AVB_MDC,\n-\tFN_MSIOF2_SS2_C,\n-\tIFN_AVB_MAGIC,\n-\tFN_MSIOF2_SS1_C,\n-\tFN_SCK4_A,\n-\tIFN_AVB_PHY_INT,\n-\tFN_MSIOF2_SYNC_C,\n-\tFN_RX4_A,\n-\tIFN_AVB_LINK,\n-\tFN_MSIOF2_SCK_C,\n-\tFN_TX4_A,\n-\tIFN_AVB_AVTP_MATCH_A,\n-\tFN_MSIOF2_RXD_C,\n-\tFN_CTS4x_A,\n-\tFN_FSCLKST2x_A,\n-\tIFN_AVB_AVTP_CAPTURE_A,\n-\tFN_MSIOF2_TXD_C,\n-\tFN_RTS4x_TANS_A,\n-\tIFN_IRQ0,\n-\tFN_QPOLB,\n-\tFN_DU_CDE,\n-\tFN_VI4_DATA0_B,\n-\tFN_CAN0_TX_B,\n-\tFN_CANFD0_TX_B,\n-\tFN_MSIOF3_SS2_E,\n-\tIFN_IRQ1,\n-\tFN_QPOLA,\n-\tFN_DU_DISP,\n-\tFN_VI4_DATA1_B,\n-\tFN_CAN0_RX_B,\n-\tFN_CANFD0_RX_B,\n-\tFN_MSIOF3_SS1_E,\n-\n-\t/* IPSR1 */\n-\tIFN_IRQ2,\n-\tFN_QCPV_QDE,\n-\tFN_DU_EXODDF_DU_ODDF_DISP_CDE,\n-\tFN_VI4_DATA2_B,\n-\tFN_MSIOF3_SYNC_E,\n-\tFN_PWM3_B,\n-\tIFN_IRQ3,\n-\tFN_QSTVB_QVE,\n-\tFN_DU_DOTCLKOUT1,\n-\tFN_VI4_DATA3_B,\n-\tFN_MSIOF3_SCK_E,\n-\tFN_PWM4_B,\n-\tIFN_IRQ4,\n-\tFN_QSTH_QHS,\n-\tFN_DU_EXHSYNC_DU_HSYNC,\n-\tFN_VI4_DATA4_B,\n-\tFN_MSIOF3_RXD_E,\n-\tFN_PWM5_B,\n-\tIFN_IRQ5,\n-\tFN_QSTB_QHE,\n-\tFN_DU_EXVSYNC_DU_VSYNC,\n-\tFN_VI4_DATA5_B,\n-\tFN_FSCLKST2x_B,\n-\tFN_MSIOF3_TXD_E,\n-\tFN_PWM6_B,\n-\tIFN_PWM0,\n-\tFN_AVB_AVTP_PPS,\n-\tFN_VI4_DATA6_B,\n-\tFN_IECLK_B,\n-\tIFN_PWM1_A,\n-\tFN_HRX3_D,\n-\tFN_VI4_DATA7_B,\n-\tFN_IERX_B,\n-\tIFN_PWM2_A,\n-\tFN_HTX3_D,\n-\tFN_IETX_B,\n-\tIFN_A0,\n-\tFN_LCDOUT16,\n-\tFN_MSIOF3_SYNC_B,\n-\tFN_VI4_DATA8,\n-\tFN_DU_DB0,\n-\tFN_PWM3_A,\n-\n-\t/* IPSR2 */\n-\tIFN_A1,\n-\tFN_LCDOUT17,\n-\tFN_MSIOF3_TXD_B,\n-\tFN_VI4_DATA9,\n-\tFN_DU_DB1,\n-\tFN_PWM4_A,\n-\tIFN_A2,\n-\tFN_LCDOUT18,\n-\tFN_MSIOF3_SCK_B,\n-\tFN_VI4_DATA10,\n-\tFN_DU_DB2,\n-\tFN_PWM5_A,\n-\tIFN_A3,\n-\tFN_LCDOUT19,\n-\tFN_MSIOF3_RXD_B,\n-\tFN_VI4_DATA11,\n-\tFN_DU_DB3,\n-\tFN_PWM6_A,\n-\tIFN_A4,\n-\tFN_LCDOUT20,\n-\tFN_MSIOF3_SS1_B,\n-\tFN_VI4_DATA12,\n-\tFN_VI5_DATA12,\n-\tFN_DU_DB4,\n-\tIFN_A5,\n-\tFN_LCDOUT21,\n-\tFN_MSIOF3_SS2_B,\n-\tFN_SCK4_B,\n-\tFN_VI4_DATA13,\n-\tFN_VI5_DATA13,\n-\tFN_DU_DB5,\n-\tIFN_A6,\n-\tFN_LCDOUT22,\n-\tFN_MSIOF2_SS1_A,\n-\tFN_RX4_B,\n-\tFN_VI4_DATA14,\n-\tFN_VI5_DATA14,\n-\tFN_DU_DB6,\n-\tIFN_A7,\n-\tFN_LCDOUT23,\n-\tFN_MSIOF2_SS2_A,\n-\tFN_TX4_B,\n-\tFN_VI4_DATA15,\n-\tFN_V15_DATA15,\n-\tFN_DU_DB7,\n-\tIFN_A8,\n-\tFN_RX3_B,\n-\tFN_MSIOF2_SYNC_A,\n-\tFN_HRX4_B,\n-\tFN_SDA6_A,\n-\tFN_AVB_AVTP_MATCH_B,\n-\tFN_PWM1_B,\n-\n-\t/* IPSR3 */\n-\tIFN_A9,\n-\tFN_MSIOF2_SCK_A,\n-\tFN_CTS4x_B,\n-\tFN_VI5_VSYNCx,\n-\tIFN_A10,\n-\tFN_MSIOF2_RXD_A,\n-\tFN_RTS4n_TANS_B,\n-\tFN_VI5_HSYNCx,\n-\tIFN_A11,\n-\tFN_TX3_B,\n-\tFN_MSIOF2_TXD_A,\n-\tFN_HTX4_B,\n-\tFN_HSCK4,\n-\tFN_VI5_FIELD,\n-\tFN_SCL6_A,\n-\tFN_AVB_AVTP_CAPTURE_B,\n-\tFN_PWM2_B,\n-\tIFN_A12,\n-\tFN_LCDOUT12,\n-\tFN_MSIOF3_SCK_C,\n-\tFN_HRX4_A,\n-\tFN_VI5_DATA8,\n-\tFN_DU_DG4,\n-\tIFN_A13,\n-\tFN_LCDOUT13,\n-\tFN_MSIOF3_SYNC_C,\n-\tFN_HTX4_A,\n-\tFN_VI5_DATA9,\n-\tFN_DU_DG5,\n-\tIFN_A14,\n-\tFN_LCDOUT14,\n-\tFN_MSIOF3_RXD_C,\n-\tFN_HCTS4x,\n-\tFN_VI5_DATA10,\n-\tFN_DU_DG6,\n-\tIFN_A15,\n-\tFN_LCDOUT15,\n-\tFN_MSIOF3_TXD_C,\n-\tFN_HRTS4x,\n-\tFN_VI5_DATA11,\n-\tFN_DU_DG7,\n-\tIFN_A16,\n-\tFN_LCDOUT8,\n-\tFN_VI4_FIELD,\n-\tFN_DU_DG0,\n-\n-\t/* IPSR4 */\n-\tIFN_A17,\n-\tFN_LCDOUT9,\n-\tFN_VI4_VSYNCx,\n-\tFN_DU_DG1,\n-\tIFN_A18,\n-\tFN_LCDOUT10,\n-\tFN_VI4_HSYNCx,\n-\tFN_DU_DG2,\n-\tIFN_A19,\n-\tFN_LCDOUT11,\n-\tFN_VI4_CLKENB,\n-\tFN_DU_DG3,\n-\tIFN_CS0x,\n-\tFN_VI5_CLKENB,\n-\tIFN_CS1x_A26,\n-\tFN_VI5_CLK,\n-\tFN_EX_WAIT0_B,\n-\tIFN_BSx,\n-\tFN_QSTVA_QVS,\n-\tFN_MSIOF3_SCK_D,\n-\tFN_SCK3,\n-\tFN_HSCK3,\n-\tFN_CAN1_TX,\n-\tFN_CANFD1_TX,\n-\tFN_IETX_A,\n-\tIFN_RDx,\n-\tFN_MSIOF3_SYNC_D,\n-\tFN_RX3_A,\n-\tFN_HRX3_A,\n-\tFN_CAN0_TX_A,\n-\tFN_CANFD0_TX_A,\n-\tIFN_RD_WRx,\n-\tFN_MSIOF3_RXD_D,\n-\tFN_TX3_A,\n-\tFN_HTX3_A,\n-\tFN_CAN0_RX_A,\n-\tFN_CANFD0_RX_A,\n-\n-\t/* IPSR5 */\n-\tIFN_WE0x,\n-\tFN_MSIIOF3_TXD_D,\n-\tFN_CTS3x,\n-\tFN_HCTS3x,\n-\tFN_SCL6_B,\n-\tFN_CAN_CLK,\n-\tFN_IECLK_A,\n-\tIFN_WE1x,\n-\tFN_MSIOF3_SS1_D,\n-\tFN_RTS3x_TANS,\n-\tFN_HRTS3x,\n-\tFN_SDA6_B,\n-\tFN_CAN1_RX,\n-\tFN_CANFD1_RX,\n-\tFN_IERX_A,\n-\tIFN_EX_WAIT0_A,\n-\tFN_QCLK,\n-\tFN_VI4_CLK,\n-\tFN_DU_DOTCLKOUT0,\n-\tIFN_D0,\n-\tFN_MSIOF2_SS1_B,\n-\tFN_MSIOF3_SCK_A,\n-\tFN_VI4_DATA16,\n-\tFN_VI5_DATA0,\n-\tIFN_D1,\n-\tFN_MSIOF2_SS2_B,\n-\tFN_MSIOF3_SYNC_A,\n-\tFN_VI4_DATA17,\n-\tFN_VI5_DATA1,\n-\tIFN_D2,\n-\tFN_MSIOF3_RXD_A,\n-\tFN_VI4_DATA18,\n-\tFN_VI5_DATA2,\n-\tIFN_D3,\n-\tFN_MSIOF3_TXD_A,\n-\tFN_VI4_DATA19,\n-\tFN_VI5_DATA3,\n-\tIFN_D4,\n-\tFN_MSIOF2_SCK_B,\n-\tFN_VI4_DATA20,\n-\tFN_VI5_DATA4,\n-\n-\t/* IPSR6 */\n-\tIFN_D5,\n-\tFN_MSIOF2_SYNC_B,\n-\tFN_VI4_DATA21,\n-\tFN_VI5_DATA5,\n-\tIFN_D6,\n-\tFN_MSIOF2_RXD_B,\n-\tFN_VI4_DATA22,\n-\tFN_VI5_DATA6,\n-\tIFN_D7,\n-\tFN_MSIOF2_TXD_B,\n-\tFN_VI4_DATA23,\n-\tFN_VI5_DATA7,\n-\tIFN_D8,\n-\tFN_LCDOUT0,\n-\tFN_MSIOF2_SCK_D,\n-\tFN_SCK4_C,\n-\tFN_VI4_DATA0_A,\n-\tFN_DU_DR0,\n-\tIFN_D9,\n-\tFN_LCDOUT1,\n-\tFN_MSIOF2_SYNC_D,\n-\tFN_VI4_DATA1_A,\n-\tFN_DU_DR1,\n-\tIFN_D10,\n-\tFN_LCDOUT2,\n-\tFN_MSIOF2_RXD_D,\n-\tFN_HRX3_B,\n-\tFN_VI4_DATA2_A,\n-\tFN_CTS4x_C,\n-\tFN_DU_DR2,\n-\tIFN_D11,\n-\tFN_LCDOUT3,\n-\tFN_MSIOF2_TXD_D,\n-\tFN_HTX3_B,\n-\tFN_VI4_DATA3_A,\n-\tFN_RTS4x_TANS_C,\n-\tFN_DU_DR3,\n-\tIFN_D12,\n-\tFN_LCDOUT4,\n-\tFN_MSIOF2_SS1_D,\n-\tFN_RX4_C,\n-\tFN_VI4_DATA4_A,\n-\tFN_DU_DR4,\n-\n-\t/* IPSR7 */\n-\tIFN_D13,\n-\tFN_LCDOUT5,\n-\tFN_MSIOF2_SS2_D,\n-\tFN_TX4_C,\n-\tFN_VI4_DATA5_A,\n-\tFN_DU_DR5,\n-\tIFN_D14,\n-\tFN_LCDOUT6,\n-\tFN_MSIOF3_SS1_A,\n-\tFN_HRX3_C,\n-\tFN_VI4_DATA6_A,\n-\tFN_DU_DR6,\n-\tFN_SCL6_C,\n-\tIFN_D15,\n-\tFN_LCDOUT7,\n-\tFN_MSIOF3_SS2_A,\n-\tFN_HTX3_C,\n-\tFN_VI4_DATA7_A,\n-\tFN_DU_DR7,\n-\tFN_SDA6_C,\n-\tFN_FSCLKST,\n-\tIFN_SD0_CLK,\n-\tFN_MSIOF1_SCK_E,\n-\tFN_STP_OPWM_0_B,\n-\tIFN_SD0_CMD,\n-\tFN_MSIOF1_SYNC_E,\n-\tFN_STP_IVCXO27_0_B,\n-\tIFN_SD0_DAT0,\n-\tFN_MSIOF1_RXD_E,\n-\tFN_TS_SCK0_B,\n-\tFN_STP_ISCLK_0_B,\n-\tIFN_SD0_DAT1,\n-\tFN_MSIOF1_TXD_E,\n-\tFN_TS_SPSYNC0_B,\n-\tFN_STP_ISSYNC_0_B,\n-\n-\t/* IPSR8 */\n-\tIFN_SD0_DAT2,\n-\tFN_MSIOF1_SS1_E,\n-\tFN_TS_SDAT0_B,\n-\tFN_STP_ISD_0_B,\n-\tIFN_SD0_DAT3,\n-\tFN_MSIOF1_SS2_E,\n-\tFN_TS_SDEN0_B,\n-\tFN_STP_ISEN_0_B,\n-\tIFN_SD1_CLK,\n-\tFN_MSIOF1_SCK_G,\n-\tFN_SIM0_CLK_A,\n-\tIFN_SD1_CMD,\n-\tFN_MSIOF1_SYNC_G,\n-\tFN_NFCEx_B,\n-\tFN_SIM0_D_A,\n-\tFN_STP_IVCXO27_1_B,\n-\tIFN_SD1_DAT0,\n-\tFN_SD2_DAT4,\n-\tFN_MSIOF1_RXD_G,\n-\tFN_NFWPx_B,\n-\tFN_TS_SCK1_B,\n-\tFN_STP_ISCLK_1_B,\n-\tIFN_SD1_DAT1,\n-\tFN_SD2_DAT5,\n-\tFN_MSIOF1_TXD_G,\n-\tFN_NFDATA14_B,\n-\tFN_TS_SPSYNC1_B,\n-\tFN_STP_ISSYNC_1_B,\n-\tIFN_SD1_DAT2,\n-\tFN_SD2_DAT6,\n-\tFN_MSIOF1_SS1_G,\n-\tFN_NFDATA15_B,\n-\tFN_TS_SDAT1_B,\n-\tFN_STP_IOD_1_B,\n-\tIFN_SD1_DAT3,\n-\tFN_SD2_DAT7,\n-\tFN_MSIOF1_SS2_G,\n-\tFN_NFRBx_B,\n-\tFN_TS_SDEN1_B,\n-\tFN_STP_ISEN_1_B,\n-\n-\t/* IPSR9 */\n-\tIFN_SD2_CLK,\n-\tFN_NFDATA8,\n-\tIFN_SD2_CMD,\n-\tFN_NFDATA9,\n-\tIFN_SD2_DAT0,\n-\tFN_NFDATA10,\n-\tIFN_SD2_DAT1,\n-\tFN_NFDATA11,\n-\tIFN_SD2_DAT2,\n-\tFN_NFDATA12,\n-\tIFN_SD2_DAT3,\n-\tFN_NFDATA13,\n-\tIFN_SD2_DS,\n-\tFN_NFALE,\n-\tFN_SATA_DEVSLP_B,\n-\tIFN_SD3_CLK,\n-\tFN_NFWEx,\n-\n-\t/* IPSR10 */\n-\tIFN_SD3_CMD,\n-\tFN_NFREx,\n-\tIFN_SD3_DAT0,\n-\tFN_NFDATA0,\n-\tIFN_SD3_DAT1,\n-\tFN_NFDATA1,\n-\tIFN_SD3_DAT2,\n-\tFN_NFDATA2,\n-\tIFN_SD3_DAT3,\n-\tFN_NFDATA3,\n-\tIFN_SD3_DAT4,\n-\tFN_SD2_CD_A,\n-\tFN_NFDATA4,\n-\tIFN_SD3_DAT5,\n-\tFN_SD2_WP_A,\n-\tFN_NFDATA5,\n-\tIFN_SD3_DAT6,\n-\tFN_SD3_CD,\n-\tFN_NFDATA6,\n-\n-\t/* IPSR11 */\n-\tIFN_SD3_DAT7,\n-\tFN_SD3_WP,\n-\tFN_NFDATA7,\n-\tIFN_SD3_DS,\n-\tFN_NFCLE,\n-\tIFN_SD0_CD,\n-\tFN_NFDATA14_A,\n-\tFN_SCL2_B,\n-\tFN_SIM0_RST_A,\n-\tIFN_SD0_WP,\n-\tFN_NFDATA15_A,\n-\tFN_SDA2_B,\n-\tIFN_SD1_CD,\n-\tFN_NFRBx_A,\n-\tFN_SIM0_CLK_B,\n-\tIFN_SD1_WP,\n-\tFN_NFCEx_A,\n-\tFN_SIM0_D_B,\n-\tIFN_SCK0,\n-\tFN_HSCK1_B,\n-\tFN_MSIOF1_SS2_B,\n-\tFN_AUDIO_CLKC_B,\n-\tFN_SDA2_A,\n-\tFN_SIM0_RST_B,\n-\tFN_STP_OPWM_0_C,\n-\tFN_RIF0_CLK_B,\n-\tFN_ADICHS2,\n-\tFN_SCK5_B,\n-\tIFN_RX0,\n-\tFN_HRX1_B,\n-\tFN_TS_SCK0_C,\n-\tFN_STP_ISCLK_0_C,\n-\tFN_RIF0_D0_B,\n-\n-\t/* IPSR12 */\n-\tIFN_TX0,\n-\tFN_HTX1_B,\n-\tFN_TS_SPSYNC0_C,\n-\tFN_STP_ISSYNC_0_C,\n-\tFN_RIF0_D1_B,\n-\tIFN_CTS0x,\n-\tFN_HCTS1x_B,\n-\tFN_MSIOF1_SYNC_B,\n-\tFN_TS_SPSYNC1_C,\n-\tFN_STP_ISSYNC_1_C,\n-\tFN_RIF1_SYNC_B,\n-\tFN_AUDIO_CLKOUT_C,\n-\tFN_ADICS_SAMP,\n-\tIFN_RTS0x_TANS,\n-\tFN_HRTS1x_B,\n-\tFN_MSIOF1_SS1_B,\n-\tFN_AUDIO_CLKA_B,\n-\tFN_SCL2_A,\n-\tFN_STP_IVCXO27_1_C,\n-\tFN_RIF0_SYNC_B,\n-\tFN_ADICHS1,\n-\tIFN_RX1_A,\n-\tFN_HRX1_A,\n-\tFN_TS_SDAT0_C,\n-\tFN_STP_ISD_0_C,\n-\tFN_RIF1_CLK_C,\n-\tIFN_TX1_A,\n-\tFN_HTX1_A,\n-\tFN_TS_SDEN0_C,\n-\tFN_STP_ISEN_0_C,\n-\tFN_RIF1_D0_C,\n-\tIFN_CTS1x,\n-\tFN_HCTS1x_A,\n-\tFN_MSIOF1_RXD_B,\n-\tFN_TS_SDEN1_C,\n-\tFN_STP_ISEN_1_C,\n-\tFN_RIF1_D0_B,\n-\tFN_ADIDATA,\n-\tIFN_RTS1x_TANS,\n-\tFN_HRTS1x_A,\n-\tFN_MSIOF1_TXD_B,\n-\tFN_TS_SDAT1_C,\n-\tFN_STP_ISD_1_C,\n-\tFN_RIF1_D1_B,\n-\tFN_ADICHS0,\n-\tIFN_SCK2,\n-\tFN_SCIF_CLK_B,\n-\tFN_MSIOF1_SCK_B,\n-\tFN_TS_SCK1_C,\n-\tFN_STP_ISCLK_1_C,\n-\tFN_RIF1_CLK_B,\n-\tFN_ADICLK,\n-\n-\t/* IPSR13 */\n-\tIFN_TX2_A,\n-\tFN_SD2_CD_B,\n-\tFN_SCL1_A,\n-\tFN_FMCLK_A,\n-\tFN_RIF1_D1_C,\n-\tFN_FSO_CFE_0x,\n-\tIFN_RX2_A,\n-\tFN_SD2_WP_B,\n-\tFN_SDA1_A,\n-\tFN_FMIN_A,\n-\tFN_RIF1_SYNC_C,\n-\tFN_FSO_CFE_1x,\n-\tIFN_HSCK0,\n-\tFN_MSIOF1_SCK_D,\n-\tFN_AUDIO_CLKB_A,\n-\tFN_SSI_SDATA1_B,\n-\tFN_TS_SCK0_D,\n-\tFN_STP_ISCLK_0_D,\n-\tFN_RIF0_CLK_C,\n-\tFN_RX5_B,\n-\tIFN_HRX0,\n-\tFN_MSIOF1_RXD_D,\n-\tFN_SSI_SDATA2_B,\n-\tFN_TS_SDEN0_D,\n-\tFN_STP_ISEN_0_D,\n-\tFN_RIF0_D0_C,\n-\tIFN_HTX0,\n-\tFN_MSIOF1_TXD_D,\n-\tFN_SSI_SDATA9_B,\n-\tFN_TS_SDAT0_D,\n-\tFN_STP_ISD_0_D,\n-\tFN_RIF0_D1_C,\n-\tIFN_HCTS0x,\n-\tFN_RX2_B,\n-\tFN_MSIOF1_SYNC_D,\n-\tFN_SSI_SCK9_A,\n-\tFN_TS_SPSYNC0_D,\n-\tFN_STP_ISSYNC_0_D,\n-\tFN_RIF0_SYNC_C,\n-\tFN_AUDIO_CLKOUT1_A,\n-\tIFN_HRTS0x,\n-\tFN_TX2_B,\n-\tFN_MSIOF1_SS1_D,\n-\tFN_SSI_WS9_A,\n-\tFN_STP_IVCXO27_0_D,\n-\tFN_BPFCLK_A,\n-\tFN_AUDIO_CLKOUT2_A,\n-\tIFN_MSIOF0_SYNC,\n-\tFN_AUDIO_CLKOUT_A,\n-\tFN_TX5_B,\n-\tFN_BPFCLK_D,\n-\n-\t/* IPSR14 */\n-\tIFN_MSIOF0_SS1,\n-\tFN_RX5_A,\n-\tFN_NFWPx_A,\n-\tFN_AUDIO_CLKA_C,\n-\tFN_SSI_SCK2_A,\n-\tFN_STP_IVCXO27_0_C,\n-\tFN_AUDIO_CLKOUT3_A,\n-\tFN_TCLK1_B,\n-\tIFN_MSIOF0_SS2,\n-\tFN_TX5_A,\n-\tFN_MSIOF1_SS2_D,\n-\tFN_AUDIO_CLKC_A,\n-\tFN_SSI_WS2_A,\n-\tFN_STP_OPWM_0_D,\n-\tFN_AUDIO_CLKOUT_D,\n-\tFN_SPEEDIN_B,\n-\tIFN_MLB_CLK,\n-\tFN_MSIOF1_SCK_F,\n-\tFN_SCL1_B,\n-\tIFN_MLB_SIG,\n-\tFN_RX1_B,\n-\tFN_MSIOF1_SYNC_F,\n-\tFN_SDA1_B,\n-\tIFN_MLB_DAT,\n-\tFN_TX1_B,\n-\tFN_MSIOF1_RXD_F,\n-\tIFN_SSI_SCK01239,\n-\tFN_MSIOF1_TXD_F,\n-\tFN_MOUT0,\n-\tIFN_SSI_WS01239,\n-\tFN_MSIOF1_SS1_F,\n-\tFN_MOUT1,\n-\tIFN_SSI_SDATA0,\n-\tFN_MSIOF1_SS2_F,\n-\tFN_MOUT2,\n-\n-\t/* IPSR15 */\n-\tIFN_SSI_SDATA1_A,\n-\tFN_MOUT5,\n-\tIFN_SSI_SDATA2_A,\n-\tFN_SSI_SCK1_B,\n-\tFN_MOUT6,\n-\tIFN_SSI_SCK34,\n-\tFN_MSIOF1_SS1_A,\n-\tFN_STP_OPWM_0_A,\n-\tIFN_SSI_WS34,\n-\tFN_HCTS2x_A,\n-\tFN_MSIOF1_SS2_A,\n-\tFN_STP_IVCXO27_0_A,\n-\tIFN_SSI_SDATA3,\n-\tFN_HRTS2x_A,\n-\tFN_MSIOF1_TXD_A,\n-\tFN_TS_SCK0_A,\n-\tFN_STP_ISCLK_0_A,\n-\tFN_RIF0_D1_A,\n-\tFN_RIF2_D0_A,\n-\tIFN_SSI_SCK4,\n-\tFN_HRX2_A,\n-\tFN_MSIOF1_SCK_A,\n-\tFN_TS_SDAT0_A,\n-\tFN_STP_ISD_0_A,\n-\tFN_RIF0_CLK_A,\n-\tFN_RIF2_CLK_A,\n-\tIFN_SSI_WS4,\n-\tFN_HTX2_A,\n-\tFN_MSIOF1_SYNC_A,\n-\tFN_TS_SDEN0_A,\n-\tFN_STP_ISEN_0_A,\n-\tFN_RIF0_SYNC_A,\n-\tFN_RIF2_SYNC_A,\n-\tIFN_SSI_SDATA4,\n-\tFN_HSCK2_A,\n-\tFN_MSIOF1_RXD_A,\n-\tFN_TS_SPSYNC0_A,\n-\tFN_STP_ISSYNC_0_A,\n-\tFN_RIF0_D0_A,\n-\tFN_RIF2_D1_A,\n-\n-\t/* IPSR16 */\n-\tIFN_SSI_SCK6,\n-\tFN_SIM0_RST_D,\n-\tIFN_SSI_WS6,\n-\tFN_SIM0_D_D,\n-\tIFN_SSI_SDATA6,\n-\tFN_SIM0_CLK_D,\n-\tFN_SATA_DEVSLP_A,\n-\tIFN_SSI_SCK78,\n-\tFN_HRX2_B,\n-\tFN_MSIOF1_SCK_C,\n-\tFN_TS_SCK1_A,\n-\tFN_STP_ISCLK_1_A,\n-\tFN_RIF1_CLK_A,\n-\tFN_RIF3_CLK_A,\n-\tIFN_SSI_WS78,\n-\tFN_HTX2_B,\n-\tFN_MSIOF1_SYNC_C,\n-\tFN_TS_SDAT1_A,\n-\tFN_STP_ISD_1_A,\n-\tFN_RIF1_SYNC_A,\n-\tFN_RIF3_SYNC_A,\n-\tIFN_SSI_SDATA7,\n-\tFN_HCTS2x_B,\n-\tFN_MSIOF1_RXD_C,\n-\tFN_TS_SDEN1_A,\n-\tFN_STP_ISEN_1_A,\n-\tFN_RIF1_D0_A,\n-\tFN_RIF3_D0_A,\n-\tFN_TCLK2_A,\n-\tIFN_SSI_SDATA8,\n-\tFN_HRTS2x_B,\n-\tFN_MSIOF1_TXD_C,\n-\tFN_TS_SPSYNC1_A,\n-\tFN_STP_ISSYNC_1_A,\n-\tFN_RIF1_D1_A,\n-\tFN_RIF3_D1_A,\n-\tIFN_SSI_SDATA9_A,\n-\tFN_HSCK2_B,\n-\tFN_MSIOF1_SS1_C,\n-\tFN_HSCK1_A,\n-\tFN_SSI_WS1_B,\n-\tFN_SCK1,\n-\tFN_STP_IVCXO27_1_A,\n-\tFN_SCK5_A,\n-\n-\t/* IPSR17 */\n-\tIFN_AUDIO_CLKA_A,\n-\tFN_CC5_OSCOUT,\n-\tIFN_AUDIO_CLKB_B,\n-\tFN_SCIF_CLK_A,\n-\tFN_STP_IVCXO27_1_D,\n-\tFN_REMOCON_A,\n-\tFN_TCLK1_A,\n-\tIFN_USB0_PWEN,\n-\tFN_SIM0_RST_C,\n-\tFN_TS_SCK1_D,\n-\tFN_STP_ISCLK_1_D,\n-\tFN_BPFCLK_B,\n-\tFN_RIF3_CLK_B,\n-\tFN_HSCK2_C,\n-\tIFN_USB0_OVC,\n-\tFN_SIM0_D_C,\n-\tFN_TS_SDAT1_D,\n-\tFN_STP_ISD_1_D,\n-\tFN_RIF3_SYNC_B,\n-\tFN_HRX2_C,\n-\tIFN_USB1_PWEN,\n-\tFN_SIM0_CLK_C,\n-\tFN_SSI_SCK1_A,\n-\tFN_TS_SCK0_E,\n-\tFN_STP_ISCLK_0_E,\n-\tFN_FMCLK_B,\n-\tFN_RIF2_CLK_B,\n-\tFN_SPEEDIN_A,\n-\tFN_HTX2_C,\n-\tIFN_USB1_OVC,\n-\tFN_MSIOF1_SS2_C,\n-\tFN_SSI_WS1_A,\n-\tFN_TS_SDAT0_E,\n-\tFN_STP_ISD_0_E,\n-\tFN_FMIN_B,\n-\tFN_RIF2_SYNC_B,\n-\tFN_REMOCON_B,\n-\tFN_HCTS2x_C,\n-\tIFN_USB30_PWEN,\n-\tFN_AUDIO_CLKOUT_B,\n-\tFN_SSI_SCK2_B,\n-\tFN_TS_SDEN1_D,\n-\tFN_STP_ISEN_1_D,\n-\tFN_STP_OPWM_0_E,\n-\tFN_RIF3_D0_B,\n-\tFN_TCLK2_B,\n-\tFN_TPU0TO0,\n-\tFN_BPFCLK_C,\n-\tFN_HRTS2x_C,\n-\tIFN_USB30_OVC,\n-\tFN_AUDIO_CLKOUT1_B,\n-\tFN_SSI_WS2_B,\n-\tFN_TS_SPSYNC1_D,\n-\tFN_STP_ISSYNC_1_D,\n-\tFN_STP_IVCXO27_0_E,\n-\tFN_RIF3_D1_B,\n-\tFN_FSO_TOEx,\n-\tFN_TPU0TO1,\n-\n-\t/* IPSR18 */\n-\tIFN_USB3_PWEN,\n-\tFN_AUDIO_CLKOUT2_B,\n-\tFN_SSI_SCK9_B,\n-\tFN_TS_SDEN0_E,\n-\tFN_STP_ISEN_0_E,\n-\tFN_RIF2_D0_B,\n-\tFN_TPU0TO2,\n-\tFN_FMCLK_C,\n-\tFN_FMCLK_D,\n-\tIFN_USB3_OVC,\n-\tFN_AUDIO_CLKOUT3_B,\n-\tFN_SSI_WS9_B,\n-\tFN_TS_SPSYNC0_E,\n-\tFN_STP_ISSYNC_0_E,\n-\tFN_RIF2_D1_B,\n-\tFN_TPU0TO3,\n-\tFN_FMIN_C,\n-\tFN_FMIN_D,\n-\n-\t/* MOD_SEL0 */\n-\t/* sel_msiof3[3](0,1,2,3,4) */\n-\tFN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1,\n-\tFN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3,\n-\tFN_SEL_MSIOF3_4,\n-\t/* sel_msiof2[2](0,1,2,3) */\n-\tFN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1,\n-\tFN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3,\n-\t/* sel_msiof1[3](0,1,2,3,4,5,6) */\n-\tFN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,\n-\tFN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3,\n-\tFN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5,\n-\tFN_SEL_MSIOF1_6,\n-\t/* sel_lbsc[1](0,1) */\n-\tFN_SEL_LBSC_0, FN_SEL_LBSC_1,\n-\t/* sel_iebus[1](0,1) */\n-\tFN_SEL_IEBUS_0, FN_SEL_IEBUS_1,\n-\t/* sel_i2c2[1](0,1) */\n-\tFN_SEL_I2C2_0, FN_SEL_I2C2_1,\n-\t/* sel_i2c1[1](0,1) */\n-\tFN_SEL_I2C1_0, FN_SEL_I2C1_1,\n-\t/* sel_hscif4[1](0,1) */\n-\tFN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1,\n-\t/* sel_hscif3[2](0,1,2,3) */\n-\tFN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1,\n-\tFN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3,\n-\t/* sel_hscif1[1](0,1) */\n-\tFN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,\n-\t/* reserved[1] */\n-\t/* sel_hscif2[2](0,1,2) */\n-\tFN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,\n-\tFN_SEL_HSCIF2_2,\n-\t/* sel_etheravb[1](0,1) */\n-\tFN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1,\n-\t/* sel_drif3[1](0,1) */\n-\tFN_SEL_DRIF3_0, FN_SEL_DRIF3_1,\n-\t/* sel_drif2[1](0,1) */\n-\tFN_SEL_DRIF2_0, FN_SEL_DRIF2_1,\n-\t/* sel_drif1[2](0,1,2) */\n-\tFN_SEL_DRIF1_0, FN_SEL_DRIF1_1,\n-\tFN_SEL_DRIF1_2,\n-\t/* sel_drif0[2](0,1,2) */\n-\tFN_SEL_DRIF0_0, FN_SEL_DRIF0_1,\n-\tFN_SEL_DRIF0_2,\n-\t/* sel_canfd0[1](0,1) */\n-\tFN_SEL_CANFD_0, FN_SEL_CANFD_1,\n-\t/* sel_adg_a[2](0,1,2) */\n-\tFN_SEL_ADG_A_0, FN_SEL_ADG_A_1,\n-\tFN_SEL_ADG_A_2,\n-\t/* reserved[3]*/\n-\n-\t/* MOD_SEL1 */\n-\t/* sel_tsif1[2](0,1,2,3) */\n-\tFN_SEL_TSIF1_0, FN_SEL_TSIF1_1,\n-\tFN_SEL_TSIF1_2, FN_SEL_TSIF1_3,\n-\t/* sel_tsif0[3](0,1,2,3,4) */\n-\tFN_SEL_TSIF0_0, FN_SEL_TSIF0_1,\n-\tFN_SEL_TSIF0_2, FN_SEL_TSIF0_3,\n-\tFN_SEL_TSIF0_4,\n-\t/* sel_timer_tmu1[1](0,1) */\n-\tFN_SEL_TIMER_TMU1_0, FN_SEL_TIMER_TMU1_1,\n-\t/* sel_ssp1_1[2](0,1,2,3) */\n-\tFN_SEL_SSP1_1_0, FN_SEL_SSP1_1_1,\n-\tFN_SEL_SSP1_1_2, FN_SEL_SSP1_1_3,\n-\t/* sel_ssp1_0[3](0,1,2,3,4) */\n-\tFN_SEL_SSP1_0_0, FN_SEL_SSP1_0_1,\n-\tFN_SEL_SSP1_0_2, FN_SEL_SSP1_0_3,\n-\tFN_SEL_SSP1_0_4,\n-\t/* sel_ssi1[1](0,1) */\n-\tFN_SEL_SSI_0, FN_SEL_SSI_1,\n-\t/* sel_speed_pulse_if[1](0,1) */\n-\tFN_SEL_SPEED_PULSE_IF_0, FN_SEL_SPEED_PULSE_IF_1,\n-\t/* sel_simcard[2](0,1,2,3) */\n-\tFN_SEL_SIMCARD_0, FN_SEL_SIMCARD_1,\n-\tFN_SEL_SIMCARD_2, FN_SEL_SIMCARD_3,\n-\t/* sel_sdhi2[1](0,1) */\n-\tFN_SEL_SDHI2_0, FN_SEL_SDHI2_1,\n-\t/* sel_scif4[2](0,1,2) */\n-\tFN_SEL_SCIF4_0, FN_SEL_SCIF4_1,\n-\tFN_SEL_SCIF4_2,\n-\t/* sel_scif3[1](0,1) */\n-\tFN_SEL_SCIF3_0, FN_SEL_SCIF3_1,\n-\t/* sel_scif2[1](0,1) */\n-\tFN_SEL_SCIF2_0, FN_SEL_SCIF2_1,\n-\t/* sel_scif1[1](0,1) */\n-\tFN_SEL_SCIF1_0, FN_SEL_SCIF1_1,\n-\t/* sel_scif[1](0,1) */\n-\tFN_SEL_SCIF_0, FN_SEL_SCIF_1,\n-\t/* sel_remocon[1](0,1) */\n-\tFN_SEL_REMOCON_0, FN_SEL_REMOCON_1,\n-\t/* reserved[8..7] */\n-\t/* sel_rcan0[1](0,1) */\n-\tFN_SEL_RCAN_0, FN_SEL_RCAN_1,\n-\t/* sel_pwm6[1](0,1) */\n-\tFN_SEL_PWM6_0, FN_SEL_PWM6_1,\n-\t/* sel_pwm5[1](0,1) */\n-\tFN_SEL_PWM5_0, FN_SEL_PWM5_1,\n-\t/* sel_pwm4[1](0,1) */\n-\tFN_SEL_PWM4_0, FN_SEL_PWM4_1,\n-\t/* sel_pwm3[1](0,1) */\n-\tFN_SEL_PWM3_0, FN_SEL_PWM3_1,\n-\t/* sel_pwm2[1](0,1) */\n-\tFN_SEL_PWM2_0, FN_SEL_PWM2_1,\n-\t/* sel_pwm1[1](0,1) */\n-\tFN_SEL_PWM1_0, FN_SEL_PWM1_1,\n-\n-\t/* MOD_SEL2 */\n-\t/* i2c_sel_5[1](0,1) */\n-\tFN_I2C_SEL_5_0, FN_I2C_SEL_5_1,\n-\t/* i2c_sel_3[1](0,1) */\n-\tFN_I2C_SEL_3_0, FN_I2C_SEL_3_1,\n-\t/* i2c_sel_0[1](0,1) */\n-\tFN_I2C_SEL_0_0, FN_I2C_SEL_0_1,\n-\t/* sel_fm[2](0,1,2,3) */\n-\tFN_SEL_FM_0, FN_SEL_FM_1,\n-\tFN_SEL_FM_2, FN_SEL_FM_3,\n-\t/* sel_scif5[1](0,1) */\n-\tFN_SEL_SCIF5_0, FN_SEL_SCIF5_1,\n-\t/* sel_i2c6[3](0,1,2) */\n-\tFN_SEL_I2C6_0, FN_SEL_I2C6_1,\n-\tFN_SEL_I2C6_2,\n-\t/* sel_ndfc[1](0,1) */\n-\tFN_SEL_NDFC_0, FN_SEL_NDFC_1,\n-\t/* sel_ssi2[1](0,1) */\n-\tFN_SEL_SSI2_0, FN_SEL_SSI2_1,\n-\t/* sel_ssi9[1](0,1) */\n-\tFN_SEL_SSI9_0, FN_SEL_SSI9_1,\n-\t/* sel_timer_tmu2[1](0,1) */\n-\tFN_SEL_TIMER_TMU2_0, FN_SEL_TIMER_TMU2_1,\n-\t/* sel_adg_b[1](0,1) */\n-\tFN_SEL_ADG_B_0, FN_SEL_ADG_B_1,\n-\t/* sel_adg_c[1](0,1) */\n-\tFN_SEL_ADG_C_0, FN_SEL_ADG_C_1,\n-\t/* reserved[16..16] */\n-\t/* reserved[15..8] */\n-\t/* reserved[7..1] */\n-\t/* sel_vin4[1](0,1) */\n-\tFN_SEL_VIN4_0, FN_SEL_VIN4_1,\n-\n-\tPINMUX_FUNCTION_END,\n-\n-\tPINMUX_MARK_BEGIN,\n-\n-\t/* GPSR0 */\n-\tD15_GMARK,\n-\tD14_GMARK,\n-\tD13_GMARK,\n-\tD12_GMARK,\n-\tD11_GMARK,\n-\tD10_GMARK,\n-\tD9_GMARK,\n-\tD8_GMARK,\n-\tD7_GMARK,\n-\tD6_GMARK,\n-\tD5_GMARK,\n-\tD4_GMARK,\n-\tD3_GMARK,\n-\tD2_GMARK,\n-\tD1_GMARK,\n-\tD0_GMARK,\n-\n-\t/* GPSR1 */\n-\tCLKOUT_GMARK,\n-\tEX_WAIT0_A_GMARK,\n-\tWE1x_GMARK,\n-\tWE0x_GMARK,\n-\tRD_WRx_GMARK,\n-\tRDx_GMARK,\n-\tBSx_GMARK,\n-\tCS1x_A26_GMARK,\n-\tCS0x_GMARK,\n-\tA19_GMARK,\n-\tA18_GMARK,\n-\tA17_GMARK,\n-\tA16_GMARK,\n-\tA15_GMARK,\n-\tA14_GMARK,\n-\tA13_GMARK,\n-\tA12_GMARK,\n-\tA11_GMARK,\n-\tA10_GMARK,\n-\tA9_GMARK,\n-\tA8_GMARK,\n-\tA7_GMARK,\n-\tA6_GMARK,\n-\tA5_GMARK,\n-\tA4_GMARK,\n-\tA3_GMARK,\n-\tA2_GMARK,\n-\tA1_GMARK,\n-\tA0_GMARK,\n-\n-\t/* GPSR2 */\n-\tAVB_AVTP_CAPTURE_A_GMARK,\n-\tAVB_AVTP_MATCH_A_GMARK,\n-\tAVB_LINK_GMARK,\n-\tAVB_PHY_INT_GMARK,\n-\tAVB_MAGIC_GMARK,\n-\tAVB_MDC_GMARK,\n-\tPWM2_A_GMARK,\n-\tPWM1_A_GMARK,\n-\tPWM0_GMARK,\n-\tIRQ5_GMARK,\n-\tIRQ4_GMARK,\n-\tIRQ3_GMARK,\n-\tIRQ2_GMARK,\n-\tIRQ1_GMARK,\n-\tIRQ0_GMARK,\n-\n-\t/* GPSR3 */\n-\tSD1_WP_GMARK,\n-\tSD1_CD_GMARK,\n-\tSD0_WP_GMARK,\n-\tSD0_CD_GMARK,\n-\tSD1_DAT3_GMARK,\n-\tSD1_DAT2_GMARK,\n-\tSD1_DAT1_GMARK,\n-\tSD1_DAT0_GMARK,\n-\tSD1_CMD_GMARK,\n-\tSD1_CLK_GMARK,\n-\tSD0_DAT3_GMARK,\n-\tSD0_DAT2_GMARK,\n-\tSD0_DAT1_GMARK,\n-\tSD0_DAT0_GMARK,\n-\tSD0_CMD_GMARK,\n-\tSD0_CLK_GMARK,\n-\n-\t/* GPSR4 */\n-\tSD3_DS_GMARK,\n-\tSD3_DAT7_GMARK,\n-\tSD3_DAT6_GMARK,\n-\tSD3_DAT5_GMARK,\n-\tSD3_DAT4_GMARK,\n-\tSD3_DAT3_GMARK,\n-\tSD3_DAT2_GMARK,\n-\tSD3_DAT1_GMARK,\n-\tSD3_DAT0_GMARK,\n-\tSD3_CMD_GMARK,\n-\tSD3_CLK_GMARK,\n-\tSD2_DS_GMARK,\n-\tSD2_DAT3_GMARK,\n-\tSD2_DAT2_GMARK,\n-\tSD2_DAT1_GMARK,\n-\tSD2_DAT0_GMARK,\n-\tSD2_CMD_GMARK,\n-\tSD2_CLK_GMARK,\n-\n-\t/* GPSR5 */\n-\tMLB_DAT_GMARK,\n-\tMLB_SIG_GMARK,\n-\tMLB_CLK_GMARK,\n-\tMSIOF0_RXD_MARK,\n-\tMSIOF0_SS2_GMARK,\n-\tMSIOF0_TXD_MARK,\n-\tMSIOF0_SS1_GMARK,\n-\tMSIOF0_SYNC_GMARK,\n-\tMSIOF0_SCK_MARK,\n-\tHRTS0x_GMARK,\n-\tHCTS0x_GMARK,\n-\tHTX0_GMARK,\n-\tHRX0_GMARK,\n-\tHSCK0_GMARK,\n-\tRX2_A_GMARK,\n-\tTX2_A_GMARK,\n-\tSCK2_GMARK,\n-\tRTS1x_TANS_GMARK,\n-\tCTS1x_GMARK,\n-\tTX1_A_GMARK,\n-\tRX1_A_GMARK,\n-\tRTS0x_TANS_GMARK,\n-\tCTS0x_GMARK,\n-\tTX0_GMARK,\n-\tRX0_GMARK,\n-\tSCK0_GMARK,\n-\n-\t/* GPSR6 */\n-\tUSB3_OVC_GMARK,\n-\tUSB3_PWEN_GMARK,\n-\tUSB30_OVC_GMARK,\n-\tUSB30_PWEN_GMARK,\n-\tUSB1_OVC_GMARK,\n-\tUSB1_PWEN_GMARK,\n-\tUSB0_OVC_GMARK,\n-\tUSB0_PWEN_GMARK,\n-\tAUDIO_CLKB_B_GMARK,\n-\tAUDIO_CLKA_A_GMARK,\n-\tSSI_SDATA9_A_GMARK,\n-\tSSI_SDATA8_GMARK,\n-\tSSI_SDATA7_GMARK,\n-\tSSI_WS78_GMARK,\n-\tSSI_SCK78_GMARK,\n-\tSSI_SDATA6_GMARK,\n-\tSSI_WS6_GMARK,\n-\tSSI_SCK6_GMARK,\n-\tSSI_SDATA5_MARK,\n-\tSSI_WS5_MARK,\n-\tSSI_SCK5_MARK,\n-\tSSI_SDATA4_GMARK,\n-\tSSI_WS4_GMARK,\n-\tSSI_SCK4_GMARK,\n-\tSSI_SDATA3_GMARK,\n-\tSSI_WS34_GMARK,\n-\tSSI_SCK34_GMARK,\n-\tSSI_SDATA2_A_GMARK,\n-\tSSI_SDATA1_A_GMARK,\n-\tSSI_SDATA0_GMARK,\n-\tSSI_WS01239_GMARK,\n-\tSSI_SCK01239_GMARK,\n-\n-\t/* GPSR7 */\n-\tHDMI1_CEC_MARK,\n-\tHDMI0_CEC_MARK,\n-\tAVS2_MARK,\n-\tAVS1_MARK,\n-\n-\t/* IPSR0 */\n-\tAVB_MDC_IMARK,\n-\tMSIOF2_SS2_C_MARK,\n-\tAVB_MAGIC_IMARK,\n-\tMSIOF2_SS1_C_MARK,\n-\tSCK4_A_MARK,\n-\tAVB_PHY_INT_IMARK,\n-\tMSIOF2_SYNC_C_MARK,\n-\tRX4_A_MARK,\n-\tAVB_LINK_IMARK,\n-\tMSIOF2_SCK_C_MARK,\n-\tTX4_A_MARK,\n-\tAVB_AVTP_MATCH_A_IMARK,\n-\tMSIOF2_RXD_C_MARK,\n-\tCTS4x_A_MARK,\n-\tFSCLKST2x_A_MARK,\n-\tAVB_AVTP_CAPTURE_A_IMARK,\n-\tMSIOF2_TXD_C_MARK,\n-\tRTS4x_TANS_A_MARK,\n-\tIRQ0_IMARK,\n-\tQPOLB_MARK,\n-\tDU_CDE_MARK,\n-\tVI4_DATA0_B_MARK,\n-\tCAN0_TX_B_MARK,\n-\tCANFD0_TX_B_MARK,\n-\tMSIOF3_SS2_E_MARK,\n-\tIRQ1_IMARK,\n-\tQPOLA_MARK,\n-\tDU_DISP_MARK,\n-\tVI4_DATA1_B_MARK,\n-\tCAN0_RX_B_MARK,\n-\tCANFD0_RX_B_MARK,\n-\tMSIOF3_SS1_E_MARK,\n-\n-\t/* IPSR1 */\n-\tIRQ2_IMARK,\n-\tQCPV_QDE_MARK,\n-\tDU_EXODDF_DU_ODDF_DISP_CDE_MARK,\n-\tVI4_DATA2_B_MARK,\n-\tMSIOF3_SYNC_E_MARK,\n-\tPWM3_B_MARK,\n-\tIRQ3_IMARK,\n-\tQSTVB_QVE_MARK,\n-\tDU_DOTCLKOUT1_MARK,\n-\tVI4_DATA3_B_MARK,\n-\tMSIOF3_SCK_E_MARK,\n-\tPWM4_B_MARK,\n-\tIRQ4_IMARK,\n-\tQSTH_QHS_MARK,\n-\tDU_EXHSYNC_DU_HSYNC_MARK,\n-\tVI4_DATA4_B_MARK,\n-\tMSIOF3_RXD_E_MARK,\n-\tPWM5_B_MARK,\n-\tIRQ5_IMARK,\n-\tQSTB_QHE_MARK,\n-\tDU_EXVSYNC_DU_VSYNC_MARK,\n-\tVI4_DATA5_B_MARK,\n-\tFSCLKST2x_B_MARK,\n-\tMSIOF3_TXD_E_MARK,\n-\tPWM6_B_MARK,\n-\tPWM0_IMARK,\n-\tAVB_AVTP_PPS_MARK,\n-\tVI4_DATA6_B_MARK,\n-\tIECLK_B_MARK,\n-\tPWM1_A_IMARK,\n-\tHRX3_D_MARK,\n-\tVI4_DATA7_B_MARK,\n-\tIERX_B_MARK,\n-\tPWM2_A_IMARK,\n-\tPWMFSW0_MARK,\n-\tHTX3_D_MARK,\n-\tIETX_B_MARK,\n-\tA0_IMARK,\n-\tLCDOUT16_MARK,\n-\tMSIOF3_SYNC_B_MARK,\n-\tVI4_DATA8_MARK,\n-\tDU_DB0_MARK,\n-\tPWM3_A_MARK,\n-\n-\t/* IPSR2 */\n-\tA1_IMARK,\n-\tLCDOUT17_MARK,\n-\tMSIOF3_TXD_B_MARK,\n-\tVI4_DATA9_MARK,\n-\tDU_DB1_MARK,\n-\tPWM4_A_MARK,\n-\tA2_IMARK,\n-\tLCDOUT18_MARK,\n-\tMSIOF3_SCK_B_MARK,\n-\tVI4_DATA10_MARK,\n-\tDU_DB2_MARK,\n-\tPWM5_A_MARK,\n-\tA3_IMARK,\n-\tLCDOUT19_MARK,\n-\tMSIOF3_RXD_B_MARK,\n-\tVI4_DATA11_MARK,\n-\tDU_DB3_MARK,\n-\tPWM6_A_MARK,\n-\tA4_IMARK,\n-\tLCDOUT20_MARK,\n-\tMSIOF3_SS1_B_MARK,\n-\tVI4_DATA12_MARK,\n-\tVI5_DATA12_MARK,\n-\tDU_DB4_MARK,\n-\tA5_IMARK,\n-\tLCDOUT21_MARK,\n-\tMSIOF3_SS2_B_MARK,\n-\tSCK4_B_MARK,\n-\tVI4_DATA13_MARK,\n-\tVI5_DATA13_MARK,\n-\tDU_DB5_MARK,\n-\tA6_IMARK,\n-\tLCDOUT22_MARK,\n-\tMSIOF2_SS1_A_MARK,\n-\tRX4_B_MARK,\n-\tVI4_DATA14_MARK,\n-\tVI5_DATA14_MARK,\n-\tDU_DB6_MARK,\n-\tA7_IMARK,\n-\tLCDOUT23_MARK,\n-\tMSIOF2_SS2_A_MARK,\n-\tTX4_B_MARK,\n-\tVI4_DATA15_MARK,\n-\tV15_DATA15_MARK,\n-\tDU_DB7_MARK,\n-\tA8_IMARK,\n-\tRX3_B_MARK,\n-\tMSIOF2_SYNC_A_MARK,\n-\tHRX4_B_MARK,\n-\tSDA6_A_MARK,\n-\tAVB_AVTP_MATCH_B_MARK,\n-\tPWM1_B_MARK,\n-\n-\t/* IPSR3 */\n-\tA9_IMARK,\n-\tMSIOF2_SCK_A_MARK,\n-\tCTS4x_B_MARK,\n-\tVI5_VSYNCx_MARK,\n-\tA10_IMARK,\n-\tMSIOF2_RXD_A_MARK,\n-\tRTS4n_TANS_B_MARK,\n-\tVI5_HSYNCx_MARK,\n-\tA11_IMARK,\n-\tTX3_B_MARK,\n-\tMSIOF2_TXD_A_MARK,\n-\tHTX4_B_MARK,\n-\tHSCK4_MARK,\n-\tVI5_FIELD_MARK,\n-\tSCL6_A_MARK,\n-\tAVB_AVTP_CAPTURE_B_MARK,\n-\tPWM2_B_MARK,\n-\tA12_IMARK,\n-\tLCDOUT12_MARK,\n-\tMSIOF3_SCK_C_MARK,\n-\tHRX4_A_MARK,\n-\tVI5_DATA8_MARK,\n-\tDU_DG4_MARK,\n-\tA13_IMARK,\n-\tLCDOUT13_MARK,\n-\tMSIOF3_SYNC_C_MARK,\n-\tHTX4_A_MARK,\n-\tVI5_DATA9_MARK,\n-\tDU_DG5_MARK,\n-\tA14_IMARK,\n-\tLCDOUT14_MARK,\n-\tMSIOF3_RXD_C_MARK,\n-\tHCTS4x_MARK,\n-\tVI5_DATA10_MARK,\n-\tDU_DG6_MARK,\n-\tA15_IMARK,\n-\tLCDOUT15_MARK,\n-\tMSIOF3_TXD_C_MARK,\n-\tHRTS4x_MARK,\n-\tVI5_DATA11_MARK,\n-\tDU_DG7_MARK,\n-\tA16_IMARK,\n-\tLCDOUT8_MARK,\n-\tVI4_FIELD_MARK,\n-\tDU_DG0_MARK,\n-\n-\t/* IPSR4 */\n-\tA17_IMARK,\n-\tLCDOUT9_MARK,\n-\tVI4_VSYNCx_MARK,\n-\tDU_DG1_MARK,\n-\tA18_IMARK,\n-\tLCDOUT10_MARK,\n-\tVI4_HSYNCx_MARK,\n-\tDU_DG2_MARK,\n-\tA19_IMARK,\n-\tLCDOUT11_MARK,\n-\tVI4_CLKENB_MARK,\n-\tDU_DG3_MARK,\n-\tCS0x_IMARK,\n-\tVI5_CLKENB_MARK,\n-\tCS1x_A26_IMARK,\n-\tVI5_CLK_MARK,\n-\tEX_WAIT0_B_MARK,\n-\tBSx_IMARK,\n-\tQSTVA_QVS_MARK,\n-\tMSIOF3_SCK_D_MARK,\n-\tSCK3_MARK,\n-\tHSCK3_MARK,\n-\tCAN1_TX_MARK,\n-\tCANFD1_TX_MARK,\n-\tIETX_A_MARK,\n-\tRDx_IMARK,\n-\tMSIOF3_SYNC_D_MARK,\n-\tRX3_A_MARK,\n-\tHRX3_A_MARK,\n-\tCAN0_TX_A_MARK,\n-\tCANFD0_TX_A_MARK,\n-\tRD_WRx_IMARK,\n-\tMSIOF3_RXD_D_MARK,\n-\tTX3_A_MARK,\n-\tHTX3_A_MARK,\n-\tCAN0_RX_A_MARK,\n-\tCANFD0_RX_A_MARK,\n-\n-\t/* IPSR5 */\n-\tWE0x_IMARK,\n-\tMSIIOF3_TXD_D_MARK,\n-\tCTS3x_MARK,\n-\tHCTS3x_MARK,\n-\tSCL6_B_MARK,\n-\tCAN_CLK_MARK,\n-\tIECLK_A_MARK,\n-\tWE1x_IMARK,\n-\tMSIOF3_SS1_D_MARK,\n-\tRTS3x_TANS_MARK,\n-\tHRTS3x_MARK,\n-\tSDA6_B_MARK,\n-\tCAN1_RX_MARK,\n-\tCANFD1_RX_MARK,\n-\tIERX_A_MARK,\n-\tEX_WAIT0_A_IMARK,\n-\tQCLK_MARK,\n-\tVI4_CLK_MARK,\n-\tDU_DOTCLKOUT0_MARK,\n-\tD0_IMARK,\n-\tMSIOF2_SS1_B_MARK,\n-\tMSIOF3_SCK_A_MARK,\n-\tVI4_DATA16_MARK,\n-\tVI5_DATA0_MARK,\n-\tD1_IMARK,\n-\tMSIOF2_SS2_B_MARK,\n-\tMSIOF3_SYNC_A_MARK,\n-\tVI4_DATA17_MARK,\n-\tVI5_DATA1_MARK,\n-\tD2_IMARK,\n-\tMSIOF3_RXD_A_MARK,\n-\tVI4_DATA18_MARK,\n-\tVI5_DATA2_MARK,\n-\tD3_IMARK,\n-\tMSIOF3_TXD_A_MARK,\n-\tVI4_DATA19_MARK,\n-\tVI5_DATA3_MARK,\n-\tD4_IMARK,\n-\tMSIOF2_SCK_B_MARK,\n-\tVI4_DATA20_MARK,\n-\tVI5_DATA4_MARK,\n-\n-\t/* IPSR6 */\n-\tD5_IMARK,\n-\tMSIOF2_SYNC_B_MARK,\n-\tVI4_DATA21_MARK,\n-\tVI5_DATA5_MARK,\n-\tD6_IMARK,\n-\tMSIOF2_RXD_B_MARK,\n-\tVI4_DATA22_MARK,\n-\tVI5_DATA6_MARK,\n-\tD7_IMARK,\n-\tMSIOF2_TXD_B_MARK,\n-\tVI4_DATA23_MARK,\n-\tVI5_DATA7_MARK,\n-\tD8_IMARK,\n-\tLCDOUT0_MARK,\n-\tMSIOF2_SCK_D_MARK,\n-\tSCK4_C_MARK,\n-\tVI4_DATA0_A_MARK,\n-\tDU_DR0_MARK,\n-\tD9_IMARK,\n-\tLCDOUT1_MARK,\n-\tMSIOF2_SYNC_D_MARK,\n-\tVI4_DATA1_A_MARK,\n-\tDU_DR1_MARK,\n-\tD10_IMARK,\n-\tLCDOUT2_MARK,\n-\tMSIOF2_RXD_D_MARK,\n-\tHRX3_B_MARK,\n-\tVI4_DATA2_A_MARK,\n-\tCTS4x_C_MARK,\n-\tDU_DR2_MARK,\n-\tD11_IMARK,\n-\tLCDOUT3_MARK,\n-\tMSIOF2_TXD_D_MARK,\n-\tHTX3_B_MARK,\n-\tVI4_DATA3_A_MARK,\n-\tRTS4x_TANS_C_MARK,\n-\tDU_DR3_MARK,\n-\tD12_IMARK,\n-\tLCDOUT4_MARK,\n-\tMSIOF2_SS1_D_MARK,\n-\tRX4_C_MARK,\n-\tVI4_DATA4_A_MARK,\n-\tDU_DR4_MARK,\n-\n-\t/* IPSR7 */\n-\tD13_IMARK,\n-\tLCDOUT5_MARK,\n-\tMSIOF2_SS2_D_MARK,\n-\tTX4_C_MARK,\n-\tVI4_DATA5_A_MARK,\n-\tDU_DR5_MARK,\n-\tD14_IMARK,\n-\tLCDOUT6_MARK,\n-\tMSIOF3_SS1_A_MARK,\n-\tHRX3_C_MARK,\n-\tVI4_DATA6_A_MARK,\n-\tDU_DR6_MARK,\n-\tSCL6_C_MARK,\n-\tD15_IMARK,\n-\tLCDOUT7_MARK,\n-\tMSIOF3_SS2_A_MARK,\n-\tHTX3_C_MARK,\n-\tVI4_DATA7_A_MARK,\n-\tDU_DR7_MARK,\n-\tSDA6_C_MARK,\n-\tFSCLKST_MARK,\n-\tSD0_CLK_IMARK,\n-\tMSIOF1_SCK_E_MARK,\n-\tSTP_OPWM_0_B_MARK,\n-\tSD0_CMD_IMARK,\n-\tMSIOF1_SYNC_E_MARK,\n-\tSTP_IVCXO27_0_B_MARK,\n-\tSD0_DAT0_IMARK,\n-\tMSIOF1_RXD_E_MARK,\n-\tTS_SCK0_B_MARK,\n-\tSTP_ISCLK_0_B_MARK,\n-\tSD0_DAT1_IMARK,\n-\tMSIOF1_TXD_E_MARK,\n-\tTS_SPSYNC0_B_MARK,\n-\tSTP_ISSYNC_0_B_MARK,\n-\n-\t/* IPSR8 */\n-\tSD0_DAT2_IMARK,\n-\tMSIOF1_SS1_E_MARK,\n-\tTS_SDAT0_B_MARK,\n-\tSTP_ISD_0_B_MARK,\n-\tSD0_DAT3_IMARK,\n-\tMSIOF1_SS2_E_MARK,\n-\tTS_SDEN0_B_MARK,\n-\tSTP_ISEN_0_B_MARK,\n-\tSD1_CLK_IMARK,\n-\tMSIOF1_SCK_G_MARK,\n-\tSIM0_CLK_A_MARK,\n-\tSD1_CMD_IMARK,\n-\tMSIOF1_SYNC_G_MARK,\n-\tNFCEx_B_MARK,\n-\tSIM0_D_A_MARK,\n-\tSTP_IVCXO27_1_B_MARK,\n-\tSD1_DAT0_IMARK,\n-\tSD2_DAT4_MARK,\n-\tMSIOF1_RXD_G_MARK,\n-\tNFWPx_B_MARK,\n-\tTS_SCK1_B_MARK,\n-\tSTP_ISCLK_1_B_MARK,\n-\tSD1_DAT1_IMARK,\n-\tSD2_DAT5_MARK,\n-\tMSIOF1_TXD_G_MARK,\n-\tNFDATA14_B_MARK,\n-\tTS_SPSYNC1_B_MARK,\n-\tSTP_ISSYNC_1_B_MARK,\n-\tSD1_DAT2_IMARK,\n-\tSD2_DAT6_MARK,\n-\tMSIOF1_SS1_G_MARK,\n-\tNFDATA15_B_MARK,\n-\tTS_SDAT1_B_MARK,\n-\tSTP_IOD_1_B_MARK,\n-\tSD1_DAT3_IMARK,\n-\tSD2_DAT7_MARK,\n-\tMSIOF1_SS2_G_MARK,\n-\tNFRBx_B_MARK,\n-\tTS_SDEN1_B_MARK,\n-\tSTP_ISEN_1_B_MARK,\n-\n-\t/* IPSR9 */\n-\tSD2_CLK_IMARK,\n-\tNFDATA8_MARK,\n-\tSD2_CMD_IMARK,\n-\tNFDATA9_MARK,\n-\tSD2_DAT0_IMARK,\n-\tNFDATA10_MARK,\n-\tSD2_DAT1_IMARK,\n-\tNFDATA11_MARK,\n-\tSD2_DAT2_IMARK,\n-\tNFDATA12_MARK,\n-\tSD2_DAT3_IMARK,\n-\tNFDATA13_MARK,\n-\tSD2_DS_IMARK,\n-\tNFALE_MARK,\n-\tSATA_DEVSLP_B_MARK,\n-\tSD3_CLK_IMARK,\n-\tNFWEx_MARK,\n-\n-\t/* IPSR10 */\n-\tSD3_CMD_IMARK,\n-\tNFREx_MARK,\n-\tSD3_DAT0_IMARK,\n-\tNFDATA0_MARK,\n-\tSD3_DAT1_IMARK,\n-\tNFDATA1_MARK,\n-\tSD3_DAT2_IMARK,\n-\tNFDATA2_MARK,\n-\tSD3_DAT3_IMARK,\n-\tNFDATA3_MARK,\n-\tSD3_DAT4_IMARK,\n-\tSD2_CD_A_MARK,\n-\tNFDATA4_MARK,\n-\tSD3_DAT5_IMARK,\n-\tSD2_WP_A_MARK,\n-\tNFDATA5_MARK,\n-\tSD3_DAT6_IMARK,\n-\tSD3_CD_MARK,\n-\tNFDATA6_MARK,\n-\n-\t/* IPSR11 */\n-\tSD3_DAT7_IMARK,\n-\tSD3_WP_MARK,\n-\tNFDATA7_MARK,\n-\tSD3_DS_IMARK,\n-\tNFCLE_MARK,\n-\tSD0_CD_IMARK,\n-\tNFDATA14_A_MARK,\n-\tSCL2_B_MARK,\n-\tSIM0_RST_A_MARK,\n-\tSD0_WP_IMARK,\n-\tNFDATA15_A_MARK,\n-\tSDA2_B_MARK,\n-\tSD1_CD_IMARK,\n-\tNFRBx_A_MARK,\n-\tSIM0_CLK_B_MARK,\n-\tSD1_WP_IMARK,\n-\tNFCEx_A_MARK,\n-\tSIM0_D_B_MARK,\n-\tSCK0_IMARK,\n-\tHSCK1_B_MARK,\n-\tMSIOF1_SS2_B_MARK,\n-\tAUDIO_CLKC_B_MARK,\n-\tSDA2_A_MARK,\n-\tSIM0_RST_B_MARK,\n-\tSTP_OPWM_0_C_MARK,\n-\tRIF0_CLK_B_MARK,\n-\tADICHS2_MARK,\n-\tSCK5_B_MARK,\n-\tRX0_IMARK,\n-\tHRX1_B_MARK,\n-\tTS_SCK0_C_MARK,\n-\tSTP_ISCLK_0_C_MARK,\n-\tRIF0_D0_B_MARK,\n-\n-\t/* IPSR12 */\n-\tTX0_IMARK,\n-\tHTX1_B_MARK,\n-\tTS_SPSYNC0_C_MARK,\n-\tSTP_ISSYNC_0_C_MARK,\n-\tRIF0_D1_B_MARK,\n-\tCTS0x_IMARK,\n-\tHCTS1x_B_MARK,\n-\tMSIOF1_SYNC_B_MARK,\n-\tTS_SPSYNC1_C_MARK,\n-\tSTP_ISSYNC_1_C_MARK,\n-\tRIF1_SYNC_B_MARK,\n-\tAUDIO_CLKOUT_C_MARK,\n-\tADICS_SAMP_MARK,\n-\tRTS0x_TANS_IMARK,\n-\tHRTS1x_B_MARK,\n-\tMSIOF1_SS1_B_MARK,\n-\tAUDIO_CLKA_B_MARK,\n-\tSCL2_A_MARK,\n-\tSTP_IVCXO27_1_C_MARK,\n-\tRIF0_SYNC_B_MARK,\n-\tADICHS1_MARK,\n-\tRX1_A_IMARK,\n-\tHRX1_A_MARK,\n-\tTS_SDAT0_C_MARK,\n-\tSTP_ISD_0_C_MARK,\n-\tRIF1_CLK_C_MARK,\n-\tTX1_A_IMARK,\n-\tHTX1_A_MARK,\n-\tTS_SDEN0_C_MARK,\n-\tSTP_ISEN_0_C_MARK,\n-\tRIF1_D0_C_MARK,\n-\tCTS1x_IMARK,\n-\tHCTS1x_A_MARK,\n-\tMSIOF1_RXD_B_MARK,\n-\tTS_SDEN1_C_MARK,\n-\tSTP_ISEN_1_C_MARK,\n-\tRIF1_D0_B_MARK,\n-\tADIDATA_MARK,\n-\tRTS1x_TANS_IMARK,\n-\tHRTS1x_A_MARK,\n-\tMSIOF1_TXD_B_MARK,\n-\tTS_SDAT1_C_MARK,\n-\tSTP_ISD_1_C_MARK,\n-\tRIF1_D1_B_MARK,\n-\tADICHS0_MARK,\n-\tSCK2_IMARK,\n-\tSCIF_CLK_B_MARK,\n-\tMSIOF1_SCK_B_MARK,\n-\tTS_SCK1_C_MARK,\n-\tSTP_ISCLK_1_C_MARK,\n-\tRIF1_CLK_B_MARK,\n-\tADICLK_MARK,\n-\n-\t/* IPSR13 */\n-\tTX2_A_IMARK,\n-\tSD2_CD_B_MARK,\n-\tSCL1_A_MARK,\n-\tFMCLK_A_MARK,\n-\tRIF1_D1_C_MARK,\n-\tFSO_CFE_0x_MARK,\n-\tRX2_A_IMARK,\n-\tSD2_WP_B_MARK,\n-\tSDA1_A_MARK,\n-\tFMIN_A_MARK,\n-\tRIF1_SYNC_C_MARK,\n-\tFSO_CFE_1x_MARK,\n-\tHSCK0_IMARK,\n-\tMSIOF1_SCK_D_MARK,\n-\tAUDIO_CLKB_A_MARK,\n-\tSSI_SDATA1_B_MARK,\n-\tTS_SCK0_D_MARK,\n-\tSTP_ISCLK_0_D_MARK,\n-\tRIF0_CLK_C_MARK,\n-\tRX5_B_MARK,\n-\tHRX0_IMARK,\n-\tMSIOF1_RXD_D_MARK,\n-\tSSI_SDATA2_B_MARK,\n-\tTS_SDEN0_D_MARK,\n-\tSTP_ISEN_0_D_MARK,\n-\tRIF0_D0_C_MARK,\n-\tHTX0_IMARK,\n-\tMSIOF1_TXD_D_MARK,\n-\tSSI_SDATA9_B_MARK,\n-\tTS_SDAT0_D_MARK,\n-\tSTP_ISD_0_D_MARK,\n-\tRIF0_D1_C_MARK,\n-\tHCTS0x_IMARK,\n-\tRX2_B_MARK,\n-\tMSIOF1_SYNC_D_MARK,\n-\tSSI_SCK9_A_MARK,\n-\tTS_SPSYNC0_D_MARK,\n-\tSTP_ISSYNC_0_D_MARK,\n-\tRIF0_SYNC_C_MARK,\n-\tAUDIO_CLKOUT1_A_MARK,\n-\tHRTS0x_IMARK,\n-\tTX2_B_MARK,\n-\tMSIOF1_SS1_D_MARK,\n-\tSSI_WS9_A_MARK,\n-\tSTP_IVCXO27_0_D_MARK,\n-\tBPFCLK_A_MARK,\n-\tAUDIO_CLKOUT2_A_MARK,\n-\tMSIOF0_SYNC_IMARK,\n-\tAUDIO_CLKOUT_A_MARK,\n-\tTX5_B_MARK,\n-\tBPFCLK_D_MARK,\n-\n-\t/* IPSR14 */\n-\tMSIOF0_SS1_IMARK,\n-\tRX5_A_MARK,\n-\tNFWPx_A_MARK,\n-\tAUDIO_CLKA_C_MARK,\n-\tSSI_SCK2_A_MARK,\n-\tSTP_IVCXO27_0_C_MARK,\n-\tAUDIO_CLKOUT3_A_MARK,\n-\tTCLK1_B_MARK,\n-\tMSIOF0_SS2_IMARK,\n-\tTX5_A_MARK,\n-\tMSIOF1_SS2_D_MARK,\n-\tAUDIO_CLKC_A_MARK,\n-\tSSI_WS2_A_MARK,\n-\tSTP_OPWM_0_D_MARK,\n-\tAUDIO_CLKOUT_D_MARK,\n-\tSPEEDIN_B_MARK,\n-\tMLB_CLK_IMARK,\n-\tMSIOF1_SCK_F_MARK,\n-\tSCL1_B_MARK,\n-\tMLB_SIG_IMARK,\n-\tRX1_B_MARK,\n-\tMSIOF1_SYNC_F_MARK,\n-\tSDA1_B_MARK,\n-\tMLB_DAT_IMARK,\n-\tTX1_B_MARK,\n-\tMSIOF1_RXD_F_MARK,\n-\tSSI_SCK01239_IMARK,\n-\tMSIOF1_TXD_F_MARK,\n-\tMOUT0_MARK,\n-\tSSI_WS01239_IMARK,\n-\tMSIOF1_SS1_F_MARK,\n-\tMOUT1_MARK,\n-\tSSI_SDATA0_IMARK,\n-\tMSIOF1_SS2_F_MARK,\n-\tMOUT2_MARK,\n-\n-\t/* IPSR15 */\n-\tSSI_SDATA1_A_IMARK,\n-\tMOUT5_MARK,\n-\tSSI_SDATA2_A_IMARK,\n-\tSSI_SCK1_B_MARK,\n-\tMOUT6_MARK,\n-\tSSI_SCK34_IMARK,\n-\tMSIOF1_SS1_A_MARK,\n-\tSTP_OPWM_0_A_MARK,\n-\tSSI_WS34_IMARK,\n-\tHCTS2x_A_MARK,\n-\tMSIOF1_SS2_A_MARK,\n-\tSTP_IVCXO27_0_A_MARK,\n-\tSSI_SDATA3_IMARK,\n-\tHRTS2x_A_MARK,\n-\tMSIOF1_TXD_A_MARK,\n-\tTS_SCK0_A_MARK,\n-\tSTP_ISCLK_0_A_MARK,\n-\tRIF0_D1_A_MARK,\n-\tRIF2_D0_A_MARK,\n-\tSSI_SCK4_IMARK,\n-\tHRX2_A_MARK,\n-\tMSIOF1_SCK_A_MARK,\n-\tTS_SDAT0_A_MARK,\n-\tSTP_ISD_0_A_MARK,\n-\tRIF0_CLK_A_MARK,\n-\tRIF2_CLK_A_MARK,\n-\tSSI_WS4_IMARK,\n-\tHTX2_A_MARK,\n-\tMSIOF1_SYNC_A_MARK,\n-\tTS_SDEN0_A_MARK,\n-\tSTP_ISEN_0_A_MARK,\n-\tRIF0_SYNC_A_MARK,\n-\tRIF2_SYNC_A_MARK,\n-\tSSI_SDATA4_IMARK,\n-\tHSCK2_A_MARK,\n-\tMSIOF1_RXD_A_MARK,\n-\tTS_SPSYNC0_A_MARK,\n-\tSTP_ISSYNC_0_A_MARK,\n-\tRIF0_D0_A_MARK,\n-\tRIF2_D1_A_MARK,\n-\n-\t/* IPSR16 */\n-\tSSI_SCK6_IMARK,\n-\tSIM0_RST_D_MARK,\n-\tSSI_WS6_IMARK,\n-\tSIM0_D_D_MARK,\n-\tSSI_SDATA6_IMARK,\n-\tSIM0_CLK_D_MARK,\n-\tSATA_DEVSLP_A_MARK,\n-\tSSI_SCK78_IMARK,\n-\tHRX2_B_MARK,\n-\tMSIOF1_SCK_C_MARK,\n-\tTS_SCK1_A_MARK,\n-\tSTP_ISCLK_1_A_MARK,\n-\tRIF1_CLK_A_MARK,\n-\tRIF3_CLK_A_MARK,\n-\tSSI_WS78_IMARK,\n-\tHTX2_B_MARK,\n-\tMSIOF1_SYNC_C_MARK,\n-\tTS_SDAT1_A_MARK,\n-\tSTP_ISD_1_A_MARK,\n-\tRIF1_SYNC_A_MARK,\n-\tRIF3_SYNC_A_MARK,\n-\tSSI_SDATA7_IMARK,\n-\tHCTS2x_B_MARK,\n-\tMSIOF1_RXD_C_MARK,\n-\tTS_SDEN1_A_MARK,\n-\tSTP_ISEN_1_A_MARK,\n-\tRIF1_D0_A_MARK,\n-\tRIF3_D0_A_MARK,\n-\tTCLK2_A_MARK,\n-\tSSI_SDATA8_IMARK,\n-\tHRTS2x_B_MARK,\n-\tMSIOF1_TXD_C_MARK,\n-\tTS_SPSYNC1_A_MARK,\n-\tSTP_ISSYNC_1_A_MARK,\n-\tRIF1_D1_A_MARK,\n-\tRIF3_D1_A_MARK,\n-\tSSI_SDATA9_A_IMARK,\n-\tHSCK2_B_MARK,\n-\tMSIOF1_SS1_C_MARK,\n-\tHSCK1_A_MARK,\n-\tSSI_WS1_B_MARK,\n-\tSCK1_MARK,\n-\tSTP_IVCXO27_1_A_MARK,\n-\tSCK5_A_MARK,\n-\n-\t/* IPSR17 */\n-\tAUDIO_CLKA_A_IMARK,\n-\tCC5_OSCOUT_MARK,\n-\tAUDIO_CLKB_B_IMARK,\n-\tSCIF_CLK_A_MARK,\n-\tSTP_IVCXO27_1_D_MARK,\n-\tREMOCON_A_MARK,\n-\tTCLK1_A_MARK,\n-\tUSB0_PWEN_IMARK,\n-\tSIM0_RST_C_MARK,\n-\tTS_SCK1_D_MARK,\n-\tSTP_ISCLK_1_D_MARK,\n-\tBPFCLK_B_MARK,\n-\tRIF3_CLK_B_MARK,\n-\tHSCK2_C_MARK,\n-\tUSB0_OVC_IMARK,\n-\tSIM0_D_C_MARK,\n-\tTS_SDAT1_D_MARK,\n-\tSTP_ISD_1_D_MARK,\n-\tRIF3_SYNC_B_MARK,\n-\tHRX2_C_MARK,\n-\tUSB1_PWEN_IMARK,\n-\tSIM0_CLK_C_MARK,\n-\tSSI_SCK1_A_MARK,\n-\tTS_SCK0_E_MARK,\n-\tSTP_ISCLK_0_E_MARK,\n-\tFMCLK_B_MARK,\n-\tRIF2_CLK_B_MARK,\n-\tSPEEDIN_A_MARK,\n-\tHTX2_C_MARK,\n-\tUSB1_OVC_IMARK,\n-\tMSIOF1_SS2_C_MARK,\n-\tSSI_WS1_A_MARK,\n-\tTS_SDAT0_E_MARK,\n-\tSTP_ISD_0_E_MARK,\n-\tFMIN_B_MARK,\n-\tRIF2_SYNC_B_MARK,\n-\tREMOCON_B_MARK,\n-\tHCTS2x_C_MARK,\n-\tUSB30_PWEN_IMARK,\n-\tAUDIO_CLKOUT_B_MARK,\n-\tSSI_SCK2_B_MARK,\n-\tTS_SDEN1_D_MARK,\n-\tSTP_ISEN_1_D_MARK,\n-\tSTP_OPWM_0_E_MARK,\n-\tRIF3_D0_B_MARK,\n-\tTCLK2_B_MARK,\n-\tTPU0TO0_MARK,\n-\tBPFCLK_C_MARK,\n-\tHRTS2x_C_MARK,\n-\tUSB30_OVC_IMARK,\n-\tAUDIO_CLKOUT1_B_MARK,\n-\tSSI_WS2_B_MARK,\n-\tTS_SPSYNC1_D_MARK,\n-\tSTP_ISSYNC_1_D_MARK,\n-\tSTP_IVCXO27_0_E_MARK,\n-\tRIF3_D1_B_MARK,\n-\tFSO_TOEx_MARK,\n-\tTPU0TO1_MARK,\n-\n-\t/* IPSR18 */\n-\tUSB3_PWEN_IMARK,\n-\tAUDIO_CLKOUT2_B_MARK,\n-\tSSI_SCK9_B_MARK,\n-\tTS_SDEN0_E_MARK,\n-\tSTP_ISEN_0_E_MARK,\n-\tRIF2_D0_B_MARK,\n-\tTPU0TO2_MARK,\n-\tFMCLK_C_MARK,\n-\tFMCLK_D_MARK,\n-\n-\tUSB3_OVC_IMARK,\n-\tAUDIO_CLKOUT3_B_MARK,\n-\tSSI_WS9_B_MARK,\n-\tTS_SPSYNC0_E_MARK,\n-\tSTP_ISSYNC_0_E_MARK,\n-\tRIF2_D1_B_MARK,\n-\tTPU0TO3_MARK,\n-\tFMIN_C_MARK,\n-\tFMIN_D_MARK,\n-\n-\tPINMUX_MARK_END,\n-};\n-\n-static pinmux_enum_t pinmux_data[] = {\n-\tPINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */\n-\n-\t/* GPSR0 */\n-\tPINMUX_DATA(D15_GMARK, GFN_D15),\n-\tPINMUX_DATA(D14_GMARK, GFN_D14),\n-\tPINMUX_DATA(D13_GMARK, GFN_D13),\n-\tPINMUX_DATA(D12_GMARK, GFN_D12),\n-\tPINMUX_DATA(D11_GMARK, GFN_D11),\n-\tPINMUX_DATA(D10_GMARK, GFN_D10),\n-\tPINMUX_DATA(D9_GMARK, GFN_D9),\n-\tPINMUX_DATA(D8_GMARK, GFN_D8),\n-\tPINMUX_DATA(D7_GMARK, GFN_D7),\n-\tPINMUX_DATA(D6_GMARK, GFN_D6),\n-\tPINMUX_DATA(D5_GMARK, GFN_D5),\n-\tPINMUX_DATA(D4_GMARK, GFN_D4),\n-\tPINMUX_DATA(D3_GMARK, GFN_D3),\n-\tPINMUX_DATA(D2_GMARK, GFN_D2),\n-\tPINMUX_DATA(D1_GMARK, GFN_D1),\n-\tPINMUX_DATA(D0_GMARK, GFN_D0),\n-\n-\t/* GPSR1 */\n-\tPINMUX_DATA(CLKOUT_GMARK, GFN_CLKOUT),\n-\tPINMUX_DATA(EX_WAIT0_A_GMARK, GFN_EX_WAIT0_A),\n-\tPINMUX_DATA(WE1x_GMARK, GFN_WE1x),\n-\tPINMUX_DATA(WE0x_GMARK, GFN_WE0x),\n-\tPINMUX_DATA(RD_WRx_GMARK, GFN_RD_WRx),\n-\tPINMUX_DATA(RDx_GMARK, GFN_RDx),\n-\tPINMUX_DATA(BSx_GMARK, GFN_BSx),\n-\tPINMUX_DATA(CS1x_A26_GMARK, GFN_CS1x_A26),\n-\tPINMUX_DATA(CS0x_GMARK, GFN_CS0x),\n-\tPINMUX_DATA(A19_GMARK, GFN_A19),\n-\tPINMUX_DATA(A18_GMARK, GFN_A18),\n-\tPINMUX_DATA(A17_GMARK, GFN_A17),\n-\tPINMUX_DATA(A16_GMARK, GFN_A16),\n-\tPINMUX_DATA(A15_GMARK, GFN_A15),\n-\tPINMUX_DATA(A14_GMARK, GFN_A14),\n-\tPINMUX_DATA(A13_GMARK, GFN_A13),\n-\tPINMUX_DATA(A12_GMARK, GFN_A12),\n-\tPINMUX_DATA(A11_GMARK, GFN_A11),\n-\tPINMUX_DATA(A10_GMARK, GFN_A10),\n-\tPINMUX_DATA(A9_GMARK, GFN_A9),\n-\tPINMUX_DATA(A8_GMARK, GFN_A8),\n-\tPINMUX_DATA(A7_GMARK, GFN_A7),\n-\tPINMUX_DATA(A6_GMARK, GFN_A6),\n-\tPINMUX_DATA(A5_GMARK, GFN_A5),\n-\tPINMUX_DATA(A4_GMARK, GFN_A4),\n-\tPINMUX_DATA(A3_GMARK, GFN_A3),\n-\tPINMUX_DATA(A2_GMARK, GFN_A2),\n-\tPINMUX_DATA(A1_GMARK, GFN_A1),\n-\tPINMUX_DATA(A0_GMARK, GFN_A0),\n-\n-\t/* GPSR2 */\n-\tPINMUX_DATA(AVB_AVTP_CAPTURE_A_GMARK, GFN_AVB_AVTP_CAPTURE_A),\n-\tPINMUX_DATA(AVB_AVTP_MATCH_A_GMARK, GFN_AVB_AVTP_MATCH_A),\n-\tPINMUX_DATA(AVB_LINK_GMARK, GFN_AVB_LINK),\n-\tPINMUX_DATA(AVB_PHY_INT_GMARK, GFN_AVB_PHY_INT),\n-\tPINMUX_DATA(AVB_MAGIC_GMARK, GFN_AVB_MAGIC),\n-\tPINMUX_DATA(AVB_MDC_GMARK, GFN_AVB_MDC),\n-\tPINMUX_DATA(PWM2_A_GMARK, GFN_PWM2_A),\n-\tPINMUX_DATA(PWM1_A_GMARK, GFN_PWM1_A),\n-\tPINMUX_DATA(PWM0_GMARK, GFN_PWM0),\n-\tPINMUX_DATA(IRQ5_GMARK, GFN_IRQ5),\n-\tPINMUX_DATA(IRQ4_GMARK, GFN_IRQ4),\n-\tPINMUX_DATA(IRQ3_GMARK, GFN_IRQ3),\n-\tPINMUX_DATA(IRQ2_GMARK, GFN_IRQ2),\n-\tPINMUX_DATA(IRQ1_GMARK, GFN_IRQ1),\n-\tPINMUX_DATA(IRQ0_GMARK, GFN_IRQ0),\n-\n-\t/* GPSR3 */\n-\tPINMUX_DATA(SD1_WP_GMARK, GFN_SD1_WP),\n-\tPINMUX_DATA(SD1_CD_GMARK, GFN_SD1_CD),\n-\tPINMUX_DATA(SD0_WP_GMARK, GFN_SD0_WP),\n-\tPINMUX_DATA(SD0_CD_GMARK, GFN_SD0_CD),\n-\tPINMUX_DATA(SD1_DAT3_GMARK, GFN_SD1_DAT3),\n-\tPINMUX_DATA(SD1_DAT2_GMARK, GFN_SD1_DAT2),\n-\tPINMUX_DATA(SD1_DAT1_GMARK, GFN_SD1_DAT1),\n-\tPINMUX_DATA(SD1_DAT0_GMARK, GFN_SD1_DAT0),\n-\tPINMUX_DATA(SD1_CMD_GMARK, GFN_SD1_CMD),\n-\tPINMUX_DATA(SD1_CLK_GMARK, GFN_SD1_CLK),\n-\tPINMUX_DATA(SD0_DAT3_GMARK, GFN_SD0_DAT3),\n-\tPINMUX_DATA(SD0_DAT2_GMARK, GFN_SD0_DAT2),\n-\tPINMUX_DATA(SD0_DAT1_GMARK, GFN_SD0_DAT1),\n-\tPINMUX_DATA(SD0_DAT0_GMARK, GFN_SD0_DAT0),\n-\tPINMUX_DATA(SD0_CMD_GMARK, GFN_SD0_CMD),\n-\tPINMUX_DATA(SD0_CLK_GMARK, GFN_SD0_CLK),\n-\n-\t/* GPSR4 */\n-\tPINMUX_DATA(SD3_DS_GMARK, GFN_SD3_DS),\n-\tPINMUX_DATA(SD3_DAT7_GMARK, GFN_SD3_DAT7),\n-\tPINMUX_DATA(SD3_DAT6_GMARK, GFN_SD3_DAT6),\n-\tPINMUX_DATA(SD3_DAT5_GMARK, GFN_SD3_DAT5),\n-\tPINMUX_DATA(SD3_DAT4_GMARK, GFN_SD3_DAT4),\n-\tPINMUX_DATA(SD3_DAT3_GMARK, GFN_SD3_DAT3),\n-\tPINMUX_DATA(SD3_DAT2_GMARK, GFN_SD3_DAT2),\n-\tPINMUX_DATA(SD3_DAT1_GMARK, GFN_SD3_DAT1),\n-\tPINMUX_DATA(SD3_DAT0_GMARK, GFN_SD3_DAT0),\n-\tPINMUX_DATA(SD3_CMD_GMARK, GFN_SD3_CMD),\n-\tPINMUX_DATA(SD3_CLK_GMARK, GFN_SD3_CLK),\n-\tPINMUX_DATA(SD2_DS_GMARK, GFN_SD2_DS),\n-\tPINMUX_DATA(SD2_DAT3_GMARK, GFN_SD2_DAT3),\n-\tPINMUX_DATA(SD2_DAT2_GMARK, GFN_SD2_DAT2),\n-\tPINMUX_DATA(SD2_DAT1_GMARK, GFN_SD2_DAT1),\n-\tPINMUX_DATA(SD2_DAT0_GMARK, GFN_SD2_DAT0),\n-\tPINMUX_DATA(SD2_CMD_GMARK, GFN_SD2_CMD),\n-\tPINMUX_DATA(SD2_CLK_GMARK, GFN_SD2_CLK),\n-\n-\t/* GPSR5 */\n-\tPINMUX_DATA(MLB_DAT_GMARK, GFN_MLB_DAT),\n-\tPINMUX_DATA(MLB_SIG_GMARK, GFN_MLB_SIG),\n-\tPINMUX_DATA(MLB_CLK_GMARK, GFN_MLB_CLK),\n-\tPINMUX_DATA(MSIOF0_RXD_MARK, FN_MSIOF0_RXD),\n-\tPINMUX_DATA(MSIOF0_SS2_GMARK, GFN_MSIOF0_SS2),\n-\tPINMUX_DATA(MSIOF0_TXD_MARK, FN_MSIOF0_TXD),\n-\tPINMUX_DATA(MSIOF0_SS1_GMARK, GFN_MSIOF0_SS1),\n-\tPINMUX_DATA(MSIOF0_SYNC_GMARK, GFN_MSIOF0_SYNC),\n-\tPINMUX_DATA(MSIOF0_SCK_MARK, FN_MSIOF0_SCK),\n-\tPINMUX_DATA(HRTS0x_GMARK, GFN_HRTS0x),\n-\tPINMUX_DATA(HCTS0x_GMARK, GFN_HCTS0x),\n-\tPINMUX_DATA(HTX0_GMARK, GFN_HTX0),\n-\tPINMUX_DATA(HRX0_GMARK, GFN_HRX0),\n-\tPINMUX_DATA(HSCK0_GMARK, GFN_HSCK0),\n-\tPINMUX_DATA(RX2_A_GMARK, GFN_RX2_A),\n-\tPINMUX_DATA(TX2_A_GMARK, GFN_TX2_A),\n-\tPINMUX_DATA(SCK2_GMARK, GFN_SCK2),\n-\tPINMUX_DATA(RTS1x_TANS_GMARK, GFN_RTS1x_TANS),\n-\tPINMUX_DATA(CTS1x_GMARK, GFN_CTS1x),\n-\tPINMUX_DATA(TX1_A_GMARK, GFN_TX1_A),\n-\tPINMUX_DATA(RX1_A_GMARK, GFN_RX1_A),\n-\tPINMUX_DATA(RTS0x_TANS_GMARK, GFN_RTS0x_TANS),\n-\tPINMUX_DATA(CTS0x_GMARK, GFN_CTS0x),\n-\tPINMUX_DATA(TX0_GMARK, GFN_TX0),\n-\tPINMUX_DATA(RX0_GMARK, GFN_RX0),\n-\tPINMUX_DATA(SCK0_GMARK, GFN_SCK0),\n-\n-\t/* GPSR6 */\n-\tPINMUX_DATA(USB3_OVC_GMARK, GFN_USB3_OVC),\n-\tPINMUX_DATA(USB3_PWEN_GMARK, GFN_USB3_PWEN),\n-\tPINMUX_DATA(USB30_OVC_GMARK, GFN_USB30_OVC),\n-\tPINMUX_DATA(USB30_PWEN_GMARK, GFN_USB30_PWEN),\n-\tPINMUX_DATA(USB1_OVC_GMARK, GFN_USB1_OVC),\n-\tPINMUX_DATA(USB1_PWEN_GMARK, GFN_USB1_PWEN),\n-\tPINMUX_DATA(USB0_OVC_GMARK, GFN_USB0_OVC),\n-\tPINMUX_DATA(USB0_PWEN_GMARK, GFN_USB0_PWEN),\n-\tPINMUX_DATA(AUDIO_CLKB_B_GMARK, GFN_AUDIO_CLKB_B),\n-\tPINMUX_DATA(AUDIO_CLKA_A_GMARK, GFN_AUDIO_CLKA_A),\n-\tPINMUX_DATA(SSI_SDATA9_A_GMARK, GFN_SSI_SDATA9_A),\n-\tPINMUX_DATA(SSI_SDATA8_GMARK, GFN_SSI_SDATA8),\n-\tPINMUX_DATA(SSI_SDATA7_GMARK, GFN_SSI_SDATA7),\n-\tPINMUX_DATA(SSI_WS78_GMARK, GFN_SSI_WS78),\n-\tPINMUX_DATA(SSI_SCK78_GMARK, GFN_SSI_SCK78),\n-\tPINMUX_DATA(SSI_SDATA6_GMARK, GFN_SSI_SDATA6),\n-\tPINMUX_DATA(SSI_WS6_GMARK, GFN_SSI_WS6),\n-\tPINMUX_DATA(SSI_SCK6_GMARK, GFN_SSI_SCK6),\n-\tPINMUX_DATA(SSI_SDATA5_MARK, FN_SSI_SDATA5),\n-\tPINMUX_DATA(SSI_WS5_MARK, FN_SSI_WS5),\n-\tPINMUX_DATA(SSI_SCK5_MARK, FN_SSI_SCK5),\n-\tPINMUX_DATA(SSI_SDATA4_GMARK, GFN_SSI_SDATA4),\n-\tPINMUX_DATA(SSI_WS4_GMARK, GFN_SSI_WS4),\n-\tPINMUX_DATA(SSI_SCK4_GMARK, GFN_SSI_SCK4),\n-\tPINMUX_DATA(SSI_SDATA3_GMARK, GFN_SSI_SDATA3),\n-\tPINMUX_DATA(SSI_WS34_GMARK, GFN_SSI_WS34),\n-\tPINMUX_DATA(SSI_SCK34_GMARK, GFN_SSI_SCK34),\n-\tPINMUX_DATA(SSI_SDATA2_A_GMARK, GFN_SSI_SDATA2_A),\n-\tPINMUX_DATA(SSI_SDATA1_A_GMARK, GFN_SSI_SDATA1_A),\n-\tPINMUX_DATA(SSI_SDATA0_GMARK, GFN_SSI_SDATA0),\n-\tPINMUX_DATA(SSI_WS01239_GMARK, GFN_SSI_WS01239),\n-\tPINMUX_DATA(SSI_SCK01239_GMARK, GFN_SSI_SCK01239),\n-\n-\t/* GPSR7 */\n-\tPINMUX_DATA(HDMI1_CEC_MARK, FN_HDMI1_CEC),\n-\tPINMUX_DATA(HDMI0_CEC_MARK, FN_HDMI0_CEC),\n-\tPINMUX_DATA(AVS2_MARK, FN_AVS2),\n-\tPINMUX_DATA(AVS1_MARK, FN_AVS1),\n-};\n-\n-static struct pinmux_gpio pinmux_gpios[] = {\n-\tPINMUX_GPIO_GP_ALL(),\n-\t/* GPSR0 */\n-\tGPIO_GFN(D15),\n-\tGPIO_GFN(D14),\n-\tGPIO_GFN(D13),\n-\tGPIO_GFN(D12),\n-\tGPIO_GFN(D11),\n-\tGPIO_GFN(D10),\n-\tGPIO_GFN(D9),\n-\tGPIO_GFN(D8),\n-\tGPIO_GFN(D7),\n-\tGPIO_GFN(D6),\n-\tGPIO_GFN(D5),\n-\tGPIO_GFN(D4),\n-\tGPIO_GFN(D3),\n-\tGPIO_GFN(D2),\n-\tGPIO_GFN(D1),\n-\tGPIO_GFN(D0),\n-\t/* GPSR1 */\n-\tGPIO_GFN(CLKOUT),\n-\tGPIO_GFN(EX_WAIT0_A),\n-\tGPIO_GFN(WE1x),\n-\tGPIO_GFN(WE0x),\n-\tGPIO_GFN(RD_WRx),\n-\tGPIO_GFN(RDx),\n-\tGPIO_GFN(BSx),\n-\tGPIO_GFN(CS1x_A26),\n-\tGPIO_GFN(CS0x),\n-\tGPIO_GFN(A19),\n-\tGPIO_GFN(A18),\n-\tGPIO_GFN(A17),\n-\tGPIO_GFN(A16),\n-\tGPIO_GFN(A15),\n-\tGPIO_GFN(A14),\n-\tGPIO_GFN(A13),\n-\tGPIO_GFN(A12),\n-\tGPIO_GFN(A11),\n-\tGPIO_GFN(A10),\n-\tGPIO_GFN(A9),\n-\tGPIO_GFN(A8),\n-\tGPIO_GFN(A7),\n-\tGPIO_GFN(A6),\n-\tGPIO_GFN(A5),\n-\tGPIO_GFN(A4),\n-\tGPIO_GFN(A3),\n-\tGPIO_GFN(A2),\n-\tGPIO_GFN(A1),\n-\tGPIO_GFN(A0),\n-\n-\t/* GPSR2 */\n-\tGPIO_GFN(AVB_AVTP_CAPTURE_A),\n-\tGPIO_GFN(AVB_AVTP_MATCH_A),\n-\tGPIO_GFN(AVB_LINK),\n-\tGPIO_GFN(AVB_PHY_INT),\n-\tGPIO_GFN(AVB_MAGIC),\n-\tGPIO_GFN(AVB_MDC),\n-\tGPIO_GFN(PWM2_A),\n-\tGPIO_GFN(PWM1_A),\n-\tGPIO_GFN(PWM0),\n-\tGPIO_GFN(IRQ5),\n-\tGPIO_GFN(IRQ4),\n-\tGPIO_GFN(IRQ3),\n-\tGPIO_GFN(IRQ2),\n-\tGPIO_GFN(IRQ1),\n-\tGPIO_GFN(IRQ0),\n-\n-\t/* GPSR3 */\n-\tGPIO_GFN(SD1_WP),\n-\tGPIO_GFN(SD1_CD),\n-\tGPIO_GFN(SD0_WP),\n-\tGPIO_GFN(SD0_CD),\n-\tGPIO_GFN(SD1_DAT3),\n-\tGPIO_GFN(SD1_DAT2),\n-\tGPIO_GFN(SD1_DAT1),\n-\tGPIO_GFN(SD1_DAT0),\n-\tGPIO_GFN(SD1_CMD),\n-\tGPIO_GFN(SD1_CLK),\n-\tGPIO_GFN(SD0_DAT3),\n-\tGPIO_GFN(SD0_DAT2),\n-\tGPIO_GFN(SD0_DAT1),\n-\tGPIO_GFN(SD0_DAT0),\n-\tGPIO_GFN(SD0_CMD),\n-\tGPIO_GFN(SD0_CLK),\n-\n-\t/* GPSR4 */\n-\tGPIO_GFN(SD3_DS),\n-\tGPIO_GFN(SD3_DAT7),\n-\tGPIO_GFN(SD3_DAT6),\n-\tGPIO_GFN(SD3_DAT5),\n-\tGPIO_GFN(SD3_DAT4),\n-\tGPIO_GFN(SD3_DAT3),\n-\tGPIO_GFN(SD3_DAT2),\n-\tGPIO_GFN(SD3_DAT1),\n-\tGPIO_GFN(SD3_DAT0),\n-\tGPIO_GFN(SD3_CMD),\n-\tGPIO_GFN(SD3_CLK),\n-\tGPIO_GFN(SD2_DS),\n-\tGPIO_GFN(SD2_DAT3),\n-\tGPIO_GFN(SD2_DAT2),\n-\tGPIO_GFN(SD2_DAT1),\n-\tGPIO_GFN(SD2_DAT0),\n-\tGPIO_GFN(SD2_CMD),\n-\tGPIO_GFN(SD2_CLK),\n-\n-\t/* GPSR5 */\n-\tGPIO_GFN(MLB_DAT),\n-\tGPIO_GFN(MLB_SIG),\n-\tGPIO_GFN(MLB_CLK),\n-\tGPIO_FN(MSIOF0_RXD),\n-\tGPIO_GFN(MSIOF0_SS2),\n-\tGPIO_FN(MSIOF0_TXD),\n-\tGPIO_GFN(MSIOF0_SS1),\n-\tGPIO_GFN(MSIOF0_SYNC),\n-\tGPIO_FN(MSIOF0_SCK),\n-\tGPIO_GFN(HRTS0x),\n-\tGPIO_GFN(HCTS0x),\n-\tGPIO_GFN(HTX0),\n-\tGPIO_GFN(HRX0),\n-\tGPIO_GFN(HSCK0),\n-\tGPIO_GFN(RX2_A),\n-\tGPIO_GFN(TX2_A),\n-\tGPIO_GFN(SCK2),\n-\tGPIO_GFN(RTS1x_TANS),\n-\tGPIO_GFN(CTS1x),\n-\tGPIO_GFN(TX1_A),\n-\tGPIO_GFN(RX1_A),\n-\tGPIO_GFN(RTS0x_TANS),\n-\tGPIO_GFN(CTS0x),\n-\tGPIO_GFN(TX0),\n-\tGPIO_GFN(RX0),\n-\tGPIO_GFN(SCK0),\n-\n-\t/* GPSR6 */\n-\tGPIO_GFN(USB3_OVC),\n-\tGPIO_GFN(USB3_PWEN),\n-\tGPIO_GFN(USB30_OVC),\n-\tGPIO_GFN(USB30_PWEN),\n-\tGPIO_GFN(USB1_OVC),\n-\tGPIO_GFN(USB1_PWEN),\n-\tGPIO_GFN(USB0_OVC),\n-\tGPIO_GFN(USB0_PWEN),\n-\tGPIO_GFN(AUDIO_CLKB_B),\n-\tGPIO_GFN(AUDIO_CLKA_A),\n-\tGPIO_GFN(SSI_SDATA9_A),\n-\tGPIO_GFN(SSI_SDATA8),\n-\tGPIO_GFN(SSI_SDATA7),\n-\tGPIO_GFN(SSI_WS78),\n-\tGPIO_GFN(SSI_SCK78),\n-\tGPIO_GFN(SSI_SDATA6),\n-\tGPIO_GFN(SSI_WS6),\n-\tGPIO_GFN(SSI_SCK6),\n-\tGPIO_FN(SSI_SDATA5),\n-\tGPIO_FN(SSI_WS5),\n-\tGPIO_FN(SSI_SCK5),\n-\tGPIO_GFN(SSI_SDATA4),\n-\tGPIO_GFN(SSI_WS4),\n-\tGPIO_GFN(SSI_SCK4),\n-\tGPIO_GFN(SSI_SDATA3),\n-\tGPIO_GFN(SSI_WS34),\n-\tGPIO_GFN(SSI_SCK34),\n-\tGPIO_GFN(SSI_SDATA2_A),\n-\tGPIO_GFN(SSI_SDATA1_A),\n-\tGPIO_GFN(SSI_SDATA0),\n-\tGPIO_GFN(SSI_WS01239),\n-\tGPIO_GFN(SSI_SCK01239),\n-\n-\t/* GPSR7 */\n-\tGPIO_FN(HDMI1_CEC),\n-\tGPIO_FN(HDMI0_CEC),\n-\tGPIO_FN(AVS2),\n-\tGPIO_FN(AVS1),\n-\n-\t/* IPSR0 */\n-\tGPIO_IFN(AVB_MDC),\n-\tGPIO_FN(MSIOF2_SS2_C),\n-\tGPIO_IFN(AVB_MAGIC),\n-\tGPIO_FN(MSIOF2_SS1_C),\n-\tGPIO_FN(SCK4_A),\n-\tGPIO_IFN(AVB_PHY_INT),\n-\tGPIO_FN(MSIOF2_SYNC_C),\n-\tGPIO_FN(RX4_A),\n-\tGPIO_IFN(AVB_LINK),\n-\tGPIO_FN(MSIOF2_SCK_C),\n-\tGPIO_FN(TX4_A),\n-\tGPIO_IFN(AVB_AVTP_MATCH_A),\n-\tGPIO_FN(MSIOF2_RXD_C),\n-\tGPIO_FN(CTS4x_A),\n-\tGPIO_FN(FSCLKST2x_A),\n-\tGPIO_IFN(AVB_AVTP_CAPTURE_A),\n-\tGPIO_FN(MSIOF2_TXD_C),\n-\tGPIO_FN(RTS4x_TANS_A),\n-\tGPIO_IFN(IRQ0),\n-\tGPIO_FN(QPOLB),\n-\tGPIO_FN(DU_CDE),\n-\tGPIO_FN(VI4_DATA0_B),\n-\tGPIO_FN(CAN0_TX_B),\n-\tGPIO_FN(CANFD0_TX_B),\n-\tGPIO_FN(MSIOF3_SS2_E),\n-\tGPIO_IFN(IRQ1),\n-\tGPIO_FN(QPOLA),\n-\tGPIO_FN(DU_DISP),\n-\tGPIO_FN(VI4_DATA1_B),\n-\tGPIO_FN(CAN0_RX_B),\n-\tGPIO_FN(CANFD0_RX_B),\n-\tGPIO_FN(MSIOF3_SS1_E),\n-\n-\t/* IPSR1 */\n-\tGPIO_IFN(IRQ2),\n-\tGPIO_FN(QCPV_QDE),\n-\tGPIO_FN(DU_EXODDF_DU_ODDF_DISP_CDE),\n-\tGPIO_FN(VI4_DATA2_B),\n-\tGPIO_FN(MSIOF3_SYNC_E),\n-\tGPIO_FN(PWM3_B),\n-\tGPIO_IFN(IRQ3),\n-\tGPIO_FN(QSTVB_QVE),\n-\tGPIO_FN(DU_DOTCLKOUT1),\n-\tGPIO_FN(VI4_DATA3_B),\n-\tGPIO_FN(MSIOF3_SCK_E),\n-\tGPIO_FN(PWM4_B),\n-\tGPIO_IFN(IRQ4),\n-\tGPIO_FN(QSTH_QHS),\n-\tGPIO_FN(DU_EXHSYNC_DU_HSYNC),\n-\tGPIO_FN(VI4_DATA4_B),\n-\tGPIO_FN(MSIOF3_RXD_E),\n-\tGPIO_FN(PWM5_B),\n-\tGPIO_IFN(IRQ5),\n-\tGPIO_FN(QSTB_QHE),\n-\tGPIO_FN(DU_EXVSYNC_DU_VSYNC),\n-\tGPIO_FN(VI4_DATA5_B),\n-\tGPIO_FN(FSCLKST2x_B),\n-\tGPIO_FN(MSIOF3_TXD_E),\n-\tGPIO_FN(PWM6_B),\n-\tGPIO_IFN(PWM0),\n-\tGPIO_FN(AVB_AVTP_PPS),\n-\tGPIO_FN(VI4_DATA6_B),\n-\tGPIO_FN(IECLK_B),\n-\tGPIO_IFN(PWM1_A),\n-\tGPIO_FN(HRX3_D),\n-\tGPIO_FN(VI4_DATA7_B),\n-\tGPIO_FN(IERX_B),\n-\tGPIO_IFN(PWM2_A),\n-\tGPIO_FN(HTX3_D),\n-\tGPIO_FN(IETX_B),\n-\tGPIO_IFN(A0),\n-\tGPIO_FN(LCDOUT16),\n-\tGPIO_FN(MSIOF3_SYNC_B),\n-\tGPIO_FN(VI4_DATA8),\n-\tGPIO_FN(DU_DB0),\n-\tGPIO_FN(PWM3_A),\n-\n-\t/* IPSR2 */\n-\tGPIO_IFN(A1),\n-\tGPIO_FN(LCDOUT17),\n-\tGPIO_FN(MSIOF3_TXD_B),\n-\tGPIO_FN(VI4_DATA9),\n-\tGPIO_FN(DU_DB1),\n-\tGPIO_FN(PWM4_A),\n-\tGPIO_IFN(A2),\n-\tGPIO_FN(LCDOUT18),\n-\tGPIO_FN(MSIOF3_SCK_B),\n-\tGPIO_FN(VI4_DATA10),\n-\tGPIO_FN(DU_DB2),\n-\tGPIO_FN(PWM5_A),\n-\tGPIO_IFN(A3),\n-\tGPIO_FN(LCDOUT19),\n-\tGPIO_FN(MSIOF3_RXD_B),\n-\tGPIO_FN(VI4_DATA11),\n-\tGPIO_FN(DU_DB3),\n-\tGPIO_FN(PWM6_A),\n-\tGPIO_IFN(A4),\n-\tGPIO_FN(LCDOUT20),\n-\tGPIO_FN(MSIOF3_SS1_B),\n-\tGPIO_FN(VI4_DATA12),\n-\tGPIO_FN(VI5_DATA12),\n-\tGPIO_FN(DU_DB4),\n-\tGPIO_IFN(A5),\n-\tGPIO_FN(LCDOUT21),\n-\tGPIO_FN(MSIOF3_SS2_B),\n-\tGPIO_FN(SCK4_B),\n-\tGPIO_FN(VI4_DATA13),\n-\tGPIO_FN(VI5_DATA13),\n-\tGPIO_FN(DU_DB5),\n-\tGPIO_IFN(A6),\n-\tGPIO_FN(LCDOUT22),\n-\tGPIO_FN(MSIOF2_SS1_A),\n-\tGPIO_FN(RX4_B),\n-\tGPIO_FN(VI4_DATA14),\n-\tGPIO_FN(VI5_DATA14),\n-\tGPIO_FN(DU_DB6),\n-\tGPIO_IFN(A7),\n-\tGPIO_FN(LCDOUT23),\n-\tGPIO_FN(MSIOF2_SS2_A),\n-\tGPIO_FN(TX4_B),\n-\tGPIO_FN(VI4_DATA15),\n-\tGPIO_FN(V15_DATA15),\n-\tGPIO_FN(DU_DB7),\n-\tGPIO_IFN(A8),\n-\tGPIO_FN(RX3_B),\n-\tGPIO_FN(MSIOF2_SYNC_A),\n-\tGPIO_FN(HRX4_B),\n-\tGPIO_FN(SDA6_A),\n-\tGPIO_FN(AVB_AVTP_MATCH_B),\n-\tGPIO_FN(PWM1_B),\n-\n-\t/* IPSR3 */\n-\tGPIO_IFN(A9),\n-\tGPIO_FN(MSIOF2_SCK_A),\n-\tGPIO_FN(CTS4x_B),\n-\tGPIO_FN(VI5_VSYNCx),\n-\tGPIO_IFN(A10),\n-\tGPIO_FN(MSIOF2_RXD_A),\n-\tGPIO_FN(RTS4n_TANS_B),\n-\tGPIO_FN(VI5_HSYNCx),\n-\tGPIO_IFN(A11),\n-\tGPIO_FN(TX3_B),\n-\tGPIO_FN(MSIOF2_TXD_A),\n-\tGPIO_FN(HTX4_B),\n-\tGPIO_FN(HSCK4),\n-\tGPIO_FN(VI5_FIELD),\n-\tGPIO_FN(SCL6_A),\n-\tGPIO_FN(AVB_AVTP_CAPTURE_B),\n-\tGPIO_FN(PWM2_B),\n-\tGPIO_IFN(A12),\n-\tGPIO_FN(LCDOUT12),\n-\tGPIO_FN(MSIOF3_SCK_C),\n-\tGPIO_FN(HRX4_A),\n-\tGPIO_FN(VI5_DATA8),\n-\tGPIO_FN(DU_DG4),\n-\tGPIO_IFN(A13),\n-\tGPIO_FN(LCDOUT13),\n-\tGPIO_FN(MSIOF3_SYNC_C),\n-\tGPIO_FN(HTX4_A),\n-\tGPIO_FN(VI5_DATA9),\n-\tGPIO_FN(DU_DG5),\n-\tGPIO_IFN(A14),\n-\tGPIO_FN(LCDOUT14),\n-\tGPIO_FN(MSIOF3_RXD_C),\n-\tGPIO_FN(HCTS4x),\n-\tGPIO_FN(VI5_DATA10),\n-\tGPIO_FN(DU_DG6),\n-\tGPIO_IFN(A15),\n-\tGPIO_FN(LCDOUT15),\n-\tGPIO_FN(MSIOF3_TXD_C),\n-\tGPIO_FN(HRTS4x),\n-\tGPIO_FN(VI5_DATA11),\n-\tGPIO_FN(DU_DG7),\n-\tGPIO_IFN(A16),\n-\tGPIO_FN(LCDOUT8),\n-\tGPIO_FN(VI4_FIELD),\n-\tGPIO_FN(DU_DG0),\n-\n-\t/* IPSR4 */\n-\tGPIO_IFN(A17),\n-\tGPIO_FN(LCDOUT9),\n-\tGPIO_FN(VI4_VSYNCx),\n-\tGPIO_FN(DU_DG1),\n-\tGPIO_IFN(A18),\n-\tGPIO_FN(LCDOUT10),\n-\tGPIO_FN(VI4_HSYNCx),\n-\tGPIO_FN(DU_DG2),\n-\tGPIO_IFN(A19),\n-\tGPIO_FN(LCDOUT11),\n-\tGPIO_FN(VI4_CLKENB),\n-\tGPIO_FN(DU_DG3),\n-\tGPIO_IFN(CS0x),\n-\tGPIO_FN(VI5_CLKENB),\n-\tGPIO_IFN(CS1x_A26),\n-\tGPIO_FN(VI5_CLK),\n-\tGPIO_FN(EX_WAIT0_B),\n-\tGPIO_IFN(BSx),\n-\tGPIO_FN(QSTVA_QVS),\n-\tGPIO_FN(MSIOF3_SCK_D),\n-\tGPIO_FN(SCK3),\n-\tGPIO_FN(HSCK3),\n-\tGPIO_FN(CAN1_TX),\n-\tGPIO_FN(CANFD1_TX),\n-\tGPIO_FN(IETX_A),\n-\tGPIO_IFN(RDx),\n-\tGPIO_FN(MSIOF3_SYNC_D),\n-\tGPIO_FN(RX3_A),\n-\tGPIO_FN(HRX3_A),\n-\tGPIO_FN(CAN0_TX_A),\n-\tGPIO_FN(CANFD0_TX_A),\n-\tGPIO_IFN(RD_WRx),\n-\tGPIO_FN(MSIOF3_RXD_D),\n-\tGPIO_FN(TX3_A),\n-\tGPIO_FN(HTX3_A),\n-\tGPIO_FN(CAN0_RX_A),\n-\tGPIO_FN(CANFD0_RX_A),\n-\n-\t/* IPSR5 */\n-\tGPIO_IFN(WE0x),\n-\tGPIO_FN(MSIIOF3_TXD_D),\n-\tGPIO_FN(CTS3x),\n-\tGPIO_FN(HCTS3x),\n-\tGPIO_FN(SCL6_B),\n-\tGPIO_FN(CAN_CLK),\n-\tGPIO_FN(IECLK_A),\n-\tGPIO_IFN(WE1x),\n-\tGPIO_FN(MSIOF3_SS1_D),\n-\tGPIO_FN(RTS3x_TANS),\n-\tGPIO_FN(HRTS3x),\n-\tGPIO_FN(SDA6_B),\n-\tGPIO_FN(CAN1_RX),\n-\tGPIO_FN(CANFD1_RX),\n-\tGPIO_FN(IERX_A),\n-\tGPIO_IFN(EX_WAIT0_A),\n-\tGPIO_FN(QCLK),\n-\tGPIO_FN(VI4_CLK),\n-\tGPIO_FN(DU_DOTCLKOUT0),\n-\tGPIO_IFN(D0),\n-\tGPIO_FN(MSIOF2_SS1_B),\n-\tGPIO_FN(MSIOF3_SCK_A),\n-\tGPIO_FN(VI4_DATA16),\n-\tGPIO_FN(VI5_DATA0),\n-\tGPIO_IFN(D1),\n-\tGPIO_FN(MSIOF2_SS2_B),\n-\tGPIO_FN(MSIOF3_SYNC_A),\n-\tGPIO_FN(VI4_DATA17),\n-\tGPIO_FN(VI5_DATA1),\n-\tGPIO_IFN(D2),\n-\tGPIO_FN(MSIOF3_RXD_A),\n-\tGPIO_FN(VI4_DATA18),\n-\tGPIO_FN(VI5_DATA2),\n-\tGPIO_IFN(D3),\n-\tGPIO_FN(MSIOF3_TXD_A),\n-\tGPIO_FN(VI4_DATA19),\n-\tGPIO_FN(VI5_DATA3),\n-\tGPIO_IFN(D4),\n-\tGPIO_FN(MSIOF2_SCK_B),\n-\tGPIO_FN(VI4_DATA20),\n-\tGPIO_FN(VI5_DATA4),\n-\n-\t/* IPSR6 */\n-\tGPIO_IFN(D5),\n-\tGPIO_FN(MSIOF2_SYNC_B),\n-\tGPIO_FN(VI4_DATA21),\n-\tGPIO_FN(VI5_DATA5),\n-\tGPIO_IFN(D6),\n-\tGPIO_FN(MSIOF2_RXD_B),\n-\tGPIO_FN(VI4_DATA22),\n-\tGPIO_FN(VI5_DATA6),\n-\tGPIO_IFN(D7),\n-\tGPIO_FN(MSIOF2_TXD_B),\n-\tGPIO_FN(VI4_DATA23),\n-\tGPIO_FN(VI5_DATA7),\n-\tGPIO_IFN(D8),\n-\tGPIO_FN(LCDOUT0),\n-\tGPIO_FN(MSIOF2_SCK_D),\n-\tGPIO_FN(SCK4_C),\n-\tGPIO_FN(VI4_DATA0_A),\n-\tGPIO_FN(DU_DR0),\n-\tGPIO_IFN(D9),\n-\tGPIO_FN(LCDOUT1),\n-\tGPIO_FN(MSIOF2_SYNC_D),\n-\tGPIO_FN(VI4_DATA1_A),\n-\tGPIO_FN(DU_DR1),\n-\tGPIO_IFN(D10),\n-\tGPIO_FN(LCDOUT2),\n-\tGPIO_FN(MSIOF2_RXD_D),\n-\tGPIO_FN(HRX3_B),\n-\tGPIO_FN(VI4_DATA2_A),\n-\tGPIO_FN(CTS4x_C),\n-\tGPIO_FN(DU_DR2),\n-\tGPIO_IFN(D11),\n-\tGPIO_FN(LCDOUT3),\n-\tGPIO_FN(MSIOF2_TXD_D),\n-\tGPIO_FN(HTX3_B),\n-\tGPIO_FN(VI4_DATA3_A),\n-\tGPIO_FN(RTS4x_TANS_C),\n-\tGPIO_FN(DU_DR3),\n-\tGPIO_IFN(D12),\n-\tGPIO_FN(LCDOUT4),\n-\tGPIO_FN(MSIOF2_SS1_D),\n-\tGPIO_FN(RX4_C),\n-\tGPIO_FN(VI4_DATA4_A),\n-\tGPIO_FN(DU_DR4),\n-\n-\t/* IPSR7 */\n-\tGPIO_IFN(D13),\n-\tGPIO_FN(LCDOUT5),\n-\tGPIO_FN(MSIOF2_SS2_D),\n-\tGPIO_FN(TX4_C),\n-\tGPIO_FN(VI4_DATA5_A),\n-\tGPIO_FN(DU_DR5),\n-\tGPIO_IFN(D14),\n-\tGPIO_FN(LCDOUT6),\n-\tGPIO_FN(MSIOF3_SS1_A),\n-\tGPIO_FN(HRX3_C),\n-\tGPIO_FN(VI4_DATA6_A),\n-\tGPIO_FN(DU_DR6),\n-\tGPIO_FN(SCL6_C),\n-\tGPIO_IFN(D15),\n-\tGPIO_FN(LCDOUT7),\n-\tGPIO_FN(MSIOF3_SS2_A),\n-\tGPIO_FN(HTX3_C),\n-\tGPIO_FN(VI4_DATA7_A),\n-\tGPIO_FN(DU_DR7),\n-\tGPIO_FN(SDA6_C),\n-\tGPIO_FN(FSCLKST),\n-\tGPIO_IFN(SD0_CLK),\n-\tGPIO_FN(MSIOF1_SCK_E),\n-\tGPIO_FN(STP_OPWM_0_B),\n-\tGPIO_IFN(SD0_CMD),\n-\tGPIO_FN(MSIOF1_SYNC_E),\n-\tGPIO_FN(STP_IVCXO27_0_B),\n-\tGPIO_IFN(SD0_DAT0),\n-\tGPIO_FN(MSIOF1_RXD_E),\n-\tGPIO_FN(TS_SCK0_B),\n-\tGPIO_FN(STP_ISCLK_0_B),\n-\tGPIO_IFN(SD0_DAT1),\n-\tGPIO_FN(MSIOF1_TXD_E),\n-\tGPIO_FN(TS_SPSYNC0_B),\n-\tGPIO_FN(STP_ISSYNC_0_B),\n-\n-\t/* IPSR8 */\n-\tGPIO_IFN(SD0_DAT2),\n-\tGPIO_FN(MSIOF1_SS1_E),\n-\tGPIO_FN(TS_SDAT0_B),\n-\tGPIO_FN(STP_ISD_0_B),\n-\tGPIO_IFN(SD0_DAT3),\n-\tGPIO_FN(MSIOF1_SS2_E),\n-\tGPIO_FN(TS_SDEN0_B),\n-\tGPIO_FN(STP_ISEN_0_B),\n-\tGPIO_IFN(SD1_CLK),\n-\tGPIO_FN(MSIOF1_SCK_G),\n-\tGPIO_FN(SIM0_CLK_A),\n-\tGPIO_IFN(SD1_CMD),\n-\tGPIO_FN(MSIOF1_SYNC_G),\n-\tGPIO_FN(NFCEx_B),\n-\tGPIO_FN(SIM0_D_A),\n-\tGPIO_FN(STP_IVCXO27_1_B),\n-\tGPIO_IFN(SD1_DAT0),\n-\tGPIO_FN(SD2_DAT4),\n-\tGPIO_FN(MSIOF1_RXD_G),\n-\tGPIO_FN(NFWPx_B),\n-\tGPIO_FN(TS_SCK1_B),\n-\tGPIO_FN(STP_ISCLK_1_B),\n-\tGPIO_IFN(SD1_DAT1),\n-\tGPIO_FN(SD2_DAT5),\n-\tGPIO_FN(MSIOF1_TXD_G),\n-\tGPIO_FN(NFDATA14_B),\n-\tGPIO_FN(TS_SPSYNC1_B),\n-\tGPIO_FN(STP_ISSYNC_1_B),\n-\tGPIO_IFN(SD1_DAT2),\n-\tGPIO_FN(SD2_DAT6),\n-\tGPIO_FN(MSIOF1_SS1_G),\n-\tGPIO_FN(NFDATA15_B),\n-\tGPIO_FN(TS_SDAT1_B),\n-\tGPIO_FN(STP_IOD_1_B),\n-\tGPIO_IFN(SD1_DAT3),\n-\tGPIO_FN(SD2_DAT7),\n-\tGPIO_FN(MSIOF1_SS2_G),\n-\tGPIO_FN(NFRBx_B),\n-\tGPIO_FN(TS_SDEN1_B),\n-\tGPIO_FN(STP_ISEN_1_B),\n-\n-\t/* IPSR9 */\n-\tGPIO_IFN(SD2_CLK),\n-\tGPIO_FN(NFDATA8),\n-\tGPIO_IFN(SD2_CMD),\n-\tGPIO_FN(NFDATA9),\n-\tGPIO_IFN(SD2_DAT0),\n-\tGPIO_FN(NFDATA10),\n-\tGPIO_IFN(SD2_DAT1),\n-\tGPIO_FN(NFDATA11),\n-\tGPIO_IFN(SD2_DAT2),\n-\tGPIO_FN(NFDATA12),\n-\tGPIO_IFN(SD2_DAT3),\n-\tGPIO_FN(NFDATA13),\n-\tGPIO_IFN(SD2_DS),\n-\tGPIO_FN(NFALE),\n-\tGPIO_FN(SATA_DEVSLP_B),\n-\tGPIO_IFN(SD3_CLK),\n-\tGPIO_FN(NFWEx),\n-\n-\t/* IPSR10 */\n-\tGPIO_IFN(SD3_CMD),\n-\tGPIO_FN(NFREx),\n-\tGPIO_IFN(SD3_DAT0),\n-\tGPIO_FN(NFDATA0),\n-\tGPIO_IFN(SD3_DAT1),\n-\tGPIO_FN(NFDATA1),\n-\tGPIO_IFN(SD3_DAT2),\n-\tGPIO_FN(NFDATA2),\n-\tGPIO_IFN(SD3_DAT3),\n-\tGPIO_FN(NFDATA3),\n-\tGPIO_IFN(SD3_DAT4),\n-\tGPIO_FN(SD2_CD_A),\n-\tGPIO_FN(NFDATA4),\n-\tGPIO_IFN(SD3_DAT5),\n-\tGPIO_FN(SD2_WP_A),\n-\tGPIO_FN(NFDATA5),\n-\tGPIO_IFN(SD3_DAT6),\n-\tGPIO_FN(SD3_CD),\n-\tGPIO_FN(NFDATA6),\n-\n-\t/* IPSR11 */\n-\tGPIO_IFN(SD3_DAT7),\n-\tGPIO_FN(SD3_WP),\n-\tGPIO_FN(NFDATA7),\n-\tGPIO_IFN(SD3_DS),\n-\tGPIO_FN(NFCLE),\n-\tGPIO_IFN(SD0_CD),\n-\tGPIO_FN(NFDATA14_A),\n-\tGPIO_FN(SCL2_B),\n-\tGPIO_FN(SIM0_RST_A),\n-\tGPIO_IFN(SD0_WP),\n-\tGPIO_FN(NFDATA15_A),\n-\tGPIO_FN(SDA2_B),\n-\tGPIO_IFN(SD1_CD),\n-\tGPIO_FN(NFRBx_A),\n-\tGPIO_FN(SIM0_CLK_B),\n-\tGPIO_IFN(SD1_WP),\n-\tGPIO_FN(NFCEx_A),\n-\tGPIO_FN(SIM0_D_B),\n-\tGPIO_IFN(SCK0),\n-\tGPIO_FN(HSCK1_B),\n-\tGPIO_FN(MSIOF1_SS2_B),\n-\tGPIO_FN(AUDIO_CLKC_B),\n-\tGPIO_FN(SDA2_A),\n-\tGPIO_FN(SIM0_RST_B),\n-\tGPIO_FN(STP_OPWM_0_C),\n-\tGPIO_FN(RIF0_CLK_B),\n-\tGPIO_FN(ADICHS2),\n-\tGPIO_FN(SCK5_B),\n-\tGPIO_IFN(RX0),\n-\tGPIO_FN(HRX1_B),\n-\tGPIO_FN(TS_SCK0_C),\n-\tGPIO_FN(STP_ISCLK_0_C),\n-\tGPIO_FN(RIF0_D0_B),\n-\n-\t/* IPSR12 */\n-\tGPIO_IFN(TX0),\n-\tGPIO_FN(HTX1_B),\n-\tGPIO_FN(TS_SPSYNC0_C),\n-\tGPIO_FN(STP_ISSYNC_0_C),\n-\tGPIO_FN(RIF0_D1_B),\n-\tGPIO_IFN(CTS0x),\n-\tGPIO_FN(HCTS1x_B),\n-\tGPIO_FN(MSIOF1_SYNC_B),\n-\tGPIO_FN(TS_SPSYNC1_C),\n-\tGPIO_FN(STP_ISSYNC_1_C),\n-\tGPIO_FN(RIF1_SYNC_B),\n-\tGPIO_FN(AUDIO_CLKOUT_C),\n-\tGPIO_FN(ADICS_SAMP),\n-\tGPIO_IFN(RTS0x_TANS),\n-\tGPIO_FN(HRTS1x_B),\n-\tGPIO_FN(MSIOF1_SS1_B),\n-\tGPIO_FN(AUDIO_CLKA_B),\n-\tGPIO_FN(SCL2_A),\n-\tGPIO_FN(STP_IVCXO27_1_C),\n-\tGPIO_FN(RIF0_SYNC_B),\n-\tGPIO_FN(ADICHS1),\n-\tGPIO_IFN(RX1_A),\n-\tGPIO_FN(HRX1_A),\n-\tGPIO_FN(TS_SDAT0_C),\n-\tGPIO_FN(STP_ISD_0_C),\n-\tGPIO_FN(RIF1_CLK_C),\n-\tGPIO_IFN(TX1_A),\n-\tGPIO_FN(HTX1_A),\n-\tGPIO_FN(TS_SDEN0_C),\n-\tGPIO_FN(STP_ISEN_0_C),\n-\tGPIO_FN(RIF1_D0_C),\n-\tGPIO_IFN(CTS1x),\n-\tGPIO_FN(HCTS1x_A),\n-\tGPIO_FN(MSIOF1_RXD_B),\n-\tGPIO_FN(TS_SDEN1_C),\n-\tGPIO_FN(STP_ISEN_1_C),\n-\tGPIO_FN(RIF1_D0_B),\n-\tGPIO_FN(ADIDATA),\n-\tGPIO_IFN(RTS1x_TANS),\n-\tGPIO_FN(HRTS1x_A),\n-\tGPIO_FN(MSIOF1_TXD_B),\n-\tGPIO_FN(TS_SDAT1_C),\n-\tGPIO_FN(STP_ISD_1_C),\n-\tGPIO_FN(RIF1_D1_B),\n-\tGPIO_FN(ADICHS0),\n-\tGPIO_IFN(SCK2),\n-\tGPIO_FN(SCIF_CLK_B),\n-\tGPIO_FN(MSIOF1_SCK_B),\n-\tGPIO_FN(TS_SCK1_C),\n-\tGPIO_FN(STP_ISCLK_1_C),\n-\tGPIO_FN(RIF1_CLK_B),\n-\tGPIO_FN(ADICLK),\n-\n-\t/* IPSR13 */\n-\tGPIO_IFN(TX2_A),\n-\tGPIO_FN(SD2_CD_B),\n-\tGPIO_FN(SCL1_A),\n-\tGPIO_FN(FMCLK_A),\n-\tGPIO_FN(RIF1_D1_C),\n-\tGPIO_FN(FSO_CFE_0x),\n-\tGPIO_IFN(RX2_A),\n-\tGPIO_FN(SD2_WP_B),\n-\tGPIO_FN(SDA1_A),\n-\tGPIO_FN(FMIN_A),\n-\tGPIO_FN(RIF1_SYNC_C),\n-\tGPIO_FN(FSO_CFE_1x),\n-\tGPIO_IFN(HSCK0),\n-\tGPIO_FN(MSIOF1_SCK_D),\n-\tGPIO_FN(AUDIO_CLKB_A),\n-\tGPIO_FN(SSI_SDATA1_B),\n-\tGPIO_FN(TS_SCK0_D),\n-\tGPIO_FN(STP_ISCLK_0_D),\n-\tGPIO_FN(RIF0_CLK_C),\n-\tGPIO_FN(RX5_B),\n-\tGPIO_IFN(HRX0),\n-\tGPIO_FN(MSIOF1_RXD_D),\n-\tGPIO_FN(SSI_SDATA2_B),\n-\tGPIO_FN(TS_SDEN0_D),\n-\tGPIO_FN(STP_ISEN_0_D),\n-\tGPIO_FN(RIF0_D0_C),\n-\tGPIO_IFN(HTX0),\n-\tGPIO_FN(MSIOF1_TXD_D),\n-\tGPIO_FN(SSI_SDATA9_B),\n-\tGPIO_FN(TS_SDAT0_D),\n-\tGPIO_FN(STP_ISD_0_D),\n-\tGPIO_FN(RIF0_D1_C),\n-\tGPIO_IFN(HCTS0x),\n-\tGPIO_FN(RX2_B),\n-\tGPIO_FN(MSIOF1_SYNC_D),\n-\tGPIO_FN(SSI_SCK9_A),\n-\tGPIO_FN(TS_SPSYNC0_D),\n-\tGPIO_FN(STP_ISSYNC_0_D),\n-\tGPIO_FN(RIF0_SYNC_C),\n-\tGPIO_FN(AUDIO_CLKOUT1_A),\n-\tGPIO_IFN(HRTS0x),\n-\tGPIO_FN(TX2_B),\n-\tGPIO_FN(MSIOF1_SS1_D),\n-\tGPIO_FN(SSI_WS9_A),\n-\tGPIO_FN(STP_IVCXO27_0_D),\n-\tGPIO_FN(BPFCLK_A),\n-\tGPIO_FN(AUDIO_CLKOUT2_A),\n-\tGPIO_IFN(MSIOF0_SYNC),\n-\tGPIO_FN(AUDIO_CLKOUT_A),\n-\tGPIO_FN(TX5_B),\n-\tGPIO_FN(BPFCLK_D),\n-\n-\t/* IPSR14 */\n-\tGPIO_IFN(MSIOF0_SS1),\n-\tGPIO_FN(RX5_A),\n-\tGPIO_FN(NFWPx_A),\n-\tGPIO_FN(AUDIO_CLKA_C),\n-\tGPIO_FN(SSI_SCK2_A),\n-\tGPIO_FN(STP_IVCXO27_0_C),\n-\tGPIO_FN(AUDIO_CLKOUT3_A),\n-\tGPIO_FN(TCLK1_B),\n-\tGPIO_IFN(MSIOF0_SS2),\n-\tGPIO_FN(TX5_A),\n-\tGPIO_FN(MSIOF1_SS2_D),\n-\tGPIO_FN(AUDIO_CLKC_A),\n-\tGPIO_FN(SSI_WS2_A),\n-\tGPIO_FN(STP_OPWM_0_D),\n-\tGPIO_FN(AUDIO_CLKOUT_D),\n-\tGPIO_FN(SPEEDIN_B),\n-\tGPIO_IFN(MLB_CLK),\n-\tGPIO_FN(MSIOF1_SCK_F),\n-\tGPIO_FN(SCL1_B),\n-\tGPIO_IFN(MLB_SIG),\n-\tGPIO_FN(RX1_B),\n-\tGPIO_FN(MSIOF1_SYNC_F),\n-\tGPIO_FN(SDA1_B),\n-\tGPIO_IFN(MLB_DAT),\n-\tGPIO_FN(TX1_B),\n-\tGPIO_FN(MSIOF1_RXD_F),\n-\tGPIO_IFN(SSI_SCK01239),\n-\tGPIO_FN(MSIOF1_TXD_F),\n-\tGPIO_FN(MOUT0),\n-\tGPIO_IFN(SSI_WS01239),\n-\tGPIO_FN(MSIOF1_SS1_F),\n-\tGPIO_FN(MOUT1),\n-\tGPIO_IFN(SSI_SDATA0),\n-\tGPIO_FN(MSIOF1_SS2_F),\n-\tGPIO_FN(MOUT2),\n-\n-\t/* IPSR15 */\n-\tGPIO_IFN(SSI_SDATA1_A),\n-\tGPIO_FN(MOUT5),\n-\tGPIO_IFN(SSI_SDATA2_A),\n-\tGPIO_FN(SSI_SCK1_B),\n-\tGPIO_FN(MOUT6),\n-\tGPIO_IFN(SSI_SCK34),\n-\tGPIO_FN(MSIOF1_SS1_A),\n-\tGPIO_FN(STP_OPWM_0_A),\n-\tGPIO_IFN(SSI_WS34),\n-\tGPIO_FN(HCTS2x_A),\n-\tGPIO_FN(MSIOF1_SS2_A),\n-\tGPIO_FN(STP_IVCXO27_0_A),\n-\tGPIO_IFN(SSI_SDATA3),\n-\tGPIO_FN(HRTS2x_A),\n-\tGPIO_FN(MSIOF1_TXD_A),\n-\tGPIO_FN(TS_SCK0_A),\n-\tGPIO_FN(STP_ISCLK_0_A),\n-\tGPIO_FN(RIF0_D1_A),\n-\tGPIO_FN(RIF2_D0_A),\n-\tGPIO_IFN(SSI_SCK4),\n-\tGPIO_FN(HRX2_A),\n-\tGPIO_FN(MSIOF1_SCK_A),\n-\tGPIO_FN(TS_SDAT0_A),\n-\tGPIO_FN(STP_ISD_0_A),\n-\tGPIO_FN(RIF0_CLK_A),\n-\tGPIO_FN(RIF2_CLK_A),\n-\tGPIO_IFN(SSI_WS4),\n-\tGPIO_FN(HTX2_A),\n-\tGPIO_FN(MSIOF1_SYNC_A),\n-\tGPIO_FN(TS_SDEN0_A),\n-\tGPIO_FN(STP_ISEN_0_A),\n-\tGPIO_FN(RIF0_SYNC_A),\n-\tGPIO_FN(RIF2_SYNC_A),\n-\tGPIO_IFN(SSI_SDATA4),\n-\tGPIO_FN(HSCK2_A),\n-\tGPIO_FN(MSIOF1_RXD_A),\n-\tGPIO_FN(TS_SPSYNC0_A),\n-\tGPIO_FN(STP_ISSYNC_0_A),\n-\tGPIO_FN(RIF0_D0_A),\n-\tGPIO_FN(RIF2_D1_A),\n-\n-\t/* IPSR16 */\n-\tGPIO_IFN(SSI_SCK6),\n-\tGPIO_FN(SIM0_RST_D),\n-\tGPIO_IFN(SSI_WS6),\n-\tGPIO_FN(SIM0_D_D),\n-\tGPIO_IFN(SSI_SDATA6),\n-\tGPIO_FN(SIM0_CLK_D),\n-\tGPIO_FN(SATA_DEVSLP_A),\n-\tGPIO_IFN(SSI_SCK78),\n-\tGPIO_FN(HRX2_B),\n-\tGPIO_FN(MSIOF1_SCK_C),\n-\tGPIO_FN(TS_SCK1_A),\n-\tGPIO_FN(STP_ISCLK_1_A),\n-\tGPIO_FN(RIF1_CLK_A),\n-\tGPIO_FN(RIF3_CLK_A),\n-\tGPIO_IFN(SSI_WS78),\n-\tGPIO_FN(HTX2_B),\n-\tGPIO_FN(MSIOF1_SYNC_C),\n-\tGPIO_FN(TS_SDAT1_A),\n-\tGPIO_FN(STP_ISD_1_A),\n-\tGPIO_FN(RIF1_SYNC_A),\n-\tGPIO_FN(RIF3_SYNC_A),\n-\tGPIO_IFN(SSI_SDATA7),\n-\tGPIO_FN(HCTS2x_B),\n-\tGPIO_FN(MSIOF1_RXD_C),\n-\tGPIO_FN(TS_SDEN1_A),\n-\tGPIO_FN(STP_ISEN_1_A),\n-\tGPIO_FN(RIF1_D0_A),\n-\tGPIO_FN(RIF3_D0_A),\n-\tGPIO_FN(TCLK2_A),\n-\tGPIO_IFN(SSI_SDATA8),\n-\tGPIO_FN(HRTS2x_B),\n-\tGPIO_FN(MSIOF1_TXD_C),\n-\tGPIO_FN(TS_SPSYNC1_A),\n-\tGPIO_FN(STP_ISSYNC_1_A),\n-\tGPIO_FN(RIF1_D1_A),\n-\tGPIO_FN(RIF3_D1_A),\n-\tGPIO_IFN(SSI_SDATA9_A),\n-\tGPIO_FN(HSCK2_B),\n-\tGPIO_FN(MSIOF1_SS1_C),\n-\tGPIO_FN(HSCK1_A),\n-\tGPIO_FN(SSI_WS1_B),\n-\tGPIO_FN(SCK1),\n-\tGPIO_FN(STP_IVCXO27_1_A),\n-\tGPIO_FN(SCK5_A),\n-\n-\t/* IPSR17 */\n-\tGPIO_IFN(AUDIO_CLKA_A),\n-\tGPIO_FN(CC5_OSCOUT),\n-\tGPIO_IFN(AUDIO_CLKB_B),\n-\tGPIO_FN(SCIF_CLK_A),\n-\tGPIO_FN(STP_IVCXO27_1_D),\n-\tGPIO_FN(REMOCON_A),\n-\tGPIO_FN(TCLK1_A),\n-\tGPIO_IFN(USB0_PWEN),\n-\tGPIO_FN(SIM0_RST_C),\n-\tGPIO_FN(TS_SCK1_D),\n-\tGPIO_FN(STP_ISCLK_1_D),\n-\tGPIO_FN(BPFCLK_B),\n-\tGPIO_FN(RIF3_CLK_B),\n-\tGPIO_FN(HSCK2_C),\n-\tGPIO_IFN(USB0_OVC),\n-\tGPIO_FN(SIM0_D_C),\n-\tGPIO_FN(TS_SDAT1_D),\n-\tGPIO_FN(STP_ISD_1_D),\n-\tGPIO_FN(RIF3_SYNC_B),\n-\tGPIO_FN(HRX2_C),\n-\tGPIO_IFN(USB1_PWEN),\n-\tGPIO_FN(SIM0_CLK_C),\n-\tGPIO_FN(SSI_SCK1_A),\n-\tGPIO_FN(TS_SCK0_E),\n-\tGPIO_FN(STP_ISCLK_0_E),\n-\tGPIO_FN(FMCLK_B),\n-\tGPIO_FN(RIF2_CLK_B),\n-\tGPIO_FN(SPEEDIN_A),\n-\tGPIO_FN(HTX2_C),\n-\tGPIO_IFN(USB1_OVC),\n-\tGPIO_FN(MSIOF1_SS2_C),\n-\tGPIO_FN(SSI_WS1_A),\n-\tGPIO_FN(TS_SDAT0_E),\n-\tGPIO_FN(STP_ISD_0_E),\n-\tGPIO_FN(FMIN_B),\n-\tGPIO_FN(RIF2_SYNC_B),\n-\tGPIO_FN(REMOCON_B),\n-\tGPIO_FN(HCTS2x_C),\n-\tGPIO_IFN(USB30_PWEN),\n-\tGPIO_FN(AUDIO_CLKOUT_B),\n-\tGPIO_FN(SSI_SCK2_B),\n-\tGPIO_FN(TS_SDEN1_D),\n-\tGPIO_FN(STP_ISEN_1_D),\n-\tGPIO_FN(STP_OPWM_0_E),\n-\tGPIO_FN(RIF3_D0_B),\n-\tGPIO_FN(TCLK2_B),\n-\tGPIO_FN(TPU0TO0),\n-\tGPIO_FN(BPFCLK_C),\n-\tGPIO_FN(HRTS2x_C),\n-\tGPIO_IFN(USB30_OVC),\n-\tGPIO_FN(AUDIO_CLKOUT1_B),\n-\tGPIO_FN(SSI_WS2_B),\n-\tGPIO_FN(TS_SPSYNC1_D),\n-\tGPIO_FN(STP_ISSYNC_1_D),\n-\tGPIO_FN(STP_IVCXO27_0_E),\n-\tGPIO_FN(RIF3_D1_B),\n-\tGPIO_FN(FSO_TOEx),\n-\tGPIO_FN(TPU0TO1),\n-\n-\t/* IPSR18 */\n-\tGPIO_IFN(USB3_PWEN),\n-\tGPIO_FN(AUDIO_CLKOUT2_B),\n-\tGPIO_FN(SSI_SCK9_B),\n-\tGPIO_FN(TS_SDEN0_E),\n-\tGPIO_FN(STP_ISEN_0_E),\n-\tGPIO_FN(RIF2_D0_B),\n-\tGPIO_FN(TPU0TO2),\n-\tGPIO_FN(FMCLK_C),\n-\tGPIO_FN(FMCLK_D),\n-\n-\tGPIO_IFN(USB3_OVC),\n-\tGPIO_FN(AUDIO_CLKOUT3_B),\n-\tGPIO_FN(SSI_WS9_B),\n-\tGPIO_FN(TS_SPSYNC0_E),\n-\tGPIO_FN(STP_ISSYNC_0_E),\n-\tGPIO_FN(RIF2_D1_B),\n-\tGPIO_FN(TPU0TO3),\n-\tGPIO_FN(FMIN_C),\n-\tGPIO_FN(FMIN_D),\n-};\n-\n-static struct pinmux_cfg_reg pinmux_config_regs[] = {\n-\t/* GPSR0(0xE6060100) md[3:1] controls initial value */\n-\t/*   md[3:1] .. 0     : 0x0000FFFF                  */\n-\t/*           .. other : 0x00000000                  */\n-\t{ PINMUX_CFG_REG(\"GPSR0\", 0xE6060100, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\tGP_0_15_FN, GFN_D15,\n-\t\tGP_0_14_FN, GFN_D14,\n-\t\tGP_0_13_FN, GFN_D13,\n-\t\tGP_0_12_FN, GFN_D12,\n-\t\tGP_0_11_FN, GFN_D11,\n-\t\tGP_0_10_FN, GFN_D10,\n-\t\tGP_0_9_FN, GFN_D9,\n-\t\tGP_0_8_FN, GFN_D8,\n-\t\tGP_0_7_FN, GFN_D7,\n-\t\tGP_0_6_FN, GFN_D6,\n-\t\tGP_0_5_FN, GFN_D5,\n-\t\tGP_0_4_FN, GFN_D4,\n-\t\tGP_0_3_FN, GFN_D3,\n-\t\tGP_0_2_FN, GFN_D2,\n-\t\tGP_0_1_FN, GFN_D1,\n-\t\tGP_0_0_FN, GFN_D0 }\n-\t},\n-\t/* GPSR1(0xE6060104) is md[3:1] controls initial value */\n-\t/*   md[3:1] .. 0     : 0x0EFFFFFF                     */\n-\t/*           .. other : 0x00000000                     */\n-\t{ PINMUX_CFG_REG(\"GPSR1\", 0xE6060104, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\tGP_1_28_FN, GFN_CLKOUT,\n-\t\tGP_1_27_FN, GFN_EX_WAIT0_A,\n-\t\tGP_1_26_FN, GFN_WE1x,\n-\t\tGP_1_25_FN, GFN_WE0x,\n-\t\tGP_1_24_FN, GFN_RD_WRx,\n-\t\tGP_1_23_FN, GFN_RDx,\n-\t\tGP_1_22_FN, GFN_BSx,\n-\t\tGP_1_21_FN, GFN_CS1x_A26,\n-\t\tGP_1_20_FN, GFN_CS0x,\n-\t\tGP_1_19_FN, GFN_A19,\n-\t\tGP_1_18_FN, GFN_A18,\n-\t\tGP_1_17_FN, GFN_A17,\n-\t\tGP_1_16_FN, GFN_A16,\n-\t\tGP_1_15_FN, GFN_A15,\n-\t\tGP_1_14_FN, GFN_A14,\n-\t\tGP_1_13_FN, GFN_A13,\n-\t\tGP_1_12_FN, GFN_A12,\n-\t\tGP_1_11_FN, GFN_A11,\n-\t\tGP_1_10_FN, GFN_A10,\n-\t\tGP_1_9_FN, GFN_A9,\n-\t\tGP_1_8_FN, GFN_A8,\n-\t\tGP_1_7_FN, GFN_A7,\n-\t\tGP_1_6_FN, GFN_A6,\n-\t\tGP_1_5_FN, GFN_A5,\n-\t\tGP_1_4_FN, GFN_A4,\n-\t\tGP_1_3_FN, GFN_A3,\n-\t\tGP_1_2_FN, GFN_A2,\n-\t\tGP_1_1_FN, GFN_A1,\n-\t\tGP_1_0_FN, GFN_A0 }\n-\t},\n-\t/* GPSR2(0xE6060108) is md[3:1] controls               */\n-\t/*   md[3:1] .. 0     : 0x000003C0                     */\n-\t/*           .. other : 0x00000200                     */\n-\t{ PINMUX_CFG_REG(\"GPSR2\", 0xE6060108, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\tGP_2_14_FN, GFN_AVB_AVTP_CAPTURE_A,\n-\t\tGP_2_13_FN, GFN_AVB_AVTP_MATCH_A,\n-\t\tGP_2_12_FN, GFN_AVB_LINK,\n-\t\tGP_2_11_FN, GFN_AVB_PHY_INT,\n-\t\tGP_2_10_FN, GFN_AVB_MAGIC,\n-\t\tGP_2_9_FN, GFN_AVB_MDC,\n-\t\tGP_2_8_FN, GFN_PWM2_A,\n-\t\tGP_2_7_FN, GFN_PWM1_A,\n-\t\tGP_2_6_FN, GFN_PWM0,\n-\t\tGP_2_5_FN, GFN_IRQ5,\n-\t\tGP_2_4_FN, GFN_IRQ4,\n-\t\tGP_2_3_FN, GFN_IRQ3,\n-\t\tGP_2_2_FN, GFN_IRQ2,\n-\t\tGP_2_1_FN, GFN_IRQ1,\n-\t\tGP_2_0_FN, GFN_IRQ0 }\n-\t},\n-\n-\t/* GPSR3 */\n-\t{ PINMUX_CFG_REG(\"GPSR3\", 0xE606010C, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\tGP_3_15_FN, GFN_SD1_WP,\n-\t\tGP_3_14_FN, GFN_SD1_CD,\n-\t\tGP_3_13_FN, GFN_SD0_WP,\n-\t\tGP_3_12_FN, GFN_SD0_CD,\n-\t\tGP_3_11_FN, GFN_SD1_DAT3,\n-\t\tGP_3_10_FN, GFN_SD1_DAT2,\n-\t\tGP_3_9_FN, GFN_SD1_DAT1,\n-\t\tGP_3_8_FN, GFN_SD1_DAT0,\n-\t\tGP_3_7_FN, GFN_SD1_CMD,\n-\t\tGP_3_6_FN, GFN_SD1_CLK,\n-\t\tGP_3_5_FN, GFN_SD0_DAT3,\n-\t\tGP_3_4_FN, GFN_SD0_DAT2,\n-\t\tGP_3_3_FN, GFN_SD0_DAT1,\n-\t\tGP_3_2_FN, GFN_SD0_DAT0,\n-\t\tGP_3_1_FN, GFN_SD0_CMD,\n-\t\tGP_3_0_FN, GFN_SD0_CLK }\n-\t},\n-\t/* GPSR4 */\n-\t{ PINMUX_CFG_REG(\"GPSR4\", 0xE6060110, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\tGP_4_17_FN, GFN_SD3_DS,\n-\t\tGP_4_16_FN, GFN_SD3_DAT7,\n-\n-\t\tGP_4_15_FN, GFN_SD3_DAT6,\n-\t\tGP_4_14_FN, GFN_SD3_DAT5,\n-\t\tGP_4_13_FN, GFN_SD3_DAT4,\n-\t\tGP_4_12_FN, GFN_SD3_DAT3,\n-\t\tGP_4_11_FN, GFN_SD3_DAT2,\n-\t\tGP_4_10_FN, GFN_SD3_DAT1,\n-\t\tGP_4_9_FN, GFN_SD3_DAT0,\n-\t\tGP_4_8_FN, GFN_SD3_CMD,\n-\t\tGP_4_7_FN, GFN_SD3_CLK,\n-\t\tGP_4_6_FN, GFN_SD2_DS,\n-\t\tGP_4_5_FN, GFN_SD2_DAT3,\n-\t\tGP_4_4_FN, GFN_SD2_DAT2,\n-\t\tGP_4_3_FN, GFN_SD2_DAT1,\n-\t\tGP_4_2_FN, GFN_SD2_DAT0,\n-\t\tGP_4_1_FN, GFN_SD2_CMD,\n-\t\tGP_4_0_FN, GFN_SD2_CLK }\n-\t},\n-\t/* GPSR5 */\n-\t{ PINMUX_CFG_REG(\"GPSR5\", 0xE6060114, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\tGP_5_25_FN, GFN_MLB_DAT,\n-\t\tGP_5_24_FN, GFN_MLB_SIG,\n-\t\tGP_5_23_FN, GFN_MLB_CLK,\n-\t\tGP_5_22_FN, FN_MSIOF0_RXD,\n-\t\tGP_5_21_FN, GFN_MSIOF0_SS2,\n-\t\tGP_5_20_FN, FN_MSIOF0_TXD,\n-\t\tGP_5_19_FN, GFN_MSIOF0_SS1,\n-\t\tGP_5_18_FN, GFN_MSIOF0_SYNC,\n-\t\tGP_5_17_FN, FN_MSIOF0_SCK,\n-\t\tGP_5_16_FN, GFN_HRTS0x,\n-\t\tGP_5_15_FN, GFN_HCTS0x,\n-\t\tGP_5_14_FN, GFN_HTX0,\n-\t\tGP_5_13_FN, GFN_HRX0,\n-\t\tGP_5_12_FN, GFN_HSCK0,\n-\t\tGP_5_11_FN, GFN_RX2_A,\n-\t\tGP_5_10_FN, GFN_TX2_A,\n-\t\tGP_5_9_FN, GFN_SCK2,\n-\t\tGP_5_8_FN, GFN_RTS1x_TANS,\n-\t\tGP_5_7_FN, GFN_CTS1x,\n-\t\tGP_5_6_FN, GFN_TX1_A,\n-\t\tGP_5_5_FN, GFN_RX1_A,\n-\t\tGP_5_4_FN, GFN_RTS0x_TANS,\n-\t\tGP_5_3_FN, GFN_CTS0x,\n-\t\tGP_5_2_FN, GFN_TX0,\n-\t\tGP_5_1_FN, GFN_RX0,\n-\t\tGP_5_0_FN, GFN_SCK0 }\n-\t},\n-\t/* GPSR6 */\n-\t{ PINMUX_CFG_REG(\"GPSR6\", 0xE6060118, 32, 1) {\n-\t\tGP_6_31_FN, GFN_USB3_OVC,\n-\t\tGP_6_30_FN, GFN_USB3_PWEN,\n-\t\tGP_6_29_FN, GFN_USB30_OVC,\n-\t\tGP_6_28_FN, GFN_USB30_PWEN,\n-\t\tGP_6_27_FN, GFN_USB1_OVC,\n-\t\tGP_6_26_FN, GFN_USB1_PWEN,\n-\t\tGP_6_25_FN, GFN_USB0_OVC,\n-\t\tGP_6_24_FN, GFN_USB0_PWEN,\n-\t\tGP_6_23_FN, GFN_AUDIO_CLKB_B,\n-\t\tGP_6_22_FN, GFN_AUDIO_CLKA_A,\n-\t\tGP_6_21_FN, GFN_SSI_SDATA9_A,\n-\t\tGP_6_20_FN, GFN_SSI_SDATA8,\n-\t\tGP_6_19_FN, GFN_SSI_SDATA7,\n-\t\tGP_6_18_FN, GFN_SSI_WS78,\n-\t\tGP_6_17_FN, GFN_SSI_SCK78,\n-\t\tGP_6_16_FN, GFN_SSI_SDATA6,\n-\t\tGP_6_15_FN, GFN_SSI_WS6,\n-\t\tGP_6_14_FN, GFN_SSI_SCK6,\n-\t\tGP_6_13_FN, FN_SSI_SDATA5,\n-\t\tGP_6_12_FN, FN_SSI_WS5,\n-\t\tGP_6_11_FN, FN_SSI_SCK5,\n-\t\tGP_6_10_FN, GFN_SSI_SDATA4,\n-\t\tGP_6_9_FN, GFN_SSI_WS4,\n-\t\tGP_6_8_FN, GFN_SSI_SCK4,\n-\t\tGP_6_7_FN, GFN_SSI_SDATA3,\n-\t\tGP_6_6_FN, GFN_SSI_WS34,\n-\t\tGP_6_5_FN, GFN_SSI_SCK34,\n-\t\tGP_6_4_FN, GFN_SSI_SDATA2_A,\n-\t\tGP_6_3_FN, GFN_SSI_SDATA1_A,\n-\t\tGP_6_2_FN, GFN_SSI_SDATA0,\n-\t\tGP_6_1_FN, GFN_SSI_WS01239,\n-\t\tGP_6_0_FN, GFN_SSI_SCK01239 }\n-\t},\n-\t/* GPSR7 */\n-\t{ PINMUX_CFG_REG(\"GPSR7\", 0xE606011C, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\tGP_7_3_FN, FN_HDMI1_CEC,\n-\t\tGP_7_2_FN, FN_HDMI0_CEC,\n-\t\tGP_7_1_FN, FN_AVS2,\n-\t\tGP_7_0_FN, FN_AVS1 }\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR0\", 0xE6060200, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR0_31_28 [4] */\n-\t\tIFN_IRQ1, FN_QPOLA, 0, FN_DU_DISP,\n-\t\tFN_VI4_DATA1_B, FN_CAN0_RX_B, FN_CANFD0_RX_B, FN_MSIOF3_SS1_E,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR0_27_24 [4] */\n-\t\tIFN_IRQ0, FN_QPOLB, 0, FN_DU_CDE,\n-\t\tFN_VI4_DATA0_B, FN_CAN0_TX_B, FN_CANFD0_TX_B, FN_MSIOF3_SS2_E,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR0_23_20 [4] */\n-\t\tIFN_AVB_AVTP_CAPTURE_A, 0, FN_MSIOF2_TXD_C, FN_RTS4x_TANS_A,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR0_19_16 [4] */\n-\t\tIFN_AVB_AVTP_MATCH_A, 0, FN_MSIOF2_RXD_C, FN_CTS4x_A,\n-\t\t0, FN_FSCLKST2x_A, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR0_15_12 [4] */\n-\t\tIFN_AVB_LINK, 0, FN_MSIOF2_SCK_C, FN_TX4_A,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR0_11_8 [4] */\n-\t\tIFN_AVB_PHY_INT, 0, FN_MSIOF2_SYNC_C, FN_RX4_A,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR0_7_4 [4] */\n-\t\tIFN_AVB_MAGIC, 0, FN_MSIOF2_SS1_C, FN_SCK4_A,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR0_3_0 [4] */\n-\t\tIFN_AVB_MDC, 0, FN_MSIOF2_SS2_C, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR1\", 0xE6060204, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR1_31_28 [4] */\n-\t\tIFN_A0, FN_LCDOUT16, FN_MSIOF3_SYNC_B, 0,\n-\t\tFN_VI4_DATA8, 0, FN_DU_DB0, 0,\n-\t\t0, FN_PWM3_A, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR1_27_24 [4] */\n-\t\tIFN_PWM2_A, 0, 0, FN_HTX3_D,\n-\t\t0, 0, 0, 0,\n-\t\t0, FN_IETX_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR1_23_20 [4] */\n-\t\tIFN_PWM1_A, 0, 0, FN_HRX3_D,\n-\t\tFN_VI4_DATA7_B, 0, 0, 0,\n-\t\t0, FN_IERX_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR1_19_16 [4] */\n-\t\tIFN_PWM0, FN_AVB_AVTP_PPS, 0, 0,\n-\t\tFN_VI4_DATA6_B, 0, 0, 0,\n-\t\t0, FN_IECLK_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR1_15_12 [4] */\n-\t\tIFN_IRQ5, FN_QSTB_QHE, 0, FN_DU_EXVSYNC_DU_VSYNC,\n-\t\tFN_VI4_DATA5_B, FN_FSCLKST2x_B, 0, FN_MSIOF3_TXD_E,\n-\t\t0, FN_PWM6_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR1_11_8 [4] */\n-\t\tIFN_IRQ4, FN_QSTH_QHS, 0, FN_DU_EXHSYNC_DU_HSYNC,\n-\t\tFN_VI4_DATA4_B, 0, 0, FN_MSIOF3_RXD_E,\n-\t\t0, FN_PWM5_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR1_7_4 [4] */\n-\t\tIFN_IRQ3, FN_QSTVB_QVE, 0, FN_DU_DOTCLKOUT1,\n-\t\tFN_VI4_DATA3_B, 0, 0, FN_MSIOF3_SCK_E,\n-\t\t0, FN_PWM4_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR1_3_0 [4] */\n-\t\tIFN_IRQ2, FN_QCPV_QDE, 0, FN_DU_EXODDF_DU_ODDF_DISP_CDE,\n-\t\tFN_VI4_DATA2_B, 0, 0, FN_MSIOF3_SYNC_E,\n-\t\t0, FN_PWM3_B, 0, 0,\n-\t\t0, 0, 0, 0\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR2\", 0xE6060208, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR2_31_28 [4] */\n-\t\tIFN_A8, FN_RX3_B, FN_MSIOF2_SYNC_A, FN_HRX4_B,\n-\t\t0, 0, 0, FN_SDA6_A,\n-\t\tFN_AVB_AVTP_MATCH_B, FN_PWM1_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR2_27_24 [4] */\n-\t\tIFN_A7, FN_LCDOUT23, FN_MSIOF2_SS2_A, FN_TX4_B,\n-\t\tFN_VI4_DATA15, FN_V15_DATA15, FN_DU_DB7, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR2_23_20 [4] */\n-\t\tIFN_A6, FN_LCDOUT22, FN_MSIOF2_SS1_A, FN_RX4_B,\n-\t\tFN_VI4_DATA14, FN_VI5_DATA14, FN_DU_DB6, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR2_19_16 [4] */\n-\t\tIFN_A5, FN_LCDOUT21, FN_MSIOF3_SS2_B, FN_SCK4_B,\n-\t\tFN_VI4_DATA13, FN_VI5_DATA13, FN_DU_DB5, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR2_15_12 [4] */\n-\t\tIFN_A4, FN_LCDOUT20, FN_MSIOF3_SS1_B, 0,\n-\t\tFN_VI4_DATA12, FN_VI5_DATA12, FN_DU_DB4, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR2_11_8 [4] */\n-\t\tIFN_A3, FN_LCDOUT19, FN_MSIOF3_RXD_B, 0,\n-\t\tFN_VI4_DATA11, 0, FN_DU_DB3, 0,\n-\t\t0, FN_PWM6_A, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR2_7_4 [4] */\n-\t\tIFN_A2, FN_LCDOUT18, FN_MSIOF3_SCK_B, 0,\n-\t\tFN_VI4_DATA10, 0, FN_DU_DB2, 0,\n-\t\t0, FN_PWM5_A, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR2_3_0 [4] */\n-\t\tIFN_A1, FN_LCDOUT17, FN_MSIOF3_TXD_B, 0,\n-\t\tFN_VI4_DATA9, 0, FN_DU_DB1, 0,\n-\t\t0, FN_PWM4_A, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR3\", 0xE606020C, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR3_31_28 [4] */\n-\t\tIFN_A16, FN_LCDOUT8, 0, 0,\n-\t\tFN_VI4_FIELD, 0, FN_DU_DG0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR3_27_24 [4] */\n-\t\tIFN_A15, FN_LCDOUT15, FN_MSIOF3_TXD_C, 0,\n-\t\tFN_HRTS4x, FN_VI5_DATA11, FN_DU_DG7, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR3_23_20 [4] */\n-\t\tIFN_A14, FN_LCDOUT14, FN_MSIOF3_RXD_C, 0,\n-\t\tFN_HCTS4x, FN_VI5_DATA10, FN_DU_DG6, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR3_19_16 [4] */\n-\t\tIFN_A13, FN_LCDOUT13, FN_MSIOF3_SYNC_C, 0,\n-\t\tFN_HTX4_A, FN_VI5_DATA9, FN_DU_DG5, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR3_15_12 [4] */\n-\t\tIFN_A12, FN_LCDOUT12, FN_MSIOF3_SCK_C, 0,\n-\t\tFN_HRX4_A, FN_VI5_DATA8, FN_DU_DG4, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR3_11_8 [4] */\n-\t\tIFN_A11, FN_TX3_B, FN_MSIOF2_TXD_A, FN_HTX4_B,\n-\t\tFN_HSCK4, FN_VI5_FIELD, 0, FN_SCL6_A,\n-\t\tFN_AVB_AVTP_CAPTURE_B, FN_PWM2_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR3_7_4 [4] */\n-\t\tIFN_A10, 0, FN_MSIOF2_RXD_A, FN_RTS4n_TANS_B,\n-\t\t0, FN_VI5_HSYNCx, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR3_3_0 [4] */\n-\t\tIFN_A9, 0, FN_MSIOF2_SCK_A, FN_CTS4x_B,\n-\t\t0, FN_VI5_VSYNCx, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR4\", 0xE6060210, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR4_31_28 [4] */\n-\t\tIFN_RD_WRx, 0, FN_MSIOF3_RXD_D, FN_TX3_A,\n-\t\tFN_HTX3_A, 0, 0, 0,\n-\t\tFN_CAN0_RX_A, FN_CANFD0_RX_A, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR4_27_24 [4] */\n-\t\tIFN_RDx, 0, FN_MSIOF3_SYNC_D, FN_RX3_A,\n-\t\tFN_HRX3_A, 0, 0, 0,\n-\t\tFN_CAN0_TX_A, FN_CANFD0_TX_A, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR4_23_20 [4] */\n-\t\tIFN_BSx, FN_QSTVA_QVS, FN_MSIOF3_SCK_D, FN_SCK3,\n-\t\tFN_HSCK3, 0, 0, 0,\n-\t\tFN_CAN1_TX, FN_CANFD1_TX, FN_IETX_A, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR4_19_16 [4] */\n-\t\tIFN_CS1x_A26, 0, 0, 0,\n-\t\t0, FN_VI5_CLK, 0, FN_EX_WAIT0_B,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR4_15_12 [4] */\n-\t\tIFN_CS0x, 0, 0, 0,\n-\t\t0, FN_VI5_CLKENB, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR4_11_8 [4] */\n-\t\tIFN_A19, FN_LCDOUT11, 0, 0,\n-\t\tFN_VI4_CLKENB, 0, FN_DU_DG3, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR4_7_4 [4] */\n-\t\tIFN_A18, FN_LCDOUT10, 0, 0,\n-\t\tFN_VI4_HSYNCx, 0, FN_DU_DG2, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR4_3_0 [4] */\n-\t\tIFN_A17, FN_LCDOUT9, 0, 0,\n-\t\tFN_VI4_VSYNCx, 0, FN_DU_DG1, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR5\", 0xE6060214, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR5_31_28 [4] */\n-\t\tIFN_D4, FN_MSIOF2_SCK_B, 0, 0,\n-\t\tFN_VI4_DATA20, FN_VI5_DATA4, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR5_27_24 [4] */\n-\t\tIFN_D3, 0, FN_MSIOF3_TXD_A, 0,\n-\t\tFN_VI4_DATA19, FN_VI5_DATA3, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR5_23_20 [4] */\n-\t\tIFN_D2, 0, FN_MSIOF3_RXD_A, 0,\n-\t\tFN_VI4_DATA18, FN_VI5_DATA2, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR5_19_16 [4] */\n-\t\tIFN_D1, FN_MSIOF2_SS2_B, FN_MSIOF3_SYNC_A, 0,\n-\t\tFN_VI4_DATA17, FN_VI5_DATA1, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR5_15_12 [4] */\n-\t\tIFN_D0, FN_MSIOF2_SS1_B, FN_MSIOF3_SCK_A, 0,\n-\t\tFN_VI4_DATA16, FN_VI5_DATA0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR5_11_8 [4] */\n-\t\tIFN_EX_WAIT0_A, FN_QCLK, 0, 0,\n-\t\tFN_VI4_CLK, 0, FN_DU_DOTCLKOUT0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR5_7_4 [4] */\n-\t\tIFN_WE1x, 0, FN_MSIOF3_SS1_D, FN_RTS3x_TANS,\n-\t\tFN_HRTS3x, 0, 0, FN_SDA6_B,\n-\t\tFN_CAN1_RX, FN_CANFD1_RX, FN_IERX_A, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR5_3_0 [4] */\n-\t\tIFN_WE0x, 0, FN_MSIIOF3_TXD_D, FN_CTS3x,\n-\t\tFN_HCTS3x, 0, 0, FN_SCL6_B,\n-\t\tFN_CAN_CLK, 0, FN_IECLK_A, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR6\", 0xE6060218, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR6_31_28 [4] */\n-\t\tIFN_D12, FN_LCDOUT4, FN_MSIOF2_SS1_D, FN_RX4_C,\n-\t\tFN_VI4_DATA4_A, 0, FN_DU_DR4, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR6_27_24 [4] */\n-\t\tIFN_D11, FN_LCDOUT3, FN_MSIOF2_TXD_D, FN_HTX3_B,\n-\t\tFN_VI4_DATA3_A, FN_RTS4x_TANS_C, FN_DU_DR3, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR6_23_20 [4] */\n-\t\tIFN_D10, FN_LCDOUT2, FN_MSIOF2_RXD_D, FN_HRX3_B,\n-\t\tFN_VI4_DATA2_A, FN_CTS4x_C, FN_DU_DR2, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR6_19_16 [4] */\n-\t\tIFN_D9, FN_LCDOUT1, FN_MSIOF2_SYNC_D, 0,\n-\t\tFN_VI4_DATA1_A, 0, FN_DU_DR1, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR6_15_12 [4] */\n-\t\tIFN_D8, FN_LCDOUT0, FN_MSIOF2_SCK_D, FN_SCK4_C,\n-\t\tFN_VI4_DATA0_A, 0, FN_DU_DR0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR6_11_8 [4] */\n-\t\tIFN_D7, FN_MSIOF2_TXD_B, 0, 0,\n-\t\tFN_VI4_DATA23, FN_VI5_DATA7, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR6_7_4 [4] */\n-\t\tIFN_D6, FN_MSIOF2_RXD_B, 0, 0,\n-\t\tFN_VI4_DATA22, FN_VI5_DATA6, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR6_3_0 [4] */\n-\t\tIFN_D5, FN_MSIOF2_SYNC_B, 0, 0,\n-\t\tFN_VI4_DATA21, FN_VI5_DATA5, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR7\", 0xE606021C, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR7_31_28 [4] */\n-\t\tIFN_SD0_DAT1, 0, FN_MSIOF1_TXD_E, 0,\n-\t\t0, FN_TS_SPSYNC0_B, FN_STP_ISSYNC_0_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR7_27_24 [4] */\n-\t\tIFN_SD0_DAT0, 0, FN_MSIOF1_RXD_E, 0,\n-\t\t0, FN_TS_SCK0_B, FN_STP_ISCLK_0_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR7_23_20 [4] */\n-\t\tIFN_SD0_CMD, 0, FN_MSIOF1_SYNC_E, 0,\n-\t\t0, 0, FN_STP_IVCXO27_0_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR7_19_16 [4] */\n-\t\tIFN_SD0_CLK, 0, FN_MSIOF1_SCK_E, 0,\n-\t\t0, 0, FN_STP_OPWM_0_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR7_15_12 [4] */\n-\t\tFN_FSCLKST, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR7_11_8 [4] */\n-\t\tIFN_D15, FN_LCDOUT7, FN_MSIOF3_SS2_A, FN_HTX3_C,\n-\t\tFN_VI4_DATA7_A, 0, FN_DU_DR7, FN_SDA6_C,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR7_7_4 [4] */\n-\t\tIFN_D14, FN_LCDOUT6, FN_MSIOF3_SS1_A, FN_HRX3_C,\n-\t\tFN_VI4_DATA6_A, 0, FN_DU_DR6, FN_SCL6_C,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR7_3_0 [4] */\n-\t\tIFN_D13, FN_LCDOUT5, FN_MSIOF2_SS2_D, FN_TX4_C,\n-\t\tFN_VI4_DATA5_A, 0, FN_DU_DR5, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR8\", 0xE6060220, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR8_31_28 [4] */\n-\t\tIFN_SD1_DAT3, FN_SD2_DAT7, FN_MSIOF1_SS2_G, FN_NFRBx_B,\n-\t\t0, FN_TS_SDEN1_B, FN_STP_ISEN_1_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR8_27_24 [4] */\n-\t\tIFN_SD1_DAT2, FN_SD2_DAT6, FN_MSIOF1_SS1_G, FN_NFDATA15_B,\n-\t\t0, FN_TS_SDAT1_B, FN_STP_IOD_1_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR8_23_20 [4] */\n-\t\tIFN_SD1_DAT1, FN_SD2_DAT5, FN_MSIOF1_TXD_G, FN_NFDATA14_B,\n-\t\t0, FN_TS_SPSYNC1_B, FN_STP_ISSYNC_1_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR8_19_16 [4] */\n-\t\tIFN_SD1_DAT0, FN_SD2_DAT4, FN_MSIOF1_RXD_G, FN_NFWPx_B,\n-\t\t0, FN_TS_SCK1_B, FN_STP_ISCLK_1_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR8_15_12 [4] */\n-\t\tIFN_SD1_CMD, 0, FN_MSIOF1_SYNC_G, FN_NFCEx_B,\n-\t\t0, FN_SIM0_D_A, FN_STP_IVCXO27_1_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR8_11_8 [4] */\n-\t\tIFN_SD1_CLK, 0, FN_MSIOF1_SCK_G, 0,\n-\t\t0, FN_SIM0_CLK_A, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR8_7_4 [4] */\n-\t\tIFN_SD0_DAT3, 0, FN_MSIOF1_SS2_E, 0,\n-\t\t0, FN_TS_SDEN0_B, FN_STP_ISEN_0_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR8_3_0 [4] */\n-\t\tIFN_SD0_DAT2, 0, FN_MSIOF1_SS1_E, 0,\n-\t\t0, FN_TS_SDAT0_B, FN_STP_ISD_0_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR9\", 0xE6060224, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR9_31_28 [4] */\n-\t\tIFN_SD3_CLK, 0, FN_NFWEx, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR9_27_24 [4] */\n-\t\tIFN_SD2_DS, 0, FN_NFALE, 0,\n-\t\t0, 0, 0, 0,\n-\t\tFN_SATA_DEVSLP_B, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR9_23_20 [4] */\n-\t\tIFN_SD2_DAT3, 0, FN_NFDATA13, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR9_19_16 [4] */\n-\t\tIFN_SD2_DAT2, 0, FN_NFDATA12, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR9_15_12 [4] */\n-\t\tIFN_SD2_DAT1, 0, FN_NFDATA11, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR9_11_8 [4] */\n-\t\tIFN_SD2_DAT0, 0, FN_NFDATA10, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR9_7_4 [4] */\n-\t\tIFN_SD2_CMD, 0, FN_NFDATA9, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR9_3_0 [4] */\n-\t\tIFN_SD2_CLK, 0, FN_NFDATA8, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR10\", 0xE6060228, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR10_31_28 [4] */\n-\t\tIFN_SD3_DAT6, FN_SD3_CD, FN_NFDATA6, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR10_27_24 [4] */\n-\t\tIFN_SD3_DAT5, FN_SD2_WP_A, FN_NFDATA5, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR10_23_20 [4] */\n-\t\tIFN_SD3_DAT4, FN_SD2_CD_A, FN_NFDATA4, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR10_19_16 [4] */\n-\t\tIFN_SD3_DAT3, 0, FN_NFDATA3, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR10_15_12 [4] */\n-\t\tIFN_SD3_DAT2, 0, FN_NFDATA2, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR10_11_8 [4] */\n-\t\tIFN_SD3_DAT1, 0, FN_NFDATA1, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR10_7_4 [4] */\n-\t\tIFN_SD3_DAT0, 0, FN_NFDATA0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR10_3_0 [4] */\n-\t\tIFN_SD3_CMD, 0, FN_NFREx, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR11\", 0xE606022C, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR11_31_28 [4] */\n-\t\tIFN_RX0, FN_HRX1_B, 0, 0,\n-\t\t0, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, FN_RIF0_D0_B,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR11_27_24 [4] */\n-\t\tIFN_SCK0, FN_HSCK1_B, FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B,\n-\t\tFN_SDA2_A, FN_SIM0_RST_B, FN_STP_OPWM_0_C, FN_RIF0_CLK_B,\n-\t\tFN_ADICHS2, FN_SCK5_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR11_23_20 [4] */\n-\t\tIFN_SD1_WP, 0, FN_NFCEx_A, 0,\n-\t\t0, FN_SIM0_D_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR11_19_16 [4] */\n-\t\tIFN_SD1_CD, 0, FN_NFRBx_A, 0,\n-\t\t0, FN_SIM0_CLK_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR11_15_12 [4] */\n-\t\tIFN_SD0_WP, 0, FN_NFDATA15_A, 0,\n-\t\tFN_SDA2_B, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR11_11_8 [4] */\n-\t\tIFN_SD0_CD, 0, FN_NFDATA14_A, 0,\n-\t\tFN_SCL2_B, FN_SIM0_RST_A, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR11_7_4 [4] */\n-\t\tIFN_SD3_DS, 0, FN_NFCLE, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR11_3_0 [4] */\n-\t\tIFN_SD3_DAT7, FN_SD3_WP, FN_NFDATA7, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR12\", 0xE6060230, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR12_31_28 [4] */\n-\t\tIFN_SCK2, FN_SCIF_CLK_B, FN_MSIOF1_SCK_B, 0,\n-\t\t0, FN_TS_SCK1_C, FN_STP_ISCLK_1_C, FN_RIF1_CLK_B,\n-\t\t0, FN_ADICLK, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR12_27_24 [4] */\n-\t\tIFN_RTS1x_TANS, FN_HRTS1x_A, FN_MSIOF1_TXD_B, 0,\n-\t\t0, FN_TS_SDAT1_C, FN_STP_ISD_1_C, FN_RIF1_D1_B,\n-\t\t0, FN_ADICHS0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR12_23_20 [4] */\n-\t\tIFN_CTS1x, FN_HCTS1x_A, FN_MSIOF1_RXD_B, 0,\n-\t\t0, FN_TS_SDEN1_C, FN_STP_ISEN_1_C, FN_RIF1_D0_B,\n-\t\t0, FN_ADIDATA, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR12_19_16 [4] */\n-\t\tIFN_TX1_A, FN_HTX1_A, 0, 0,\n-\t\t0, FN_TS_SDEN0_C, FN_STP_ISEN_0_C, FN_RIF1_D0_C,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR12_15_12 [4] */\n-\t\tIFN_RX1_A, FN_HRX1_A, 0, 0,\n-\t\t0, FN_TS_SDAT0_C, FN_STP_ISD_0_C, FN_RIF1_CLK_C,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR12_11_8 [4] */\n-\t\tIFN_RTS0x_TANS, FN_HRTS1x_B, FN_MSIOF1_SS1_B, FN_AUDIO_CLKA_B,\n-\t\tFN_SCL2_A, 0, FN_STP_IVCXO27_1_C, FN_RIF0_SYNC_B,\n-\t\t0, FN_ADICHS1, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR12_7_4 [4] */\n-\t\tIFN_CTS0x, FN_HCTS1x_B, FN_MSIOF1_SYNC_B, 0,\n-\t\t0, FN_TS_SPSYNC1_C, FN_STP_ISSYNC_1_C, FN_RIF1_SYNC_B,\n-\t\tFN_AUDIO_CLKOUT_C, FN_ADICS_SAMP, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR12_3_0 [4] */\n-\t\tIFN_TX0, FN_HTX1_B, 0, 0,\n-\t\t0, FN_TS_SPSYNC0_C, FN_STP_ISSYNC_0_C, FN_RIF0_D1_B,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR13\", 0xE6060234, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR13_31_28 [4] */\n-\t\tIFN_MSIOF0_SYNC, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\tFN_AUDIO_CLKOUT_A, 0, FN_TX5_B, 0,\n-\t\t0, FN_BPFCLK_D, 0, 0,\n-\t\t/* IPSR13_27_24 [4] */\n-\t\tIFN_HRTS0x, FN_TX2_B, FN_MSIOF1_SS1_D, 0,\n-\t\tFN_SSI_WS9_A, 0, FN_STP_IVCXO27_0_D, FN_BPFCLK_A,\n-\t\tFN_AUDIO_CLKOUT2_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR13_23_20 [4] */\n-\t\tIFN_HCTS0x, FN_RX2_B, FN_MSIOF1_SYNC_D, 0,\n-\t\tFN_SSI_SCK9_A, FN_TS_SPSYNC0_D,\n-\t\tFN_STP_ISSYNC_0_D, FN_RIF0_SYNC_C,\n-\t\tFN_AUDIO_CLKOUT1_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR13_19_16 [4] */\n-\t\tIFN_HTX0, 0, FN_MSIOF1_TXD_D, 0,\n-\t\tFN_SSI_SDATA9_B, FN_TS_SDAT0_D, FN_STP_ISD_0_D, FN_RIF0_D1_C,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR13_15_12 [4] */\n-\t\tIFN_HRX0, 0, FN_MSIOF1_RXD_D, 0,\n-\t\tFN_SSI_SDATA2_B, FN_TS_SDEN0_D, FN_STP_ISEN_0_D, FN_RIF0_D0_C,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR13_11_8 [4] */\n-\t\tIFN_HSCK0, 0, FN_MSIOF1_SCK_D, FN_AUDIO_CLKB_A,\n-\t\tFN_SSI_SDATA1_B, FN_TS_SCK0_D, FN_STP_ISCLK_0_D, FN_RIF0_CLK_C,\n-\t\t0, 0, FN_RX5_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR13_7_4 [4] */\n-\t\tIFN_RX2_A, 0, 0, FN_SD2_WP_B,\n-\t\tFN_SDA1_A, 0, FN_FMIN_A, FN_RIF1_SYNC_C,\n-\t\t0, FN_FSO_CFE_1x, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR13_3_0 [4] */\n-\t\tIFN_TX2_A, 0, 0, FN_SD2_CD_B,\n-\t\tFN_SCL1_A, 0, FN_FMCLK_A, FN_RIF1_D1_C,\n-\t\t0, FN_FSO_CFE_0x, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR14\", 0xE6060238, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR14_31_28 [4] */\n-\t\tIFN_SSI_SDATA0, 0, FN_MSIOF1_SS2_F, 0,\n-\t\t0, 0, 0, FN_MOUT2,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR14_27_24 [4] */\n-\t\tIFN_SSI_WS01239, 0, FN_MSIOF1_SS1_F, 0,\n-\t\t0, 0, 0, 0, FN_MOUT1,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR14_23_20 [4] */\n-\t\tIFN_SSI_SCK01239, 0, FN_MSIOF1_TXD_F, 0,\n-\t\t0, 0, 0, FN_MOUT0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR14_19_16 [4] */\n-\t\tIFN_MLB_DAT, FN_TX1_B, FN_MSIOF1_RXD_F, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR14_15_12 [4] */\n-\t\tIFN_MLB_SIG, FN_RX1_B, FN_MSIOF1_SYNC_F, 0,\n-\t\tFN_SDA1_B, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR14_11_8 [4] */\n-\t\tIFN_MLB_CLK, 0, FN_MSIOF1_SCK_F, 0,\n-\t\tFN_SCL1_B, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR14_7_4 [4] */\n-\t\tIFN_MSIOF0_SS2, FN_TX5_A, FN_MSIOF1_SS2_D, FN_AUDIO_CLKC_A,\n-\t\tFN_SSI_WS2_A, 0, FN_STP_OPWM_0_D, 0,\n-\t\tFN_AUDIO_CLKOUT_D, 0, FN_SPEEDIN_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR14_3_0 [4] */\n-\t\tIFN_MSIOF0_SS1, FN_RX5_A, FN_NFWPx_A, FN_AUDIO_CLKA_C,\n-\t\tFN_SSI_SCK2_A, 0, FN_STP_IVCXO27_0_C, 0,\n-\t\tFN_AUDIO_CLKOUT3_A, 0, FN_TCLK1_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR15\", 0xE606023C, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR15_31_28 [4] */\n-\t\tIFN_SSI_SDATA4, FN_HSCK2_A, FN_MSIOF1_RXD_A, 0,\n-\t\t0, FN_TS_SPSYNC0_A, FN_STP_ISSYNC_0_A, FN_RIF0_D0_A,\n-\t\tFN_RIF2_D1_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR15_27_24 [4] */\n-\t\tIFN_SSI_WS4, FN_HTX2_A, FN_MSIOF1_SYNC_A, 0,\n-\t\t0, FN_TS_SDEN0_A, FN_STP_ISEN_0_A, FN_RIF0_SYNC_A,\n-\t\tFN_RIF2_SYNC_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR15_23_20 [4] */\n-\t\tIFN_SSI_SCK4, FN_HRX2_A, FN_MSIOF1_SCK_A, 0,\n-\t\t0, FN_TS_SDAT0_A, FN_STP_ISD_0_A, FN_RIF0_CLK_A,\n-\t\tFN_RIF2_CLK_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR15_19_16 [4] */\n-\t\tIFN_SSI_SDATA3, FN_HRTS2x_A, FN_MSIOF1_TXD_A, 0,\n-\t\t0, FN_TS_SCK0_A, FN_STP_ISCLK_0_A, FN_RIF0_D1_A,\n-\t\tFN_RIF2_D0_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR15_15_12 [4] */\n-\t\tIFN_SSI_WS34, FN_HCTS2x_A, FN_MSIOF1_SS2_A, 0,\n-\t\t0, 0, FN_STP_IVCXO27_0_A, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR15_11_8 [4] */\n-\t\tIFN_SSI_SCK34, 0, FN_MSIOF1_SS1_A, 0,\n-\t\t0, 0, FN_STP_OPWM_0_A, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR15_7_4 [4] */\n-\t\tIFN_SSI_SDATA2_A, 0, 0, 0,\n-\t\tFN_SSI_SCK1_B, 0, 0, FN_MOUT6,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR15_3_0 [4] */\n-\t\tIFN_SSI_SDATA1_A, 0, 0, 0,\n-\t\t0, 0, 0, FN_MOUT5,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR16\", 0xE6060240, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR16_31_28 [4] */\n-\t\tIFN_SSI_SDATA9_A, FN_HSCK2_B, FN_MSIOF1_SS1_C, FN_HSCK1_A,\n-\t\tFN_SSI_WS1_B, FN_SCK1, FN_STP_IVCXO27_1_A, FN_SCK5_A,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR16_27_24 [4] */\n-\t\tIFN_SSI_SDATA8, FN_HRTS2x_B, FN_MSIOF1_TXD_C, 0,\n-\t\t0, FN_TS_SPSYNC1_A, FN_STP_ISSYNC_1_A, FN_RIF1_D1_A,\n-\t\tFN_RIF3_D1_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR16_23_20 [4] */\n-\t\tIFN_SSI_SDATA7, FN_HCTS2x_B, FN_MSIOF1_RXD_C, 0,\n-\t\t0, FN_TS_SDEN1_A, FN_STP_ISEN_1_A, FN_RIF1_D0_A,\n-\t\tFN_RIF3_D0_A, 0, FN_TCLK2_A, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR16_19_16 [4] */\n-\t\tIFN_SSI_WS78, FN_HTX2_B, FN_MSIOF1_SYNC_C, 0,\n-\t\t0, FN_TS_SDAT1_A, FN_STP_ISD_1_A, FN_RIF1_SYNC_A,\n-\t\tFN_RIF3_SYNC_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR16_15_12 [4] */\n-\t\tIFN_SSI_SCK78, FN_HRX2_B, FN_MSIOF1_SCK_C, 0,\n-\t\t0, FN_TS_SCK1_A, FN_STP_ISCLK_1_A, FN_RIF1_CLK_A,\n-\t\tFN_RIF3_CLK_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR16_11_8 [4] */\n-\t\tIFN_SSI_SDATA6, 0, 0, FN_SIM0_CLK_D,\n-\t\t0, 0, 0, 0,\n-\t\tFN_SATA_DEVSLP_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR16_7_4 [4] */\n-\t\tIFN_SSI_WS6, 0, 0, FN_SIM0_D_D,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR16_3_0 [4] */\n-\t\tIFN_SSI_SCK6, 0, 0, FN_SIM0_RST_D,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR17\", 0xE6060244, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR17_31_28 [4] */\n-\t\tIFN_USB30_OVC, 0, 0, FN_AUDIO_CLKOUT1_B,\n-\t\tFN_SSI_WS2_B, FN_TS_SPSYNC1_D, FN_STP_ISSYNC_1_D, FN_STP_IVCXO27_0_E,\n-\t\tFN_RIF3_D1_B, 0, FN_FSO_TOEx, FN_TPU0TO1,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR17_27_24 [4] */\n-\t\tIFN_USB30_PWEN, 0, 0, FN_AUDIO_CLKOUT_B,\n-\t\tFN_SSI_SCK2_B, FN_TS_SDEN1_D, FN_STP_ISEN_1_D, FN_STP_OPWM_0_E,\n-\t\tFN_RIF3_D0_B, 0, FN_TCLK2_B, FN_TPU0TO0,\n-\t\tFN_BPFCLK_C, FN_HRTS2x_C, 0, 0,\n-\t\t/* IPSR17_23_20 [4] */\n-\t\tIFN_USB1_OVC, 0, FN_MSIOF1_SS2_C, 0,\n-\t\tFN_SSI_WS1_A, FN_TS_SDAT0_E, FN_STP_ISD_0_E, FN_FMIN_B,\n-\t\tFN_RIF2_SYNC_B, 0, FN_REMOCON_B, 0,\n-\t\t0, FN_HCTS2x_C, 0, 0,\n-\t\t/* IPSR17_19_16 [4] */\n-\t\tIFN_USB1_PWEN, 0, 0, FN_SIM0_CLK_C,\n-\t\tFN_SSI_SCK1_A, FN_TS_SCK0_E, FN_STP_ISCLK_0_E, FN_FMCLK_B,\n-\t\tFN_RIF2_CLK_B, 0, FN_SPEEDIN_A, 0,\n-\t\t0, FN_HTX2_C, 0, 0,\n-\t\t/* IPSR17_15_12 [4] */\n-\t\tIFN_USB0_OVC, 0, 0, FN_SIM0_D_C,\n-\t\t0, FN_TS_SDAT1_D, FN_STP_ISD_1_D, 0,\n-\t\tFN_RIF3_SYNC_B, 0, 0, 0,\n-\t\t0, FN_HRX2_C, 0, 0,\n-\t\t/* IPSR17_11_8 [4] */\n-\t\tIFN_USB0_PWEN, 0, 0, FN_SIM0_RST_C,\n-\t\t0, FN_TS_SCK1_D, FN_STP_ISCLK_1_D, FN_BPFCLK_B,\n-\t\tFN_RIF3_CLK_B, 0, 0, 0,\n-\t\t0, FN_HSCK2_C, 0, 0,\n-\t\t/* IPSR17_7_4 [4] */\n-\t\tIFN_AUDIO_CLKB_B, FN_SCIF_CLK_A, 0, 0,\n-\t\t0, 0, FN_STP_IVCXO27_1_D, FN_REMOCON_A,\n-\t\t0, 0, FN_TCLK1_A, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR17_3_0 [4] */\n-\t\tIFN_AUDIO_CLKA_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, FN_CC5_OSCOUT,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR18\", 0xE6060248, 32,\n-\t\t\t\t1, 1, 1, 1, 1, 1, 1, 1,\n-\t\t\t\t1, 1, 1, 1, 1, 1, 1, 1,\n-\t\t\t\t1, 1, 1, 1, 1, 1, 1, 1,\n-\t\t\t\t4, 4) {\n-\t\t/* reserved [31..24] */\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t/* reserved [23..16] */\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t/* reserved [15..8] */\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t/* IPSR18_7_4 [4] */\n-\t\tIFN_USB3_OVC, 0, 0, FN_AUDIO_CLKOUT3_B,\n-\t\tFN_SSI_WS9_B, FN_TS_SPSYNC0_E, FN_STP_ISSYNC_0_E, 0,\n-\t\tFN_RIF2_D1_B, 0, 0, FN_TPU0TO3,\n-\t\tFN_FMIN_C, FN_FMIN_D, 0, 0,\n-\t\t/* IPSR18_3_0 [4] */\n-\t\tIFN_USB3_PWEN, 0, 0, FN_AUDIO_CLKOUT2_B,\n-\t\tFN_SSI_SCK9_B, FN_TS_SDEN0_E, FN_STP_ISEN_0_E, 0,\n-\t\tFN_RIF2_D0_B, 0, 0, FN_TPU0TO2,\n-\t\tFN_FMCLK_C, FN_FMCLK_D, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"MOD_SEL0\", 0xE6060500, 32,\n-\t\t\t\t3, 2, 3, 1, 1, 1, 1, 1, 2, 1,\n-\t\t\t\t1, 2, 1, 1, 1, 2, 2, 1, 2, 1, 1, 1) {\n-\t\t/* MOD_SEL0 */\n-\t\t/* sel_msiof3[3](0,1,2,3,4) */\n-\t\tFN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1,\n-\t\tFN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3,\n-\t\tFN_SEL_MSIOF3_4, 0,\n-\t\t0, 0,\n-\t\t/* sel_msiof2[2](0,1,2,3) */\n-\t\tFN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1,\n-\t\tFN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3,\n-\t\t/* sel_msiof1[3](0,1,2,3,4,5,6) */\n-\t\tFN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,\n-\t\tFN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3,\n-\t\tFN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5,\n-\t\tFN_SEL_MSIOF1_6, 0,\n-\t\t/* sel_lbsc[1](0,1) */\n-\t\tFN_SEL_LBSC_0, FN_SEL_LBSC_1,\n-\t\t/* sel_iebus[1](0,1) */\n-\t\tFN_SEL_IEBUS_0, FN_SEL_IEBUS_1,\n-\t\t/* sel_i2c2[1](0,1) */\n-\t\tFN_SEL_I2C2_0, FN_SEL_I2C2_1,\n-\t\t/* sel_i2c1[1](0,1) */\n-\t\tFN_SEL_I2C1_0, FN_SEL_I2C1_1,\n-\t\t/* sel_hscif4[1](0,1) */\n-\t\tFN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1,\n-\t\t/* sel_hscif3[2](0,1,2,3) */\n-\t\tFN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1,\n-\t\tFN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3,\n-\t\t/* sel_hscif1[1](0,1) */\n-\t\tFN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,\n-\t\t/* reserved[1] */\n-\t\t0, 0,\n-\t\t/* sel_hscif2[2](0,1,2) */\n-\t\tFN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,\n-\t\tFN_SEL_HSCIF2_2, 0,\n-\t\t/* sel_etheravb[1](0,1) */\n-\t\tFN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1,\n-\t\t/* sel_drif3[1](0,1) */\n-\t\tFN_SEL_DRIF3_0, FN_SEL_DRIF3_1,\n-\t\t/* sel_drif2[1](0,1) */\n-\t\tFN_SEL_DRIF2_0, FN_SEL_DRIF2_1,\n-\t\t/* sel_drif1[2](0,1,2) */\n-\t\tFN_SEL_DRIF1_0, FN_SEL_DRIF1_1,\n-\t\tFN_SEL_DRIF1_2, 0,\n-\t\t/* sel_drif0[2](0,1,2) */\n-\t\tFN_SEL_DRIF0_0, FN_SEL_DRIF0_1,\n-\t\tFN_SEL_DRIF0_2, 0,\n-\t\t/* sel_canfd0[1](0,1) */\n-\t\tFN_SEL_CANFD_0, FN_SEL_CANFD_1,\n-\t\t/* sel_adg_a[2](0,1,2) */\n-\t\tFN_SEL_ADG_A_0, FN_SEL_ADG_A_1,\n-\t\tFN_SEL_ADG_A_2, 0,\n-\t\t/* reserved[3]*/\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"MOD_SEL1\", 0xE6060504, 32,\n-\t\t\t\t2, 3, 1, 2,\n-\t\t\t\t3, 1, 1, 2, 1,\n-\t\t\t\t2, 1, 1, 1, 1, 1, 1,\n-\t\t\t\t1, 1, 1, 1, 1, 1, 1, 1) {\n-\t\t/* sel_tsif1[2](0,1,2,3) */\n-\t\tFN_SEL_TSIF1_0, FN_SEL_TSIF1_1,\n-\t\tFN_SEL_TSIF1_2, FN_SEL_TSIF1_3,\n-\t\t/* sel_tsif0[3](0,1,2,3,4) */\n-\t\tFN_SEL_TSIF0_0, FN_SEL_TSIF0_1,\n-\t\tFN_SEL_TSIF0_2, FN_SEL_TSIF0_3,\n-\t\tFN_SEL_TSIF0_4, 0,\n-\t\t0, 0,\n-\t\t/* sel_timer_tmu1[1](0,1) */\n-\t\tFN_SEL_TIMER_TMU1_0, FN_SEL_TIMER_TMU1_1,\n-\t\t/* sel_ssp1_1[2](0,1,2,3) */\n-\t\tFN_SEL_SSP1_1_0, FN_SEL_SSP1_1_1,\n-\t\tFN_SEL_SSP1_1_2, FN_SEL_SSP1_1_3,\n-\t\t/* sel_ssp1_0[3](0,1,2,3,4) */\n-\t\tFN_SEL_SSP1_0_0, FN_SEL_SSP1_0_1,\n-\t\tFN_SEL_SSP1_0_2, FN_SEL_SSP1_0_3,\n-\t\tFN_SEL_SSP1_0_4, 0,\n-\t\t0, 0,\n-\t\t/* sel_ssi1[1](0,1) */\n-\t\tFN_SEL_SSI_0, FN_SEL_SSI_1,\n-\t\t/* sel_speed_pulse_if[1](0,1) */\n-\t\tFN_SEL_SPEED_PULSE_IF_0, FN_SEL_SPEED_PULSE_IF_1,\n-\t\t/* sel_simcard[2](0,1,2,3) */\n-\t\tFN_SEL_SIMCARD_0, FN_SEL_SIMCARD_1,\n-\t\tFN_SEL_SIMCARD_2, FN_SEL_SIMCARD_3,\n-\t\t/* sel_sdhi2[1](0,1) */\n-\t\tFN_SEL_SDHI2_0, FN_SEL_SDHI2_1,\n-\t\t/* sel_scif4[2](0,1,2) */\n-\t\tFN_SEL_SCIF4_0, FN_SEL_SCIF4_1,\n-\t\tFN_SEL_SCIF4_2, 0,\n-\t\t/* sel_scif3[1](0,1) */\n-\t\tFN_SEL_SCIF3_0, FN_SEL_SCIF3_1,\n-\t\t/* sel_scif2[1](0,1) */\n-\t\tFN_SEL_SCIF2_0, FN_SEL_SCIF2_1,\n-\t\t/* sel_scif1[1](0,1) */\n-\t\tFN_SEL_SCIF1_0, FN_SEL_SCIF1_1,\n-\t\t/* sel_scif[1](0,1) */\n-\t\tFN_SEL_SCIF_0, FN_SEL_SCIF_1,\n-\t\t/* sel_remocon[1](0,1) */\n-\t\tFN_SEL_REMOCON_0, FN_SEL_REMOCON_1,\n-\t\t/* reserved[8..7] */\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t/* sel_rcan0[1](0,1) */\n-\t\tFN_SEL_RCAN_0, FN_SEL_RCAN_1,\n-\t\t/* sel_pwm6[1](0,1) */\n-\t\tFN_SEL_PWM6_0, FN_SEL_PWM6_1,\n-\t\t/* sel_pwm5[1](0,1) */\n-\t\tFN_SEL_PWM5_0, FN_SEL_PWM5_1,\n-\t\t/* sel_pwm4[1](0,1) */\n-\t\tFN_SEL_PWM4_0, FN_SEL_PWM4_1,\n-\t\t/* sel_pwm3[1](0,1) */\n-\t\tFN_SEL_PWM3_0, FN_SEL_PWM3_1,\n-\t\t/* sel_pwm2[1](0,1) */\n-\t\tFN_SEL_PWM2_0, FN_SEL_PWM2_1,\n-\t\t/* sel_pwm1[1](0,1) */\n-\t\tFN_SEL_PWM1_0, FN_SEL_PWM1_1,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"MOD_SEL2\", 0xE6060508, 32,\n-\t\t\t1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,\n-\t\t\t1, 1, 1, 1, 1, 1, 1, 1,\n-\t\t\t1, 1, 1, 1, 1, 1, 1, 1) {\n-\t\t/* i2c_sel_5[1](0,1) */\n-\t\tFN_I2C_SEL_5_0, FN_I2C_SEL_5_1,\n-\t\t/* i2c_sel_3[1](0,1) */\n-\t\tFN_I2C_SEL_3_0, FN_I2C_SEL_3_1,\n-\t\t/* i2c_sel_0[1](0,1) */\n-\t\tFN_I2C_SEL_0_0, FN_I2C_SEL_0_1,\n-\t\t/* sel_fm[2](0,1,2,3) */\n-\t\tFN_SEL_FM_0, FN_SEL_FM_1,\n-\t\tFN_SEL_FM_2, FN_SEL_FM_3,\n-\t\t/* sel_scif5[1](0,1) */\n-\t\tFN_SEL_SCIF5_0, FN_SEL_SCIF5_1,\n-\t\t/* sel_i2c6[3](0,1,2) */\n-\t\tFN_SEL_I2C6_0, FN_SEL_I2C6_1,\n-\t\tFN_SEL_I2C6_2, 0,\n-\t\t/* sel_ndfc[1](0,1) */\n-\t\tFN_SEL_NDFC_0, FN_SEL_NDFC_1,\n-\t\t/* sel_ssi2[1](0,1) */\n-\t\tFN_SEL_SSI2_0, FN_SEL_SSI2_1,\n-\t\t/* sel_ssi9[1](0,1) */\n-\t\tFN_SEL_SSI9_0, FN_SEL_SSI9_1,\n-\t\t/* sel_timer_tmu2[1](0,1) */\n-\t\tFN_SEL_TIMER_TMU2_0, FN_SEL_TIMER_TMU2_1,\n-\t\t/* sel_adg_b[1](0,1) */\n-\t\tFN_SEL_ADG_B_0, FN_SEL_ADG_B_1,\n-\t\t/* sel_adg_c[1](0,1) */\n-\t\tFN_SEL_ADG_C_0, FN_SEL_ADG_C_1,\n-\t\t/* reserved[16..16] */\n-\t\t0, 0,\n-\t\t/* reserved[15..8] */\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t/* reserved[7..1] */\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t/* sel_vin4[1](0,1) */\n-\t\tFN_SEL_VIN4_0, FN_SEL_VIN4_1,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG(\"INOUTSEL0\", 0xE6050004, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\tGP_0_15_IN, GP_0_15_OUT,\n-\t\tGP_0_14_IN, GP_0_14_OUT,\n-\t\tGP_0_13_IN, GP_0_13_OUT,\n-\t\tGP_0_12_IN, GP_0_12_OUT,\n-\t\tGP_0_11_IN, GP_0_11_OUT,\n-\t\tGP_0_10_IN, GP_0_10_OUT,\n-\t\tGP_0_9_IN, GP_0_9_OUT,\n-\t\tGP_0_8_IN, GP_0_8_OUT,\n-\t\tGP_0_7_IN, GP_0_7_OUT,\n-\t\tGP_0_6_IN, GP_0_6_OUT,\n-\t\tGP_0_5_IN, GP_0_5_OUT,\n-\t\tGP_0_4_IN, GP_0_4_OUT,\n-\t\tGP_0_3_IN, GP_0_3_OUT,\n-\t\tGP_0_2_IN, GP_0_2_OUT,\n-\t\tGP_0_1_IN, GP_0_1_OUT,\n-\t\tGP_0_0_IN, GP_0_0_OUT,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG(\"INOUTSEL1\", 0xE6051004, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\tGP_1_28_IN, GP_1_28_OUT,\n-\t\tGP_1_27_IN, GP_1_27_OUT,\n-\t\tGP_1_26_IN, GP_1_26_OUT,\n-\t\tGP_1_25_IN, GP_1_25_OUT,\n-\t\tGP_1_24_IN, GP_1_24_OUT,\n-\t\tGP_1_23_IN, GP_1_23_OUT,\n-\t\tGP_1_22_IN, GP_1_22_OUT,\n-\t\tGP_1_21_IN, GP_1_21_OUT,\n-\t\tGP_1_20_IN, GP_1_20_OUT,\n-\t\tGP_1_19_IN, GP_1_19_OUT,\n-\t\tGP_1_18_IN, GP_1_18_OUT,\n-\t\tGP_1_17_IN, GP_1_17_OUT,\n-\t\tGP_1_16_IN, GP_1_16_OUT,\n-\t\tGP_1_15_IN, GP_1_15_OUT,\n-\t\tGP_1_14_IN, GP_1_14_OUT,\n-\t\tGP_1_13_IN, GP_1_13_OUT,\n-\t\tGP_1_12_IN, GP_1_12_OUT,\n-\t\tGP_1_11_IN, GP_1_11_OUT,\n-\t\tGP_1_10_IN, GP_1_10_OUT,\n-\t\tGP_1_9_IN, GP_1_9_OUT,\n-\t\tGP_1_8_IN, GP_1_8_OUT,\n-\t\tGP_1_7_IN, GP_1_7_OUT,\n-\t\tGP_1_6_IN, GP_1_6_OUT,\n-\t\tGP_1_5_IN, GP_1_5_OUT,\n-\t\tGP_1_4_IN, GP_1_4_OUT,\n-\t\tGP_1_3_IN, GP_1_3_OUT,\n-\t\tGP_1_2_IN, GP_1_2_OUT,\n-\t\tGP_1_1_IN, GP_1_1_OUT,\n-\t\tGP_1_0_IN, GP_1_0_OUT,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG(\"INOUTSEL2\", 0xE6052004, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\tGP_2_14_IN, GP_2_14_OUT,\n-\t\tGP_2_13_IN, GP_2_13_OUT,\n-\t\tGP_2_12_IN, GP_2_12_OUT,\n-\t\tGP_2_11_IN, GP_2_11_OUT,\n-\t\tGP_2_10_IN, GP_2_10_OUT,\n-\t\tGP_2_9_IN, GP_2_9_OUT,\n-\t\tGP_2_8_IN, GP_2_8_OUT,\n-\t\tGP_2_7_IN, GP_2_7_OUT,\n-\t\tGP_2_6_IN, GP_2_6_OUT,\n-\t\tGP_2_5_IN, GP_2_5_OUT,\n-\t\tGP_2_4_IN, GP_2_4_OUT,\n-\t\tGP_2_3_IN, GP_2_3_OUT,\n-\t\tGP_2_2_IN, GP_2_2_OUT,\n-\t\tGP_2_1_IN, GP_2_1_OUT,\n-\t\tGP_2_0_IN, GP_2_0_OUT,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG(\"INOUTSEL3\", 0xE6053004, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\tGP_3_15_IN, GP_3_15_OUT,\n-\t\tGP_3_14_IN, GP_3_14_OUT,\n-\t\tGP_3_13_IN, GP_3_13_OUT,\n-\t\tGP_3_12_IN, GP_3_12_OUT,\n-\t\tGP_3_11_IN, GP_3_11_OUT,\n-\t\tGP_3_10_IN, GP_3_10_OUT,\n-\t\tGP_3_9_IN, GP_3_9_OUT,\n-\t\tGP_3_8_IN, GP_3_8_OUT,\n-\t\tGP_3_7_IN, GP_3_7_OUT,\n-\t\tGP_3_6_IN, GP_3_6_OUT,\n-\t\tGP_3_5_IN, GP_3_5_OUT,\n-\t\tGP_3_4_IN, GP_3_4_OUT,\n-\t\tGP_3_3_IN, GP_3_3_OUT,\n-\t\tGP_3_2_IN, GP_3_2_OUT,\n-\t\tGP_3_1_IN, GP_3_1_OUT,\n-\t\tGP_3_0_IN, GP_3_0_OUT,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG(\"INOUTSEL4\", 0xE6054004, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\tGP_4_17_IN, GP_4_17_OUT,\n-\t\tGP_4_16_IN, GP_4_16_OUT,\n-\n-\t\tGP_4_15_IN, GP_4_15_OUT,\n-\t\tGP_4_14_IN, GP_4_14_OUT,\n-\t\tGP_4_13_IN, GP_4_13_OUT,\n-\t\tGP_4_12_IN, GP_4_12_OUT,\n-\t\tGP_4_11_IN, GP_4_11_OUT,\n-\t\tGP_4_10_IN, GP_4_10_OUT,\n-\t\tGP_4_9_IN, GP_4_9_OUT,\n-\t\tGP_4_8_IN, GP_4_8_OUT,\n-\t\tGP_4_7_IN, GP_4_7_OUT,\n-\t\tGP_4_6_IN, GP_4_6_OUT,\n-\t\tGP_4_5_IN, GP_4_5_OUT,\n-\t\tGP_4_4_IN, GP_4_4_OUT,\n-\t\tGP_4_3_IN, GP_4_3_OUT,\n-\t\tGP_4_2_IN, GP_4_2_OUT,\n-\t\tGP_4_1_IN, GP_4_1_OUT,\n-\t\tGP_4_0_IN, GP_4_0_OUT,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG(\"INOUTSEL5\", 0xE6055004, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\tGP_5_25_IN, GP_5_25_OUT,\n-\t\tGP_5_24_IN, GP_5_24_OUT,\n-\n-\t\tGP_5_23_IN, GP_5_23_OUT,\n-\t\tGP_5_22_IN, GP_5_22_OUT,\n-\t\tGP_5_21_IN, GP_5_21_OUT,\n-\t\tGP_5_20_IN, GP_5_20_OUT,\n-\t\tGP_5_19_IN, GP_5_19_OUT,\n-\t\tGP_5_18_IN, GP_5_18_OUT,\n-\t\tGP_5_17_IN, GP_5_17_OUT,\n-\t\tGP_5_16_IN, GP_5_16_OUT,\n-\n-\t\tGP_5_15_IN, GP_5_15_OUT,\n-\t\tGP_5_14_IN, GP_5_14_OUT,\n-\t\tGP_5_13_IN, GP_5_13_OUT,\n-\t\tGP_5_12_IN, GP_5_12_OUT,\n-\t\tGP_5_11_IN, GP_5_11_OUT,\n-\t\tGP_5_10_IN, GP_5_10_OUT,\n-\t\tGP_5_9_IN, GP_5_9_OUT,\n-\t\tGP_5_8_IN, GP_5_8_OUT,\n-\t\tGP_5_7_IN, GP_5_7_OUT,\n-\t\tGP_5_6_IN, GP_5_6_OUT,\n-\t\tGP_5_5_IN, GP_5_5_OUT,\n-\t\tGP_5_4_IN, GP_5_4_OUT,\n-\t\tGP_5_3_IN, GP_5_3_OUT,\n-\t\tGP_5_2_IN, GP_5_2_OUT,\n-\t\tGP_5_1_IN, GP_5_1_OUT,\n-\t\tGP_5_0_IN, GP_5_0_OUT,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG(\"INOUTSEL6\", 0xE6055404, 32, 1) {\n-\t\tGP_INOUTSEL(6)\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG(\"INOUTSEL7\", 0xE6055804, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\tGP_6_3_IN, GP_6_3_OUT,\n-\t\tGP_6_2_IN, GP_6_2_OUT,\n-\t\tGP_6_1_IN, GP_6_1_OUT,\n-\t\tGP_6_0_IN, GP_6_0_OUT,\n-\t\t}\n-\t},\n-\t{ },\n-};\n-\n-static struct pinmux_data_reg pinmux_data_regs[] = {\n-\t/* use OUTDT registers? */\n-\t{ PINMUX_DATA_REG(\"INDT0\", 0xE6050008, 32) {\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\tGP_0_15_DATA, GP_0_14_DATA, GP_0_13_DATA, GP_0_12_DATA,\n-\t\tGP_0_11_DATA, GP_0_10_DATA, GP_0_9_DATA, GP_0_8_DATA,\n-\t\tGP_0_7_DATA, GP_0_6_DATA, GP_0_5_DATA, GP_0_4_DATA,\n-\t\tGP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA }\n-\t},\n-\t{ PINMUX_DATA_REG(\"INDT1\", 0xE6051008, 32) {\n-\t\t0, 0, 0, GP_1_28_DATA,\n-\t\tGP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA,\n-\t\tGP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,\n-\t\tGP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,\n-\t\tGP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,\n-\t\tGP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,\n-\t\tGP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,\n-\t\tGP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }\n-\t},\n-\t{ PINMUX_DATA_REG(\"INDT2\", 0xE6052008, 32) {\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\t0, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA,\n-\t\tGP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA,\n-\t\tGP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA,\n-\t\tGP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA }\n-\t},\n-\t{ PINMUX_DATA_REG(\"INDT3\", 0xE6053008, 32) {\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\tGP_3_15_DATA, GP_3_14_DATA, GP_3_13_DATA, GP_3_12_DATA,\n-\t\tGP_3_11_DATA, GP_3_10_DATA, GP_3_9_DATA, GP_3_8_DATA,\n-\t\tGP_3_7_DATA, GP_3_6_DATA, GP_3_5_DATA, GP_3_4_DATA,\n-\t\tGP_3_3_DATA, GP_3_2_DATA, GP_3_1_DATA, GP_3_0_DATA }\n-\t},\n-\t{ PINMUX_DATA_REG(\"INDT4\", 0xE6054008, 32) {\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\t0, 0, 0, 0, 0, 0, GP_4_17_DATA, GP_4_16_DATA,\n-\t\tGP_4_15_DATA, GP_4_14_DATA, GP_4_13_DATA, GP_4_12_DATA,\n-\t\tGP_4_11_DATA, GP_4_10_DATA, GP_4_9_DATA, GP_4_8_DATA,\n-\t\tGP_4_7_DATA, GP_4_6_DATA, GP_4_5_DATA, GP_4_4_DATA,\n-\t\tGP_4_3_DATA, GP_4_2_DATA, GP_4_1_DATA, GP_4_0_DATA }\n-\t},\n-\t{ PINMUX_DATA_REG(\"INDT5\", 0xE6055008, 32) {\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, GP_5_25_DATA, GP_5_24_DATA,\n-\t\tGP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA,\n-\t\tGP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA,\n-\t\tGP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA,\n-\t\tGP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,\n-\t\tGP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,\n-\t\tGP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }\n-\t},\n-\t{ PINMUX_DATA_REG(\"INDT6\", 0xE6055408, 32) {\n-\t\tGP_INDT(6) }\n-\t},\n-\t{ PINMUX_DATA_REG(\"INDT7\", 0xE6055808, 32) {\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\tGP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA }\n-\t},\n-\t{ },\n-};\n-\n-\n-static struct pinmux_info r8a7795_pinmux_info = {\n-\t.name = \"r8a7795_pfc\",\n-\n-\t.unlock_reg = 0xe6060000, /* PMMR */\n-\n-\t.reserved_id = PINMUX_RESERVED,\n-\t.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },\n-\t.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },\n-\t.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },\n-\t.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },\n-\t.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },\n-\n-\t.first_gpio = GPIO_GP_0_0,\n-\t.last_gpio = GPIO_FN_FMIN_D,\n-\n-\t.gpios = pinmux_gpios,\n-\t.cfg_regs = pinmux_config_regs,\n-\t.data_regs = pinmux_data_regs,\n-\n-\t.gpio_data = pinmux_data,\n-\t.gpio_data_size = ARRAY_SIZE(pinmux_data),\n-};\n-\n-void r8a7795_pinmux_init(void)\n-{\n-\tregister_pinmux(&r8a7795_pinmux_info);\n-}\ndiff --git a/arch/arm/mach-rmobile/pfc-r8a7796.c b/arch/arm/mach-rmobile/pfc-r8a7796.c\ndeleted file mode 100644\nindex f734f96dd0..0000000000\n--- a/arch/arm/mach-rmobile/pfc-r8a7796.c\n+++ /dev/null\n@@ -1,5253 +0,0 @@\n-/*\n- * arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7796.c\n- *     This file is r8a7796 processor support - PFC hardware block.\n- *\n- * Copyright (C) 2016 Renesas Electronics Corporation\n- *\n- * SPDX-License-Identifier:\tGPL-2.0+\n- */\n-\n-#include <common.h>\n-#include <sh_pfc.h>\n-#include <asm/gpio.h>\n-\n-#define CPU_32_PORT(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),\t\\\n-\tPORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx),\t\\\n-\tPORT_1(fn, pfx##31, sfx)\n-\n-#define CPU_32_PORT1(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),\t\\\n-\tPORT_10(fn, pfx##2, sfx)\n-\n-#define CPU_32_PORT2(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),\t\\\n-\tPORT_10(fn, pfx##2, sfx)\n-\n-#define CPU_32_PORT_29(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_10(fn, pfx, sfx),\t\t\t\t\t\\\n-\tPORT_10(fn, pfx##1, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##20, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##21, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##22, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##23, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##24, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##25, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##26, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##27, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##28, sfx)\n-\n-#define CPU_32_PORT_26(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_10(fn, pfx, sfx),\t\t\t\t\t\\\n-\tPORT_10(fn, pfx##1, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##20, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##21, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##22, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##23, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##24, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##25, sfx)\n-\n-#define CPU_32_PORT_18(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_10(fn, pfx, sfx),\t\t\t\t\t\\\n-\tPORT_1(fn, pfx##10, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##11, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##12, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##13, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##14, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##15, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##16, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##17, sfx)\n-\n-#define CPU_32_PORT_16(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_10(fn, pfx, sfx),\t\t\t\t\t\\\n-\tPORT_1(fn, pfx##10, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##11, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##12, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##13, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##14, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##15, sfx)\n-\n-#define CPU_32_PORT_15(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_10(fn, pfx, sfx),\t\t\t\t\t\\\n-\tPORT_1(fn, pfx##10, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##11, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##12, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##13, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##14, sfx)\n-\n-#define CPU_32_PORT_4(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_1(fn, pfx##0, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##1, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##2, sfx),\t\t\t\t\\\n-\tPORT_1(fn, pfx##3, sfx)\n-\n-\n-/* --gen3-- */\n-/* GP_0_0_DATA -> GP_7_4_DATA */\n-/* except for GP0[16] - [31],\n-\t\tGP1[28] - [31],\n-\t\tGP2[15] - [31],\n-\t\tGP3[16] - [31],\n-\t\tGP4[18] - [31],\n-\t\tGP5[26] - [31],\n-\t\tGP7[4] - [31] */\n-\n-#define CPU_ALL_PORT(fn, pfx, sfx)\t\t\\\n-\tCPU_32_PORT_16(fn, pfx##_0_, sfx),\t\\\n-\tCPU_32_PORT_29(fn, pfx##_1_, sfx),\t\\\n-\tCPU_32_PORT_15(fn, pfx##_2_, sfx),\t\\\n-\tCPU_32_PORT_16(fn, pfx##_3_, sfx),\t\\\n-\tCPU_32_PORT_18(fn, pfx##_4_, sfx),\t\\\n-\tCPU_32_PORT_26(fn, pfx##_5_, sfx),\t\\\n-\tCPU_32_PORT(fn, pfx##_6_, sfx),\t\t\\\n-\tCPU_32_PORT_4(fn, pfx##_7_, sfx)\n-\n-#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)\n-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN,\t\\\n-\t\t\t\t       GP##pfx##_IN, GP##pfx##_OUT)\n-\n-#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT\n-#define _GP_INDT(pfx, sfx) GP##pfx##_DATA\n-\n-#define GP_ALL(str)\tCPU_ALL_PORT(_PORT_ALL, GP, str)\n-#define PINMUX_GPIO_GP_ALL()\tCPU_ALL_PORT(_GP_GPIO, , unused)\n-#define PINMUX_DATA_GP_ALL()\tCPU_ALL_PORT(_GP_DATA, , unused)\n-\n-\n-#define PORT_10_REV(fn, pfx, sfx)\t\t\t\t\\\n-\tPORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx),\t\\\n-\tPORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx),\t\\\n-\tPORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx),\t\\\n-\tPORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx),\t\\\n-\tPORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)\n-\n-#define CPU_32_PORT_REV(fn, pfx, sfx)\t\t\t\t\t\\\n-\tPORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx),\t\t\\\n-\tPORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx),\t\\\n-\tPORT_10_REV(fn, pfx, sfx)\n-\n-#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)\n-#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)\n-\n-#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)\n-#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \\\n-\t\t\t\t\t\t\t  FN_##ipsr, FN_##fn)\n-\n-enum {\n-\tPINMUX_RESERVED = 0,\n-\n-\tPINMUX_DATA_BEGIN,\n-\tGP_ALL(DATA),\n-\tPINMUX_DATA_END,\n-\n-\tPINMUX_INPUT_BEGIN,\n-\tGP_ALL(IN),\n-\tPINMUX_INPUT_END,\n-\n-\tPINMUX_OUTPUT_BEGIN,\n-\tGP_ALL(OUT),\n-\tPINMUX_OUTPUT_END,\n-\n-\tPINMUX_FUNCTION_BEGIN,\n-\tGP_ALL(FN),\n-\n-\t/* GPSR0 */\n-\tGFN_D15,\n-\tGFN_D14,\n-\tGFN_D13,\n-\tGFN_D12,\n-\tGFN_D11,\n-\tGFN_D10,\n-\tGFN_D9,\n-\tGFN_D8,\n-\tGFN_D7,\n-\tGFN_D6,\n-\tGFN_D5,\n-\tGFN_D4,\n-\tGFN_D3,\n-\tGFN_D2,\n-\tGFN_D1,\n-\tGFN_D0,\n-\n-\t/* GPSR1 */\n-\tGFN_CLKOUT,\n-\tGFN_EX_WAIT0_A,\n-\tGFN_WE1x,\n-\tGFN_WE0x,\n-\tGFN_RD_WRx,\n-\tGFN_RDx,\n-\tGFN_BSx,\n-\tGFN_CS1x_A26,\n-\tGFN_CS0x,\n-\tGFN_A19,\n-\tGFN_A18,\n-\tGFN_A17,\n-\tGFN_A16,\n-\tGFN_A15,\n-\tGFN_A14,\n-\tGFN_A13,\n-\tGFN_A12,\n-\tGFN_A11,\n-\tGFN_A10,\n-\tGFN_A9,\n-\tGFN_A8,\n-\tGFN_A7,\n-\tGFN_A6,\n-\tGFN_A5,\n-\tGFN_A4,\n-\tGFN_A3,\n-\tGFN_A2,\n-\tGFN_A1,\n-\tGFN_A0,\n-\n-\t/* GPSR2 */\n-\tGFN_AVB_AVTP_CAPTURE_A,\n-\tGFN_AVB_AVTP_MATCH_A,\n-\tGFN_AVB_LINK,\n-\tGFN_AVB_PHY_INT,\n-\tGFN_AVB_MAGIC,\n-\tGFN_AVB_MDC,\n-\tGFN_PWM2_A,\n-\tGFN_PWM1_A,\n-\tGFN_PWM0,\n-\tGFN_IRQ5,\n-\tGFN_IRQ4,\n-\tGFN_IRQ3,\n-\tGFN_IRQ2,\n-\tGFN_IRQ1,\n-\tGFN_IRQ0,\n-\n-\t/* GPSR3 */\n-\tGFN_SD1_WP,\n-\tGFN_SD1_CD,\n-\tGFN_SD0_WP,\n-\tGFN_SD0_CD,\n-\tGFN_SD1_DAT3,\n-\tGFN_SD1_DAT2,\n-\tGFN_SD1_DAT1,\n-\tGFN_SD1_DAT0,\n-\tGFN_SD1_CMD,\n-\tGFN_SD1_CLK,\n-\tGFN_SD0_DAT3,\n-\tGFN_SD0_DAT2,\n-\tGFN_SD0_DAT1,\n-\tGFN_SD0_DAT0,\n-\tGFN_SD0_CMD,\n-\tGFN_SD0_CLK,\n-\n-\t/* GPSR4 */\n-\tGFN_SD3_DS,\n-\tGFN_SD3_DAT7,\n-\tGFN_SD3_DAT6,\n-\tGFN_SD3_DAT5,\n-\tGFN_SD3_DAT4,\n-\tFN_SD3_DAT3,\n-\tFN_SD3_DAT2,\n-\tFN_SD3_DAT1,\n-\tFN_SD3_DAT0,\n-\tFN_SD3_CMD,\n-\tFN_SD3_CLK,\n-\tGFN_SD2_DS,\n-\tGFN_SD2_DAT3,\n-\tGFN_SD2_DAT2,\n-\tGFN_SD2_DAT1,\n-\tGFN_SD2_DAT0,\n-\tFN_SD2_CMD,\n-\tGFN_SD2_CLK,\n-\n-\t/* GPSR5 */\n-\tGFN_MLB_DAT,\n-\tGFN_MLB_SIG,\n-\tGFN_MLB_CLK,\n-\tFN_MSIOF0_RXD,\n-\tGFN_MSIOF0_SS2,\n-\tFN_MSIOF0_TXD,\n-\tGFN_MSIOF0_SS1,\n-\tGFN_MSIOF0_SYNC,\n-\tFN_MSIOF0_SCK,\n-\tGFN_HRTS0x,\n-\tGFN_HCTS0x,\n-\tGFN_HTX0,\n-\tGFN_HRX0,\n-\tGFN_HSCK0,\n-\tGFN_RX2_A,\n-\tGFN_TX2_A,\n-\tGFN_SCK2,\n-\tGFN_RTS1x_TANS,\n-\tGFN_CTS1x,\n-\tGFN_TX1_A,\n-\tGFN_RX1_A,\n-\tGFN_RTS0x_TANS,\n-\tGFN_CTS0x,\n-\tGFN_TX0,\n-\tGFN_RX0,\n-\tGFN_SCK0,\n-\n-\t/* GPSR6 */\n-\tGFN_GP6_30,\n-\tGFN_GP6_31,\n-\tGFN_USB30_OVC,\n-\tGFN_USB30_PWEN,\n-\tGFN_USB1_OVC,\n-\tGFN_USB1_PWEN,\n-\tGFN_USB0_OVC,\n-\tGFN_USB0_PWEN,\n-\tGFN_AUDIO_CLKB_B,\n-\tGFN_AUDIO_CLKA_A,\n-\tGFN_SSI_SDATA9_A,\n-\tGFN_SSI_SDATA8,\n-\tGFN_SSI_SDATA7,\n-\tGFN_SSI_WS78,\n-\tGFN_SSI_SCK78,\n-\tGFN_SSI_SDATA6,\n-\tGFN_SSI_WS6,\n-\tGFN_SSI_SCK6,\n-\tFN_SSI_SDATA5,\n-\tFN_SSI_WS5,\n-\tFN_SSI_SCK5,\n-\tGFN_SSI_SDATA4,\n-\tGFN_SSI_WS4,\n-\tGFN_SSI_SCK4,\n-\tGFN_SSI_SDATA3,\n-\tGFN_SSI_WS34,\n-\tGFN_SSI_SCK34,\n-\tGFN_SSI_SDATA2_A,\n-\tGFN_SSI_SDATA1_A,\n-\tGFN_SSI_SDATA0,\n-\tGFN_SSI_WS01239,\n-\tGFN_SSI_SCK01239,\n-\n-\t/* GPSR7 */\n-\tFN_HDMI1_CEC,\n-\tFN_HDMI0_CEC,\n-\tFN_AVS2,\n-\tFN_AVS1,\n-\n-\t/* IPSR0 */\n-\tIFN_AVB_MDC,\n-\tFN_MSIOF2_SS2_C,\n-\tIFN_AVB_MAGIC,\n-\tFN_MSIOF2_SS1_C,\n-\tFN_SCK4_A,\n-\tIFN_AVB_PHY_INT,\n-\tFN_MSIOF2_SYNC_C,\n-\tFN_RX4_A,\n-\tIFN_AVB_LINK,\n-\tFN_MSIOF2_SCK_C,\n-\tFN_TX4_A,\n-\tIFN_AVB_AVTP_MATCH_A,\n-\tFN_MSIOF2_RXD_C,\n-\tFN_CTS4x_A,\n-\tIFN_AVB_AVTP_CAPTURE_A,\n-\tFN_MSIOF2_TXD_C,\n-\tFN_RTS4x_TANS_A,\n-\tIFN_IRQ0,\n-\tFN_QPOLB,\n-\tFN_DU_CDE,\n-\tFN_VI4_DATA0_B,\n-\tFN_CAN0_TX_B,\n-\tFN_CANFD0_TX_B,\n-\tFN_MSIOF3_SS2_E,\n-\tIFN_IRQ1,\n-\tFN_QPOLA,\n-\tFN_DU_DISP,\n-\tFN_VI4_DATA1_B,\n-\tFN_CAN0_RX_B,\n-\tFN_CANFD0_RX_B,\n-\tFN_MSIOF3_SS1_E,\n-\n-\t/* IPSR1 */\n-\tIFN_IRQ2,\n-\tFN_QCPV_QDE,\n-\tFN_DU_EXODDF_DU_ODDF_DISP_CDE,\n-\tFN_VI4_DATA2_B,\n-\tFN_MSIOF3_SYNC_E,\n-\tFN_PWM3_B,\n-\tIFN_IRQ3,\n-\tFN_QSTVB_QVE,\n-\tFN_DU_DOTCLKOUT1,\n-\tFN_VI4_DATA3_B,\n-\tFN_MSIOF3_SCK_E,\n-\tFN_PWM4_B,\n-\tIFN_IRQ4,\n-\tFN_QSTH_QHS,\n-\tFN_DU_EXHSYNC_DU_HSYNC,\n-\tFN_VI4_DATA4_B,\n-\tFN_MSIOF3_RXD_E,\n-\tFN_PWM5_B,\n-\tIFN_IRQ5,\n-\tFN_QSTB_QHE,\n-\tFN_DU_EXVSYNC_DU_VSYNC,\n-\tFN_VI4_DATA5_B,\n-\tFN_MSIOF3_TXD_E,\n-\tFN_PWM6_B,\n-\tIFN_PWM0,\n-\tFN_AVB_AVTP_PPS,\n-\tFN_VI4_DATA6_B,\n-\tFN_IECLK_B,\n-\tIFN_PWM1_A,\n-\tFN_HRX3_D,\n-\tFN_VI4_DATA7_B,\n-\tFN_IERX_B,\n-\tIFN_PWM2_A,\n-\tFN_PWMFSW0,\n-\tFN_HTX3_D,\n-\tFN_IETX_B,\n-\tIFN_A0,\n-\tFN_LCDOUT16,\n-\tFN_MSIOF3_SYNC_B,\n-\tFN_VI4_DATA8,\n-\tFN_DU_DB0,\n-\tFN_PWM3_A,\n-\n-\t/* IPSR2 */\n-\tIFN_A1,\n-\tFN_LCDOUT17,\n-\tFN_MSIOF3_TXD_B,\n-\tFN_VI4_DATA9,\n-\tFN_DU_DB1,\n-\tFN_PWM4_A,\n-\tIFN_A2,\n-\tFN_LCDOUT18,\n-\tFN_MSIOF3_SCK_B,\n-\tFN_VI4_DATA10,\n-\tFN_DU_DB2,\n-\tFN_PWM5_A,\n-\tIFN_A3,\n-\tFN_LCDOUT19,\n-\tFN_MSIOF3_RXD_B,\n-\tFN_VI4_DATA11,\n-\tFN_DU_DB3,\n-\tFN_PWM6_A,\n-\tIFN_A4,\n-\tFN_LCDOUT20,\n-\tFN_MSIOF3_SS1_B,\n-\tFN_VI4_DATA12,\n-\tFN_VI5_DATA12,\n-\tFN_DU_DB4,\n-\tIFN_A5,\n-\tFN_LCDOUT21,\n-\tFN_MSIOF3_SS2_B,\n-\tFN_SCK4_B,\n-\tFN_VI4_DATA13,\n-\tFN_VI5_DATA13,\n-\tFN_DU_DB5,\n-\tIFN_A6,\n-\tFN_LCDOUT22,\n-\tFN_MSIOF2_SS1_A,\n-\tFN_RX4_B,\n-\tFN_VI4_DATA14,\n-\tFN_VI5_DATA14,\n-\tFN_DU_DB6,\n-\tIFN_A7,\n-\tFN_LCDOUT23,\n-\tFN_MSIOF2_SS2_A,\n-\tFN_TX4_B,\n-\tFN_VI4_DATA15,\n-\tFN_V15_DATA15,\n-\tFN_DU_DB7,\n-\tIFN_A8,\n-\tFN_RX3_B,\n-\tFN_MSIOF2_SYNC_A,\n-\tFN_HRX4_B,\n-\tFN_SDA6_A,\n-\tFN_AVB_AVTP_MATCH_B,\n-\tFN_PWM1_B,\n-\n-\t/* IPSR3 */\n-\tIFN_A9,\n-\tFN_MSIOF2_SCK_A,\n-\tFN_CTS4x_B,\n-\tFN_VI5_VSYNCx,\n-\tIFN_A10,\n-\tFN_MSIOF2_RXD_A,\n-\tFN_RTS4n_TANS_B,\n-\tFN_VI5_HSYNCx,\n-\tIFN_A11,\n-\tFN_TX3_B,\n-\tFN_MSIOF2_TXD_A,\n-\tFN_HTX4_B,\n-\tFN_HSCK4,\n-\tFN_VI5_FIELD,\n-\tFN_SCL6_A,\n-\tFN_AVB_AVTP_CAPTURE_B,\n-\tFN_PWM2_B,\n-\tFN_SPV_EVEN,\n-\tIFN_A12,\n-\tFN_LCDOUT12,\n-\tFN_MSIOF3_SCK_C,\n-\tFN_HRX4_A,\n-\tFN_VI5_DATA8,\n-\tFN_DU_DG4,\n-\tIFN_A13,\n-\tFN_LCDOUT13,\n-\tFN_MSIOF3_SYNC_C,\n-\tFN_HTX4_A,\n-\tFN_VI5_DATA9,\n-\tFN_DU_DG5,\n-\tIFN_A14,\n-\tFN_LCDOUT14,\n-\tFN_MSIOF3_RXD_C,\n-\tFN_HCTS4x,\n-\tFN_VI5_DATA10,\n-\tFN_DU_DG6,\n-\tIFN_A15,\n-\tFN_LCDOUT15,\n-\tFN_MSIOF3_TXD_C,\n-\tFN_HRTS4x,\n-\tFN_VI5_DATA11,\n-\tFN_DU_DG7,\n-\tIFN_A16,\n-\tFN_LCDOUT8,\n-\tFN_VI4_FIELD,\n-\tFN_DU_DG0,\n-\n-\t/* IPSR4 */\n-\tIFN_A17,\n-\tFN_LCDOUT9,\n-\tFN_VI4_VSYNCx,\n-\tFN_DU_DG1,\n-\tIFN_A18,\n-\tFN_LCDOUT10,\n-\tFN_VI4_HSYNCx,\n-\tFN_DU_DG2,\n-\tIFN_A19,\n-\tFN_LCDOUT11,\n-\tFN_VI4_CLKENB,\n-\tFN_DU_DG3,\n-\tIFN_CS0x,\n-\tFN_VI5_CLKENB,\n-\tIFN_CS1x_A26,\n-\tFN_VI5_CLK,\n-\tFN_EX_WAIT0_B,\n-\tIFN_BSx,\n-\tFN_QSTVA_QVS,\n-\tFN_MSIOF3_SCK_D,\n-\tFN_SCK3,\n-\tFN_HSCK3,\n-\tFN_CAN1_TX,\n-\tFN_CANFD1_TX,\n-\tFN_IETX_A,\n-\tIFN_RDx,\n-\tFN_MSIOF3_SYNC_D,\n-\tFN_RX3_A,\n-\tFN_HRX3_A,\n-\tFN_CAN0_TX_A,\n-\tFN_CANFD0_TX_A,\n-\tIFN_RD_WRx,\n-\tFN_MSIOF3_RXD_D,\n-\tFN_TX3_A,\n-\tFN_HTX3_A,\n-\tFN_CAN0_RX_A,\n-\tFN_CANFD0_RX_A,\n-\n-\t/* IPSR5 */\n-\tIFN_WE0x,\n-\tFN_MSIIOF3_TXD_D,\n-\tFN_CTS3x,\n-\tFN_HCTS3x,\n-\tFN_SCL6_B,\n-\tFN_CAN_CLK,\n-\tFN_IECLK_A,\n-\tIFN_WE1x,\n-\tFN_MSIOF3_SS1_D,\n-\tFN_RTS3x_TANS,\n-\tFN_HRTS3x,\n-\tFN_SDA6_B,\n-\tFN_CAN1_RX,\n-\tFN_CANFD1_RX,\n-\tFN_IERX_A,\n-\tIFN_EX_WAIT0_A,\n-\tFN_QCLK,\n-\tFN_VI4_CLK,\n-\tFN_DU_DOTCLKOUT0,\n-\tIFN_D0,\n-\tFN_MSIOF2_SS1_B,\n-\tFN_MSIOF3_SCK_A,\n-\tFN_VI4_DATA16,\n-\tFN_VI5_DATA0,\n-\tIFN_D1,\n-\tFN_MSIOF2_SS2_B,\n-\tFN_MSIOF3_SYNC_A,\n-\tFN_VI4_DATA17,\n-\tFN_VI5_DATA1,\n-\tIFN_D2,\n-\tFN_MSIOF3_RXD_A,\n-\tFN_VI4_DATA18,\n-\tFN_VI5_DATA2,\n-\tIFN_D3,\n-\tFN_MSIOF3_TXD_A,\n-\tFN_VI4_DATA19,\n-\tFN_VI5_DATA3,\n-\tIFN_D4,\n-\tFN_MSIOF2_SCK_B,\n-\tFN_VI4_DATA20,\n-\tFN_VI5_DATA4,\n-\n-\t/* IPSR6 */\n-\tIFN_D5,\n-\tFN_MSIOF2_SYNC_B,\n-\tFN_VI4_DATA21,\n-\tFN_VI5_DATA5,\n-\tIFN_D6,\n-\tFN_MSIOF2_RXD_B,\n-\tFN_VI4_DATA22,\n-\tFN_VI5_DATA6,\n-\tIFN_D7,\n-\tFN_MSIOF2_TXD_B,\n-\tFN_VI4_DATA23,\n-\tFN_VI5_DATA7,\n-\tIFN_D8,\n-\tFN_LCDOUT0,\n-\tFN_MSIOF2_SCK_D,\n-\tFN_SCK4_C,\n-\tFN_VI4_DATA0_A,\n-\tFN_DU_DR0,\n-\tIFN_D9,\n-\tFN_LCDOUT1,\n-\tFN_MSIOF2_SYNC_D,\n-\tFN_VI4_DATA1_A,\n-\tFN_DU_DR1,\n-\tIFN_D10,\n-\tFN_LCDOUT2,\n-\tFN_MSIOF2_RXD_D,\n-\tFN_HRX3_B,\n-\tFN_VI4_DATA2_A,\n-\tFN_CTS4x_C,\n-\tFN_DU_DR2,\n-\tIFN_D11,\n-\tFN_LCDOUT3,\n-\tFN_MSIOF2_TXD_D,\n-\tFN_HTX3_B,\n-\tFN_VI4_DATA3_A,\n-\tFN_RTS4x_TANS_C,\n-\tFN_DU_DR3,\n-\tIFN_D12,\n-\tFN_LCDOUT4,\n-\tFN_MSIOF2_SS1_D,\n-\tFN_RX4_C,\n-\tFN_VI4_DATA4_A,\n-\tFN_DU_DR4,\n-\n-\t/* IPSR7 */\n-\tIFN_D13,\n-\tFN_LCDOUT5,\n-\tFN_MSIOF2_SS2_D,\n-\tFN_TX4_C,\n-\tFN_VI4_DATA5_A,\n-\tFN_DU_DR5,\n-\tIFN_D14,\n-\tFN_LCDOUT6,\n-\tFN_MSIOF3_SS1_A,\n-\tFN_HRX3_C,\n-\tFN_VI4_DATA6_A,\n-\tFN_DU_DR6,\n-\tFN_SCL6_C,\n-\tIFN_D15,\n-\tFN_LCDOUT7,\n-\tFN_MSIOF3_SS2_A,\n-\tFN_HTX3_C,\n-\tFN_VI4_DATA7_A,\n-\tFN_DU_DR7,\n-\tFN_SDA6_C,\n-\tFN_FSCLKST,\n-\tIFN_SD0_CLK,\n-\tFN_MSIOF1_SCK_E,\n-\tFN_STP_OPWM_0_B,\n-\tIFN_SD0_CMD,\n-\tFN_MSIOF1_SYNC_E,\n-\tFN_STP_IVCXO27_0_B,\n-\tIFN_SD0_DAT0,\n-\tFN_MSIOF1_RXD_E,\n-\tFN_TS_SCK0_B,\n-\tFN_STP_ISCLK_0_B,\n-\tIFN_SD0_DAT1,\n-\tFN_MSIOF1_TXD_E,\n-\tFN_TS_SPSYNC0_B,\n-\tFN_STP_ISSYNC_0_B,\n-\n-\t/* IPSR8 */\n-\tIFN_SD0_DAT2,\n-\tFN_MSIOF1_SS1_E,\n-\tFN_TS_SDAT0_B,\n-\tFN_STP_ISD_0_B,\n-\n-\tIFN_SD0_DAT3,\n-\tFN_MSIOF1_SS2_E,\n-\tFN_TS_SDEN0_B,\n-\tFN_STP_ISEN_0_B,\n-\n-\tIFN_SD1_CLK,\n-\tFN_MSIOF1_SCK_G,\n-\tFN_SIM0_CLK_A,\n-\n-\tIFN_SD1_CMD,\n-\tFN_MSIOF1_SYNC_G,\n-\tFN_NFCEx_B,\n-\tFN_SIM0_D_A,\n-\tFN_STP_IVCXO27_1_B,\n-\n-\tIFN_SD1_DAT0,\n-\tFN_SD2_DAT4,\n-\tFN_MSIOF1_RXD_G,\n-\tFN_NFWPx_B,\n-\tFN_TS_SCK1_B,\n-\tFN_STP_ISCLK_1_B,\n-\n-\tIFN_SD1_DAT1,\n-\tFN_SD2_DAT5,\n-\tFN_MSIOF1_TXD_G,\n-\tFN_NFDATA14_B,\n-\tFN_TS_SPSYNC1_B,\n-\tFN_STP_ISSYNC_1_B,\n-\n-\tIFN_SD1_DAT2,\n-\tFN_SD2_DAT6,\n-\tFN_MSIOF1_SS1_G,\n-\tFN_NFDATA15_B,\n-\tFN_TS_SDAT1_B,\n-\tFN_STP_IOD_1_B,\n-\n-\tIFN_SD1_DAT3,\n-\tFN_SD2_DAT7,\n-\tFN_MSIOF1_SS2_G,\n-\tFN_NFRBx_B,\n-\tFN_TS_SDEN1_B,\n-\tFN_STP_ISEN_1_B,\n-\n-\t/* IPSR9 */\n-\tIFN_SD2_CLK,\n-\tFN_NFDATA8,\n-\n-\tIFN_SD2_CMD,\n-\tFN_NFDATA9,\n-\n-\tIFN_SD2_DAT0,\n-\tFN_NFDATA10,\n-\n-\tIFN_SD2_DAT1,\n-\tFN_NFDATA11,\n-\n-\tIFN_SD2_DAT2,\n-\tFN_NFDATA12,\n-\n-\tIFN_SD2_DAT3,\n-\tFN_NFDATA13,\n-\n-\tIFN_SD2_DS,\n-\tFN_NFALE,\n-\n-\tIFN_SD3_CLK,\n-\tFN_NFWEx,\n-\n-\t/* IPSR10 */\n-\tIFN_SD3_CMD,\n-\tFN_NFREx,\n-\n-\tIFN_SD3_DAT0,\n-\tFN_NFDATA0,\n-\n-\tIFN_SD3_DAT1,\n-\tFN_NFDATA1,\n-\n-\tIFN_SD3_DAT2,\n-\tFN_NFDATA2,\n-\n-\tIFN_SD3_DAT3,\n-\tFN_NFDATA3,\n-\n-\tIFN_SD3_DAT4,\n-\tFN_SD2_CD_A,\n-\tFN_NFDATA4,\n-\n-\tIFN_SD3_DAT5,\n-\tFN_SD2_WP_A,\n-\tFN_NFDATA5,\n-\n-\tIFN_SD3_DAT6,\n-\tFN_SD3_CD,\n-\tFN_NFDATA6,\n-\n-\t/* IPSR11 */\n-\tIFN_SD3_DAT7,\n-\tFN_SD3_WP,\n-\tFN_NFDATA7,\n-\n-\tIFN_SD3_DS,\n-\tFN_NFCLE,\n-\n-\tIFN_SD0_CD,\n-\tFN_NFDATA14_A,\n-\tFN_SCL2_B,\n-\tFN_SIM0_RST_A,\n-\n-\tIFN_SD0_WP,\n-\tFN_NFDATA15_A,\n-\tFN_SDA2_B,\n-\n-\tIFN_SD1_CD,\n-\tFN_NFRBx_A,\n-\tFN_SIM0_CLK_B,\n-\n-\tIFN_SD1_WP,\n-\tFN_NFCEx_A,\n-\tFN_SIM0_D_B,\n-\n-\tIFN_SCK0,\n-\tFN_HSCK1_B,\n-\tFN_MSIOF1_SS2_B,\n-\tFN_AUDIO_CLKC_B,\n-\tFN_SDA2_A,\n-\tFN_SIM0_RST_B,\n-\tFN_STP_OPWM_0_C,\n-\tFN_RIF0_CLK_B,\n-\tFN_ADICHS2,\n-\tFN_SCK5_B,\n-\n-\tIFN_RX0,\n-\tFN_HRX1_B,\n-\tFN_TS_SCK0_C,\n-\tFN_STP_ISCLK_0_C,\n-\tFN_RIF0_D0_B,\n-\n-\t/* IPSR12 */\n-\tIFN_TX0,\n-\tFN_HTX1_B,\n-\tFN_TS_SPSYNC0_C,\n-\tFN_STP_ISSYNC_0_C,\n-\tFN_RIF0_D1_B,\n-\n-\tIFN_CTS0x,\n-\tFN_HCTS1x_B,\n-\tFN_MSIOF1_SYNC_B,\n-\tFN_TS_SPSYNC1_C,\n-\tFN_STP_ISSYNC_1_C,\n-\tFN_RIF1_SYNC_B,\n-\tFN_AUDIO_CLKOUT_C,\n-\tFN_ADICS_SAMP,\n-\n-\tIFN_RTS0x_TANS,\n-\tFN_HRTS1x_B,\n-\tFN_MSIOF1_SS1_B,\n-\tFN_AUDIO_CLKA_B,\n-\tFN_SCL2_A,\n-\tFN_STP_IVCXO27_1_C,\n-\tFN_RIF0_SYNC_B,\n-\tFN_ADICHS1,\n-\n-\tIFN_RX1_A,\n-\tFN_HRX1_A,\n-\tFN_TS_SDAT0_C,\n-\tFN_STP_ISD_0_C,\n-\tFN_RIF1_CLK_C,\n-\n-\tIFN_TX1_A,\n-\tFN_HTX1_A,\n-\tFN_TS_SDEN0_C,\n-\tFN_STP_ISEN_0_C,\n-\tFN_RIF1_D0_C,\n-\n-\tIFN_CTS1x,\n-\tFN_HCTS1x_A,\n-\tFN_MSIOF1_RXD_B,\n-\tFN_TS_SDEN1_C,\n-\tFN_STP_ISEN_1_C,\n-\tFN_RIF1_D0_B,\n-\tFN_ADIDATA,\n-\n-\tIFN_RTS1x_TANS,\n-\tFN_HRTS1x_A,\n-\tFN_MSIOF1_TXD_B,\n-\tFN_TS_SDAT1_C,\n-\tFN_STP_ISD_1_C,\n-\tFN_RIF1_D1_B,\n-\tFN_ADICHS0,\n-\n-\tIFN_SCK2,\n-\tFN_SCIF_CLK_B,\n-\tFN_MSIOF1_SCK_B,\n-\tFN_TS_SCK1_C,\n-\tFN_STP_ISCLK_1_C,\n-\tFN_RIF1_CLK_B,\n-\tFN_ADICLK,\n-\n-\t/* IPSR13 */\n-\tIFN_TX2_A,\n-\tFN_SD2_CD_B,\n-\tFN_SCL1_A,\n-\tFN_FMCLK_A,\n-\tFN_RIF1_D1_C,\n-\tFN_FSO_CFE_0_B,\n-\n-\tIFN_RX2_A,\n-\tFN_SD2_WP_B,\n-\tFN_SDA1_A,\n-\tFN_FMIN_A,\n-\tFN_RIF1_SYNC_C,\n-\tFN_FSO_CEF_1_B,\n-\n-\tIFN_HSCK0,\n-\tFN_MSIOF1_SCK_D,\n-\tFN_AUDIO_CLKB_A,\n-\tFN_SSI_SDATA1_B,\n-\tFN_TS_SCK0_D,\n-\tFN_STP_ISCLK_0_D,\n-\tFN_RIF0_CLK_C,\n-\tFN_RX5_B,\n-\n-\tIFN_HRX0,\n-\tFN_MSIOF1_RXD_D,\n-\tFN_SS1_SDATA2_B,\n-\tFN_TS_SDEN0_D,\n-\tFN_STP_ISEN_0_D,\n-\tFN_RIF0_D0_C,\n-\n-\tIFN_HTX0,\n-\tFN_MSIOF1_TXD_D,\n-\tFN_SSI_SDATA9_B,\n-\tFN_TS_SDAT0_D,\n-\tFN_STP_ISD_0_D,\n-\tFN_RIF0_D1_C,\n-\n-\tIFN_HCTS0x,\n-\tFN_RX2_B,\n-\tFN_MSIOF1_SYNC_D,\n-\tFN_SSI_SCK9_A,\n-\tFN_TS_SPSYNC0_D,\n-\tFN_STP_ISSYNC_0_D,\n-\tFN_RIF0_SYNC_C,\n-\tFN_AUDIO_CLKOUT1_A,\n-\n-\tIFN_HRTS0x,\n-\tFN_TX2_B,\n-\tFN_MSIOF1_SS1_D,\n-\tFN_SSI_WS9_A,\n-\tFN_STP_IVCXO27_0_D,\n-\tFN_BPFCLK_A,\n-\tFN_AUDIO_CLKOUT2_A,\n-\n-\tIFN_MSIOF0_SYNC,\n-\tFN_AUDIO_CLKOUT_A,\n-\tFN_TX5_B,\n-\tFN_BPFCLK_D,\n-\n-\t/* IPSR14 */\n-\tIFN_MSIOF0_SS1,\n-\tFN_RX5_A,\n-\tFN_NFWPx_A,\n-\tFN_AUDIO_CLKA_C,\n-\tFN_SSI_SCK2_A,\n-\tFN_STP_IVCXO27_0_C,\n-\tFN_AUDIO_CLKOUT3_A,\n-\tFN_TCLK1_B,\n-\n-\tIFN_MSIOF0_SS2,\n-\tFN_TX5_A,\n-\tFN_MSIOF1_SS2_D,\n-\tFN_AUDIO_CLKC_A,\n-\tFN_SSI_WS2_A,\n-\tFN_STP_OPWM_0_D,\n-\tFN_AUDIO_CLKOUT_D,\n-\tFN_SPEEDIN_B,\n-\n-\tIFN_MLB_CLK,\n-\tFN_MSIOF1_SCK_F,\n-\tFN_SCL1_B,\n-\n-\tIFN_MLB_SIG,\n-\tFN_RX1_B,\n-\tFN_MSIOF1_SYNC_F,\n-\tFN_SDA1_B,\n-\n-\tIFN_MLB_DAT,\n-\tFN_TX1_B,\n-\tFN_MSIOF1_RXD_F,\n-\n-\tIFN_SSI_SCK0129,\n-\tFN_MSIOF1_TXD_F,\n-\tFN_MOUT0,\n-\n-\tIFN_SSI_WS0129,\n-\tFN_MSIOF1_SS1_F,\n-\tFN_MOUT1,\n-\n-\tIFN_SSI_SDATA0,\n-\tFN_MSIOF1_SS2_F,\n-\tFN_MOUT2,\n-\n-\t/* IPSR15 */\n-\tIFN_SSI_SDATA1_A,\n-\tFN_MOUT5,\n-\n-\tIFN_SSI_SDATA2_A,\n-\tFN_SSI_SCK1_B,\n-\tFN_MOUT6,\n-\n-\tIFN_SSI_SCK34,\n-\tFN_MSIOF1_SS1_A,\n-\tFN_STP_OPWM_0_A,\n-\n-\tIFN_SSI_WS34,\n-\tFN_HCTS2x_A,\n-\tFN_MSIOF1_SS2_A,\n-\tFN_STP_IVCXO27_0_A,\n-\n-\tIFN_SSI_SDATA3,\n-\tFN_HRTS2x_A,\n-\tFN_MSIOF1_TXD_A,\n-\tFN_TS_SCK0_A,\n-\tFN_STP_ISCLK_0_A,\n-\tFN_RIF0_D1_A,\n-\tFN_RIF2_D0_A,\n-\n-\tIFN_SSI_SCK4,\n-\tFN_HRX2_A,\n-\tFN_MSIOF1_SCK_A,\n-\tFN_TS_SDAT0_A,\n-\tFN_STP_ISD_0_A,\n-\tFN_RIF0_CLK_A,\n-\tFN_RIF2_CLK_A,\n-\n-\tIFN_SSI_WS4,\n-\tFN_HTX2_A,\n-\tFN_MSIOF1_SYNC_A,\n-\tFN_TS_SDEN0_A,\n-\tFN_STP_ISEN_0_A,\n-\tFN_RIF0_SYNC_A,\n-\tFN_RIF2_SYNC_A,\n-\n-\tIFN_SSI_SDATA4,\n-\tFN_HSCK2_A,\n-\tFN_MSIOF1_RXD_A,\n-\tFN_TS_SPSYNC0_A,\n-\tFN_STP_ISSYNC_0_A,\n-\tFN_RIF0_D0_A,\n-\tFN_RIF2_D1_A,\n-\n-\t/* IPSR16 */\n-\tIFN_SSI_SCK6,\n-\tFN_SIM0_RST_D,\n-\tFN_FSO_TOE_A,\n-\n-\tIFN_SSI_WS6,\n-\tFN_SIM0_D_D,\n-\n-\tIFN_SSI_SDATA6,\n-\tFN_SIM0_CLK_D,\n-\n-\tIFN_SSI_SCK78,\n-\tFN_HRX2_B,\n-\tFN_MSIOF1_SCK_C,\n-\tFN_TS_SCK1_A,\n-\tFN_STP_ISCLK_1_A,\n-\tFN_RIF1_CLK_A,\n-\tFN_RIF3_CLK_A,\n-\n-\tIFN_SSI_WS78,\n-\tFN_HTX2_B,\n-\tFN_MSIOF1_SYNC_C,\n-\tFN_TS_SDAT1_A,\n-\tFN_STP_ISD_1_A,\n-\tFN_RIF1_SYNC_A,\n-\tFN_RIF3_SYNC_A,\n-\n-\tIFN_SSI_SDATA7,\n-\tFN_HCTS2x_B,\n-\tFN_MSIOF1_RXD_C,\n-\tFN_TS_SDEN1_A,\n-\tFN_STP_IEN_1_A,\n-\tFN_RIF1_D0_A,\n-\tFN_RIF3_D0_A,\n-\tFN_TCLK2_A,\n-\n-\tIFN_SSI_SDATA8,\n-\tFN_HRTS2x_B,\n-\tFN_MSIOF1_TXD_C,\n-\tFN_TS_SPSYNC1_A,\n-\tFN_STP_ISSYNC_1_A,\n-\tFN_RIF1_D1_A,\n-\tFN_EIF3_D1_A,\n-\n-\tIFN_SSI_SDATA9_A,\n-\tFN_HSCK2_B,\n-\tFN_MSIOF1_SS1_C,\n-\tFN_HSCK1_A,\n-\tFN_SSI_WS1_B,\n-\tFN_SCK1,\n-\tFN_STP_IVCXO27_1_A,\n-\tFN_SCK5,\n-\n-\t/* IPSR17 */\n-\tIFN_AUDIO_CLKA_A,\n-\tFN_CC5_OSCOUT,\n-\n-\tIFN_AUDIO_CLKB_B,\n-\tFN_SCIF_CLK_A,\n-\tFN_STP_IVCXO27_1_D,\n-\tFN_REMOCON_A,\n-\tFN_TCLK1_A,\n-\n-\tIFN_USB0_PWEN,\n-\tFN_SIM0_RST_C,\n-\tFN_TS_SCK1_D,\n-\tFN_STP_ISCLK_1_D,\n-\tFN_BPFCLK_B,\n-\tFN_RIF3_CLK_B,\n-\tFN_FSO_CFE_1_A,\n-\tFN_HSCK2_C,\n-\n-\tIFN_USB0_OVC,\n-\tFN_SIM0_D_C,\n-\tFN_TS_SDAT1_D,\n-\tFN_STP_ISD_1_D,\n-\tFN_RIF3_SYNC_B,\n-\tFN_HRX2_C,\n-\n-\tIFN_USB1_PWEN,\n-\tFN_SIM0_CLK_C,\n-\tFN_SSI_SCK1_A,\n-\tFN_TS_SCK0_E,\n-\tFN_STP_ISCLK_0_E,\n-\tFN_FMCLK_B,\n-\tFN_RIF2_CLK_B,\n-\tFN_SPEEDIN_A,\n-\tFN_HTX2_C,\n-\n-\tIFN_USB1_OVC,\n-\tFN_MSIOF1_SS2_C,\n-\tFN_SSI_WS1_A,\n-\tFN_TS_SDAT0_E,\n-\tFN_STP_ISD_0_E,\n-\tFN_FMIN_B,\n-\tFN_RIF2_SYNC_B,\n-\tFN_REMOCON_B,\n-\tFN_HCTS2x_C,\n-\n-\tIFN_USB30_PWEN,\n-\tFN_AUDIO_CLKOUT_B,\n-\tFN_SSI_SCK2_B,\n-\tFN_TS_SDEN1_D,\n-\tFN_STP_ISEN_1_D,\n-\tFN_STP_OPWM_0_E,\n-\tFN_RIF3_D0_B,\n-\tFN_TCLK2_B,\n-\tFN_TPU0TO0,\n-\tFN_BPFCLK_C,\n-\tFN_HRTS2x_C,\n-\n-\tIFN_USB30_OVC,\n-\tFN_AUDIO_CLKOUT1_B,\n-\tFN_SSI_WS2_B,\n-\tFN_TS_SPSYNC1_D,\n-\tFN_STP_ISSYNC_1_D,\n-\tFN_STP_IVCXO27_0_E,\n-\tFN_RIF3_D1_B,\n-\tFN_FSO_TOE_B,\n-\tFN_TPU0TO1,\n-\n-\t/* IPSR18 */\n-\tIFN_GP6_30,\n-\tFN_AUDIO_CLKOUT2_B,\n-\tFN_SSI_SCK9_B,\n-\tFN_TS_SDEN0_E,\n-\tFN_STP_ISEN_0_E,\n-\tFN_RIF2_D0_B,\n-\tFN_FSO_CFE_0_A,\n-\tFN_TPU0TO2,\n-\tFN_FMCLK_C,\n-\tFN_FMCLK_D,\n-\n-\tIFN_GP6_31,\n-\tFN_AUDIO_CLKOUT3_B,\n-\tFN_SSI_WS9_B,\n-\tFN_TS_SPSYNC0_E,\n-\tFN_STP_ISSYNC_0_E,\n-\tFN_RIF2_D1_B,\n-\tFN_TPU0TO3,\n-\tFN_FMIN_C,\n-\tFN_FMIN_D,\n-\n-\t/* MOD_SEL0 */\n-\tFN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1,\n-\tFN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3,\n-\tFN_SEL_MSIOF3_4, FN_SEL_MSIOF3_5,\n-\tFN_SEL_MSIOF3_6,\n-\tFN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1,\n-\tFN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3,\n-\tFN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,\n-\tFN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3,\n-\tFN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5,\n-\tFN_SEL_MSIOF1_6,\n-\tFN_SEL_LBSC_0, FN_SEL_LBSC_1,\n-\tFN_SEL_IEBUS_0, FN_SEL_IEBUS_1,\n-\tFN_SEL_I2C2_0, FN_SEL_I2C2_1,\n-\tFN_SEL_I2C1_0, FN_SEL_I2C1_1,\n-\tFN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1,\n-\tFN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1,\n-\tFN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3,\n-\tFN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,\n-\tFN_SEL_HSCIF2_2,\n-\tFN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,\n-\tFN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1,\n-\tFN_SEL_FSO_0, FN_SEL_FSO_1,\n-\tFN_SEL_DRIF3_0, FN_SEL_DRIF3_1,\n-\tFN_SEL_DRIF2_0, FN_SEL_DRIF2_1,\n-\tFN_SEL_DRIF1_0, FN_SEL_DRIF1_1,\n-\tFN_SEL_DRIF1_2,\n-\tFN_SEL_DRIF0_0, FN_SEL_DRIF0_1,\n-\tFN_SEL_DRIF0_2,\n-\tFN_SEL_CANFD_0, FN_SEL_CANFD_1,\n-\tFN_SEL_ADG_0, FN_SEL_ADG_1,\n-\tFN_SEL_ADG_2, FN_SEL_ADG_3,\n-\n-\t/* MOD_SEL1 */\n-\tFN_SEL_TSIF1_0,\n-\tFN_SEL_TSIF1_1,\n-\tFN_SEL_TSIF1_2,\n-\tFN_SEL_TSIF1_3,\n-\tFN_SEL_TSIF0_0,\n-\tFN_SEL_TSIF0_1,\n-\tFN_SEL_TSIF0_2,\n-\tFN_SEL_TSIF0_3,\n-\tFN_SEL_TSIF0_4,\n-\tFN_SEL_TIMER_TMU_0,\n-\tFN_SEL_TIMER_TMU_1,\n-\tFN_SEL_SSP1_1_0,\n-\tFN_SEL_SSP1_1_1,\n-\tFN_SEL_SSP1_1_2,\n-\tFN_SEL_SSP1_1_3,\n-\tFN_SEL_SSP1_0_0,\n-\tFN_SEL_SSP1_0_1,\n-\tFN_SEL_SSP1_0_2,\n-\tFN_SEL_SSP1_0_3,\n-\tFN_SEL_SSP1_0_4,\n-\tFN_SEL_SSI_0,\n-\tFN_SEL_SSI_1,\n-\tFN_SEL_SPEED_PULSE_IF_0,\n-\tFN_SEL_SPEED_PULSE_IF_1,\n-\tFN_SEL_SIMCARD_0,\n-\tFN_SEL_SIMCARD_1,\n-\tFN_SEL_SIMCARD_2,\n-\tFN_SEL_SIMCARD_3,\n-\tFN_SEL_SDHI2_0,\n-\tFN_SEL_SDHI2_1,\n-\tFN_SEL_SCIF4_0,\n-\tFN_SEL_SCIF4_1,\n-\tFN_SEL_SCIF4_2,\n-\tFN_SEL_SCIF3_0,\n-\tFN_SEL_SCIF3_1,\n-\tFN_SEL_SCIF2_0,\n-\tFN_SEL_SCIF2_1,\n-\tFN_SEL_SCIF1_0,\n-\tFN_SEL_SCIF1_1,\n-\tFN_SEL_SCIF_0,\n-\tFN_SEL_SCIF_1,\n-\tFN_SEL_REMOCON_0,\n-\tFN_SEL_REMOCON_1,\n-\tFN_SEL_RCAN_0,\n-\tFN_SEL_RCAN_1,\n-\tFN_SEL_PWM6_0,\n-\tFN_SEL_PWM6_1,\n-\tFN_SEL_PWM5_0,\n-\tFN_SEL_PWM5_1,\n-\tFN_SEL_PWM4_0,\n-\tFN_SEL_PWM4_1,\n-\tFN_SEL_PWM3_0,\n-\tFN_SEL_PWM3_1,\n-\tFN_SEL_PWM2_0,\n-\tFN_SEL_PWM2_1,\n-\tFN_SEL_PWM1_0,\n-\tFN_SEL_PWM1_1,\n-\n-\t/* MOD_SEL2 */\n-\tFN_I2C_SEL_5_0,\n-\tFN_I2C_SEL_5_1,\n-\tFN_I2C_SEL_3_0,\n-\tFN_I2C_SEL_3_1,\n-\tFN_I2C_SEL_0_0,\n-\tFN_I2C_SEL_0_1,\n-\tFN_SEL_FM_0,\n-\tFN_SEL_FM_1,\n-\tFN_SEL_FM_2,\n-\tFN_SEL_FM_3,\n-\tFN_SEL_SCIF5_0,\n-\tFN_SEL_SCIF5_1,\n-\tFN_SEL_I2C6_0,\n-\tFN_SEL_I2C6_1,\n-\tFN_SEL_I2C6_2,\n-\tFN_SEL_NDF_0,\n-\tFN_SEL_NDF_1,\n-\tFN_SEL_SSI2_0,\n-\tFN_SEL_SSI2_1,\n-\tFN_SEL_SSI9_0,\n-\tFN_SEL_SSI9_1,\n-\tFN_SEL_TIMER_TMU2_0,\n-\tFN_SEL_TIMER_TMU2_1,\n-\tFN_SEL_ADG_B_0,\n-\tFN_SEL_ADG_B_1,\n-\tFN_SEL_ADG_C_0,\n-\tFN_SEL_ADG_C_1,\n-\tFN_SEL_VIN4_0,\n-\tFN_SEL_VIN4_1,\n-\n-\tPINMUX_FUNCTION_END,\n-\n-\tPINMUX_MARK_BEGIN,\n-\n-\t/* GPSR0 */\n-\tD15_GMARK,\n-\tD14_GMARK,\n-\tD13_GMARK,\n-\tD12_GMARK,\n-\tD11_GMARK,\n-\tD10_GMARK,\n-\tD9_GMARK,\n-\tD8_GMARK,\n-\tD7_GMARK,\n-\tD6_GMARK,\n-\tD5_GMARK,\n-\tD4_GMARK,\n-\tD3_GMARK,\n-\tD2_GMARK,\n-\tD1_GMARK,\n-\tD0_GMARK,\n-\n-\t/* GPSR1 */\n-\tCLKOUT_GMARK,\n-\tEX_WAIT0_A_GMARK,\n-\tWE1x_GMARK,\n-\tWE0x_GMARK,\n-\tRD_WRx_GMARK,\n-\tRDx_GMARK,\n-\tBSx_GMARK,\n-\tCS1x_A26_GMARK,\n-\tCS0x_GMARK,\n-\tA19_GMARK,\n-\tA18_GMARK,\n-\tA17_GMARK,\n-\tA16_GMARK,\n-\tA15_GMARK,\n-\tA14_GMARK,\n-\tA13_GMARK,\n-\tA12_GMARK,\n-\tA11_GMARK,\n-\tA10_GMARK,\n-\tA9_GMARK,\n-\tA8_GMARK,\n-\tA7_GMARK,\n-\tA6_GMARK,\n-\tA5_GMARK,\n-\tA4_GMARK,\n-\tA3_GMARK,\n-\tA2_GMARK,\n-\tA1_GMARK,\n-\tA0_GMARK,\n-\n-\t/* GPSR2 */\n-\tAVB_AVTP_CAPTURE_A_GMARK,\n-\tAVB_AVTP_MATCH_A_GMARK,\n-\tAVB_LINK_GMARK,\n-\tAVB_PHY_INT_GMARK,\n-\tAVB_MAGIC_GMARK,\n-\tAVB_MDC_GMARK,\n-\tPWM2_A_GMARK,\n-\tPWM1_A_GMARK,\n-\tPWM0_GMARK,\n-\tIRQ5_GMARK,\n-\tIRQ4_GMARK,\n-\tIRQ3_GMARK,\n-\tIRQ2_GMARK,\n-\tIRQ1_GMARK,\n-\tIRQ0_GMARK,\n-\n-\t/* GPSR3 */\n-\tSD1_WP_GMARK,\n-\tSD1_CD_GMARK,\n-\tSD0_WP_GMARK,\n-\tSD0_CD_GMARK,\n-\tSD1_DAT3_GMARK,\n-\tSD1_DAT2_GMARK,\n-\tSD1_DAT1_GMARK,\n-\tSD1_DAT0_GMARK,\n-\tSD1_CMD_GMARK,\n-\tSD1_CLK_GMARK,\n-\tSD0_DAT3_GMARK,\n-\tSD0_DAT2_GMARK,\n-\tSD0_DAT1_GMARK,\n-\tSD0_DAT0_GMARK,\n-\tSD0_CMD_GMARK,\n-\tSD0_CLK_GMARK,\n-\n-\t/* GPSR4 */\n-\tSD3_DS_GMARK,\n-\tSD3_DAT7_GMARK,\n-\tSD3_DAT6_GMARK,\n-\tSD3_DAT5_GMARK,\n-\tSD3_DAT4_GMARK,\n-\tSD3_DAT3_MARK,\n-\tSD3_DAT2_MARK,\n-\tSD3_DAT1_MARK,\n-\tSD3_DAT0_MARK,\n-\tSD3_CMD_MARK,\n-\tSD3_CLK_MARK,\n-\tSD2_DS_GMARK,\n-\tSD2_DAT3_GMARK,\n-\tSD2_DAT2_GMARK,\n-\tSD2_DAT1_GMARK,\n-\tSD2_DAT0_GMARK,\n-\tSD2_CMD_MARK,\n-\tSD2_CLK_GMARK,\n-\n-\t/* GPSR5 */\n-\tMLB_DAT_GMARK,\n-\tMLB_SIG_GMARK,\n-\tMLB_CLK_GMARK,\n-\tMSIOF0_RXD_MARK,\n-\tMSIOF0_SS2_GMARK,\n-\tMSIOF0_TXD_MARK,\n-\tMSIOF0_SS1_GMARK,\n-\tMSIOF0_SYNC_GMARK,\n-\tMSIOF0_SCK_MARK,\n-\tHRTS0x_GMARK,\n-\tHCTS0x_GMARK,\n-\tHTX0_GMARK,\n-\tHRX0_GMARK,\n-\tHSCK0_GMARK,\n-\tRX2_A_GMARK,\n-\tTX2_A_GMARK,\n-\tSCK2_GMARK,\n-\tRTS1x_TANS_GMARK,\n-\tCTS1x_GMARK,\n-\tTX1_A_GMARK,\n-\tRX1_A_GMARK,\n-\tRTS0x_TANS_GMARK,\n-\tCTS0x_GMARK,\n-\tTX0_GMARK,\n-\tRX0_GMARK,\n-\tSCK0_GMARK,\n-\n-\t/* GPSR6 */\n-\tGP6_30_GMARK,\n-\tGP6_31_GMARK,\n-\tUSB30_OVC_GMARK,\n-\tUSB30_PWEN_GMARK,\n-\tUSB1_OVC_GMARK,\n-\tUSB1_PWEN_GMARK,\n-\tUSB0_OVC_GMARK,\n-\tUSB0_PWEN_GMARK,\n-\tAUDIO_CLKB_B_GMARK,\n-\tAUDIO_CLKA_A_GMARK,\n-\tSSI_SDATA9_A_GMARK,\n-\tSSI_SDATA8_GMARK,\n-\tSSI_SDATA7_GMARK,\n-\tSSI_WS78_GMARK,\n-\tSSI_SCK78_GMARK,\n-\tSSI_SDATA6_GMARK,\n-\tSSI_WS6_GMARK,\n-\tSSI_SCK6_GMARK,\n-\tSSI_SDATA5_MARK,\n-\tSSI_WS5_MARK,\n-\tSSI_SCK5_MARK,\n-\tSSI_SDATA4_GMARK,\n-\tSSI_WS4_GMARK,\n-\tSSI_SCK4_GMARK,\n-\tSSI_SDATA3_GMARK,\n-\tSSI_WS34_GMARK,\n-\tSSI_SCK34_GMARK,\n-\tSSI_SDATA2_A_GMARK,\n-\tSSI_SDATA1_A_GMARK,\n-\tSSI_SDATA0_GMARK,\n-\tSSI_WS01239_GMARK,\n-\tSSI_SCK01239_GMARK,\n-\n-\t/* GPSR7 */\n-\tHDMI1_CEC_MARK,\n-\tHDMI0_CEC_MARK,\n-\tAVS2_MARK,\n-\tAVS1_MARK,\n-\n-\t/* IPSR0 */\n-\tAVB_MDC_IMARK,\n-\tMSIOF2_SS2_C_MARK,\n-\tAVB_MAGIC_IMARK,\n-\tMSIOF2_SS1_C_MARK,\n-\tSCK4_A_MARK,\n-\tAVB_PHY_INT_IMARK,\n-\tMSIOF2_SYNC_C_MARK,\n-\tRX4_A_MARK,\n-\tAVB_LINK_IMARK,\n-\tMSIOF2_SCK_C_MARK,\n-\tTX4_A_MARK,\n-\tAVB_AVTP_MATCH_A_IMARK,\n-\tMSIOF2_RXD_C_MARK,\n-\tCTS4x_A_MARK,\n-\tAVB_AVTP_CAPTURE_A_IMARK,\n-\tMSIOF2_TXD_C_MARK,\n-\tRTS4x_TANS_A_MARK,\n-\tIRQ0_IMARK,\n-\tQPOLB_MARK,\n-\tDU_CDE_MARK,\n-\tVI4_DATA0_B_MARK,\n-\tCAN0_TX_B_MARK,\n-\tCANFD0_TX_B_MARK,\n-\tMSIOF3_SS2_E_MARK,\n-\tIRQ1_IMARK,\n-\tQPOLA_MARK,\n-\tDU_DISP_MARK,\n-\tVI4_DATA1_B_MARK,\n-\tCAN0_RX_B_MARK,\n-\tCANFD0_RX_B_MARK,\n-\tMSIOF3_SS1_E_MARK,\n-\n-\t/* IPSR1 */\n-\tIRQ2_IMARK,\n-\tQCPV_QDE_MARK,\n-\tDU_EXODDF_DU_ODDF_DISP_CDE_MARK,\n-\tVI4_DATA2_B_MARK,\n-\tMSIOF3_SYNC_E_MARK,\n-\tPWM3_B_MARK,\n-\tIRQ3_IMARK,\n-\tQSTVB_QVE_MARK,\n-\tDU_DOTCLKOUT1_MARK,\n-\tVI4_DATA3_B_MARK,\n-\tMSIOF3_SCK_E_MARK,\n-\tPWM4_B_MARK,\n-\tIRQ4_IMARK,\n-\tQSTH_QHS_MARK,\n-\tDU_EXHSYNC_DU_HSYNC_MARK,\n-\tVI4_DATA4_B_MARK,\n-\tMSIOF3_RXD_E_MARK,\n-\tPWM5_B_MARK,\n-\tIRQ5_IMARK,\n-\tQSTB_QHE_MARK,\n-\tDU_EXVSYNC_DU_VSYNC_MARK,\n-\tVI4_DATA5_B_MARK,\n-\tMSIOF3_TXD_E_MARK,\n-\tPWM6_B_MARK,\n-\tPWM0_IMARK,\n-\tAVB_AVTP_PPS_MARK,\n-\tVI4_DATA6_B_MARK,\n-\tIECLK_B_MARK,\n-\tPWM1_A_IMARK,\n-\tHRX3_D_MARK,\n-\tVI4_DATA7_B_MARK,\n-\tIERX_B_MARK,\n-\tPWM2_A_IMARK,\n-\tPWMFSW0_MARK,\n-\tHTX3_D_MARK,\n-\tIETX_B_MARK,\n-\tA0_IMARK,\n-\tLCDOUT16_MARK,\n-\tMSIOF3_SYNC_B_MARK,\n-\tVI4_DATA8_MARK,\n-\tDU_DB0_MARK,\n-\tPWM3_A_MARK,\n-\n-\t/* IPSR2 */\n-\tA1_IMARK,\n-\tLCDOUT17_MARK,\n-\tMSIOF3_TXD_B_MARK,\n-\tVI4_DATA9_MARK,\n-\tDU_DB1_MARK,\n-\tPWM4_A_MARK,\n-\tA2_IMARK,\n-\tLCDOUT18_MARK,\n-\tMSIOF3_SCK_B_MARK,\n-\tVI4_DATA10_MARK,\n-\tDU_DB2_MARK,\n-\tPWM5_A_MARK,\n-\tA3_IMARK,\n-\tLCDOUT19_MARK,\n-\tMSIOF3_RXD_B_MARK,\n-\tVI4_DATA11_MARK,\n-\tDU_DB3_MARK,\n-\tPWM6_A_MARK,\n-\tA4_IMARK,\n-\tLCDOUT20_MARK,\n-\tMSIOF3_SS1_B_MARK,\n-\tVI4_DATA12_MARK,\n-\tVI5_DATA12_MARK,\n-\tDU_DB4_MARK,\n-\tA5_IMARK,\n-\tLCDOUT21_MARK,\n-\tMSIOF3_SS2_B_MARK,\n-\tSCK4_B_MARK,\n-\tVI4_DATA13_MARK,\n-\tVI5_DATA13_MARK,\n-\tDU_DB5_MARK,\n-\tA6_IMARK,\n-\tLCDOUT22_MARK,\n-\tMSIOF2_SS1_A_MARK,\n-\tRX4_B_MARK,\n-\tVI4_DATA14_MARK,\n-\tVI5_DATA14_MARK,\n-\tDU_DB6_MARK,\n-\tA7_IMARK,\n-\tLCDOUT23_MARK,\n-\tMSIOF2_SS2_A_MARK,\n-\tTX4_B_MARK,\n-\tVI4_DATA15_MARK,\n-\tV15_DATA15_MARK,\n-\tDU_DB7_MARK,\n-\tA8_IMARK,\n-\tRX3_B_MARK,\n-\tMSIOF2_SYNC_A_MARK,\n-\tHRX4_B_MARK,\n-\tSDA6_A_MARK,\n-\tAVB_AVTP_MATCH_B_MARK,\n-\tPWM1_B_MARK,\n-\n-\t/* IPSR3 */\n-\tA9_IMARK,\n-\tMSIOF2_SCK_A_MARK,\n-\tCTS4x_B_MARK,\n-\tVI5_VSYNCx_MARK,\n-\tA10_IMARK,\n-\tMSIOF2_RXD_A_MARK,\n-\tRTS4n_TANS_B_MARK,\n-\tVI5_HSYNCx_MARK,\n-\tA11_IMARK,\n-\tTX3_B_MARK,\n-\tMSIOF2_TXD_A_MARK,\n-\tHTX4_B_MARK,\n-\tHSCK4_MARK,\n-\tVI5_FIELD_MARK,\n-\tSCL6_A_MARK,\n-\tAVB_AVTP_CAPTURE_B_MARK,\n-\tPWM2_B_MARK,\n-\tSPV_EVEN_MARK,\n-\tA12_IMARK,\n-\tLCDOUT12_MARK,\n-\tMSIOF3_SCK_C_MARK,\n-\tHRX4_A_MARK,\n-\tVI5_DATA8_MARK,\n-\tDU_DG4_MARK,\n-\tA13_IMARK,\n-\tLCDOUT13_MARK,\n-\tMSIOF3_SYNC_C_MARK,\n-\tHTX4_A_MARK,\n-\tVI5_DATA9_MARK,\n-\tDU_DG5_MARK,\n-\tA14_IMARK,\n-\tLCDOUT14_MARK,\n-\tMSIOF3_RXD_C_MARK,\n-\tHCTS4x_MARK,\n-\tVI5_DATA10_MARK,\n-\tDU_DG6_MARK,\n-\tA15_IMARK,\n-\tLCDOUT15_MARK,\n-\tMSIOF3_TXD_C_MARK,\n-\tHRTS4x_MARK,\n-\tVI5_DATA11_MARK,\n-\tDU_DG7_MARK,\n-\tA16_IMARK,\n-\tLCDOUT8_MARK,\n-\tVI4_FIELD_MARK,\n-\tDU_DG0_MARK,\n-\n-\t/* IPSR4 */\n-\tA17_IMARK,\n-\tLCDOUT9_MARK,\n-\tVI4_VSYNCx_MARK,\n-\tDU_DG1_MARK,\n-\tA18_IMARK,\n-\tLCDOUT10_MARK,\n-\tVI4_HSYNCx_MARK,\n-\tDU_DG2_MARK,\n-\tA19_IMARK,\n-\tLCDOUT11_MARK,\n-\tVI4_CLKENB_MARK,\n-\tDU_DG3_MARK,\n-\tCS0x_IMARK,\n-\tVI5_CLKENB_MARK,\n-\tCS1x_A26_IMARK,\n-\tVI5_CLK_MARK,\n-\tEX_WAIT0_B_MARK,\n-\tBSx_IMARK,\n-\tQSTVA_QVS_MARK,\n-\tMSIOF3_SCK_D_MARK,\n-\tSCK3_MARK,\n-\tHSCK3_MARK,\n-\tCAN1_TX_MARK,\n-\tCANFD1_TX_MARK,\n-\tIETX_A_MARK,\n-\tRDx_IMARK,\n-\tMSIOF3_SYNC_D_MARK,\n-\tRX3_A_MARK,\n-\tHRX3_A_MARK,\n-\tCAN0_TX_A_MARK,\n-\tCANFD0_TX_A_MARK,\n-\tRD_WRx_IMARK,\n-\tMSIOF3_RXD_D_MARK,\n-\tTX3_A_MARK,\n-\tHTX3_A_MARK,\n-\tCAN0_RX_A_MARK,\n-\tCANFD0_RX_A_MARK,\n-\n-\t/* IPSR5 */\n-\tWE0x_IMARK,\n-\tMSIIOF3_TXD_D_MARK,\n-\tCTS3x_MARK,\n-\tHCTS3x_MARK,\n-\tSCL6_B_MARK,\n-\tCAN_CLK_MARK,\n-\tIECLK_A_MARK,\n-\tWE1x_IMARK,\n-\tMSIOF3_SS1_D_MARK,\n-\tRTS3x_TANS_MARK,\n-\tHRTS3x_MARK,\n-\tSDA6_B_MARK,\n-\tCAN1_RX_MARK,\n-\tCANFD1_RX_MARK,\n-\tIERX_A_MARK,\n-\tEX_WAIT0_A_IMARK,\n-\tQCLK_MARK,\n-\tVI4_CLK_MARK,\n-\tDU_DOTCLKOUT0_MARK,\n-\tD0_IMARK,\n-\tMSIOF2_SS1_B_MARK,\n-\tMSIOF3_SCK_A_MARK,\n-\tVI4_DATA16_MARK,\n-\tVI5_DATA0_MARK,\n-\tD1_IMARK,\n-\tMSIOF2_SS2_B_MARK,\n-\tMSIOF3_SYNC_A_MARK,\n-\tVI4_DATA17_MARK,\n-\tVI5_DATA1_MARK,\n-\tD2_IMARK,\n-\tMSIOF3_RXD_A_MARK,\n-\tVI4_DATA18_MARK,\n-\tVI5_DATA2_MARK,\n-\tD3_IMARK,\n-\tMSIOF3_TXD_A_MARK,\n-\tVI4_DATA19_MARK,\n-\tVI5_DATA3_MARK,\n-\tD4_IMARK,\n-\tMSIOF2_SCK_B_MARK,\n-\tVI4_DATA20_MARK,\n-\tVI5_DATA4_MARK,\n-\n-\t/* IPSR6 */\n-\tD5_IMARK,\n-\tMSIOF2_SYNC_B_MARK,\n-\tVI4_DATA21_MARK,\n-\tVI5_DATA5_MARK,\n-\tD6_IMARK,\n-\tMSIOF2_RXD_B_MARK,\n-\tVI4_DATA22_MARK,\n-\tVI5_DATA6_MARK,\n-\tD7_IMARK,\n-\tMSIOF2_TXD_B_MARK,\n-\tVI4_DATA23_MARK,\n-\tVI5_DATA7_MARK,\n-\tD8_IMARK,\n-\tLCDOUT0_MARK,\n-\tMSIOF2_SCK_D_MARK,\n-\tSCK4_C_MARK,\n-\tVI4_DATA0_A_MARK,\n-\tDU_DR0_MARK,\n-\tD9_IMARK,\n-\tLCDOUT1_MARK,\n-\tMSIOF2_SYNC_D_MARK,\n-\tVI4_DATA1_A_MARK,\n-\tDU_DR1_MARK,\n-\tD10_IMARK,\n-\tLCDOUT2_MARK,\n-\tMSIOF2_RXD_D_MARK,\n-\tHRX3_B_MARK,\n-\tVI4_DATA2_A_MARK,\n-\tCTS4x_C_MARK,\n-\tDU_DR2_MARK,\n-\tD11_IMARK,\n-\tLCDOUT3_MARK,\n-\tMSIOF2_TXD_D_MARK,\n-\tHTX3_B_MARK,\n-\tVI4_DATA3_A_MARK,\n-\tRTS4x_TANS_C_MARK,\n-\tDU_DR3_MARK,\n-\tD12_IMARK,\n-\tLCDOUT4_MARK,\n-\tMSIOF2_SS1_D_MARK,\n-\tRX4_C_MARK,\n-\tVI4_DATA4_A_MARK,\n-\tDU_DR4_MARK,\n-\n-\t/* IPSR7 */\n-\tD13_IMARK,\n-\tLCDOUT5_MARK,\n-\tMSIOF2_SS2_D_MARK,\n-\tTX4_C_MARK,\n-\tVI4_DATA5_A_MARK,\n-\tDU_DR5_MARK,\n-\tD14_IMARK,\n-\tLCDOUT6_MARK,\n-\tMSIOF3_SS1_A_MARK,\n-\tHRX3_C_MARK,\n-\tVI4_DATA6_A_MARK,\n-\tDU_DR6_MARK,\n-\tSCL6_C_MARK,\n-\tD15_IMARK,\n-\tLCDOUT7_MARK,\n-\tMSIOF3_SS2_A_MARK,\n-\tHTX3_C_MARK,\n-\tVI4_DATA7_A_MARK,\n-\tDU_DR7_MARK,\n-\tSDA6_C_MARK,\n-\tFSCLKST_MARK,\n-\tSD0_CLK_IMARK,\n-\tMSIOF1_SCK_E_MARK,\n-\tSTP_OPWM_0_B_MARK,\n-\tSD0_CMD_IMARK,\n-\tMSIOF1_SYNC_E_MARK,\n-\tSTP_IVCXO27_0_B_MARK,\n-\tSD0_DAT0_IMARK,\n-\tMSIOF1_RXD_E_MARK,\n-\tTS_SCK0_B_MARK,\n-\tSTP_ISCLK_0_B_MARK,\n-\tSD0_DAT1_IMARK,\n-\tMSIOF1_TXD_E_MARK,\n-\tTS_SPSYNC0_B_MARK,\n-\tSTP_ISSYNC_0_B_MARK,\n-\n-\t/* IPSR8 */\n-\tSD0_DAT2_IMARK,\n-\tMSIOF1_SS1_E_MARK,\n-\tTS_SDAT0_B_MARK,\n-\tSTP_ISD_0_B_MARK,\n-\n-\tSD0_DAT3_IMARK,\n-\tMSIOF1_SS2_E_MARK,\n-\tTS_SDEN0_B_MARK,\n-\tSTP_ISEN_0_B_MARK,\n-\n-\tSD1_CLK_IMARK,\n-\tMSIOF1_SCK_G_MARK,\n-\tSIM0_CLK_A_MARK,\n-\n-\tSD1_CMD_IMARK,\n-\tMSIOF1_SYNC_G_MARK,\n-\tNFCEx_B_MARK,\n-\tSIM0_D_A_MARK,\n-\tSTP_IVCXO27_1_B_MARK,\n-\n-\tSD1_DAT0_IMARK,\n-\tSD2_DAT4_MARK,\n-\tMSIOF1_RXD_G_MARK,\n-\tNFWPx_B_MARK,\n-\tTS_SCK1_B_MARK,\n-\tSTP_ISCLK_1_B_MARK,\n-\n-\tSD1_DAT1_IMARK,\n-\tSD2_DAT5_MARK,\n-\tMSIOF1_TXD_G_MARK,\n-\tNFDATA14_B_MARK,\n-\tTS_SPSYNC1_B_MARK,\n-\tSTP_ISSYNC_1_B_MARK,\n-\n-\tSD1_DAT2_IMARK,\n-\tSD2_DAT6_MARK,\n-\tMSIOF1_SS1_G_MARK,\n-\tNFDATA15_B_MARK,\n-\tTS_SDAT1_B_MARK,\n-\tSTP_IOD_1_B_MARK,\n-\n-\tSD1_DAT3_IMARK,\n-\tSD2_DAT7_MARK,\n-\tMSIOF1_SS2_G_MARK,\n-\tNFRBx_B_MARK,\n-\tTS_SDEN1_B_MARK,\n-\tSTP_ISEN_1_B_MARK,\n-\n-\t/* IPSR9 */\n-\tSD2_CLK_IMARK,\n-\tNFDATA8_MARK,\n-\n-\tSD2_CMD_IMARK,\n-\tNFDATA9_MARK,\n-\n-\tSD2_DAT0_IMARK,\n-\tNFDATA10_MARK,\n-\n-\tSD2_DAT1_IMARK,\n-\tNFDATA11_MARK,\n-\n-\tSD2_DAT2_IMARK,\n-\tNFDATA12_MARK,\n-\n-\tSD2_DAT3_IMARK,\n-\tNFDATA13_MARK,\n-\n-\tSD2_DS_IMARK,\n-\tNFALE_MARK,\n-\n-\tSD3_CLK_IMARK,\n-\tNFWEx_MARK,\n-\n-\t/* IPSR10 */\n-\tSD3_CMD_IMARK,\n-\tNFREx_MARK,\n-\n-\tSD3_DAT0_IMARK,\n-\tNFDATA0_MARK,\n-\n-\tSD3_DAT1_IMARK,\n-\tNFDATA1_MARK,\n-\n-\tSD3_DAT2_IMARK,\n-\tNFDATA2_MARK,\n-\n-\tSD3_DAT3_IMARK,\n-\tNFDATA3_MARK,\n-\n-\tSD3_DAT4_IMARK,\n-\tSD2_CD_A_MARK,\n-\tNFDATA4_MARK,\n-\n-\tSD3_DAT5_IMARK,\n-\tSD2_WP_A_MARK,\n-\tNFDATA5_MARK,\n-\n-\tSD3_DAT6_IMARK,\n-\tSD3_CD_MARK,\n-\tNFDATA6_MARK,\n-\n-\t/* IPSR11 */\n-\tSD3_DAT7_IMARK,\n-\tSD3_WP_MARK,\n-\tNFDATA7_MARK,\n-\n-\tSD3_DS_IMARK,\n-\tNFCLE_MARK,\n-\n-\tSD0_CD_IMARK,\n-\tNFDATA14_A_MARK,\n-\tSCL2_B_MARK,\n-\tSIM0_RST_A_MARK,\n-\n-\tSD0_WP_IMARK,\n-\tNFDATA15_A_MARK,\n-\tSDA2_B_MARK,\n-\n-\tSD1_CD_IMARK,\n-\tNFRBx_A_MARK,\n-\tSIM0_CLK_B_MARK,\n-\n-\tSD1_WP_IMARK,\n-\tNFCEx_A_MARK,\n-\tSIM0_D_B_MARK,\n-\n-\tSCK0_IMARK,\n-\tHSCK1_B_MARK,\n-\tMSIOF1_SS2_B_MARK,\n-\tAUDIO_CLKC_B_MARK,\n-\tSDA2_A_MARK,\n-\tSIM0_RST_B_MARK,\n-\tSTP_OPWM_0_C_MARK,\n-\tRIF0_CLK_B_MARK,\n-\tADICHS2_MARK,\n-\tSCK5_B_MARK,\n-\n-\tRX0_IMARK,\n-\tHRX1_B_MARK,\n-\tTS_SCK0_C_MARK,\n-\tSTP_ISCLK_0_C_MARK,\n-\tRIF0_D0_B_MARK,\n-\n-\t/* IPSR12 */\n-\tTX0_IMARK,\n-\tHTX1_B_MARK,\n-\tTS_SPSYNC0_C_MARK,\n-\tSTP_ISSYNC_0_C_MARK,\n-\tRIF0_D1_B_MARK,\n-\n-\tCTS0x_IMARK,\n-\tHCTS1x_B_MARK,\n-\tMSIOF1_SYNC_B_MARK,\n-\tTS_SPSYNC1_C_MARK,\n-\tSTP_ISSYNC_1_C_MARK,\n-\tRIF1_SYNC_B_MARK,\n-\tAUDIO_CLKOUT_C_MARK,\n-\tADICS_SAMP_MARK,\n-\n-\tRTS0x_TANS_IMARK,\n-\tHRTS1x_B_MARK,\n-\tMSIOF1_SS1_B_MARK,\n-\tAUDIO_CLKA_B_MARK,\n-\tSCL2_A_MARK,\n-\tSTP_IVCXO27_1_C_MARK,\n-\tRIF0_SYNC_B_MARK,\n-\tADICHS1_MARK,\n-\n-\tRX1_A_IMARK,\n-\tHRX1_A_MARK,\n-\tTS_SDAT0_C_MARK,\n-\tSTP_ISD_0_C_MARK,\n-\tRIF1_CLK_C_MARK,\n-\n-\tTX1_A_IMARK,\n-\tHTX1_A_MARK,\n-\tTS_SDEN0_C_MARK,\n-\tSTP_ISEN_0_C_MARK,\n-\tRIF1_D0_C_MARK,\n-\n-\tCTS1x_IMARK,\n-\tHCTS1x_A_MARK,\n-\tMSIOF1_RXD_B_MARK,\n-\tTS_SDEN1_C_MARK,\n-\tSTP_ISEN_1_C_MARK,\n-\tRIF1_D0_B_MARK,\n-\tADIDATA_MARK,\n-\n-\tRTS1x_TANS_IMARK,\n-\tHRTS1x_A_MARK,\n-\tMSIOF1_TXD_B_MARK,\n-\tTS_SDAT1_C_MARK,\n-\tSTP_ISD_1_C_MARK,\n-\tRIF1_D1_B_MARK,\n-\tADICHS0_MARK,\n-\n-\tSCK2_IMARK,\n-\tSCIF_CLK_B_MARK,\n-\tMSIOF1_SCK_B_MARK,\n-\tTS_SCK1_C_MARK,\n-\tSTP_ISCLK_1_C_MARK,\n-\tRIF1_CLK_B_MARK,\n-\tADICLK_MARK,\n-\n-\t/* IPSR13 */\n-\tTX2_A_IMARK,\n-\tSD2_CD_B_MARK,\n-\tSCL1_A_MARK,\n-\tFMCLK_A_MARK,\n-\tRIF1_D1_C_MARK,\n-\tFSO_CFE_0_B_MARK,\n-\n-\tRX2_A_IMARK,\n-\tSD2_WP_B_MARK,\n-\tSDA1_A_MARK,\n-\tFMIN_A_MARK,\n-\tRIF1_SYNC_C_MARK,\n-\tFSO_CEF_1_B_MARK,\n-\n-\tHSCK0_IMARK,\n-\tMSIOF1_SCK_D_MARK,\n-\tAUDIO_CLKB_A_MARK,\n-\tSSI_SDATA1_B_MARK,\n-\tTS_SCK0_D_MARK,\n-\tSTP_ISCLK_0_D_MARK,\n-\tRIF0_CLK_C_MARK,\n-\tRX5_B_MARK,\n-\n-\tHRX0_IMARK,\n-\tMSIOF1_RXD_D_MARK,\n-\tSS1_SDATA2_B_MARK,\n-\tTS_SDEN0_D_MARK,\n-\tSTP_ISEN_0_D_MARK,\n-\tRIF0_D0_C_MARK,\n-\n-\tHTX0_IMARK,\n-\tMSIOF1_TXD_D_MARK,\n-\tSSI_SDATA9_B_MARK,\n-\tTS_SDAT0_D_MARK,\n-\tSTP_ISD_0_D_MARK,\n-\tRIF0_D1_C_MARK,\n-\n-\tHCTS0x_IMARK,\n-\tRX2_B_MARK,\n-\tMSIOF1_SYNC_D_MARK,\n-\tSSI_SCK9_A_MARK,\n-\tTS_SPSYNC0_D_MARK,\n-\tSTP_ISSYNC_0_D_MARK,\n-\tRIF0_SYNC_C_MARK,\n-\tAUDIO_CLKOUT1_A_MARK,\n-\n-\tHRTS0x_IMARK,\n-\tTX2_B_MARK,\n-\tMSIOF1_SS1_D_MARK,\n-\tSSI_WS9_A_MARK,\n-\tSTP_IVCXO27_0_D_MARK,\n-\tBPFCLK_A_MARK,\n-\tAUDIO_CLKOUT2_A_MARK,\n-\n-\tMSIOF0_SYNC_IMARK,\n-\tAUDIO_CLKOUT_A_MARK,\n-\tTX5_B_MARK,\n-\tBPFCLK_D_MARK,\n-\n-\t/* IPSR14 */\n-\tMSIOF0_SS1_IMARK,\n-\tRX5_A_MARK,\n-\tNFWPx_A_MARK,\n-\tAUDIO_CLKA_C_MARK,\n-\tSSI_SCK2_A_MARK,\n-\tSTP_IVCXO27_0_C_MARK,\n-\tAUDIO_CLKOUT3_A_MARK,\n-\tTCLK1_B_MARK,\n-\n-\tMSIOF0_SS2_IMARK,\n-\tTX5_A_MARK,\n-\tMSIOF1_SS2_D_MARK,\n-\tAUDIO_CLKC_A_MARK,\n-\tSSI_WS2_A_MARK,\n-\tSTP_OPWM_0_D_MARK,\n-\tAUDIO_CLKOUT_D_MARK,\n-\tSPEEDIN_B_MARK,\n-\n-\tMLB_CLK_IMARK,\n-\tMSIOF1_SCK_F_MARK,\n-\tSCL1_B_MARK,\n-\n-\tMLB_SIG_IMARK,\n-\tRX1_B_MARK,\n-\tMSIOF1_SYNC_F_MARK,\n-\tSDA1_B_MARK,\n-\n-\tMLB_DAT_IMARK,\n-\tTX1_B_MARK,\n-\tMSIOF1_RXD_F_MARK,\n-\n-\tSSI_SCK0129_IMARK,\n-\tMSIOF1_TXD_F_MARK,\n-\tMOUT0_MARK,\n-\n-\tSSI_WS0129_IMARK,\n-\tMSIOF1_SS1_F_MARK,\n-\tMOUT1_MARK,\n-\n-\tSSI_SDATA0_IMARK,\n-\tMSIOF1_SS2_F_MARK,\n-\tMOUT2_MARK,\n-\n-\t/* IPSR15 */\n-\tSSI_SDATA1_A_IMARK,\n-\tMOUT5_MARK,\n-\n-\tSSI_SDATA2_A_IMARK,\n-\tSSI_SCK1_B_MARK,\n-\tMOUT6_MARK,\n-\n-\tSSI_SCK34_IMARK,\n-\tMSIOF1_SS1_A_MARK,\n-\tSTP_OPWM_0_A_MARK,\n-\n-\tSSI_WS34_IMARK,\n-\tHCTS2x_A_MARK,\n-\tMSIOF1_SS2_A_MARK,\n-\tSTP_IVCXO27_0_A_MARK,\n-\n-\tSSI_SDATA3_IMARK,\n-\tHRTS2x_A_MARK,\n-\tMSIOF1_TXD_A_MARK,\n-\tTS_SCK0_A_MARK,\n-\tSTP_ISCLK_0_A_MARK,\n-\tRIF0_D1_A_MARK,\n-\tRIF2_D0_A_MARK,\n-\n-\tSSI_SCK4_IMARK,\n-\tHRX2_A_MARK,\n-\tMSIOF1_SCK_A_MARK,\n-\tTS_SDAT0_A_MARK,\n-\tSTP_ISD_0_A_MARK,\n-\tRIF0_CLK_A_MARK,\n-\tRIF2_CLK_A_MARK,\n-\n-\tSSI_WS4_IMARK,\n-\tHTX2_A_MARK,\n-\tMSIOF1_SYNC_A_MARK,\n-\tTS_SDEN0_A_MARK,\n-\tSTP_ISEN_0_A_MARK,\n-\tRIF0_SYNC_A_MARK,\n-\tRIF2_SYNC_A_MARK,\n-\n-\tSSI_SDATA4_IMARK,\n-\tHSCK2_A_MARK,\n-\tMSIOF1_RXD_A_MARK,\n-\tTS_SPSYNC0_A_MARK,\n-\tSTP_ISSYNC_0_A_MARK,\n-\tRIF0_D0_A_MARK,\n-\tRIF2_D1_A_MARK,\n-\n-\t/* IPSR16 */\n-\tSSI_SCK6_IMARK,\n-\tSIM0_RST_D_MARK,\n-\tFSO_TOE_A_MARK,\n-\n-\tSSI_WS6_IMARK,\n-\tSIM0_D_D_MARK,\n-\n-\tSSI_SDATA6_IMARK,\n-\tSIM0_CLK_D_MARK,\n-\n-\tSSI_SCK78_IMARK,\n-\tHRX2_B_MARK,\n-\tMSIOF1_SCK_C_MARK,\n-\tTS_SCK1_A_MARK,\n-\tSTP_ISCLK_1_A_MARK,\n-\tRIF1_CLK_A_MARK,\n-\tRIF3_CLK_A_MARK,\n-\n-\tSSI_WS78_IMARK,\n-\tHTX2_B_MARK,\n-\tMSIOF1_SYNC_C_MARK,\n-\tTS_SDAT1_A_MARK,\n-\tSTP_ISD_1_A_MARK,\n-\tRIF1_SYNC_A_MARK,\n-\tRIF3_SYNC_A_MARK,\n-\n-\tSSI_SDATA7_IMARK,\n-\tHCTS2x_B_MARK,\n-\tMSIOF1_RXD_C_MARK,\n-\tTS_SDEN1_A_MARK,\n-\tSTP_IEN_1_A_MARK,\n-\tRIF1_D0_A_MARK,\n-\tRIF3_D0_A_MARK,\n-\tTCLK2_A_MARK,\n-\n-\tSSI_SDATA8_IMARK,\n-\tHRTS2x_B_MARK,\n-\tMSIOF1_TXD_C_MARK,\n-\tTS_SPSYNC1_A_MARK,\n-\tSTP_ISSYNC_1_A_MARK,\n-\tRIF1_D1_A_MARK,\n-\tEIF3_D1_A_MARK,\n-\n-\tSSI_SDATA9_A_IMARK,\n-\tHSCK2_B_MARK,\n-\tMSIOF1_SS1_C_MARK,\n-\tHSCK1_A_MARK,\n-\tSSI_WS1_B_MARK,\n-\tSCK1_MARK,\n-\tSTP_IVCXO27_1_A_MARK,\n-\tSCK5_MARK,\n-\n-\t/* IPSR17 */\n-\tAUDIO_CLKA_A_IMARK,\n-\tCC5_OSCOUT_MARK,\n-\n-\tAUDIO_CLKB_B_IMARK,\n-\tSCIF_CLK_A_MARK,\n-\tSTP_IVCXO27_1_D_MARK,\n-\tREMOCON_A_MARK,\n-\tTCLK1_A_MARK,\n-\n-\tUSB0_PWEN_IMARK,\n-\tSIM0_RST_C_MARK,\n-\tTS_SCK1_D_MARK,\n-\tSTP_ISCLK_1_D_MARK,\n-\tBPFCLK_B_MARK,\n-\tRIF3_CLK_B_MARK,\n-\tFSO_CFE_1_A_MARK,\n-\tHSCK2_C_MARK,\n-\n-\tUSB0_OVC_IMARK,\n-\tSIM0_D_C_MARK,\n-\tTS_SDAT1_D_MARK,\n-\tSTP_ISD_1_D_MARK,\n-\tRIF3_SYNC_B_MARK,\n-\tHRX2_C_MARK,\n-\n-\tUSB1_PWEN_IMARK,\n-\tSIM0_CLK_C_MARK,\n-\tSSI_SCK1_A_MARK,\n-\tTS_SCK0_E_MARK,\n-\tSTP_ISCLK_0_E_MARK,\n-\tFMCLK_B_MARK,\n-\tRIF2_CLK_B_MARK,\n-\tSPEEDIN_A_MARK,\n-\tHTX2_C_MARK,\n-\n-\tUSB1_OVC_IMARK,\n-\tMSIOF1_SS2_C_MARK,\n-\tSSI_WS1_A_MARK,\n-\tTS_SDAT0_E_MARK,\n-\tSTP_ISD_0_E_MARK,\n-\tFMIN_B_MARK,\n-\tRIF2_SYNC_B_MARK,\n-\tREMOCON_B_MARK,\n-\tHCTS2x_C_MARK,\n-\n-\tUSB30_PWEN_IMARK,\n-\tAUDIO_CLKOUT_B_MARK,\n-\tSSI_SCK2_B_MARK,\n-\tTS_SDEN1_D_MARK,\n-\tSTP_ISEN_1_D_MARK,\n-\tSTP_OPWM_0_E_MARK,\n-\tRIF3_D0_B_MARK,\n-\tTCLK2_B_MARK,\n-\tTPU0TO0_MARK,\n-\tBPFCLK_C_MARK,\n-\tHRTS2x_C_MARK,\n-\n-\tUSB30_OVC_IMARK,\n-\tAUDIO_CLKOUT1_B_MARK,\n-\tSSI_WS2_B_MARK,\n-\tTS_SPSYNC1_D_MARK,\n-\tSTP_ISSYNC_1_D_MARK,\n-\tSTP_IVCXO27_0_E_MARK,\n-\tRIF3_D1_B_MARK,\n-\tFSO_TOE_B_MARK,\n-\tTPU0TO1_MARK,\n-\n-\t/* IPSR18 */\n-\tGP6_30_IMARK,\n-\tAUDIO_CLKOUT2_B_MARK,\n-\tSSI_SCK9_B_MARK,\n-\tTS_SDEN0_E_MARK,\n-\tSTP_ISEN_0_E_MARK,\n-\tRIF2_D0_B_MARK,\n-\tFSO_CFE_0_A_MARK,\n-\tTPU0TO2_MARK,\n-\tFMCLK_C_MARK,\n-\tFMCLK_D_MARK,\n-\n-\tGP6_31_IMARK,\n-\tAUDIO_CLKOUT3_B_MARK,\n-\tSSI_WS9_B_MARK,\n-\tTS_SPSYNC0_E_MARK,\n-\tSTP_ISSYNC_0_E_MARK,\n-\tRIF2_D1_B_MARK,\n-\tTPU0TO3_MARK,\n-\tFMIN_C_MARK,\n-\tFMIN_D_MARK,\n-\n-\tPINMUX_MARK_END,\n-};\n-\n-static pinmux_enum_t pinmux_data[] = {\n-\tPINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */\n-\n-\t/* GPSR0 */\n-\tPINMUX_DATA(D15_GMARK, GFN_D15),\n-\tPINMUX_DATA(D14_GMARK, GFN_D14),\n-\tPINMUX_DATA(D13_GMARK, GFN_D13),\n-\tPINMUX_DATA(D12_GMARK, GFN_D12),\n-\tPINMUX_DATA(D11_GMARK, GFN_D11),\n-\tPINMUX_DATA(D10_GMARK, GFN_D10),\n-\tPINMUX_DATA(D9_GMARK, GFN_D9),\n-\tPINMUX_DATA(D8_GMARK, GFN_D8),\n-\tPINMUX_DATA(D7_GMARK, GFN_D7),\n-\tPINMUX_DATA(D6_GMARK, GFN_D6),\n-\tPINMUX_DATA(D5_GMARK, GFN_D5),\n-\tPINMUX_DATA(D4_GMARK, GFN_D4),\n-\tPINMUX_DATA(D3_GMARK, GFN_D3),\n-\tPINMUX_DATA(D2_GMARK, GFN_D2),\n-\tPINMUX_DATA(D1_GMARK, GFN_D1),\n-\tPINMUX_DATA(D0_GMARK, GFN_D0),\n-\n-\t/* GPSR1 */\n-\tPINMUX_DATA(CLKOUT_GMARK, GFN_CLKOUT),\n-\tPINMUX_DATA(EX_WAIT0_A_GMARK, GFN_EX_WAIT0_A),\n-\tPINMUX_DATA(WE1x_GMARK, GFN_WE1x),\n-\tPINMUX_DATA(WE0x_GMARK, GFN_WE0x),\n-\tPINMUX_DATA(RD_WRx_GMARK, GFN_RD_WRx),\n-\tPINMUX_DATA(RDx_GMARK, GFN_RDx),\n-\tPINMUX_DATA(BSx_GMARK, GFN_BSx),\n-\tPINMUX_DATA(CS1x_A26_GMARK, GFN_CS1x_A26),\n-\tPINMUX_DATA(CS0x_GMARK, GFN_CS0x),\n-\tPINMUX_DATA(A19_GMARK, GFN_A19),\n-\tPINMUX_DATA(A18_GMARK, GFN_A18),\n-\tPINMUX_DATA(A17_GMARK, GFN_A17),\n-\tPINMUX_DATA(A16_GMARK, GFN_A16),\n-\tPINMUX_DATA(A15_GMARK, GFN_A15),\n-\tPINMUX_DATA(A14_GMARK, GFN_A14),\n-\tPINMUX_DATA(A13_GMARK, GFN_A13),\n-\tPINMUX_DATA(A12_GMARK, GFN_A12),\n-\tPINMUX_DATA(A11_GMARK, GFN_A11),\n-\tPINMUX_DATA(A10_GMARK, GFN_A10),\n-\tPINMUX_DATA(A9_GMARK, GFN_A9),\n-\tPINMUX_DATA(A8_GMARK, GFN_A8),\n-\tPINMUX_DATA(A7_GMARK, GFN_A7),\n-\tPINMUX_DATA(A6_GMARK, GFN_A6),\n-\tPINMUX_DATA(A5_GMARK, GFN_A5),\n-\tPINMUX_DATA(A4_GMARK, GFN_A4),\n-\tPINMUX_DATA(A3_GMARK, GFN_A3),\n-\tPINMUX_DATA(A2_GMARK, GFN_A2),\n-\tPINMUX_DATA(A1_GMARK, GFN_A1),\n-\tPINMUX_DATA(A0_GMARK, GFN_A0),\n-\n-\t/* GPSR2 */\n-\tPINMUX_DATA(AVB_AVTP_CAPTURE_A_GMARK, GFN_AVB_AVTP_CAPTURE_A),\n-\tPINMUX_DATA(AVB_AVTP_MATCH_A_GMARK, GFN_AVB_AVTP_MATCH_A),\n-\tPINMUX_DATA(AVB_LINK_GMARK, GFN_AVB_LINK),\n-\tPINMUX_DATA(AVB_PHY_INT_GMARK, GFN_AVB_PHY_INT),\n-\tPINMUX_DATA(AVB_MAGIC_GMARK, GFN_AVB_MAGIC),\n-\tPINMUX_DATA(AVB_MDC_GMARK, GFN_AVB_MDC),\n-\tPINMUX_DATA(PWM2_A_GMARK, GFN_PWM2_A),\n-\tPINMUX_DATA(PWM1_A_GMARK, GFN_PWM1_A),\n-\tPINMUX_DATA(PWM0_GMARK, GFN_PWM0),\n-\tPINMUX_DATA(IRQ5_GMARK, GFN_IRQ5),\n-\tPINMUX_DATA(IRQ4_GMARK, GFN_IRQ4),\n-\tPINMUX_DATA(IRQ3_GMARK, GFN_IRQ3),\n-\tPINMUX_DATA(IRQ2_GMARK, GFN_IRQ2),\n-\tPINMUX_DATA(IRQ1_GMARK, GFN_IRQ1),\n-\tPINMUX_DATA(IRQ0_GMARK, GFN_IRQ0),\n-\n-\t/* GPSR3 */\n-\tPINMUX_DATA(SD1_WP_GMARK, GFN_SD1_WP),\n-\tPINMUX_DATA(SD1_CD_GMARK, GFN_SD1_CD),\n-\tPINMUX_DATA(SD0_WP_GMARK, GFN_SD0_WP),\n-\tPINMUX_DATA(SD0_CD_GMARK, GFN_SD0_CD),\n-\tPINMUX_DATA(SD1_DAT3_GMARK, GFN_SD1_DAT3),\n-\tPINMUX_DATA(SD1_DAT2_GMARK, GFN_SD1_DAT2),\n-\tPINMUX_DATA(SD1_DAT1_GMARK, GFN_SD1_DAT1),\n-\tPINMUX_DATA(SD1_DAT0_GMARK, GFN_SD1_DAT0),\n-\tPINMUX_DATA(SD1_CMD_GMARK, GFN_SD1_CMD),\n-\tPINMUX_DATA(SD1_CLK_GMARK, GFN_SD1_CLK),\n-\tPINMUX_DATA(SD0_DAT3_GMARK, GFN_SD0_DAT3),\n-\tPINMUX_DATA(SD0_DAT2_GMARK, GFN_SD0_DAT2),\n-\tPINMUX_DATA(SD0_DAT1_GMARK, GFN_SD0_DAT1),\n-\tPINMUX_DATA(SD0_DAT0_GMARK, GFN_SD0_DAT0),\n-\tPINMUX_DATA(SD0_CMD_GMARK, GFN_SD0_CMD),\n-\tPINMUX_DATA(SD0_CLK_GMARK, GFN_SD0_CLK),\n-\n-\t/* GPSR4 */\n-\tPINMUX_DATA(SD3_DS_GMARK, GFN_SD3_DS),\n-\tPINMUX_DATA(SD3_DAT7_GMARK, GFN_SD3_DAT7),\n-\tPINMUX_DATA(SD3_DAT6_GMARK, GFN_SD3_DAT6),\n-\tPINMUX_DATA(SD3_DAT5_GMARK, GFN_SD3_DAT5),\n-\tPINMUX_DATA(SD3_DAT4_GMARK, GFN_SD3_DAT4),\n-\tPINMUX_DATA(SD3_DAT3_MARK, FN_SD3_DAT3),\n-\tPINMUX_DATA(SD3_DAT2_MARK, FN_SD3_DAT2),\n-\tPINMUX_DATA(SD3_DAT1_MARK, FN_SD3_DAT1),\n-\tPINMUX_DATA(SD3_DAT0_MARK, FN_SD3_DAT0),\n-\tPINMUX_DATA(SD3_CMD_MARK, FN_SD3_CMD),\n-\tPINMUX_DATA(SD3_CLK_MARK, FN_SD3_CLK),\n-\tPINMUX_DATA(SD2_DS_GMARK, GFN_SD2_DS),\n-\tPINMUX_DATA(SD2_DAT3_GMARK, GFN_SD2_DAT3),\n-\tPINMUX_DATA(SD2_DAT2_GMARK, GFN_SD2_DAT2),\n-\tPINMUX_DATA(SD2_DAT1_GMARK, GFN_SD2_DAT1),\n-\tPINMUX_DATA(SD2_DAT0_GMARK, GFN_SD2_DAT0),\n-\tPINMUX_DATA(SD2_CMD_MARK, FN_SD2_CMD),\n-\tPINMUX_DATA(SD2_CLK_GMARK, GFN_SD2_CLK),\n-\n-\t/* GPSR5 */\n-\tPINMUX_DATA(MLB_DAT_GMARK, GFN_MLB_DAT),\n-\tPINMUX_DATA(MLB_SIG_GMARK, GFN_MLB_SIG),\n-\tPINMUX_DATA(MLB_CLK_GMARK, GFN_MLB_CLK),\n-\tPINMUX_DATA(MSIOF0_RXD_MARK, FN_MSIOF0_RXD),\n-\tPINMUX_DATA(MSIOF0_SS2_GMARK, GFN_MSIOF0_SS2),\n-\tPINMUX_DATA(MSIOF0_TXD_MARK, FN_MSIOF0_TXD),\n-\tPINMUX_DATA(MSIOF0_SS1_GMARK, GFN_MSIOF0_SS1),\n-\tPINMUX_DATA(MSIOF0_SYNC_GMARK, GFN_MSIOF0_SYNC),\n-\tPINMUX_DATA(MSIOF0_SCK_MARK, FN_MSIOF0_SCK),\n-\tPINMUX_DATA(HRTS0x_GMARK, GFN_HRTS0x),\n-\tPINMUX_DATA(HCTS0x_GMARK, GFN_HCTS0x),\n-\tPINMUX_DATA(HTX0_GMARK, GFN_HTX0),\n-\tPINMUX_DATA(HRX0_GMARK, GFN_HRX0),\n-\tPINMUX_DATA(HSCK0_GMARK, GFN_HSCK0),\n-\tPINMUX_DATA(RX2_A_GMARK, GFN_RX2_A),\n-\tPINMUX_DATA(TX2_A_GMARK, GFN_TX2_A),\n-\tPINMUX_DATA(SCK2_GMARK, GFN_SCK2),\n-\tPINMUX_DATA(RTS1x_TANS_GMARK, GFN_RTS1x_TANS),\n-\tPINMUX_DATA(CTS1x_GMARK, GFN_CTS1x),\n-\tPINMUX_DATA(TX1_A_GMARK, GFN_TX1_A),\n-\tPINMUX_DATA(RX1_A_GMARK, GFN_RX1_A),\n-\tPINMUX_DATA(RTS0x_TANS_GMARK, GFN_RTS0x_TANS),\n-\tPINMUX_DATA(CTS0x_GMARK, GFN_CTS0x),\n-\tPINMUX_DATA(TX0_GMARK, GFN_TX0),\n-\tPINMUX_DATA(RX0_GMARK, GFN_RX0),\n-\tPINMUX_DATA(SCK0_GMARK, GFN_SCK0),\n-\n-\t/* GPSR6 */\n-\tPINMUX_DATA(GP6_30_GMARK, GFN_GP6_30),\n-\tPINMUX_DATA(GP6_31_GMARK, GFN_GP6_31),\n-\tPINMUX_DATA(USB30_OVC_GMARK, GFN_USB30_OVC),\n-\tPINMUX_DATA(USB30_PWEN_GMARK, GFN_USB30_PWEN),\n-\tPINMUX_DATA(USB1_OVC_GMARK, GFN_USB1_OVC),\n-\tPINMUX_DATA(USB1_PWEN_GMARK, GFN_USB1_PWEN),\n-\tPINMUX_DATA(USB0_OVC_GMARK, GFN_USB0_OVC),\n-\tPINMUX_DATA(USB0_PWEN_GMARK, GFN_USB0_PWEN),\n-\tPINMUX_DATA(AUDIO_CLKB_B_GMARK, GFN_AUDIO_CLKB_B),\n-\tPINMUX_DATA(AUDIO_CLKA_A_GMARK, GFN_AUDIO_CLKA_A),\n-\tPINMUX_DATA(SSI_SDATA9_A_GMARK, GFN_SSI_SDATA9_A),\n-\tPINMUX_DATA(SSI_SDATA8_GMARK, GFN_SSI_SDATA8),\n-\tPINMUX_DATA(SSI_SDATA7_GMARK, GFN_SSI_SDATA7),\n-\tPINMUX_DATA(SSI_WS78_GMARK, GFN_SSI_WS78),\n-\tPINMUX_DATA(SSI_SCK78_GMARK, GFN_SSI_SCK78),\n-\tPINMUX_DATA(SSI_SDATA6_GMARK, GFN_SSI_SDATA6),\n-\tPINMUX_DATA(SSI_WS6_GMARK, GFN_SSI_WS6),\n-\tPINMUX_DATA(SSI_SCK6_GMARK, GFN_SSI_SCK6),\n-\tPINMUX_DATA(SSI_SDATA5_MARK, FN_SSI_SDATA5),\n-\tPINMUX_DATA(SSI_WS5_MARK, FN_SSI_WS5),\n-\tPINMUX_DATA(SSI_SCK5_MARK, FN_SSI_SCK5),\n-\tPINMUX_DATA(SSI_SDATA4_GMARK, GFN_SSI_SDATA4),\n-\tPINMUX_DATA(SSI_WS4_GMARK, GFN_SSI_WS4),\n-\tPINMUX_DATA(SSI_SCK4_GMARK, GFN_SSI_SCK4),\n-\tPINMUX_DATA(SSI_SDATA3_GMARK, GFN_SSI_SDATA3),\n-\tPINMUX_DATA(SSI_WS34_GMARK, GFN_SSI_WS34),\n-\tPINMUX_DATA(SSI_SCK34_GMARK, GFN_SSI_SCK34),\n-\tPINMUX_DATA(SSI_SDATA2_A_GMARK, GFN_SSI_SDATA2_A),\n-\tPINMUX_DATA(SSI_SDATA1_A_GMARK, GFN_SSI_SDATA1_A),\n-\tPINMUX_DATA(SSI_SDATA0_GMARK, GFN_SSI_SDATA0),\n-\tPINMUX_DATA(SSI_WS01239_GMARK, GFN_SSI_WS01239),\n-\tPINMUX_DATA(SSI_SCK01239_GMARK, GFN_SSI_SCK01239),\n-\n-\t/* GPSR7 */\n-\tPINMUX_DATA(HDMI1_CEC_MARK, FN_HDMI1_CEC),\n-\tPINMUX_DATA(HDMI0_CEC_MARK, FN_HDMI0_CEC),\n-\tPINMUX_DATA(AVS2_MARK, FN_AVS2),\n-\tPINMUX_DATA(AVS1_MARK, FN_AVS1),\n-\n-\t/* ipsr setting .. underconstruction */\n-};\n-\n-static struct pinmux_gpio pinmux_gpios[] = {\n-\tPINMUX_GPIO_GP_ALL(),\n-\t/* GPSR0 */\n-\tGPIO_GFN(D15),\n-\tGPIO_GFN(D14),\n-\tGPIO_GFN(D13),\n-\tGPIO_GFN(D12),\n-\tGPIO_GFN(D11),\n-\tGPIO_GFN(D10),\n-\tGPIO_GFN(D9),\n-\tGPIO_GFN(D8),\n-\tGPIO_GFN(D7),\n-\tGPIO_GFN(D6),\n-\tGPIO_GFN(D5),\n-\tGPIO_GFN(D4),\n-\tGPIO_GFN(D3),\n-\tGPIO_GFN(D2),\n-\tGPIO_GFN(D1),\n-\tGPIO_GFN(D0),\n-\t/* GPSR1 */\n-\tGPIO_GFN(CLKOUT),\n-\tGPIO_GFN(EX_WAIT0_A),\n-\tGPIO_GFN(WE1x),\n-\tGPIO_GFN(WE0x),\n-\tGPIO_GFN(RD_WRx),\n-\tGPIO_GFN(RDx),\n-\tGPIO_GFN(BSx),\n-\tGPIO_GFN(CS1x_A26),\n-\tGPIO_GFN(CS0x),\n-\tGPIO_GFN(A19),\n-\tGPIO_GFN(A18),\n-\tGPIO_GFN(A17),\n-\tGPIO_GFN(A16),\n-\tGPIO_GFN(A15),\n-\tGPIO_GFN(A14),\n-\tGPIO_GFN(A13),\n-\tGPIO_GFN(A12),\n-\tGPIO_GFN(A11),\n-\tGPIO_GFN(A10),\n-\tGPIO_GFN(A9),\n-\tGPIO_GFN(A8),\n-\tGPIO_GFN(A7),\n-\tGPIO_GFN(A6),\n-\tGPIO_GFN(A5),\n-\tGPIO_GFN(A4),\n-\tGPIO_GFN(A3),\n-\tGPIO_GFN(A2),\n-\tGPIO_GFN(A1),\n-\tGPIO_GFN(A0),\n-\n-\t/* GPSR2 */\n-\tGPIO_GFN(AVB_AVTP_CAPTURE_A),\n-\tGPIO_GFN(AVB_AVTP_MATCH_A),\n-\tGPIO_GFN(AVB_LINK),\n-\tGPIO_GFN(AVB_PHY_INT),\n-\tGPIO_GFN(AVB_MAGIC),\n-\tGPIO_GFN(AVB_MDC),\n-\tGPIO_GFN(PWM2_A),\n-\tGPIO_GFN(PWM1_A),\n-\tGPIO_GFN(PWM0),\n-\tGPIO_GFN(IRQ5),\n-\tGPIO_GFN(IRQ4),\n-\tGPIO_GFN(IRQ3),\n-\tGPIO_GFN(IRQ2),\n-\tGPIO_GFN(IRQ1),\n-\tGPIO_GFN(IRQ0),\n-\n-\t/* GPSR3 */\n-\tGPIO_GFN(SD1_WP),\n-\tGPIO_GFN(SD1_CD),\n-\tGPIO_GFN(SD0_WP),\n-\tGPIO_GFN(SD0_CD),\n-\tGPIO_GFN(SD1_DAT3),\n-\tGPIO_GFN(SD1_DAT2),\n-\tGPIO_GFN(SD1_DAT1),\n-\tGPIO_GFN(SD1_DAT0),\n-\tGPIO_GFN(SD1_CMD),\n-\tGPIO_GFN(SD1_CLK),\n-\tGPIO_GFN(SD0_DAT3),\n-\tGPIO_GFN(SD0_DAT2),\n-\tGPIO_GFN(SD0_DAT1),\n-\tGPIO_GFN(SD0_DAT0),\n-\tGPIO_GFN(SD0_CMD),\n-\tGPIO_GFN(SD0_CLK),\n-\n-\t/* GPSR4 */\n-\tGPIO_GFN(SD3_DS),\n-\tGPIO_GFN(SD3_DAT7),\n-\tGPIO_GFN(SD3_DAT6),\n-\tGPIO_GFN(SD3_DAT5),\n-\tGPIO_GFN(SD3_DAT4),\n-\tGPIO_FN(SD3_DAT3),\n-\tGPIO_FN(SD3_DAT2),\n-\tGPIO_FN(SD3_DAT1),\n-\tGPIO_FN(SD3_DAT0),\n-\tGPIO_FN(SD3_CMD),\n-\tGPIO_FN(SD3_CLK),\n-\tGPIO_GFN(SD2_DS),\n-\tGPIO_GFN(SD2_DAT3),\n-\tGPIO_GFN(SD2_DAT2),\n-\tGPIO_GFN(SD2_DAT1),\n-\tGPIO_GFN(SD2_DAT0),\n-\tGPIO_FN(SD2_CMD),\n-\tGPIO_GFN(SD2_CLK),\n-\n-\t/* GPSR5 */\n-\tGPIO_GFN(MLB_DAT),\n-\tGPIO_GFN(MLB_SIG),\n-\tGPIO_GFN(MLB_CLK),\n-\tGPIO_FN(MSIOF0_RXD),\n-\tGPIO_GFN(MSIOF0_SS2),\n-\tGPIO_FN(MSIOF0_TXD),\n-\tGPIO_GFN(MSIOF0_SS1),\n-\tGPIO_GFN(MSIOF0_SYNC),\n-\tGPIO_FN(MSIOF0_SCK),\n-\tGPIO_GFN(HRTS0x),\n-\tGPIO_GFN(HCTS0x),\n-\tGPIO_GFN(HTX0),\n-\tGPIO_GFN(HRX0),\n-\tGPIO_GFN(HSCK0),\n-\tGPIO_GFN(RX2_A),\n-\tGPIO_GFN(TX2_A),\n-\tGPIO_GFN(SCK2),\n-\tGPIO_GFN(RTS1x_TANS),\n-\tGPIO_GFN(CTS1x),\n-\tGPIO_GFN(TX1_A),\n-\tGPIO_GFN(RX1_A),\n-\tGPIO_GFN(RTS0x_TANS),\n-\tGPIO_GFN(CTS0x),\n-\tGPIO_GFN(TX0),\n-\tGPIO_GFN(RX0),\n-\tGPIO_GFN(SCK0),\n-\n-\t/* GPSR6 */\n-\tGPIO_GFN(GP6_30),\n-\tGPIO_GFN(GP6_31),\n-\tGPIO_GFN(USB30_OVC),\n-\tGPIO_GFN(USB30_PWEN),\n-\tGPIO_GFN(USB1_OVC),\n-\tGPIO_GFN(USB1_PWEN),\n-\tGPIO_GFN(USB0_OVC),\n-\tGPIO_GFN(USB0_PWEN),\n-\tGPIO_GFN(AUDIO_CLKB_B),\n-\tGPIO_GFN(AUDIO_CLKA_A),\n-\tGPIO_GFN(SSI_SDATA9_A),\n-\tGPIO_GFN(SSI_SDATA8),\n-\tGPIO_GFN(SSI_SDATA7),\n-\tGPIO_GFN(SSI_WS78),\n-\tGPIO_GFN(SSI_SCK78),\n-\tGPIO_GFN(SSI_SDATA6),\n-\tGPIO_GFN(SSI_WS6),\n-\tGPIO_GFN(SSI_SCK6),\n-\tGPIO_FN(SSI_SDATA5),\n-\tGPIO_FN(SSI_WS5),\n-\tGPIO_FN(SSI_SCK5),\n-\tGPIO_GFN(SSI_SDATA4),\n-\tGPIO_GFN(SSI_WS4),\n-\tGPIO_GFN(SSI_SCK4),\n-\tGPIO_GFN(SSI_SDATA3),\n-\tGPIO_GFN(SSI_WS34),\n-\tGPIO_GFN(SSI_SCK34),\n-\tGPIO_GFN(SSI_SDATA2_A),\n-\tGPIO_GFN(SSI_SDATA1_A),\n-\tGPIO_GFN(SSI_SDATA0),\n-\tGPIO_GFN(SSI_WS01239),\n-\tGPIO_GFN(SSI_SCK01239),\n-\n-\t/* GPSR7 */\n-\tGPIO_FN(HDMI1_CEC),\n-\tGPIO_FN(HDMI0_CEC),\n-\tGPIO_FN(AVS2),\n-\tGPIO_FN(AVS1),\n-\n-\t/* IPSR0 */\n-\tGPIO_IFN(AVB_MDC),\n-\tGPIO_FN(MSIOF2_SS2_C),\n-\tGPIO_IFN(AVB_MAGIC),\n-\tGPIO_FN(MSIOF2_SS1_C),\n-\tGPIO_FN(SCK4_A),\n-\tGPIO_IFN(AVB_PHY_INT),\n-\tGPIO_FN(MSIOF2_SYNC_C),\n-\tGPIO_FN(RX4_A),\n-\tGPIO_IFN(AVB_LINK),\n-\tGPIO_FN(MSIOF2_SCK_C),\n-\tGPIO_FN(TX4_A),\n-\tGPIO_IFN(AVB_AVTP_MATCH_A),\n-\tGPIO_FN(MSIOF2_RXD_C),\n-\tGPIO_FN(CTS4x_A),\n-\tGPIO_IFN(AVB_AVTP_CAPTURE_A),\n-\tGPIO_FN(MSIOF2_TXD_C),\n-\tGPIO_FN(RTS4x_TANS_A),\n-\tGPIO_IFN(IRQ0),\n-\tGPIO_FN(QPOLB),\n-\tGPIO_FN(DU_CDE),\n-\tGPIO_FN(VI4_DATA0_B),\n-\tGPIO_FN(CAN0_TX_B),\n-\tGPIO_FN(CANFD0_TX_B),\n-\tGPIO_FN(MSIOF3_SS2_E),\n-\tGPIO_IFN(IRQ1),\n-\tGPIO_FN(QPOLA),\n-\tGPIO_FN(DU_DISP),\n-\tGPIO_FN(VI4_DATA1_B),\n-\tGPIO_FN(CAN0_RX_B),\n-\tGPIO_FN(CANFD0_RX_B),\n-\tGPIO_FN(MSIOF3_SS1_E),\n-\n-\t/* IPSR1 */\n-\tGPIO_IFN(IRQ2),\n-\tGPIO_FN(QCPV_QDE),\n-\tGPIO_FN(DU_EXODDF_DU_ODDF_DISP_CDE),\n-\tGPIO_FN(VI4_DATA2_B),\n-\tGPIO_FN(MSIOF3_SYNC_E),\n-\tGPIO_FN(PWM3_B),\n-\tGPIO_IFN(IRQ3),\n-\tGPIO_FN(QSTVB_QVE),\n-\tGPIO_FN(DU_DOTCLKOUT1),\n-\tGPIO_FN(VI4_DATA3_B),\n-\tGPIO_FN(MSIOF3_SCK_E),\n-\tGPIO_FN(PWM4_B),\n-\tGPIO_IFN(IRQ4),\n-\tGPIO_FN(QSTH_QHS),\n-\tGPIO_FN(DU_EXHSYNC_DU_HSYNC),\n-\tGPIO_FN(VI4_DATA4_B),\n-\tGPIO_FN(MSIOF3_RXD_E),\n-\tGPIO_FN(PWM5_B),\n-\tGPIO_IFN(IRQ5),\n-\tGPIO_FN(QSTB_QHE),\n-\tGPIO_FN(DU_EXVSYNC_DU_VSYNC),\n-\tGPIO_FN(VI4_DATA5_B),\n-\tGPIO_FN(MSIOF3_TXD_E),\n-\tGPIO_FN(PWM6_B),\n-\tGPIO_IFN(PWM0),\n-\tGPIO_FN(AVB_AVTP_PPS),\n-\tGPIO_FN(VI4_DATA6_B),\n-\tGPIO_FN(IECLK_B),\n-\tGPIO_IFN(PWM1_A),\n-\tGPIO_FN(HRX3_D),\n-\tGPIO_FN(VI4_DATA7_B),\n-\tGPIO_FN(IERX_B),\n-\tGPIO_IFN(PWM2_A),\n-\tGPIO_FN(PWMFSW0),\n-\tGPIO_FN(HTX3_D),\n-\tGPIO_FN(IETX_B),\n-\tGPIO_IFN(A0),\n-\tGPIO_FN(LCDOUT16),\n-\tGPIO_FN(MSIOF3_SYNC_B),\n-\tGPIO_FN(VI4_DATA8),\n-\tGPIO_FN(DU_DB0),\n-\tGPIO_FN(PWM3_A),\n-\n-\t/* IPSR2 */\n-\tGPIO_IFN(A1),\n-\tGPIO_FN(LCDOUT17),\n-\tGPIO_FN(MSIOF3_TXD_B),\n-\tGPIO_FN(VI4_DATA9),\n-\tGPIO_FN(DU_DB1),\n-\tGPIO_FN(PWM4_A),\n-\tGPIO_IFN(A2),\n-\tGPIO_FN(LCDOUT18),\n-\tGPIO_FN(MSIOF3_SCK_B),\n-\tGPIO_FN(VI4_DATA10),\n-\tGPIO_FN(DU_DB2),\n-\tGPIO_FN(PWM5_A),\n-\tGPIO_IFN(A3),\n-\tGPIO_FN(LCDOUT19),\n-\tGPIO_FN(MSIOF3_RXD_B),\n-\tGPIO_FN(VI4_DATA11),\n-\tGPIO_FN(DU_DB3),\n-\tGPIO_FN(PWM6_A),\n-\tGPIO_IFN(A4),\n-\tGPIO_FN(LCDOUT20),\n-\tGPIO_FN(MSIOF3_SS1_B),\n-\tGPIO_FN(VI4_DATA12),\n-\tGPIO_FN(VI5_DATA12),\n-\tGPIO_FN(DU_DB4),\n-\tGPIO_IFN(A5),\n-\tGPIO_FN(LCDOUT21),\n-\tGPIO_FN(MSIOF3_SS2_B),\n-\tGPIO_FN(SCK4_B),\n-\tGPIO_FN(VI4_DATA13),\n-\tGPIO_FN(VI5_DATA13),\n-\tGPIO_FN(DU_DB5),\n-\tGPIO_IFN(A6),\n-\tGPIO_FN(LCDOUT22),\n-\tGPIO_FN(MSIOF2_SS1_A),\n-\tGPIO_FN(RX4_B),\n-\tGPIO_FN(VI4_DATA14),\n-\tGPIO_FN(VI5_DATA14),\n-\tGPIO_FN(DU_DB6),\n-\tGPIO_IFN(A7),\n-\tGPIO_FN(LCDOUT23),\n-\tGPIO_FN(MSIOF2_SS2_A),\n-\tGPIO_FN(TX4_B),\n-\tGPIO_FN(VI4_DATA15),\n-\tGPIO_FN(V15_DATA15),\n-\tGPIO_FN(DU_DB7),\n-\tGPIO_IFN(A8),\n-\tGPIO_FN(RX3_B),\n-\tGPIO_FN(MSIOF2_SYNC_A),\n-\tGPIO_FN(HRX4_B),\n-\tGPIO_FN(SDA6_A),\n-\tGPIO_FN(AVB_AVTP_MATCH_B),\n-\tGPIO_FN(PWM1_B),\n-\n-\t/* IPSR3 */\n-\tGPIO_IFN(A9),\n-\tGPIO_FN(MSIOF2_SCK_A),\n-\tGPIO_FN(CTS4x_B),\n-\tGPIO_FN(VI5_VSYNCx),\n-\tGPIO_IFN(A10),\n-\tGPIO_FN(MSIOF2_RXD_A),\n-\tGPIO_FN(RTS4n_TANS_B),\n-\tGPIO_FN(VI5_HSYNCx),\n-\tGPIO_IFN(A11),\n-\tGPIO_FN(TX3_B),\n-\tGPIO_FN(MSIOF2_TXD_A),\n-\tGPIO_FN(HTX4_B),\n-\tGPIO_FN(HSCK4),\n-\tGPIO_FN(VI5_FIELD),\n-\tGPIO_FN(SCL6_A),\n-\tGPIO_FN(AVB_AVTP_CAPTURE_B),\n-\tGPIO_FN(PWM2_B),\n-\tGPIO_FN(SPV_EVEN),\n-\tGPIO_IFN(A12),\n-\tGPIO_FN(LCDOUT12),\n-\tGPIO_FN(MSIOF3_SCK_C),\n-\tGPIO_FN(HRX4_A),\n-\tGPIO_FN(VI5_DATA8),\n-\tGPIO_FN(DU_DG4),\n-\tGPIO_IFN(A13),\n-\tGPIO_FN(LCDOUT13),\n-\tGPIO_FN(MSIOF3_SYNC_C),\n-\tGPIO_FN(HTX4_A),\n-\tGPIO_FN(VI5_DATA9),\n-\tGPIO_FN(DU_DG5),\n-\tGPIO_IFN(A14),\n-\tGPIO_FN(LCDOUT14),\n-\tGPIO_FN(MSIOF3_RXD_C),\n-\tGPIO_FN(HCTS4x),\n-\tGPIO_FN(VI5_DATA10),\n-\tGPIO_FN(DU_DG6),\n-\tGPIO_IFN(A15),\n-\tGPIO_FN(LCDOUT15),\n-\tGPIO_FN(MSIOF3_TXD_C),\n-\tGPIO_FN(HRTS4x),\n-\tGPIO_FN(VI5_DATA11),\n-\tGPIO_FN(DU_DG7),\n-\tGPIO_IFN(A16),\n-\tGPIO_FN(LCDOUT8),\n-\tGPIO_FN(VI4_FIELD),\n-\tGPIO_FN(DU_DG0),\n-\n-\t/* IPSR4 */\n-\tGPIO_IFN(A17),\n-\tGPIO_FN(LCDOUT9),\n-\tGPIO_FN(VI4_VSYNCx),\n-\tGPIO_FN(DU_DG1),\n-\tGPIO_IFN(A18),\n-\tGPIO_FN(LCDOUT10),\n-\tGPIO_FN(VI4_HSYNCx),\n-\tGPIO_FN(DU_DG2),\n-\tGPIO_IFN(A19),\n-\tGPIO_FN(LCDOUT11),\n-\tGPIO_FN(VI4_CLKENB),\n-\tGPIO_FN(DU_DG3),\n-\tGPIO_IFN(CS0x),\n-\tGPIO_FN(VI5_CLKENB),\n-\tGPIO_IFN(CS1x_A26),\n-\tGPIO_FN(VI5_CLK),\n-\tGPIO_FN(EX_WAIT0_B),\n-\tGPIO_IFN(BSx),\n-\tGPIO_FN(QSTVA_QVS),\n-\tGPIO_FN(MSIOF3_SCK_D),\n-\tGPIO_FN(SCK3),\n-\tGPIO_FN(HSCK3),\n-\tGPIO_FN(CAN1_TX),\n-\tGPIO_FN(CANFD1_TX),\n-\tGPIO_FN(IETX_A),\n-\tGPIO_IFN(RDx),\n-\tGPIO_FN(MSIOF3_SYNC_D),\n-\tGPIO_FN(RX3_A),\n-\tGPIO_FN(HRX3_A),\n-\tGPIO_FN(CAN0_TX_A),\n-\tGPIO_FN(CANFD0_TX_A),\n-\tGPIO_IFN(RD_WRx),\n-\tGPIO_FN(MSIOF3_RXD_D),\n-\tGPIO_FN(TX3_A),\n-\tGPIO_FN(HTX3_A),\n-\tGPIO_FN(CAN0_RX_A),\n-\tGPIO_FN(CANFD0_RX_A),\n-\n-\t/* IPSR5 */\n-\tGPIO_IFN(WE0x),\n-\tGPIO_FN(MSIIOF3_TXD_D),\n-\tGPIO_FN(CTS3x),\n-\tGPIO_FN(HCTS3x),\n-\tGPIO_FN(SCL6_B),\n-\tGPIO_FN(CAN_CLK),\n-\tGPIO_FN(IECLK_A),\n-\tGPIO_IFN(WE1x),\n-\tGPIO_FN(MSIOF3_SS1_D),\n-\tGPIO_FN(RTS3x_TANS),\n-\tGPIO_FN(HRTS3x),\n-\tGPIO_FN(SDA6_B),\n-\tGPIO_FN(CAN1_RX),\n-\tGPIO_FN(CANFD1_RX),\n-\tGPIO_FN(IERX_A),\n-\tGPIO_IFN(EX_WAIT0_A),\n-\tGPIO_FN(QCLK),\n-\tGPIO_FN(VI4_CLK),\n-\tGPIO_FN(DU_DOTCLKOUT0),\n-\tGPIO_IFN(D0),\n-\tGPIO_FN(MSIOF2_SS1_B),\n-\tGPIO_FN(MSIOF3_SCK_A),\n-\tGPIO_FN(VI4_DATA16),\n-\tGPIO_FN(VI5_DATA0),\n-\tGPIO_IFN(D1),\n-\tGPIO_FN(MSIOF2_SS2_B),\n-\tGPIO_FN(MSIOF3_SYNC_A),\n-\tGPIO_FN(VI4_DATA17),\n-\tGPIO_FN(VI5_DATA1),\n-\tGPIO_IFN(D2),\n-\tGPIO_FN(MSIOF3_RXD_A),\n-\tGPIO_FN(VI4_DATA18),\n-\tGPIO_FN(VI5_DATA2),\n-\tGPIO_IFN(D3),\n-\tGPIO_FN(MSIOF3_TXD_A),\n-\tGPIO_FN(VI4_DATA19),\n-\tGPIO_FN(VI5_DATA3),\n-\tGPIO_IFN(D4),\n-\tGPIO_FN(MSIOF2_SCK_B),\n-\tGPIO_FN(VI4_DATA20),\n-\tGPIO_FN(VI5_DATA4),\n-\n-\t/* IPSR6 */\n-\tGPIO_IFN(D5),\n-\tGPIO_FN(MSIOF2_SYNC_B),\n-\tGPIO_FN(VI4_DATA21),\n-\tGPIO_FN(VI5_DATA5),\n-\tGPIO_IFN(D6),\n-\tGPIO_FN(MSIOF2_RXD_B),\n-\tGPIO_FN(VI4_DATA22),\n-\tGPIO_FN(VI5_DATA6),\n-\tGPIO_IFN(D7),\n-\tGPIO_FN(MSIOF2_TXD_B),\n-\tGPIO_FN(VI4_DATA23),\n-\tGPIO_FN(VI5_DATA7),\n-\tGPIO_IFN(D8),\n-\tGPIO_FN(LCDOUT0),\n-\tGPIO_FN(MSIOF2_SCK_D),\n-\tGPIO_FN(SCK4_C),\n-\tGPIO_FN(VI4_DATA0_A),\n-\tGPIO_FN(DU_DR0),\n-\tGPIO_IFN(D9),\n-\tGPIO_FN(LCDOUT1),\n-\tGPIO_FN(MSIOF2_SYNC_D),\n-\tGPIO_FN(VI4_DATA1_A),\n-\tGPIO_FN(DU_DR1),\n-\tGPIO_IFN(D10),\n-\tGPIO_FN(LCDOUT2),\n-\tGPIO_FN(MSIOF2_RXD_D),\n-\tGPIO_FN(HRX3_B),\n-\tGPIO_FN(VI4_DATA2_A),\n-\tGPIO_FN(CTS4x_C),\n-\tGPIO_FN(DU_DR2),\n-\tGPIO_IFN(D11),\n-\tGPIO_FN(LCDOUT3),\n-\tGPIO_FN(MSIOF2_TXD_D),\n-\tGPIO_FN(HTX3_B),\n-\tGPIO_FN(VI4_DATA3_A),\n-\tGPIO_FN(RTS4x_TANS_C),\n-\tGPIO_FN(DU_DR3),\n-\tGPIO_IFN(D12),\n-\tGPIO_FN(LCDOUT4),\n-\tGPIO_FN(MSIOF2_SS1_D),\n-\tGPIO_FN(RX4_C),\n-\tGPIO_FN(VI4_DATA4_A),\n-\tGPIO_FN(DU_DR4),\n-\n-\t/* IPSR7 */\n-\tGPIO_IFN(D13),\n-\tGPIO_FN(LCDOUT5),\n-\tGPIO_FN(MSIOF2_SS2_D),\n-\tGPIO_FN(TX4_C),\n-\tGPIO_FN(VI4_DATA5_A),\n-\tGPIO_FN(DU_DR5),\n-\tGPIO_IFN(D14),\n-\tGPIO_FN(LCDOUT6),\n-\tGPIO_FN(MSIOF3_SS1_A),\n-\tGPIO_FN(HRX3_C),\n-\tGPIO_FN(VI4_DATA6_A),\n-\tGPIO_FN(DU_DR6),\n-\tGPIO_FN(SCL6_C),\n-\tGPIO_IFN(D15),\n-\tGPIO_FN(LCDOUT7),\n-\tGPIO_FN(MSIOF3_SS2_A),\n-\tGPIO_FN(HTX3_C),\n-\tGPIO_FN(VI4_DATA7_A),\n-\tGPIO_FN(DU_DR7),\n-\tGPIO_FN(SDA6_C),\n-\tGPIO_FN(FSCLKST),\n-\tGPIO_IFN(SD0_CLK),\n-\tGPIO_FN(MSIOF1_SCK_E),\n-\tGPIO_FN(STP_OPWM_0_B),\n-\tGPIO_IFN(SD0_CMD),\n-\tGPIO_FN(MSIOF1_SYNC_E),\n-\tGPIO_FN(STP_IVCXO27_0_B),\n-\tGPIO_IFN(SD0_DAT0),\n-\tGPIO_FN(MSIOF1_RXD_E),\n-\tGPIO_FN(TS_SCK0_B),\n-\tGPIO_FN(STP_ISCLK_0_B),\n-\tGPIO_IFN(SD0_DAT1),\n-\tGPIO_FN(MSIOF1_TXD_E),\n-\tGPIO_FN(TS_SPSYNC0_B),\n-\tGPIO_FN(STP_ISSYNC_0_B),\n-\n-\t/* IPSR8 */\n-\tGPIO_IFN(SD0_DAT2),\n-\tGPIO_FN(MSIOF1_SS1_E),\n-\tGPIO_FN(TS_SDAT0_B),\n-\tGPIO_FN(STP_ISD_0_B),\n-\n-\tGPIO_IFN(SD0_DAT3),\n-\tGPIO_FN(MSIOF1_SS2_E),\n-\tGPIO_FN(TS_SDEN0_B),\n-\tGPIO_FN(STP_ISEN_0_B),\n-\n-\tGPIO_IFN(SD1_CLK),\n-\tGPIO_FN(MSIOF1_SCK_G),\n-\tGPIO_FN(SIM0_CLK_A),\n-\n-\tGPIO_IFN(SD1_CMD),\n-\tGPIO_FN(MSIOF1_SYNC_G),\n-\tGPIO_FN(NFCEx_B),\n-\tGPIO_FN(SIM0_D_A),\n-\tGPIO_FN(STP_IVCXO27_1_B),\n-\n-\tGPIO_IFN(SD1_DAT0),\n-\tGPIO_FN(SD2_DAT4),\n-\tGPIO_FN(MSIOF1_RXD_G),\n-\tGPIO_FN(NFWPx_B),\n-\tGPIO_FN(TS_SCK1_B),\n-\tGPIO_FN(STP_ISCLK_1_B),\n-\n-\tGPIO_IFN(SD1_DAT1),\n-\tGPIO_FN(SD2_DAT5),\n-\tGPIO_FN(MSIOF1_TXD_G),\n-\tGPIO_FN(NFDATA14_B),\n-\tGPIO_FN(TS_SPSYNC1_B),\n-\tGPIO_FN(STP_ISSYNC_1_B),\n-\n-\tGPIO_IFN(SD1_DAT2),\n-\tGPIO_FN(SD2_DAT6),\n-\tGPIO_FN(MSIOF1_SS1_G),\n-\tGPIO_FN(NFDATA15_B),\n-\tGPIO_FN(TS_SDAT1_B),\n-\tGPIO_FN(STP_IOD_1_B),\n-\n-\tGPIO_IFN(SD1_DAT3),\n-\tGPIO_FN(SD2_DAT7),\n-\tGPIO_FN(MSIOF1_SS2_G),\n-\tGPIO_FN(NFRBx_B),\n-\tGPIO_FN(TS_SDEN1_B),\n-\tGPIO_FN(STP_ISEN_1_B),\n-\n-\t/* IPSR9 */\n-\tGPIO_IFN(SD2_CLK),\n-\tGPIO_FN(NFDATA8),\n-\n-\tGPIO_IFN(SD2_CMD),\n-\tGPIO_FN(NFDATA9),\n-\n-\tGPIO_IFN(SD2_DAT0),\n-\tGPIO_FN(NFDATA10),\n-\n-\tGPIO_IFN(SD2_DAT1),\n-\tGPIO_FN(NFDATA11),\n-\n-\tGPIO_IFN(SD2_DAT2),\n-\tGPIO_FN(NFDATA12),\n-\n-\tGPIO_IFN(SD2_DAT3),\n-\tGPIO_FN(NFDATA13),\n-\n-\tGPIO_IFN(SD2_DS),\n-\tGPIO_FN(NFALE),\n-\n-\tGPIO_IFN(SD3_CLK),\n-\tGPIO_FN(NFWEx),\n-\n-\t/* IPSR10 */\n-\tGPIO_IFN(SD3_CMD),\n-\tGPIO_FN(NFREx),\n-\n-\tGPIO_IFN(SD3_DAT0),\n-\tGPIO_FN(NFDATA0),\n-\n-\tGPIO_IFN(SD3_DAT1),\n-\tGPIO_FN(NFDATA1),\n-\n-\tGPIO_IFN(SD3_DAT2),\n-\tGPIO_FN(NFDATA2),\n-\n-\tGPIO_IFN(SD3_DAT3),\n-\tGPIO_FN(NFDATA3),\n-\n-\tGPIO_IFN(SD3_DAT4),\n-\tGPIO_FN(SD2_CD_A),\n-\tGPIO_FN(NFDATA4),\n-\n-\tGPIO_IFN(SD3_DAT5),\n-\tGPIO_FN(SD2_WP_A),\n-\tGPIO_FN(NFDATA5),\n-\n-\tGPIO_IFN(SD3_DAT6),\n-\tGPIO_FN(SD3_CD),\n-\tGPIO_FN(NFDATA6),\n-\n-\t/* IPSR11 */\n-\tGPIO_IFN(SD3_DAT7),\n-\tGPIO_FN(SD3_WP),\n-\tGPIO_FN(NFDATA7),\n-\n-\tGPIO_IFN(SD3_DS),\n-\tGPIO_FN(NFCLE),\n-\n-\tGPIO_IFN(SD0_CD),\n-\tGPIO_FN(NFDATA14_A),\n-\tGPIO_FN(SCL2_B),\n-\tGPIO_FN(SIM0_RST_A),\n-\n-\tGPIO_IFN(SD0_WP),\n-\tGPIO_FN(NFDATA15_A),\n-\tGPIO_FN(SDA2_B),\n-\n-\tGPIO_IFN(SD1_CD),\n-\tGPIO_FN(NFRBx_A),\n-\tGPIO_FN(SIM0_CLK_B),\n-\n-\tGPIO_IFN(SD1_WP),\n-\tGPIO_FN(NFCEx_A),\n-\tGPIO_FN(SIM0_D_B),\n-\n-\tGPIO_IFN(SCK0),\n-\tGPIO_FN(HSCK1_B),\n-\tGPIO_FN(MSIOF1_SS2_B),\n-\tGPIO_FN(AUDIO_CLKC_B),\n-\tGPIO_FN(SDA2_A),\n-\tGPIO_FN(SIM0_RST_B),\n-\tGPIO_FN(STP_OPWM_0_C),\n-\tGPIO_FN(RIF0_CLK_B),\n-\tGPIO_FN(ADICHS2),\n-\tGPIO_FN(SCK5_B),\n-\n-\tGPIO_IFN(RX0),\n-\tGPIO_FN(HRX1_B),\n-\tGPIO_FN(TS_SCK0_C),\n-\tGPIO_FN(STP_ISCLK_0_C),\n-\tGPIO_FN(RIF0_D0_B),\n-\n-\t/* IPSR12 */\n-\tGPIO_IFN(TX0),\n-\tGPIO_FN(HTX1_B),\n-\tGPIO_FN(TS_SPSYNC0_C),\n-\tGPIO_FN(STP_ISSYNC_0_C),\n-\tGPIO_FN(RIF0_D1_B),\n-\n-\tGPIO_IFN(CTS0x),\n-\tGPIO_FN(HCTS1x_B),\n-\tGPIO_FN(MSIOF1_SYNC_B),\n-\tGPIO_FN(TS_SPSYNC1_C),\n-\tGPIO_FN(STP_ISSYNC_1_C),\n-\tGPIO_FN(RIF1_SYNC_B),\n-\tGPIO_FN(AUDIO_CLKOUT_C),\n-\tGPIO_FN(ADICS_SAMP),\n-\n-\tGPIO_IFN(RTS0x_TANS),\n-\tGPIO_FN(HRTS1x_B),\n-\tGPIO_FN(MSIOF1_SS1_B),\n-\tGPIO_FN(AUDIO_CLKA_B),\n-\tGPIO_FN(SCL2_A),\n-\tGPIO_FN(STP_IVCXO27_1_C),\n-\tGPIO_FN(RIF0_SYNC_B),\n-\tGPIO_FN(ADICHS1),\n-\n-\tGPIO_IFN(RX1_A),\n-\tGPIO_FN(HRX1_A),\n-\tGPIO_FN(TS_SDAT0_C),\n-\tGPIO_FN(STP_ISD_0_C),\n-\tGPIO_FN(RIF1_CLK_C),\n-\n-\tGPIO_IFN(TX1_A),\n-\tGPIO_FN(HTX1_A),\n-\tGPIO_FN(TS_SDEN0_C),\n-\tGPIO_FN(STP_ISEN_0_C),\n-\tGPIO_FN(RIF1_D0_C),\n-\n-\tGPIO_IFN(CTS1x),\n-\tGPIO_FN(HCTS1x_A),\n-\tGPIO_FN(MSIOF1_RXD_B),\n-\tGPIO_FN(TS_SDEN1_C),\n-\tGPIO_FN(STP_ISEN_1_C),\n-\tGPIO_FN(RIF1_D0_B),\n-\tGPIO_FN(ADIDATA),\n-\n-\tGPIO_IFN(RTS1x_TANS),\n-\tGPIO_FN(HRTS1x_A),\n-\tGPIO_FN(MSIOF1_TXD_B),\n-\tGPIO_FN(TS_SDAT1_C),\n-\tGPIO_FN(STP_ISD_1_C),\n-\tGPIO_FN(RIF1_D1_B),\n-\tGPIO_FN(ADICHS0),\n-\n-\tGPIO_IFN(SCK2),\n-\tGPIO_FN(SCIF_CLK_B),\n-\tGPIO_FN(MSIOF1_SCK_B),\n-\tGPIO_FN(TS_SCK1_C),\n-\tGPIO_FN(STP_ISCLK_1_C),\n-\tGPIO_FN(RIF1_CLK_B),\n-\tGPIO_FN(ADICLK),\n-\n-\t/* IPSR13 */\n-\tGPIO_IFN(TX2_A),\n-\tGPIO_FN(SD2_CD_B),\n-\tGPIO_FN(SCL1_A),\n-\tGPIO_FN(FMCLK_A),\n-\tGPIO_FN(RIF1_D1_C),\n-\tGPIO_FN(FSO_CFE_0_B),\n-\n-\tGPIO_IFN(RX2_A),\n-\tGPIO_FN(SD2_WP_B),\n-\tGPIO_FN(SDA1_A),\n-\tGPIO_FN(FMIN_A),\n-\tGPIO_FN(RIF1_SYNC_C),\n-\tGPIO_FN(FSO_CEF_1_B),\n-\n-\tGPIO_IFN(HSCK0),\n-\tGPIO_FN(MSIOF1_SCK_D),\n-\tGPIO_FN(AUDIO_CLKB_A),\n-\tGPIO_FN(SSI_SDATA1_B),\n-\tGPIO_FN(TS_SCK0_D),\n-\tGPIO_FN(STP_ISCLK_0_D),\n-\tGPIO_FN(RIF0_CLK_C),\n-\tGPIO_FN(RX5_B),\n-\n-\tGPIO_IFN(HRX0),\n-\tGPIO_FN(MSIOF1_RXD_D),\n-\tGPIO_FN(SS1_SDATA2_B),\n-\tGPIO_FN(TS_SDEN0_D),\n-\tGPIO_FN(STP_ISEN_0_D),\n-\tGPIO_FN(RIF0_D0_C),\n-\n-\tGPIO_IFN(HTX0),\n-\tGPIO_FN(MSIOF1_TXD_D),\n-\tGPIO_FN(SSI_SDATA9_B),\n-\tGPIO_FN(TS_SDAT0_D),\n-\tGPIO_FN(STP_ISD_0_D),\n-\tGPIO_FN(RIF0_D1_C),\n-\n-\tGPIO_IFN(HCTS0x),\n-\tGPIO_FN(RX2_B),\n-\tGPIO_FN(MSIOF1_SYNC_D),\n-\tGPIO_FN(SSI_SCK9_A),\n-\tGPIO_FN(TS_SPSYNC0_D),\n-\tGPIO_FN(STP_ISSYNC_0_D),\n-\tGPIO_FN(RIF0_SYNC_C),\n-\tGPIO_FN(AUDIO_CLKOUT1_A),\n-\n-\tGPIO_IFN(HRTS0x),\n-\tGPIO_FN(TX2_B),\n-\tGPIO_FN(MSIOF1_SS1_D),\n-\tGPIO_FN(SSI_WS9_A),\n-\tGPIO_FN(STP_IVCXO27_0_D),\n-\tGPIO_FN(BPFCLK_A),\n-\tGPIO_FN(AUDIO_CLKOUT2_A),\n-\n-\tGPIO_IFN(MSIOF0_SYNC),\n-\tGPIO_FN(AUDIO_CLKOUT_A),\n-\tGPIO_FN(TX5_B),\n-\tGPIO_FN(BPFCLK_D),\n-\n-\t/* IPSR14 */\n-\tGPIO_IFN(MSIOF0_SS1),\n-\tGPIO_FN(RX5_A),\n-\tGPIO_FN(NFWPx_A),\n-\tGPIO_FN(AUDIO_CLKA_C),\n-\tGPIO_FN(SSI_SCK2_A),\n-\tGPIO_FN(STP_IVCXO27_0_C),\n-\tGPIO_FN(AUDIO_CLKOUT3_A),\n-\tGPIO_FN(TCLK1_B),\n-\n-\tGPIO_IFN(MSIOF0_SS2),\n-\tGPIO_FN(TX5_A),\n-\tGPIO_FN(MSIOF1_SS2_D),\n-\tGPIO_FN(AUDIO_CLKC_A),\n-\tGPIO_FN(SSI_WS2_A),\n-\tGPIO_FN(STP_OPWM_0_D),\n-\tGPIO_FN(AUDIO_CLKOUT_D),\n-\tGPIO_FN(SPEEDIN_B),\n-\n-\tGPIO_IFN(MLB_CLK),\n-\tGPIO_FN(MSIOF1_SCK_F),\n-\tGPIO_FN(SCL1_B),\n-\n-\tGPIO_IFN(MLB_SIG),\n-\tGPIO_FN(RX1_B),\n-\tGPIO_FN(MSIOF1_SYNC_F),\n-\tGPIO_FN(SDA1_B),\n-\n-\tGPIO_IFN(MLB_DAT),\n-\tGPIO_FN(TX1_B),\n-\tGPIO_FN(MSIOF1_RXD_F),\n-\n-\tGPIO_IFN(SSI_SCK0129),\n-\tGPIO_FN(MSIOF1_TXD_F),\n-\tGPIO_FN(MOUT0),\n-\n-\tGPIO_IFN(SSI_WS0129),\n-\tGPIO_FN(MSIOF1_SS1_F),\n-\tGPIO_FN(MOUT1),\n-\n-\tGPIO_IFN(SSI_SDATA0),\n-\tGPIO_FN(MSIOF1_SS2_F),\n-\tGPIO_FN(MOUT2),\n-\n-\t/* IPSR15 */\n-\tGPIO_IFN(SSI_SDATA1_A),\n-\tGPIO_FN(MOUT5),\n-\n-\tGPIO_IFN(SSI_SDATA2_A),\n-\tGPIO_FN(SSI_SCK1_B),\n-\tGPIO_FN(MOUT6),\n-\n-\tGPIO_IFN(SSI_SCK34),\n-\tGPIO_FN(MSIOF1_SS1_A),\n-\tGPIO_FN(STP_OPWM_0_A),\n-\n-\tGPIO_IFN(SSI_WS34),\n-\tGPIO_FN(HCTS2x_A),\n-\tGPIO_FN(MSIOF1_SS2_A),\n-\tGPIO_FN(STP_IVCXO27_0_A),\n-\n-\tGPIO_IFN(SSI_SDATA3),\n-\tGPIO_FN(HRTS2x_A),\n-\tGPIO_FN(MSIOF1_TXD_A),\n-\tGPIO_FN(TS_SCK0_A),\n-\tGPIO_FN(STP_ISCLK_0_A),\n-\tGPIO_FN(RIF0_D1_A),\n-\tGPIO_FN(RIF2_D0_A),\n-\n-\tGPIO_IFN(SSI_SCK4),\n-\tGPIO_FN(HRX2_A),\n-\tGPIO_FN(MSIOF1_SCK_A),\n-\tGPIO_FN(TS_SDAT0_A),\n-\tGPIO_FN(STP_ISD_0_A),\n-\tGPIO_FN(RIF0_CLK_A),\n-\tGPIO_FN(RIF2_CLK_A),\n-\n-\tGPIO_IFN(SSI_WS4),\n-\tGPIO_FN(HTX2_A),\n-\tGPIO_FN(MSIOF1_SYNC_A),\n-\tGPIO_FN(TS_SDEN0_A),\n-\tGPIO_FN(STP_ISEN_0_A),\n-\tGPIO_FN(RIF0_SYNC_A),\n-\tGPIO_FN(RIF2_SYNC_A),\n-\n-\tGPIO_IFN(SSI_SDATA4),\n-\tGPIO_FN(HSCK2_A),\n-\tGPIO_FN(MSIOF1_RXD_A),\n-\tGPIO_FN(TS_SPSYNC0_A),\n-\tGPIO_FN(STP_ISSYNC_0_A),\n-\tGPIO_FN(RIF0_D0_A),\n-\tGPIO_FN(RIF2_D1_A),\n-\n-\t/* IPSR16 */\n-\tGPIO_IFN(SSI_SCK6),\n-\tGPIO_FN(SIM0_RST_D),\n-\tGPIO_FN(FSO_TOE_A),\n-\n-\tGPIO_IFN(SSI_WS6),\n-\tGPIO_FN(SIM0_D_D),\n-\n-\tGPIO_IFN(SSI_SDATA6),\n-\tGPIO_FN(SIM0_CLK_D),\n-\n-\tGPIO_IFN(SSI_SCK78),\n-\tGPIO_FN(HRX2_B),\n-\tGPIO_FN(MSIOF1_SCK_C),\n-\tGPIO_FN(TS_SCK1_A),\n-\tGPIO_FN(STP_ISCLK_1_A),\n-\tGPIO_FN(RIF1_CLK_A),\n-\tGPIO_FN(RIF3_CLK_A),\n-\n-\tGPIO_IFN(SSI_WS78),\n-\tGPIO_FN(HTX2_B),\n-\tGPIO_FN(MSIOF1_SYNC_C),\n-\tGPIO_FN(TS_SDAT1_A),\n-\tGPIO_FN(STP_ISD_1_A),\n-\tGPIO_FN(RIF1_SYNC_A),\n-\tGPIO_FN(RIF3_SYNC_A),\n-\n-\tGPIO_IFN(SSI_SDATA7),\n-\tGPIO_FN(HCTS2x_B),\n-\tGPIO_FN(MSIOF1_RXD_C),\n-\tGPIO_FN(TS_SDEN1_A),\n-\tGPIO_FN(STP_IEN_1_A),\n-\tGPIO_FN(RIF1_D0_A),\n-\tGPIO_FN(RIF3_D0_A),\n-\tGPIO_FN(TCLK2_A),\n-\n-\tGPIO_IFN(SSI_SDATA8),\n-\tGPIO_FN(HRTS2x_B),\n-\tGPIO_FN(MSIOF1_TXD_C),\n-\tGPIO_FN(TS_SPSYNC1_A),\n-\tGPIO_FN(STP_ISSYNC_1_A),\n-\tGPIO_FN(RIF1_D1_A),\n-\tGPIO_FN(EIF3_D1_A),\n-\n-\tGPIO_IFN(SSI_SDATA9_A),\n-\tGPIO_FN(HSCK2_B),\n-\tGPIO_FN(MSIOF1_SS1_C),\n-\tGPIO_FN(HSCK1_A),\n-\tGPIO_FN(SSI_WS1_B),\n-\tGPIO_FN(SCK1),\n-\tGPIO_FN(STP_IVCXO27_1_A),\n-\tGPIO_FN(SCK5),\n-\n-\t/* IPSR17 */\n-\tGPIO_IFN(AUDIO_CLKA_A),\n-\tGPIO_FN(CC5_OSCOUT),\n-\n-\tGPIO_IFN(AUDIO_CLKB_B),\n-\tGPIO_FN(SCIF_CLK_A),\n-\tGPIO_FN(STP_IVCXO27_1_D),\n-\tGPIO_FN(REMOCON_A),\n-\tGPIO_FN(TCLK1_A),\n-\n-\tGPIO_IFN(USB0_PWEN),\n-\tGPIO_FN(SIM0_RST_C),\n-\tGPIO_FN(TS_SCK1_D),\n-\tGPIO_FN(STP_ISCLK_1_D),\n-\tGPIO_FN(BPFCLK_B),\n-\tGPIO_FN(RIF3_CLK_B),\n-\tGPIO_FN(FSO_CFE_1_A),\n-\tGPIO_FN(HSCK2_C),\n-\n-\tGPIO_IFN(USB0_OVC),\n-\tGPIO_FN(SIM0_D_C),\n-\tGPIO_FN(TS_SDAT1_D),\n-\tGPIO_FN(STP_ISD_1_D),\n-\tGPIO_FN(RIF3_SYNC_B),\n-\tGPIO_FN(HRX2_C),\n-\n-\tGPIO_IFN(USB1_PWEN),\n-\tGPIO_FN(SIM0_CLK_C),\n-\tGPIO_FN(SSI_SCK1_A),\n-\tGPIO_FN(TS_SCK0_E),\n-\tGPIO_FN(STP_ISCLK_0_E),\n-\tGPIO_FN(FMCLK_B),\n-\tGPIO_FN(RIF2_CLK_B),\n-\tGPIO_FN(SPEEDIN_A),\n-\tGPIO_FN(HTX2_C),\n-\n-\tGPIO_IFN(USB1_OVC),\n-\tGPIO_FN(MSIOF1_SS2_C),\n-\tGPIO_FN(SSI_WS1_A),\n-\tGPIO_FN(TS_SDAT0_E),\n-\tGPIO_FN(STP_ISD_0_E),\n-\tGPIO_FN(FMIN_B),\n-\tGPIO_FN(RIF2_SYNC_B),\n-\tGPIO_FN(REMOCON_B),\n-\tGPIO_FN(HCTS2x_C),\n-\n-\tGPIO_IFN(USB30_PWEN),\n-\tGPIO_FN(AUDIO_CLKOUT_B),\n-\tGPIO_FN(SSI_SCK2_B),\n-\tGPIO_FN(TS_SDEN1_D),\n-\tGPIO_FN(STP_ISEN_1_D),\n-\tGPIO_FN(STP_OPWM_0_E),\n-\tGPIO_FN(RIF3_D0_B),\n-\tGPIO_FN(TCLK2_B),\n-\tGPIO_FN(TPU0TO0),\n-\tGPIO_FN(BPFCLK_C),\n-\tGPIO_FN(HRTS2x_C),\n-\n-\tGPIO_IFN(USB30_OVC),\n-\tGPIO_FN(AUDIO_CLKOUT1_B),\n-\tGPIO_FN(SSI_WS2_B),\n-\tGPIO_FN(TS_SPSYNC1_D),\n-\tGPIO_FN(STP_ISSYNC_1_D),\n-\tGPIO_FN(STP_IVCXO27_0_E),\n-\tGPIO_FN(RIF3_D1_B),\n-\tGPIO_FN(FSO_TOE_B),\n-\tGPIO_FN(TPU0TO1),\n-\n-\t/* IPSR18 */\n-\tGPIO_IFN(GP6_30),\n-\tGPIO_FN(AUDIO_CLKOUT2_B),\n-\tGPIO_FN(SSI_SCK9_B),\n-\tGPIO_FN(TS_SDEN0_E),\n-\tGPIO_FN(STP_ISEN_0_E),\n-\tGPIO_FN(RIF2_D0_B),\n-\tGPIO_FN(FSO_CFE_0_A),\n-\tGPIO_FN(TPU0TO2),\n-\tGPIO_FN(FMCLK_C),\n-\tGPIO_FN(FMCLK_D),\n-\n-\tGPIO_IFN(GP6_31),\n-\tGPIO_FN(AUDIO_CLKOUT3_B),\n-\tGPIO_FN(SSI_WS9_B),\n-\tGPIO_FN(TS_SPSYNC0_E),\n-\tGPIO_FN(STP_ISSYNC_0_E),\n-\tGPIO_FN(RIF2_D1_B),\n-\tGPIO_FN(TPU0TO3),\n-\tGPIO_FN(FMIN_C),\n-\tGPIO_FN(FMIN_D),\n-};\n-\n-static struct pinmux_cfg_reg pinmux_config_regs[] = {\n-\t/* GPSR0(0xE6060100) md[3:1] controls initial value */\n-\t/*   md[3:1] .. 0     : 0x0000FFFF                  */\n-\t/*           .. other : 0x00000000                  */\n-\t{ PINMUX_CFG_REG(\"GPSR0\", 0xE6060100, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\tGP_0_15_FN, GFN_D15,\n-\t\tGP_0_14_FN, GFN_D14,\n-\t\tGP_0_13_FN, GFN_D13,\n-\t\tGP_0_12_FN, GFN_D12,\n-\t\tGP_0_11_FN, GFN_D11,\n-\t\tGP_0_10_FN, GFN_D10,\n-\t\tGP_0_9_FN, GFN_D9,\n-\t\tGP_0_8_FN, GFN_D8,\n-\t\tGP_0_7_FN, GFN_D7,\n-\t\tGP_0_6_FN, GFN_D6,\n-\t\tGP_0_5_FN, GFN_D5,\n-\t\tGP_0_4_FN, GFN_D4,\n-\t\tGP_0_3_FN, GFN_D3,\n-\t\tGP_0_2_FN, GFN_D2,\n-\t\tGP_0_1_FN, GFN_D1,\n-\t\tGP_0_0_FN, GFN_D0 }\n-\t},\n-\t/* GPSR1(0xE6060104) is md[3:1] controls initial value */\n-\t/*   md[3:1] .. 0     : 0x0EFFFFFF                     */\n-\t/*           .. other : 0x00000000                     */\n-\t{ PINMUX_CFG_REG(\"GPSR1\", 0xE6060104, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\tGP_1_28_FN, GFN_CLKOUT,\n-\t\tGP_1_27_FN, GFN_EX_WAIT0_A,\n-\t\tGP_1_26_FN, GFN_WE1x,\n-\t\tGP_1_25_FN, GFN_WE0x,\n-\t\tGP_1_24_FN, GFN_RD_WRx,\n-\t\tGP_1_23_FN, GFN_RDx,\n-\t\tGP_1_22_FN, GFN_BSx,\n-\t\tGP_1_21_FN, GFN_CS1x_A26,\n-\t\tGP_1_20_FN, GFN_CS0x,\n-\t\tGP_1_19_FN, GFN_A19,\n-\t\tGP_1_18_FN, GFN_A18,\n-\t\tGP_1_17_FN, GFN_A17,\n-\t\tGP_1_16_FN, GFN_A16,\n-\t\tGP_1_15_FN, GFN_A15,\n-\t\tGP_1_14_FN, GFN_A14,\n-\t\tGP_1_13_FN, GFN_A13,\n-\t\tGP_1_12_FN, GFN_A12,\n-\t\tGP_1_11_FN, GFN_A11,\n-\t\tGP_1_10_FN, GFN_A10,\n-\t\tGP_1_9_FN, GFN_A9,\n-\t\tGP_1_8_FN, GFN_A8,\n-\t\tGP_1_7_FN, GFN_A7,\n-\t\tGP_1_6_FN, GFN_A6,\n-\t\tGP_1_5_FN, GFN_A5,\n-\t\tGP_1_4_FN, GFN_A4,\n-\t\tGP_1_3_FN, GFN_A3,\n-\t\tGP_1_2_FN, GFN_A2,\n-\t\tGP_1_1_FN, GFN_A1,\n-\t\tGP_1_0_FN, GFN_A0 }\n-\t},\n-\t/* GPSR2(0xE6060108) is md[3:1] controls               */\n-\t/*   md[3:1] .. 0     : 0x000003C0                     */\n-\t/*           .. other : 0x00000200                     */\n-\t{ PINMUX_CFG_REG(\"GPSR2\", 0xE6060108, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\tGP_2_14_FN, GFN_AVB_AVTP_CAPTURE_A,\n-\t\tGP_2_13_FN, GFN_AVB_AVTP_MATCH_A,\n-\t\tGP_2_12_FN, GFN_AVB_LINK,\n-\t\tGP_2_11_FN, GFN_AVB_PHY_INT,\n-\t\tGP_2_10_FN, GFN_AVB_MAGIC,\n-\t\tGP_2_9_FN, GFN_AVB_MDC,\n-\t\tGP_2_8_FN, GFN_PWM2_A,\n-\t\tGP_2_7_FN, GFN_PWM1_A,\n-\t\tGP_2_6_FN, GFN_PWM0,\n-\t\tGP_2_5_FN, GFN_IRQ5,\n-\t\tGP_2_4_FN, GFN_IRQ4,\n-\t\tGP_2_3_FN, GFN_IRQ3,\n-\t\tGP_2_2_FN, GFN_IRQ2,\n-\t\tGP_2_1_FN, GFN_IRQ1,\n-\t\tGP_2_0_FN, GFN_IRQ0 }\n-\t},\n-\n-\t/* GPSR3 */\n-\t{ PINMUX_CFG_REG(\"GPSR3\", 0xE606010C, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\tGP_3_15_FN, GFN_SD1_WP,\n-\t\tGP_3_14_FN, GFN_SD1_CD,\n-\t\tGP_3_13_FN, GFN_SD0_WP,\n-\t\tGP_3_12_FN, GFN_SD0_CD,\n-\t\tGP_3_11_FN, GFN_SD1_DAT3,\n-\t\tGP_3_10_FN, GFN_SD1_DAT2,\n-\t\tGP_3_9_FN, GFN_SD1_DAT1,\n-\t\tGP_3_8_FN, GFN_SD1_DAT0,\n-\t\tGP_3_7_FN, GFN_SD1_CMD,\n-\t\tGP_3_6_FN, GFN_SD1_CLK,\n-\t\tGP_3_5_FN, GFN_SD0_DAT3,\n-\t\tGP_3_4_FN, GFN_SD0_DAT2,\n-\t\tGP_3_3_FN, GFN_SD0_DAT1,\n-\t\tGP_3_2_FN, GFN_SD0_DAT0,\n-\t\tGP_3_1_FN, GFN_SD0_CMD,\n-\t\tGP_3_0_FN, GFN_SD0_CLK }\n-\t},\n-\t/* GPSR4 */\n-\t{ PINMUX_CFG_REG(\"GPSR4\", 0xE6060110, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\tGP_4_17_FN, GFN_SD3_DS,\n-\t\tGP_4_16_FN, GFN_SD3_DAT7,\n-\n-\t\tGP_4_15_FN, GFN_SD3_DAT6,\n-\t\tGP_4_14_FN, GFN_SD3_DAT5,\n-\t\tGP_4_13_FN, GFN_SD3_DAT4,\n-\t\tGP_4_12_FN, FN_SD3_DAT3,\n-\t\tGP_4_11_FN, FN_SD3_DAT2,\n-\t\tGP_4_10_FN, FN_SD3_DAT1,\n-\t\tGP_4_9_FN, FN_SD3_DAT0,\n-\t\tGP_4_8_FN, FN_SD3_CMD,\n-\t\tGP_4_7_FN, FN_SD3_CLK,\n-\t\tGP_4_6_FN, GFN_SD2_DS,\n-\t\tGP_4_5_FN, GFN_SD2_DAT3,\n-\t\tGP_4_4_FN, GFN_SD2_DAT2,\n-\t\tGP_4_3_FN, GFN_SD2_DAT1,\n-\t\tGP_4_2_FN, GFN_SD2_DAT0,\n-\t\tGP_4_1_FN, FN_SD2_CMD,\n-\t\tGP_4_0_FN, GFN_SD2_CLK }\n-\t},\n-\t/* GPSR5 */\n-\t{ PINMUX_CFG_REG(\"GPSR5\", 0xE6060114, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\tGP_5_25_FN, GFN_MLB_DAT,\n-\t\tGP_5_24_FN, GFN_MLB_SIG,\n-\n-\t\tGP_5_23_FN, GFN_MLB_CLK,\n-\t\tGP_5_22_FN, FN_MSIOF0_RXD,\n-\t\tGP_5_21_FN, GFN_MSIOF0_SS2,\n-\t\tGP_5_20_FN, FN_MSIOF0_TXD,\n-\t\tGP_5_19_FN, GFN_MSIOF0_SS1,\n-\t\tGP_5_18_FN, GFN_MSIOF0_SYNC,\n-\t\tGP_5_17_FN, FN_MSIOF0_SCK,\n-\t\tGP_5_16_FN, GFN_HRTS0x,\n-\t\tGP_5_15_FN, GFN_HCTS0x,\n-\t\tGP_5_14_FN, GFN_HTX0,\n-\t\tGP_5_13_FN, GFN_HRX0,\n-\t\tGP_5_12_FN, GFN_HSCK0,\n-\t\tGP_5_11_FN, GFN_RX2_A,\n-\t\tGP_5_10_FN, GFN_TX2_A,\n-\t\tGP_5_9_FN, GFN_SCK2,\n-\t\tGP_5_8_FN, GFN_RTS1x_TANS,\n-\t\tGP_5_7_FN, GFN_CTS1x,\n-\t\tGP_5_6_FN, GFN_TX1_A,\n-\t\tGP_5_5_FN, GFN_RX1_A,\n-\t\tGP_5_4_FN, GFN_RTS0x_TANS,\n-\t\tGP_5_3_FN, GFN_CTS0x,\n-\t\tGP_5_2_FN, GFN_TX0,\n-\t\tGP_5_1_FN, GFN_RX0,\n-\t\tGP_5_0_FN, GFN_SCK0 }\n-\t},\n-\t/* GPSR6 */\n-\t{ PINMUX_CFG_REG(\"GPSR6\", 0xE6060118, 32, 1) {\n-\t\tGP_6_31_FN, GFN_GP6_31,\n-\t\tGP_6_30_FN, GFN_GP6_30,\n-\t\tGP_6_29_FN, GFN_USB30_OVC,\n-\t\tGP_6_28_FN, GFN_USB30_PWEN,\n-\t\tGP_6_27_FN, GFN_USB1_OVC,\n-\t\tGP_6_26_FN, GFN_USB1_PWEN,\n-\t\tGP_6_25_FN, GFN_USB0_OVC,\n-\t\tGP_6_24_FN, GFN_USB0_PWEN,\n-\t\tGP_6_23_FN, GFN_AUDIO_CLKB_B,\n-\t\tGP_6_22_FN, GFN_AUDIO_CLKA_A,\n-\t\tGP_6_21_FN, GFN_SSI_SDATA9_A,\n-\t\tGP_6_20_FN, GFN_SSI_SDATA8,\n-\t\tGP_6_19_FN, GFN_SSI_SDATA7,\n-\t\tGP_6_18_FN, GFN_SSI_WS78,\n-\t\tGP_6_17_FN, GFN_SSI_SCK78,\n-\t\tGP_6_16_FN, GFN_SSI_SDATA6,\n-\t\tGP_6_15_FN, GFN_SSI_WS6,\n-\t\tGP_6_14_FN, GFN_SSI_SCK6,\n-\t\tGP_6_13_FN, FN_SSI_SDATA5,\n-\t\tGP_6_12_FN, FN_SSI_WS5,\n-\t\tGP_6_11_FN, FN_SSI_SCK5,\n-\t\tGP_6_10_FN, GFN_SSI_SDATA4,\n-\t\tGP_6_9_FN, GFN_SSI_WS4,\n-\t\tGP_6_8_FN, GFN_SSI_SCK4,\n-\t\tGP_6_7_FN, GFN_SSI_SDATA3,\n-\t\tGP_6_6_FN, GFN_SSI_WS34,\n-\t\tGP_6_5_FN, GFN_SSI_SCK34,\n-\t\tGP_6_4_FN, GFN_SSI_SDATA2_A,\n-\t\tGP_6_3_FN, GFN_SSI_SDATA1_A,\n-\t\tGP_6_2_FN, GFN_SSI_SDATA0,\n-\t\tGP_6_1_FN, GFN_SSI_WS01239,\n-\t\tGP_6_0_FN, GFN_SSI_SCK01239 }\n-\t},\n-\t/* GPSR7 */\n-\t{ PINMUX_CFG_REG(\"GPSR7\", 0xE606011C, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\tGP_7_3_FN, FN_HDMI1_CEC,\n-\t\tGP_7_2_FN, FN_HDMI0_CEC,\n-\t\tGP_7_1_FN, FN_AVS2,\n-\t\tGP_7_0_FN, FN_AVS1 }\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR0\", 0xE6060200, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR0_31_28 [4] */\n-\t\tIFN_IRQ1, FN_QPOLA, 0, FN_DU_DISP,\n-\t\tFN_VI4_DATA1_B, FN_CAN0_RX_B, FN_CANFD0_RX_B,\n-\t\tFN_MSIOF3_SS1_E,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR0_27_24 [4] */\n-\t\tIFN_IRQ0, FN_QPOLB, 0, FN_DU_CDE,\n-\t\tFN_VI4_DATA0_B, FN_CAN0_TX_B, FN_CANFD0_TX_B,\n-\t\tFN_MSIOF3_SS2_E,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR0_23_20 [4] */\n-\t\tIFN_AVB_AVTP_CAPTURE_A, 0, FN_MSIOF2_TXD_C, FN_RTS4x_TANS_A,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR0_19_16 [4] */\n-\t\tIFN_AVB_AVTP_MATCH_A, 0, FN_MSIOF2_RXD_C, FN_CTS4x_A,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR0_15_12 [4] */\n-\t\tIFN_AVB_LINK, 0, FN_MSIOF2_SCK_C, FN_TX4_A,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR0_11_8 [4] */\n-\t\tIFN_AVB_PHY_INT, 0, FN_MSIOF2_SYNC_C, FN_RX4_A,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR0_7_4 [4] */\n-\t\tIFN_AVB_MAGIC, 0, FN_MSIOF2_SS1_C, FN_SCK4_A,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR0_3_0 [4] */\n-\t\tIFN_AVB_MDC, 0, FN_MSIOF2_SS2_C, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR1\", 0xE6060204, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR1_31_28 [4] */\n-\t\tIFN_A0, FN_LCDOUT16, FN_MSIOF3_SYNC_B, 0,\n-\t\tFN_VI4_DATA8, 0, FN_DU_DB0, 0,\n-\t\t0, FN_PWM3_A, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR1_27_24 [4] */\n-\t\tIFN_PWM2_A, FN_PWMFSW0, 0, FN_HTX3_D,\n-\t\t0, 0, 0, 0,\n-\t\t0, FN_IETX_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR1_23_20 [4] */\n-\t\tIFN_PWM1_A, 0, 0, FN_HRX3_D,\n-\t\tFN_VI4_DATA7_B, 0, 0, 0,\n-\t\t0, FN_IERX_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR1_19_16 [4] */\n-\t\tIFN_PWM0, FN_AVB_AVTP_PPS, 0, 0,\n-\t\tFN_VI4_DATA6_B, 0, 0, 0,\n-\t\t0, FN_IECLK_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR1_15_12 [4] */\n-\t\tIFN_IRQ5, FN_QSTB_QHE, 0, FN_DU_EXVSYNC_DU_VSYNC,\n-\t\tFN_VI4_DATA5_B, 0, 0, FN_MSIOF3_TXD_E,\n-\t\t0, FN_PWM6_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR1_11_8 [4] */\n-\t\tIFN_IRQ4, FN_QSTH_QHS, 0, FN_DU_EXHSYNC_DU_HSYNC,\n-\t\tFN_VI4_DATA4_B, 0, 0, FN_MSIOF3_RXD_E,\n-\t\t0, FN_PWM5_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR1_7_4 [4] */\n-\t\tIFN_IRQ3, FN_QSTVB_QVE, 0, FN_DU_DOTCLKOUT1,\n-\t\tFN_VI4_DATA3_B, 0, 0, FN_MSIOF3_SCK_E,\n-\t\t0, FN_PWM4_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR1_3_0 [4] */\n-\t\tIFN_IRQ2, FN_QCPV_QDE, 0, FN_DU_EXODDF_DU_ODDF_DISP_CDE,\n-\t\tFN_VI4_DATA2_B, 0, 0, FN_MSIOF3_SYNC_E,\n-\t\t0, FN_PWM3_B, 0, 0,\n-\t\t0, 0, 0, 0\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR2\", 0xE6060208, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR2_31_28 [4] */\n-\t\tIFN_A8, FN_RX3_B, FN_MSIOF2_SYNC_A, FN_HRX4_B,\n-\t\t0, 0, 0, FN_SDA6_A,\n-\t\tFN_AVB_AVTP_MATCH_B, FN_PWM1_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR2_27_24 [4] */\n-\t\tIFN_A7, FN_LCDOUT23, FN_MSIOF2_SS2_A, FN_TX4_B,\n-\t\tFN_VI4_DATA15, FN_V15_DATA15, FN_DU_DB7, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR2_23_20 [4] */\n-\t\tIFN_A6, FN_LCDOUT22, FN_MSIOF2_SS1_A, FN_RX4_B,\n-\t\tFN_VI4_DATA14, FN_VI5_DATA14, FN_DU_DB6, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR2_19_16 [4] */\n-\t\tIFN_A5, FN_LCDOUT21, FN_MSIOF3_SS2_B, FN_SCK4_B,\n-\t\tFN_VI4_DATA13, FN_VI5_DATA13, FN_DU_DB5, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR2_15_12 [4] */\n-\t\tIFN_A4, FN_LCDOUT20, FN_MSIOF3_SS1_B, 0,\n-\t\tFN_VI4_DATA12, FN_VI5_DATA12, FN_DU_DB4, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR2_11_8 [4] */\n-\t\tIFN_A3, FN_LCDOUT19, FN_MSIOF3_RXD_B, 0,\n-\t\tFN_VI4_DATA11, 0, FN_DU_DB3, 0,\n-\t\t0, FN_PWM6_A, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR2_7_4 [4] */\n-\t\tIFN_A2, FN_LCDOUT18, FN_MSIOF3_SCK_B, 0,\n-\t\tFN_VI4_DATA10, 0, FN_DU_DB2, 0,\n-\t\t0, FN_PWM5_A, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR2_3_0 [4] */\n-\t\tIFN_A1, FN_LCDOUT17, FN_MSIOF3_TXD_B, 0,\n-\t\tFN_VI4_DATA9, 0, FN_DU_DB1, 0,\n-\t\t0, FN_PWM4_A, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR3\", 0xE606020C, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR3_31_28 [4] */\n-\t\tIFN_A16, FN_LCDOUT8, 0, 0,\n-\t\tFN_VI4_FIELD, 0, FN_DU_DG0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR3_27_24 [4] */\n-\t\tIFN_A15, FN_LCDOUT15, FN_MSIOF3_TXD_C, 0,\n-\t\tFN_HRTS4x, FN_VI5_DATA11, FN_DU_DG7, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR3_23_20 [4] */\n-\t\tIFN_A14, FN_LCDOUT14, FN_MSIOF3_RXD_C, 0,\n-\t\tFN_HCTS4x, FN_VI5_DATA10, FN_DU_DG6, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR3_19_16 [4] */\n-\t\tIFN_A13, FN_LCDOUT13, FN_MSIOF3_SYNC_C, 0,\n-\t\tFN_HTX4_A, FN_VI5_DATA9, FN_DU_DG5, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR3_15_12 [4] */\n-\t\tIFN_A12, FN_LCDOUT12, FN_MSIOF3_SCK_C, 0,\n-\t\tFN_HRX4_A, FN_VI5_DATA8, FN_DU_DG4, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR3_11_8 [4] */\n-\t\tIFN_A11, FN_TX3_B, FN_MSIOF2_TXD_A, FN_HTX4_B,\n-\t\tFN_HSCK4, FN_VI5_FIELD, 0, FN_SCL6_A,\n-\t\tFN_AVB_AVTP_CAPTURE_B, FN_PWM2_B, FN_SPV_EVEN, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR3_7_4 [4] */\n-\t\tIFN_A10, 0, FN_MSIOF2_RXD_A, FN_RTS4n_TANS_B,\n-\t\t0, FN_VI5_HSYNCx, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR3_3_0 [4] */\n-\t\tIFN_A9, 0, FN_MSIOF2_SCK_A, FN_CTS4x_B,\n-\t\t0, FN_VI5_VSYNCx, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR4\", 0xE6060210, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR4_31_28 [4] */\n-\t\tIFN_RD_WRx, 0, FN_MSIOF3_RXD_D, FN_TX3_A,\n-\t\tFN_HTX3_A, 0, 0, 0,\n-\t\tFN_CAN0_RX_A, FN_CANFD0_RX_A, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR4_27_24 [4] */\n-\t\tIFN_RDx, 0, FN_MSIOF3_SYNC_D, FN_RX3_A,\n-\t\tFN_HRX3_A, 0, 0, 0,\n-\t\tFN_CAN0_TX_A, FN_CANFD0_TX_A, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR4_23_20 [4] */\n-\t\tIFN_BSx, FN_QSTVA_QVS, FN_MSIOF3_SCK_D, FN_SCK3,\n-\t\tFN_HSCK3, 0, 0, 0,\n-\t\tFN_CAN1_TX, FN_CANFD1_TX, FN_IETX_A, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR4_19_16 [4] */\n-\t\tIFN_CS1x_A26, 0, 0, 0,\n-\t\t0, FN_VI5_CLK, 0, FN_EX_WAIT0_B,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR4_15_12 [4] */\n-\t\tIFN_CS0x, 0, 0, 0,\n-\t\t0, FN_VI5_CLKENB, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR4_11_8 [4] */\n-\t\tIFN_A19, FN_LCDOUT11, 0, 0,\n-\t\tFN_VI4_CLKENB, 0, FN_DU_DG3, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR4_7_4 [4] */\n-\t\tIFN_A18, FN_LCDOUT10, 0, 0,\n-\t\tFN_VI4_HSYNCx, 0, FN_DU_DG2, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR4_3_0 [4] */\n-\t\tIFN_A17, FN_LCDOUT9, 0, 0,\n-\t\tFN_VI4_VSYNCx, 0, FN_DU_DG1, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR5\", 0xE6060214, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR5_31_28 [4] */\n-\t\tIFN_D4, FN_MSIOF2_SCK_B, 0, 0,\n-\t\tFN_VI4_DATA20, FN_VI5_DATA4, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR5_27_24 [4] */\n-\t\tIFN_D3, 0, FN_MSIOF3_TXD_A, 0,\n-\t\tFN_VI4_DATA19, FN_VI5_DATA3, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR5_23_20 [4] */\n-\t\tIFN_D2, 0, FN_MSIOF3_RXD_A, 0,\n-\t\tFN_VI4_DATA18, FN_VI5_DATA2, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR5_19_16 [4] */\n-\t\tIFN_D1, FN_MSIOF2_SS2_B, FN_MSIOF3_SYNC_A, 0,\n-\t\tFN_VI4_DATA17, FN_VI5_DATA1, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR5_15_12 [4] */\n-\t\tIFN_D0, FN_MSIOF2_SS1_B, FN_MSIOF3_SCK_A, 0,\n-\t\tFN_VI4_DATA16, FN_VI5_DATA0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR5_11_8 [4] */\n-\t\tIFN_EX_WAIT0_A, FN_QCLK, 0, 0,\n-\t\tFN_VI4_CLK, 0, FN_DU_DOTCLKOUT0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR5_7_4 [4] */\n-\t\tIFN_WE1x, 0, FN_MSIOF3_SS1_D, FN_RTS3x_TANS,\n-\t\tFN_HRTS3x, 0, 0, FN_SDA6_B,\n-\t\tFN_CAN1_RX, FN_CANFD1_RX, FN_IERX_A, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR5_3_0 [4] */\n-\t\tIFN_WE0x, 0, FN_MSIIOF3_TXD_D, FN_CTS3x,\n-\t\tFN_HCTS3x, 0, 0, FN_SCL6_B,\n-\t\tFN_CAN_CLK, 0, FN_IECLK_A, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR6\", 0xE6060218, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR6_31_28 [4] */\n-\t\tIFN_D12, FN_LCDOUT4, FN_MSIOF2_SS1_D, FN_RX4_C,\n-\t\tFN_VI4_DATA4_A, 0, FN_DU_DR4, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR6_27_24 [4] */\n-\t\tIFN_D11, FN_LCDOUT3, FN_MSIOF2_TXD_D, FN_HTX3_B,\n-\t\tFN_VI4_DATA3_A, FN_RTS4x_TANS_C, FN_DU_DR3, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR6_23_20 [4] */\n-\t\tIFN_D10, FN_LCDOUT2, FN_MSIOF2_RXD_D, FN_HRX3_B,\n-\t\tFN_VI4_DATA2_A, FN_CTS4x_C, FN_DU_DR2, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR6_19_16 [4] */\n-\t\tIFN_D9, FN_LCDOUT1, FN_MSIOF2_SYNC_D, 0,\n-\t\tFN_VI4_DATA1_A, 0, FN_DU_DR1, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR6_15_12 [4] */\n-\t\tIFN_D8, FN_LCDOUT0, FN_MSIOF2_SCK_D, FN_SCK4_C,\n-\t\tFN_VI4_DATA0_A, 0, FN_DU_DR0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR6_11_8 [4] */\n-\t\tIFN_D7, FN_MSIOF2_TXD_B, 0, 0,\n-\t\tFN_VI4_DATA23, FN_VI5_DATA7, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR6_7_4 [4] */\n-\t\tIFN_D6, FN_MSIOF2_RXD_B, 0, 0,\n-\t\tFN_VI4_DATA22, FN_VI5_DATA6, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR6_3_0 [4] */\n-\t\tIFN_D5, FN_MSIOF2_SYNC_B, 0, 0,\n-\t\tFN_VI4_DATA21, FN_VI5_DATA5, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR7\", 0xE606021C, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR7_31_28 [4] */\n-\t\tIFN_SD0_DAT1, 0, FN_MSIOF1_TXD_E, 0,\n-\t\t0, FN_TS_SPSYNC0_B, FN_STP_ISSYNC_0_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR7_27_24 [4] */\n-\t\tIFN_SD0_DAT0, 0, FN_MSIOF1_RXD_E, 0,\n-\t\t0, FN_TS_SCK0_B, FN_STP_ISCLK_0_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR7_23_20 [4] */\n-\t\tIFN_SD0_CMD, 0, FN_MSIOF1_SYNC_E, 0,\n-\t\t0, 0, FN_STP_IVCXO27_0_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR7_19_16 [4] */\n-\t\tIFN_SD0_CLK, 0, FN_MSIOF1_SCK_E, 0,\n-\t\t0, 0, FN_STP_OPWM_0_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR7_15_12 [4] */\n-\t\tFN_FSCLKST, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR7_11_8 [4] */\n-\t\tIFN_D15, FN_LCDOUT7, FN_MSIOF3_SS2_A, FN_HTX3_C,\n-\t\tFN_VI4_DATA7_A, 0, FN_DU_DR7, FN_SDA6_C,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR7_7_4 [4] */\n-\t\tIFN_D14, FN_LCDOUT6, FN_MSIOF3_SS1_A, FN_HRX3_C,\n-\t\tFN_VI4_DATA6_A, 0, FN_DU_DR6, FN_SCL6_C,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR7_3_0 [4] */\n-\t\tIFN_D13, FN_LCDOUT5, FN_MSIOF2_SS2_D, FN_TX4_C,\n-\t\tFN_VI4_DATA5_A, 0, FN_DU_DR5, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR8\", 0xE6060220, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR8_31_28 [4] */\n-\t\tIFN_SD1_DAT3, FN_SD2_DAT7, FN_MSIOF1_SS2_G,\n-\t\tFN_NFRBx_B,\n-\t\t0, FN_TS_SDEN1_B, FN_STP_ISEN_1_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR8_27_24 [4] */\n-\t\tIFN_SD1_DAT2, FN_SD2_DAT6, FN_MSIOF1_SS1_G,\n-\t\tFN_NFDATA15_B,\n-\t\t0, FN_TS_SDAT1_B, FN_STP_IOD_1_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR8_23_20 [4] */\n-\t\tIFN_SD1_DAT1, FN_SD2_DAT5, FN_MSIOF1_TXD_G,\n-\t\tFN_NFDATA14_B,\n-\t\t0, FN_TS_SPSYNC1_B, FN_STP_ISSYNC_1_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR8_19_16 [4] */\n-\t\tIFN_SD1_DAT0, FN_SD2_DAT4, FN_MSIOF1_RXD_G,\n-\t\tFN_NFWPx_B,\n-\t\t0, FN_TS_SCK1_B, FN_STP_ISCLK_1_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR8_15_12 [4] */\n-\t\tIFN_SD1_CMD, 0, FN_MSIOF1_SYNC_G,\n-\t\tFN_NFCEx_B,\n-\t\t0, FN_SIM0_D_A, FN_STP_IVCXO27_1_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR8_11_8 [4] */\n-\t\tIFN_SD1_CLK, 0, FN_MSIOF1_SCK_G, 0,\n-\t\t0, FN_SIM0_CLK_A, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR8_7_4 [4] */\n-\t\tIFN_SD0_DAT3, 0, FN_MSIOF1_SS2_E, 0,\n-\t\t0, FN_TS_SDEN0_B, FN_STP_ISEN_0_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR8_3_0 [4] */\n-\t\tIFN_SD0_DAT2, 0, FN_MSIOF1_SS1_E, 0,\n-\t\t0, FN_TS_SDAT0_B, FN_STP_ISD_0_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR9\", 0xE6060224, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR9_31_28 [4] */\n-\t\tIFN_SD3_CLK, 0, FN_NFWEx, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR9_27_24 [4] */\n-\t\tIFN_SD2_DS, 0, FN_NFALE, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR9_23_20 [4] */\n-\t\tIFN_SD2_DAT3, 0, FN_NFDATA13, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR9_19_16 [4] */\n-\t\tIFN_SD2_DAT2, 0, FN_NFDATA12, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR9_15_12 [4] */\n-\t\tIFN_SD2_DAT1, 0, FN_NFDATA11, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR9_11_8 [4] */\n-\t\tIFN_SD2_DAT0, 0, FN_NFDATA10, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR9_7_4 [4] */\n-\t\tIFN_SD2_CMD, 0, FN_NFDATA9, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR9_3_0 [4] */\n-\t\tIFN_SD3_CLK, 0, FN_NFDATA8, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR10\", 0xE6060228, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR10_31_28 [4] */\n-\t\tIFN_SD3_DAT6, FN_SD3_CD, FN_NFDATA6, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR10_27_24 [4] */\n-\t\tIFN_SD3_DAT5, FN_SD2_WP_A, FN_NFDATA5, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR10_23_20 [4] */\n-\t\tIFN_SD3_DAT4, FN_SD2_CD_A, FN_NFDATA4, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR10_19_16 [4] */\n-\t\tIFN_SD3_DAT3, 0, FN_NFDATA3, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR10_15_12 [4] */\n-\t\tIFN_SD3_DAT2, 0, FN_NFDATA2, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR10_11_8 [4] */\n-\t\tIFN_SD3_DAT1, 0, FN_NFDATA1, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR10_7_4 [4] */\n-\t\tIFN_SD3_DAT0, 0, FN_NFDATA0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR10_3_0 [4] */\n-\t\tIFN_SD3_CMD, 0, FN_NFREx, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR11\", 0xE606022C, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR11_31_28 [4] */\n-\t\tIFN_RX0, FN_HRX1_B, 0, 0,\n-\t\t0, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, FN_RIF0_D0_B,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR11_27_24 [4] */\n-\t\tIFN_SCK0, FN_HSCK1_B, FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B,\n-\t\tFN_SDA2_A, FN_SIM0_RST_B, FN_STP_OPWM_0_C,\n-\t\tFN_RIF0_CLK_B,\n-\t\t0, FN_ADICHS2, 0, FN_RIF0_CLK_B,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR11_23_20 [4] */\n-\t\tIFN_SD1_WP, 0, FN_NFCEx_A, 0,\n-\t\t0, FN_SIM0_D_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR11_19_16 [4] */\n-\t\tIFN_SD1_CD, 0, FN_NFRBx_A, 0,\n-\t\t0, FN_SIM0_CLK_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR11_15_12 [4] */\n-\t\tIFN_SD0_WP, 0, FN_NFDATA15_A, 0,\n-\t\tFN_SDA2_B, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR11_11_8 [4] */\n-\t\tIFN_SD0_CD, 0, FN_NFDATA14_A, 0,\n-\t\tFN_SCL2_B, FN_SIM0_RST_A, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR11_7_4 [4] */\n-\t\tIFN_SD3_DS, 0, FN_NFCLE, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR11_3_0 [4] */\n-\t\tIFN_SD3_DAT7, FN_SD3_WP, FN_NFDATA7, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR12\", 0xE6060230, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR12_31_28 [4] */\n-\t\tIFN_SCK2, FN_SCIF_CLK_B, FN_MSIOF1_SCK_B, 0,\n-\t\t0, FN_TS_SCK1_C, FN_STP_ISCLK_1_C, FN_RIF1_CLK_B,\n-\t\t0, FN_ADICLK, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR12_27_24 [4] */\n-\t\tIFN_RTS1x_TANS, FN_HRTS1x_A, FN_MSIOF1_TXD_B, 0,\n-\t\t0, FN_TS_SDAT1_C, FN_STP_ISD_1_C, FN_RIF1_D1_B,\n-\t\t0, FN_ADICHS0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR12_23_20 [4] */\n-\t\tIFN_CTS1x, FN_HCTS1x_A, FN_MSIOF1_RXD_B, 0,\n-\t\t0, FN_TS_SDEN1_C, FN_STP_ISEN_1_C, FN_RIF1_D0_B,\n-\t\t0, FN_ADIDATA, 0, 0,\n-\t\t/* IPSR12_19_16 [4] */\n-\t\tIFN_TX1_A, FN_HTX1_A, 0, 0,\n-\t\t0, FN_TS_SDEN0_C, FN_STP_ISEN_0_C, FN_RIF1_D0_C,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR12_15_12 [4] */\n-\t\tIFN_RX1_A, FN_HRX1_A, 0, 0,\n-\t\t0, FN_TS_SDAT0_C, FN_STP_ISD_0_C, FN_RIF1_CLK_C,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR12_11_8 [4] */\n-\t\tIFN_RTS0x_TANS, FN_HRTS1x_B, FN_MSIOF1_SS1_B, FN_AUDIO_CLKA_B,\n-\t\tFN_SCL2_A, 0, FN_STP_IVCXO27_1_C, FN_RIF0_SYNC_B,\n-\t\t0, FN_ADICHS1, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR12_7_4 [4] */\n-\t\tIFN_CTS0x, FN_HCTS1x_B, FN_MSIOF1_SYNC_B, 0,\n-\t\t0, FN_TS_SPSYNC1_C, FN_STP_ISSYNC_1_C, FN_RIF1_SYNC_B,\n-\t\tFN_AUDIO_CLKOUT_C, FN_ADICS_SAMP, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR12_3_0 [4] */\n-\t\tIFN_TX0, FN_HTX1_B, 0, 0,\n-\t\t0, FN_TS_SPSYNC0_C, FN_STP_ISSYNC_0_C, FN_RIF0_D1_B,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR13\", 0xE6060234, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR13_31_28 [4] */\n-\t\tIFN_MSIOF0_SYNC, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\tFN_AUDIO_CLKOUT_A, 0, FN_TX5_B, 0,\n-\t\t0, FN_BPFCLK_D, 0, 0,\n-\t\t/* IPSR13_27_24 [4] */\n-\t\tIFN_HRTS0x, FN_TX2_B, FN_MSIOF1_SS1_D, 0,\n-\t\tFN_SSI_WS9_A, 0, FN_STP_IVCXO27_0_D, FN_BPFCLK_A,\n-\t\tFN_AUDIO_CLKOUT2_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR13_23_20 [4] */\n-\t\tIFN_HCTS0x, FN_RX2_B, FN_MSIOF1_SYNC_D, 0,\n-\t\tFN_SSI_SCK9_A, FN_TS_SPSYNC0_D, FN_STP_ISSYNC_0_D,\n-\t\tFN_RIF0_SYNC_C,\n-\t\tFN_AUDIO_CLKOUT1_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR13_19_16 [4] */\n-\t\tIFN_HTX0, 0, FN_MSIOF1_TXD_D, 0,\n-\t\tFN_SSI_SDATA9_B, FN_TS_SDAT0_D, FN_STP_ISD_0_D, FN_RIF0_D1_C,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR13_15_12 [4] */\n-\t\tIFN_HRX0, 0, FN_MSIOF1_RXD_D, 0,\n-\t\tFN_SS1_SDATA2_B, FN_TS_SDEN0_D, FN_STP_ISEN_0_D, FN_RIF0_D0_C,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR13_11_8 [4] */\n-\t\tIFN_HSCK0, 0, FN_MSIOF1_SCK_D, FN_AUDIO_CLKB_A,\n-\t\tFN_SSI_SDATA1_B, FN_TS_SCK0_D, FN_STP_ISCLK_0_D, FN_RIF0_CLK_C,\n-\t\t0, 0, FN_RX5_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR13_7_4 [4] */\n-\t\tIFN_RX2_A, 0, 0, FN_SD2_WP_B,\n-\t\tFN_SDA1_A, 0, FN_FMIN_A, FN_RIF1_SYNC_C,\n-\t\t0, FN_FSO_CEF_1_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR13_3_0 [4] */\n-\t\tIFN_TX2_A, 0, 0, FN_SD2_CD_B,\n-\t\tFN_SCL1_A, 0, FN_FMCLK_A, FN_RIF1_D1_C,\n-\t\t0, FN_FSO_CFE_0_B, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR14\", 0xE6060238, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR14_31_28 [4] */\n-\t\tIFN_SSI_SDATA0, 0, FN_MSIOF1_SS2_F, 0,\n-\t\t0, 0, 0, FN_MOUT2,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR14_27_24 [4] */\n-\t\tIFN_SSI_WS0129, 0, FN_MSIOF1_SS1_F, 0,\n-\t\t0, 0, 0, FN_MOUT1,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR14_23_20 [4] */\n-\t\tIFN_SSI_SCK0129, 0, FN_MSIOF1_TXD_F, 0,\n-\t\t0, 0, 0, FN_MOUT0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR14_19_16 [4] */\n-\t\tIFN_MLB_DAT, FN_TX1_B, FN_MSIOF1_RXD_F, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR14_15_12 [4] */\n-\t\tIFN_MLB_SIG, FN_RX1_B, FN_MSIOF1_SYNC_F, 0,\n-\t\tFN_SDA1_B, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR14_11_8 [4] */\n-\t\tIFN_MLB_CLK, 0, FN_MSIOF1_SCK_F, 0,\n-\t\tFN_SCL1_B, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR14_7_4 [4] */\n-\t\tIFN_MSIOF0_SS2, FN_TX5_A, FN_MSIOF1_SS2_D, FN_AUDIO_CLKC_A,\n-\t\tFN_SSI_WS2_A, 0, FN_STP_OPWM_0_D, 0,\n-\t\tFN_AUDIO_CLKOUT_D, 0, FN_SPEEDIN_B, 0,\n-\t\t/* IPSR14_3_0 [4] */\n-\t\tIFN_MSIOF0_SS1, FN_RX5_A, 0, FN_AUDIO_CLKA_C,\n-\t\tFN_SSI_SCK2_A, 0, FN_STP_IVCXO27_0_C, 0,\n-\t\tFN_AUDIO_CLKOUT3_A, 0, FN_TCLK1_B, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR15\", 0xE606023C, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR15_31_28 [4] */\n-\t\tIFN_SSI_SDATA4, FN_HSCK2_A, FN_MSIOF1_RXD_A, 0,\n-\t\t0, FN_TS_SPSYNC0_A, FN_STP_ISSYNC_0_A, FN_RIF0_D0_A,\n-\t\tFN_RIF2_D1_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR15_27_24 [4] */\n-\t\tIFN_SSI_WS4, FN_HTX2_A, FN_MSIOF1_SYNC_A, 0,\n-\t\t0, FN_TS_SDEN0_A, FN_STP_ISEN_0_A, FN_RIF0_SYNC_A,\n-\t\tFN_RIF2_SYNC_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR15_23_20 [4] */\n-\t\tIFN_SSI_SCK4, FN_HRX2_A, FN_MSIOF1_SCK_A, 0,\n-\t\t0, FN_TS_SDAT0_A, FN_STP_ISD_0_A, FN_RIF0_CLK_A,\n-\t\tFN_RIF2_CLK_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR15_19_16 [4] */\n-\t\tIFN_SSI_SDATA3, FN_HRTS2x_A, FN_MSIOF1_TXD_A, 0,\n-\t\t0, FN_TS_SCK0_A, FN_STP_ISCLK_0_A, FN_RIF0_D1_A,\n-\t\tFN_RIF2_D0_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR15_15_12 [4] */\n-\t\tIFN_SSI_WS34, FN_HCTS2x_A, FN_MSIOF1_SS2_A, 0,\n-\t\t0, 0, FN_STP_IVCXO27_0_A, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR15_11_8 [4] */\n-\t\tIFN_SSI_SCK34, 0, FN_MSIOF1_SS1_A, 0,\n-\t\t0, 0, FN_STP_OPWM_0_A, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR15_7_4 [4] */\n-\t\tIFN_SSI_SDATA2_A, 0, 0, 0,\n-\t\tFN_SSI_SCK1_B, 0, 0, FN_MOUT6,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR15_3_0 [4] */\n-\t\tIFN_SSI_SDATA1_A, 0, 0, 0,\n-\t\t0, 0, 0, FN_MOUT5,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR16\", 0xE6060240, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR16_31_28 [4] */\n-\t\tIFN_SSI_SDATA9_A, FN_HSCK2_B, FN_MSIOF1_SS1_C, FN_HSCK1_A,\n-\t\tFN_SSI_WS1_B, FN_SCK1, FN_STP_IVCXO27_1_A, FN_SCK5,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR16_27_24 [4] */\n-\t\tIFN_SSI_SDATA8, FN_HRTS2x_B, FN_MSIOF1_TXD_C, 0,\n-\t\t0, FN_TS_SPSYNC1_A, FN_STP_ISSYNC_1_A, FN_RIF1_D1_A,\n-\t\tFN_EIF3_D1_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR16_23_20 [4] */\n-\t\tIFN_SSI_SDATA7, FN_HCTS2x_B, FN_MSIOF1_RXD_C, 0,\n-\t\t0, FN_TS_SDEN1_A, FN_STP_IEN_1_A, FN_RIF1_D0_A,\n-\t\tFN_RIF3_D0_A, 0, FN_TCLK2_A, 0,\n-\t\t/* IPSR16_19_16 [4] */\n-\t\tIFN_SSI_WS78, FN_HTX2_B, FN_MSIOF1_SYNC_C, 0,\n-\t\t0, FN_TS_SDAT1_A, FN_STP_ISD_1_A, FN_RIF1_SYNC_A,\n-\t\tFN_RIF3_SYNC_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR16_15_12 [4] */\n-\t\tIFN_SSI_SCK78, FN_HRX2_B, FN_MSIOF1_SCK_C, 0,\n-\t\t0, FN_TS_SCK1_A, FN_STP_ISCLK_1_A, FN_RIF1_CLK_A,\n-\t\tFN_RIF3_CLK_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR16_11_8 [4] */\n-\t\tIFN_SSI_SDATA6, 0, 0, FN_SIM0_CLK_D,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR16_7_4 [4] */\n-\t\tIFN_SSI_WS6, 0, 0, FN_SIM0_D_D,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR16_3_0 [4] */\n-\t\tIFN_SSI_SCK6, 0, 0, FN_SIM0_RST_D,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, FN_FSO_TOE_A, 0,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR17\", 0xE6060244, 32,\n-\t\t\t\t4, 4, 4, 4, 4, 4, 4, 4) {\n-\t\t/* IPSR17_31_28 [4] */\n-\t\tIFN_USB30_OVC, 0, FN_AUDIO_CLKOUT1_B, 0,\n-\t\tFN_SSI_WS2_B, FN_TS_SPSYNC1_D, FN_STP_ISSYNC_1_D,\n-\t\tFN_STP_IVCXO27_0_E,\n-\t\tFN_RIF3_D1_B, 0, FN_FSO_TOE_B, FN_TPU0TO1,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR17_27_24 [4] */\n-\t\tIFN_USB30_PWEN, 0, 0, FN_AUDIO_CLKOUT_B,\n-\t\tFN_SSI_SCK2_B, FN_TS_SDEN1_D, FN_STP_ISEN_1_D, FN_STP_OPWM_0_E,\n-\t\tFN_RIF3_D0_B, 0, FN_TCLK2_B, FN_TPU0TO0,\n-\t\tFN_BPFCLK_C, FN_HRTS2x_C, 0, 0,\n-\t\t/* IPSR17_23_20 [4] */\n-\t\tIFN_USB1_OVC, 0, FN_MSIOF1_SS2_C, 0,\n-\t\tFN_SSI_WS1_A, FN_TS_SDAT0_E, FN_STP_ISD_0_E, FN_FMIN_B,\n-\t\tFN_RIF2_SYNC_B, 0, FN_REMOCON_B, 0,\n-\t\t0, FN_HCTS2x_C, 0, 0,\n-\t\t/* IPSR17_19_16 [4] */\n-\t\tIFN_USB1_PWEN, 0, 0, FN_SIM0_CLK_C,\n-\t\tFN_SSI_SCK1_A, FN_TS_SCK0_E, FN_STP_ISCLK_0_E, FN_FMCLK_B,\n-\t\tFN_RIF2_CLK_B, 0, FN_SPEEDIN_A, 0,\n-\t\t0, FN_HTX2_C, 0, 0,\n-\t\t/* IPSR17_15_12 [4] */\n-\t\tIFN_USB0_OVC, 0, 0, FN_SIM0_D_C,\n-\t\t0, FN_TS_SDAT1_D, FN_STP_ISD_1_D, 0,\n-\t\tFN_RIF3_SYNC_B, 0, 0, 0,\n-\t\t0, FN_HRX2_C, 0, 0,\n-\t\t/* IPSR17_11_8 [4] */\n-\t\tIFN_USB0_PWEN, 0, 0, FN_SIM0_RST_C,\n-\t\t0, FN_TS_SCK1_D, FN_STP_ISCLK_1_D, FN_BPFCLK_B,\n-\t\tFN_RIF3_CLK_B, 0, FN_FSO_CFE_1_A, 0,\n-\t\t0, FN_HSCK2_C, 0, 0,\n-\t\t/* IPSR17_7_4 [4] */\n-\t\tIFN_AUDIO_CLKB_B, FN_SCIF_CLK_A, 0, 0,\n-\t\t0, 0, FN_STP_IVCXO27_1_D, FN_REMOCON_A,\n-\t\t0, 0, FN_TCLK1_A, 0,\n-\t\t0, 0, 0, 0,\n-\t\t/* IPSR17_3_0 [4] */\n-\t\tIFN_AUDIO_CLKA_A, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, 0, FN_CC5_OSCOUT,\n-\t\t0, 0, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"IPSR18\", 0xE6060248, 32,\n-\t\t\t\t1, 1, 1, 1, 1, 1, 1, 1,\n-\t\t\t\t1, 1, 1, 1, 1, 1, 1, 1,\n-\t\t\t\t1, 1, 1, 1, 1, 1, 1, 1,\n-\t\t\t\t4, 4) {\n-\t\t/* reserved [31..24] */\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t/* reserved [23..16] */\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t/* reserved [15..8] */\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t/* IPSR18_7_4 [4] */\n-\t\tIFN_GP6_31, 0, 0, FN_AUDIO_CLKOUT3_B,\n-\t\tFN_SSI_WS9_B, FN_TS_SPSYNC0_E, FN_STP_ISSYNC_0_E, 0,\n-\t\tFN_RIF2_D1_B, 0, 0, FN_TPU0TO3,\n-\t\tFN_FMIN_C, FN_FMIN_D, 0, 0,\n-\t\t/* IPSR18_3_0 [4] */\n-\t\tIFN_GP6_30, 0, 0, FN_AUDIO_CLKOUT2_B,\n-\t\tFN_SSI_SCK9_B, FN_TS_SDEN0_E, FN_STP_ISEN_0_E, 0,\n-\t\tFN_RIF2_D0_B, 0, FN_FSO_CFE_0_A, FN_TPU0TO2,\n-\t\tFN_FMCLK_C, FN_FMCLK_D, 0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"MOD_SEL0\", 0xE6060500, 32,\n-\t\t\t\t3, 2, 3,\n-\t\t\t\t1, 1, 1, 1, 1, 2, 1,\n-\t\t\t\t1, 2, 1, 1, 1, 2,\n-\t\t\t\t2, 1, 2, 1, 1, 1) {\n-\t\t/* SEL_MSIOF3 [3] */\n-\t\tFN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1,\n-\t\tFN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3,\n-\t\tFN_SEL_MSIOF3_4, FN_SEL_MSIOF3_5,\n-\t\tFN_SEL_MSIOF3_6, 0,\n-\t\t/* SEL_MSIOF2 [2] */\n-\t\tFN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1,\n-\t\tFN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3,\n-\t\t/* SEL_MSIOF1 [3] */\n-\t\tFN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,\n-\t\tFN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3,\n-\t\tFN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5,\n-\t\tFN_SEL_MSIOF1_6, 0,\n-\n-\t\t/* SEL_LBSC [1] */\n-\t\tFN_SEL_LBSC_0, FN_SEL_LBSC_1,\n-\t\t/* SEL_IEBUS [1] */\n-\t\tFN_SEL_IEBUS_0, FN_SEL_IEBUS_1,\n-\t\t/* SEL_I2C2 [1] */\n-\t\tFN_SEL_I2C2_0, FN_SEL_I2C2_1,\n-\t\t/* SEL_I2C1 [1] */\n-\t\tFN_SEL_I2C1_0, FN_SEL_I2C1_1,\n-\t\t/* SEL_HSCIF4 [1] */\n-\t\tFN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1,\n-\t\t/* SEL_HSCIF3 [2] */\n-\t\tFN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1,\n-\t\tFN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3,\n-\t\t/* SEL_HSCIF1 [1] */\n-\t\tFN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1,\n-\n-\t\t/* SEL_FSO [1] */\n-\t\tFN_SEL_FSO_0, FN_SEL_FSO_1,\n-\t\t/* SEL_HSCIF2 [2] */\n-\t\tFN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,\n-\t\tFN_SEL_HSCIF2_2, 0,\n-\t\t/* SEL_ETHERAVB [1] */\n-\t\tFN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1,\n-\t\t/* SEL_DRIF3 [1] */\n-\t\tFN_SEL_DRIF3_0, FN_SEL_DRIF3_1,\n-\t\t/* SEL_DRIF2 [1] */\n-\t\tFN_SEL_DRIF2_0, FN_SEL_DRIF2_1,\n-\t\t/* SEL_DRIF1 [2] */\n-\t\tFN_SEL_DRIF1_0, FN_SEL_DRIF1_1,\n-\t\tFN_SEL_DRIF1_2, 0,\n-\n-\t\t/* SEL_DRIF0 [2] */\n-\t\tFN_SEL_DRIF0_0, FN_SEL_DRIF0_1,\n-\t\tFN_SEL_DRIF0_2, 0,\n-\t\t/* SEL_CANFD0 [1] */\n-\t\tFN_SEL_CANFD_0, FN_SEL_CANFD_1,\n-\t\t/* SEL_ADG [2] */\n-\t\tFN_SEL_ADG_0, FN_SEL_ADG_1,\n-\t\tFN_SEL_ADG_2, FN_SEL_ADG_3,\n-\t\t/* reserved [3] */\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"MOD_SEL1\", 0xE6060504, 32,\n-\t\t\t\t2, 3, 1, 2,\n-\t\t\t\t3, 1, 1, 2, 1,\n-\t\t\t\t2, 1, 1, 1, 1, 1, 1,\n-\t\t\t\t1, 1, 1, 1, 1, 1, 1, 1) {\n-\t\t/* SEL_TSIF1 [2] */\n-\t\tFN_SEL_TSIF1_0,\n-\t\tFN_SEL_TSIF1_1,\n-\t\tFN_SEL_TSIF1_2,\n-\t\tFN_SEL_TSIF1_3,\n-\t\t/* SEL_TSIF0 [3] */\n-\t\tFN_SEL_TSIF0_0,\n-\t\tFN_SEL_TSIF0_1,\n-\t\tFN_SEL_TSIF0_2,\n-\t\tFN_SEL_TSIF0_3,\n-\t\tFN_SEL_TSIF0_4,\n-\t\t0,\n-\t\t0,\n-\t\t0,\n-\t\t/* SEL_TIMER_TMU [1] */\n-\t\tFN_SEL_TIMER_TMU_0,\n-\t\tFN_SEL_TIMER_TMU_1,\n-\t\t/* SEL_SSP1_1 [2] */\n-\t\tFN_SEL_SSP1_1_0,\n-\t\tFN_SEL_SSP1_1_1,\n-\t\tFN_SEL_SSP1_1_2,\n-\t\tFN_SEL_SSP1_1_3,\n-\n-\t\t/* SEL_SSP1_0 [3] */\n-\t\tFN_SEL_SSP1_0_0,\n-\t\tFN_SEL_SSP1_0_1,\n-\t\tFN_SEL_SSP1_0_2,\n-\t\tFN_SEL_SSP1_0_3,\n-\t\tFN_SEL_SSP1_0_4,\n-\t\t0,\n-\t\t0,\n-\t\t0,\n-\t\t/* SEL_SSI [1] */\n-\t\tFN_SEL_SSI_0,\n-\t\tFN_SEL_SSI_1,\n-\t\t/* SEL_SPEED_PULSE_IF [1] */\n-\t\tFN_SEL_SPEED_PULSE_IF_0,\n-\t\tFN_SEL_SPEED_PULSE_IF_1,\n-\t\t/* SEL_SIMCARD [2] */\n-\t\tFN_SEL_SIMCARD_0,\n-\t\tFN_SEL_SIMCARD_1,\n-\t\tFN_SEL_SIMCARD_2,\n-\t\tFN_SEL_SIMCARD_3,\n-\t\t/* SEL_SDHI2 [1] */\n-\t\tFN_SEL_SDHI2_0,\n-\t\tFN_SEL_SDHI2_1,\n-\n-\t\t/* SEL_SCIF4 [2] */\n-\t\tFN_SEL_SCIF4_0,\n-\t\tFN_SEL_SCIF4_1,\n-\t\tFN_SEL_SCIF4_2,\n-\t\t0,\n-\t\t/* SEL_SCIF3 [1] */\n-\t\tFN_SEL_SCIF3_0,\n-\t\tFN_SEL_SCIF3_1,\n-\t\t/* SEL_SCIF2 [1] */\n-\t\tFN_SEL_SCIF2_0,\n-\t\tFN_SEL_SCIF2_1,\n-\t\t/* SEL_SCIF1 [1] */\n-\t\tFN_SEL_SCIF1_0,\n-\t\tFN_SEL_SCIF1_1,\n-\t\t/* SEL_SCIF [1] */\n-\t\tFN_SEL_SCIF_0,\n-\t\tFN_SEL_SCIF_1,\n-\t\t/* SEL_REMOCON [1] */\n-\t\tFN_SEL_REMOCON_0,\n-\t\tFN_SEL_REMOCON_1,\n-\t\t/* reserved [2] */\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t/* SEL_RCAN [1] */\n-\t\tFN_SEL_RCAN_0,\n-\t\tFN_SEL_RCAN_1,\n-\t\t/* SEL_PWM6 [1] */\n-\t\tFN_SEL_PWM6_0,\n-\t\tFN_SEL_PWM6_1,\n-\t\t/* SEL_PWM5 [1] */\n-\t\tFN_SEL_PWM5_0,\n-\t\tFN_SEL_PWM5_1,\n-\t\t/* SEL_PWM4 [1] */\n-\t\tFN_SEL_PWM4_0,\n-\t\tFN_SEL_PWM4_1,\n-\t\t/* SEL_PWM3 [1] */\n-\t\tFN_SEL_PWM3_0,\n-\t\tFN_SEL_PWM3_1,\n-\t\t/* SEL_PWM2 [1] */\n-\t\tFN_SEL_PWM2_0,\n-\t\tFN_SEL_PWM2_1,\n-\t\t/* SEL_PWM1 [1] */\n-\t\tFN_SEL_PWM1_0,\n-\t\tFN_SEL_PWM1_1,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG_VAR(\"MOD_SEL2\", 0xE6060508, 32,\n-\t\t\t\t\t\t1, 1, 1, 2, 1,\n-\t\t\t\t\t\t3, 1, 1, 1, 1, 1, 1,\n-\t\t\t\t\t\t1, 1, 1, 1, 1, 1, 1, 1,\n-\t\t\t\t\t\t1, 1, 1, 1, 1, 1, 1, 1,\n-\t\t\t\t\t\t1) {\n-\t\t/* I2C_SEL_5 [1] */\n-\t\tFN_I2C_SEL_5_0,\n-\t\tFN_I2C_SEL_5_1,\n-\t\t/* I2C_SEL_3 [1] */\n-\t\tFN_I2C_SEL_3_0,\n-\t\tFN_I2C_SEL_3_1,\n-\t\t/* I2C_SEL_0 [1] */\n-\t\tFN_I2C_SEL_0_0,\n-\t\tFN_I2C_SEL_0_1,\n-\t\t/* SEL_FM [2] */\n-\t\tFN_SEL_FM_0,\n-\t\tFN_SEL_FM_1,\n-\t\tFN_SEL_FM_2,\n-\t\tFN_SEL_FM_3,\n-\t\t/* SEL_SCIF5 [1] */\n-\t\tFN_SEL_SCIF5_0,\n-\t\tFN_SEL_SCIF5_1,\n-\n-\t\t/* SEL_I2C6 [3] */\n-\t\tFN_SEL_I2C6_0,\n-\t\tFN_SEL_I2C6_1,\n-\t\tFN_SEL_I2C6_2,\n-\t\t0,\n-\t\t0,\n-\t\t0,\n-\t\t0,\n-\t\t0,\n-\t\t/* SEL_NDF [1] */\n-\t\tFN_SEL_NDF_0,\n-\t\tFN_SEL_NDF_1,\n-\t\t/* SEL_SSI2 [1] */\n-\t\tFN_SEL_SSI2_0,\n-\t\tFN_SEL_SSI2_1,\n-\t\t/* SEL_SSI9 [1] */\n-\t\tFN_SEL_SSI9_0,\n-\t\tFN_SEL_SSI9_1,\n-\t\t/* SEL_TIMER_TME2 [1] */\n-\t\tFN_SEL_TIMER_TMU2_0,\n-\t\tFN_SEL_TIMER_TMU2_1,\n-\t\t/* SEL_ADG_B [1] */\n-\t\tFN_SEL_ADG_B_0,\n-\t\tFN_SEL_ADG_B_1,\n-\n-\t\t/* SEL_ADG_C [1] */\n-\t\tFN_SEL_ADG_C_0,\n-\t\tFN_SEL_ADG_C_1,\n-\t\t/* reserved [16] */\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t/* SEL_VIN4 [1] */\n-\t\tFN_SEL_VIN4_0,\n-\t\tFN_SEL_VIN4_1,\n-\t\t}\n-\t},\n-\n-\t/* under construction */\n-\t{ PINMUX_CFG_REG(\"INOUTSEL0\", 0xE6050004, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\tGP_0_15_IN, GP_0_15_OUT,\n-\t\tGP_0_14_IN, GP_0_14_OUT,\n-\t\tGP_0_13_IN, GP_0_13_OUT,\n-\t\tGP_0_12_IN, GP_0_12_OUT,\n-\t\tGP_0_11_IN, GP_0_11_OUT,\n-\t\tGP_0_10_IN, GP_0_10_OUT,\n-\t\tGP_0_9_IN, GP_0_9_OUT,\n-\t\tGP_0_8_IN, GP_0_8_OUT,\n-\t\tGP_0_7_IN, GP_0_7_OUT,\n-\t\tGP_0_6_IN, GP_0_6_OUT,\n-\t\tGP_0_5_IN, GP_0_5_OUT,\n-\t\tGP_0_4_IN, GP_0_4_OUT,\n-\t\tGP_0_3_IN, GP_0_3_OUT,\n-\t\tGP_0_2_IN, GP_0_2_OUT,\n-\t\tGP_0_1_IN, GP_0_1_OUT,\n-\t\tGP_0_0_IN, GP_0_0_OUT,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG(\"INOUTSEL1\", 0xE6051004, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\tGP_1_28_IN, GP_1_28_OUT,\n-\t\tGP_1_27_IN, GP_1_27_OUT,\n-\t\tGP_1_26_IN, GP_1_26_OUT,\n-\t\tGP_1_25_IN, GP_1_25_OUT,\n-\t\tGP_1_24_IN, GP_1_24_OUT,\n-\t\tGP_1_23_IN, GP_1_23_OUT,\n-\t\tGP_1_22_IN, GP_1_22_OUT,\n-\t\tGP_1_21_IN, GP_1_21_OUT,\n-\t\tGP_1_20_IN, GP_1_20_OUT,\n-\t\tGP_1_19_IN, GP_1_19_OUT,\n-\t\tGP_1_18_IN, GP_1_18_OUT,\n-\t\tGP_1_17_IN, GP_1_17_OUT,\n-\t\tGP_1_16_IN, GP_1_16_OUT,\n-\t\tGP_1_15_IN, GP_1_15_OUT,\n-\t\tGP_1_14_IN, GP_1_14_OUT,\n-\t\tGP_1_13_IN, GP_1_13_OUT,\n-\t\tGP_1_12_IN, GP_1_12_OUT,\n-\t\tGP_1_11_IN, GP_1_11_OUT,\n-\t\tGP_1_10_IN, GP_1_10_OUT,\n-\t\tGP_1_9_IN, GP_1_9_OUT,\n-\t\tGP_1_8_IN, GP_1_8_OUT,\n-\t\tGP_1_7_IN, GP_1_7_OUT,\n-\t\tGP_1_6_IN, GP_1_6_OUT,\n-\t\tGP_1_5_IN, GP_1_5_OUT,\n-\t\tGP_1_4_IN, GP_1_4_OUT,\n-\t\tGP_1_3_IN, GP_1_3_OUT,\n-\t\tGP_1_2_IN, GP_1_2_OUT,\n-\t\tGP_1_1_IN, GP_1_1_OUT,\n-\t\tGP_1_0_IN, GP_1_0_OUT,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG(\"INOUTSEL2\", 0xE6052004, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\tGP_2_14_IN, GP_2_14_OUT,\n-\t\tGP_2_13_IN, GP_2_13_OUT,\n-\t\tGP_2_12_IN, GP_2_12_OUT,\n-\t\tGP_2_11_IN, GP_2_11_OUT,\n-\t\tGP_2_10_IN, GP_2_10_OUT,\n-\t\tGP_2_9_IN, GP_2_9_OUT,\n-\t\tGP_2_8_IN, GP_2_8_OUT,\n-\t\tGP_2_7_IN, GP_2_7_OUT,\n-\t\tGP_2_6_IN, GP_2_6_OUT,\n-\t\tGP_2_5_IN, GP_2_5_OUT,\n-\t\tGP_2_4_IN, GP_2_4_OUT,\n-\t\tGP_2_3_IN, GP_2_3_OUT,\n-\t\tGP_2_2_IN, GP_2_2_OUT,\n-\t\tGP_2_1_IN, GP_2_1_OUT,\n-\t\tGP_2_0_IN, GP_2_0_OUT,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG(\"INOUTSEL3\", 0xE6053004, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\tGP_3_15_IN, GP_3_15_OUT,\n-\t\tGP_3_14_IN, GP_3_14_OUT,\n-\t\tGP_3_13_IN, GP_3_13_OUT,\n-\t\tGP_3_12_IN, GP_3_12_OUT,\n-\t\tGP_3_11_IN, GP_3_11_OUT,\n-\t\tGP_3_10_IN, GP_3_10_OUT,\n-\t\tGP_3_9_IN, GP_3_9_OUT,\n-\t\tGP_3_8_IN, GP_3_8_OUT,\n-\t\tGP_3_7_IN, GP_3_7_OUT,\n-\t\tGP_3_6_IN, GP_3_6_OUT,\n-\t\tGP_3_5_IN, GP_3_5_OUT,\n-\t\tGP_3_4_IN, GP_3_4_OUT,\n-\t\tGP_3_3_IN, GP_3_3_OUT,\n-\t\tGP_3_2_IN, GP_3_2_OUT,\n-\t\tGP_3_1_IN, GP_3_1_OUT,\n-\t\tGP_3_0_IN, GP_3_0_OUT,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG(\"INOUTSEL4\", 0xE6054004, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\tGP_4_17_IN, GP_4_17_OUT,\n-\t\tGP_4_16_IN, GP_4_16_OUT,\n-\n-\t\tGP_4_15_IN, GP_4_15_OUT,\n-\t\tGP_4_14_IN, GP_4_14_OUT,\n-\t\tGP_4_13_IN, GP_4_13_OUT,\n-\t\tGP_4_12_IN, GP_4_12_OUT,\n-\t\tGP_4_11_IN, GP_4_11_OUT,\n-\t\tGP_4_10_IN, GP_4_10_OUT,\n-\t\tGP_4_9_IN, GP_4_9_OUT,\n-\t\tGP_4_8_IN, GP_4_8_OUT,\n-\t\tGP_4_7_IN, GP_4_7_OUT,\n-\t\tGP_4_6_IN, GP_4_6_OUT,\n-\t\tGP_4_5_IN, GP_4_5_OUT,\n-\t\tGP_4_4_IN, GP_4_4_OUT,\n-\t\tGP_4_3_IN, GP_4_3_OUT,\n-\t\tGP_4_2_IN, GP_4_2_OUT,\n-\t\tGP_4_1_IN, GP_4_1_OUT,\n-\t\tGP_4_0_IN, GP_4_0_OUT,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG(\"INOUTSEL5\", 0xE6055004, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\tGP_5_25_IN, GP_5_25_OUT,\n-\t\tGP_5_24_IN, GP_5_24_OUT,\n-\n-\t\tGP_5_23_IN, GP_5_23_OUT,\n-\t\tGP_5_22_IN, GP_5_22_OUT,\n-\t\tGP_5_21_IN, GP_5_21_OUT,\n-\t\tGP_5_20_IN, GP_5_20_OUT,\n-\t\tGP_5_19_IN, GP_5_19_OUT,\n-\t\tGP_5_18_IN, GP_5_18_OUT,\n-\t\tGP_5_17_IN, GP_5_17_OUT,\n-\t\tGP_5_16_IN, GP_5_16_OUT,\n-\n-\t\tGP_5_15_IN, GP_5_15_OUT,\n-\t\tGP_5_14_IN, GP_5_14_OUT,\n-\t\tGP_5_13_IN, GP_5_13_OUT,\n-\t\tGP_5_12_IN, GP_5_12_OUT,\n-\t\tGP_5_11_IN, GP_5_11_OUT,\n-\t\tGP_5_10_IN, GP_5_10_OUT,\n-\t\tGP_5_9_IN, GP_5_9_OUT,\n-\t\tGP_5_8_IN, GP_5_8_OUT,\n-\t\tGP_5_7_IN, GP_5_7_OUT,\n-\t\tGP_5_6_IN, GP_5_6_OUT,\n-\t\tGP_5_5_IN, GP_5_5_OUT,\n-\t\tGP_5_4_IN, GP_5_4_OUT,\n-\t\tGP_5_3_IN, GP_5_3_OUT,\n-\t\tGP_5_2_IN, GP_5_2_OUT,\n-\t\tGP_5_1_IN, GP_5_1_OUT,\n-\t\tGP_5_0_IN, GP_5_0_OUT,\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG(\"INOUTSEL6\", 0xE6055404, 32, 1) {\n-\t\tGP_INOUTSEL(6)\n-\t\t}\n-\t},\n-\t{ PINMUX_CFG_REG(\"INOUTSEL7\", 0xE6055804, 32, 1) {\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\t0, 0,\n-\t\tGP_6_3_IN, GP_6_3_OUT,\n-\t\tGP_6_2_IN, GP_6_2_OUT,\n-\t\tGP_6_1_IN, GP_6_1_OUT,\n-\t\tGP_6_0_IN, GP_6_0_OUT,\n-\t\t}\n-\t},\n-\t{ },\n-};\n-\n-static struct pinmux_data_reg pinmux_data_regs[] = {\n-\t/* use OUTDT registers? */\n-\t{ PINMUX_DATA_REG(\"INDT0\", 0xE6050008, 32) {\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\tGP_0_15_DATA, GP_0_14_DATA, GP_0_13_DATA, GP_0_12_DATA,\n-\t\tGP_0_11_DATA, GP_0_10_DATA, GP_0_9_DATA, GP_0_8_DATA,\n-\t\tGP_0_7_DATA, GP_0_6_DATA, GP_0_5_DATA, GP_0_4_DATA,\n-\t\tGP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA }\n-\t},\n-\t{ PINMUX_DATA_REG(\"INDT1\", 0xE6051008, 32) {\n-\t\t0, 0, 0, GP_1_28_DATA,\n-\t\tGP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA,\n-\t\tGP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,\n-\t\tGP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,\n-\t\tGP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,\n-\t\tGP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,\n-\t\tGP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,\n-\t\tGP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }\n-\t},\n-\t{ PINMUX_DATA_REG(\"INDT2\", 0xE6052008, 32) {\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\t0, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA,\n-\t\tGP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA,\n-\t\tGP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA,\n-\t\tGP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA }\n-\t},\n-\t{ PINMUX_DATA_REG(\"INDT3\", 0xE6053008, 32) {\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\tGP_3_15_DATA, GP_3_14_DATA, GP_3_13_DATA, GP_3_12_DATA,\n-\t\tGP_3_11_DATA, GP_3_10_DATA, GP_3_9_DATA, GP_3_8_DATA,\n-\t\tGP_3_7_DATA, GP_3_6_DATA, GP_3_5_DATA, GP_3_4_DATA,\n-\t\tGP_3_3_DATA, GP_3_2_DATA, GP_3_1_DATA, GP_3_0_DATA }\n-\t},\n-\t{ PINMUX_DATA_REG(\"INDT4\", 0xE6054008, 32) {\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\t0, 0, 0, 0, 0, 0, GP_4_17_DATA, GP_4_16_DATA,\n-\t\tGP_4_15_DATA, GP_4_14_DATA, GP_4_13_DATA, GP_4_12_DATA,\n-\t\tGP_4_11_DATA, GP_4_10_DATA, GP_4_9_DATA, GP_4_8_DATA,\n-\t\tGP_4_7_DATA, GP_4_6_DATA, GP_4_5_DATA, GP_4_4_DATA,\n-\t\tGP_4_3_DATA, GP_4_2_DATA, GP_4_1_DATA, GP_4_0_DATA }\n-\t},\n-\t{ PINMUX_DATA_REG(\"INDT5\", 0xE6055008, 32) {\n-\t\t0, 0, 0, 0,\n-\t\t0, 0, GP_5_25_DATA, GP_5_24_DATA,\n-\t\tGP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA,\n-\t\tGP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA,\n-\t\tGP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA,\n-\t\tGP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,\n-\t\tGP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,\n-\t\tGP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }\n-\t},\n-\t{ PINMUX_DATA_REG(\"INDT6\", 0xE6055408, 32) {\n-\t\tGP_INDT(6) }\n-\t},\n-\t{ PINMUX_DATA_REG(\"INDT7\", 0xE6055808, 32) {\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\t0, 0, 0, 0, 0, 0, 0, 0,\n-\t\t0, 0, 0, 0,\n-\t\tGP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA }\n-\t},\n-\t{ },\n-};\n-\n-static struct pinmux_info r8a7796_pinmux_info = {\n-\t.name = \"r8a7796_pfc\",\n-\n-\t.unlock_reg = 0xe6060000, /* PMMR */\n-\n-\t.reserved_id = PINMUX_RESERVED,\n-\t.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },\n-\t.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },\n-\t.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },\n-\t.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },\n-\t.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },\n-\n-\t.first_gpio = GPIO_GP_0_0,\n-\t.last_gpio = GPIO_FN_FMIN_D,\n-\n-\t.gpios = pinmux_gpios,\n-\t.cfg_regs = pinmux_config_regs,\n-\t.data_regs = pinmux_data_regs,\n-\n-\t.gpio_data = pinmux_data,\n-\t.gpio_data_size = ARRAY_SIZE(pinmux_data),\n-};\n-\n-void r8a7796_pinmux_init(void)\n-{\n-\tregister_pinmux(&r8a7796_pinmux_info);\n-}\n",
    "prefixes": [
        "U-Boot",
        "5/5"
    ]
}