Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 814382,
    "url": "http://patchwork.ozlabs.org/api/1.2/patches/814382/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170915191359.28712-1-marek.vasut+renesas@gmail.com/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170915191359.28712-1-marek.vasut+renesas@gmail.com>",
    "list_archive_url": null,
    "date": "2017-09-15T19:13:55",
    "name": "[U-Boot,1/5] pinctrl: rmobile: Add Renesas RCar pincontrol driver",
    "commit_ref": "910df4d07e370dc0dabafaaf85417508cccf43f3",
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "d16e275b2b439dfc3326ab9dd9882b9f87c163fa",
    "submitter": {
        "id": 1124,
        "url": "http://patchwork.ozlabs.org/api/1.2/people/1124/?format=api",
        "name": "Marek Vasut",
        "email": "marek.vasut@gmail.com"
    },
    "delegate": {
        "id": 1750,
        "url": "http://patchwork.ozlabs.org/api/1.2/users/1750/?format=api",
        "username": "iwamatsu",
        "first_name": "Nobuhiro",
        "last_name": "Iwamatsu",
        "email": "iwamatsu@nigauri.org"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170915191359.28712-1-marek.vasut+renesas@gmail.com/mbox/",
    "series": [
        {
            "id": 3365,
            "url": "http://patchwork.ozlabs.org/api/1.2/series/3365/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=3365",
            "date": "2017-09-15T19:13:58",
            "name": "[U-Boot,1/5] pinctrl: rmobile: Add Renesas RCar pincontrol driver",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/3365/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/814382/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/814382/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<u-boot-bounces@lists.denx.de>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Authentication-Results": [
            "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)",
            "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"NZCrVHJh\"; dkim-atps=neutral"
        ],
        "Received": [
            "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xv5GV3901z9s0Z\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 16 Sep 2017 05:35:30 +1000 (AEST)",
            "by lists.denx.de (Postfix, from userid 105)\n\tid DA1E5C221C6; Fri, 15 Sep 2017 19:23:25 +0000 (UTC)",
            "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id E19AFC21F63;\n\tFri, 15 Sep 2017 19:22:48 +0000 (UTC)",
            "by lists.denx.de (Postfix, from userid 105)\n\tid C3C34C21EE9; Fri, 15 Sep 2017 19:14:12 +0000 (UTC)",
            "from mail-wr0-f194.google.com (mail-wr0-f194.google.com\n\t[209.85.128.194])\n\tby lists.denx.de (Postfix) with ESMTPS id 3515CC21EF0\n\tfor <u-boot@lists.denx.de>; Fri, 15 Sep 2017 19:14:06 +0000 (UTC)",
            "by mail-wr0-f194.google.com with SMTP id b9so1784276wra.0\n\tfor <u-boot@lists.denx.de>; Fri, 15 Sep 2017 12:14:06 -0700 (PDT)",
            "from kurokawa.lan (ip-86-49-107-50.net.upcbroadband.cz.\n\t[86.49.107.50]) by smtp.gmail.com with ESMTPSA id\n\ta39sm1710995wrc.48.2017.09.15.12.14.02\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tFri, 15 Sep 2017 12:14:02 -0700 (PDT)"
        ],
        "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de",
        "X-Spam-Level": "",
        "X-Spam-Status": "No, score=0.0 required=5.0 tests=FREEMAIL_FROM,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,\n\tT_DKIM_INVALID autolearn=unavailable\n\tautolearn_force=no version=3.4.0",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id;\n\tbh=TRaob9epvE2nMFOAH1K5qbfvWXPkuhbSd18sBmLr/Qk=;\n\tb=NZCrVHJhjno+bA9h4ZfW5DEXKgu1LA1iyvMAyL+Abq/hr59qo2aPWsHfkXdPp7azK0\n\ti6V0+bsMAZEW+pSnsWnYikXp8WAF53POD+ztlFy6K4P9/M5HgxQSSuzux77X+hyeys1Z\n\tr0oQO2Y92PDjXmEOGE+5IxLYrM+NKmIM4avz08L5cyTjsPyNF5HC0sanaUcnUu3xV9t2\n\tkGn2E3+i9Kp20GxAydYqnH+AUvvNOwz0LepLhRa//PLKw9NLOzS2hrZ3bL8myouyq8iP\n\tecSgZXXDE7VusEoP3F/6C8th9tIggcIhjL83c2gaIc8ue4n56zrTGKfhlbnbtghRF9K+\n\tYbzg==",
        "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id;\n\tbh=TRaob9epvE2nMFOAH1K5qbfvWXPkuhbSd18sBmLr/Qk=;\n\tb=nCENI4RKqxRBtVoSZPDFR8rKgzwDNiDBCf7QSlw7D+BvnsVhwcxvebPQLMu0trEmJW\n\tpt9/nikyhWMNJpmM7EodEqz2BB7RCNRcGilEguLdX5r3PkyOwmwlImX9ePrLmUUc+Ofo\n\tILC/gPVwR/Vh0aCcwDN7//1kFfV1F3qrY/4r/nUvbZf53A2XGADUsgvxeBt3xQ531gHk\n\tWp4XBg22sbS5oqDjx722pRR7DQOSd9CKr+//jF6UhoO5Q8zOKQspgnR0YfiU7x58A64R\n\thRM+Ws6HTSYdBSU1gnjyuGwwJyfZkac/LVTG7mX/zUxDqhEz2vH+e2oBQj768DyYoc69\n\tcinA==",
        "X-Gm-Message-State": "AHPjjUhSJ+wO1/FNMta5nt5UYD3mm19Lj88BLpgStSrQPahdjZq8snUh\n\tHJmTs7ZvVOdQGbrA51s=",
        "X-Google-Smtp-Source": "ADKCNb6um49yLJmzjd3BHxjloJFCFPo6jaC3+15N9UvK/0sncKLKop7Hc5Hx1FiGtkiMc103UbNWcw==",
        "X-Received": "by 10.223.143.14 with SMTP id p14mr21056576wrb.133.1505502843796;\n\tFri, 15 Sep 2017 12:14:03 -0700 (PDT)",
        "From": "Marek Vasut <marek.vasut@gmail.com>",
        "X-Google-Original-From": "Marek Vasut <marek.vasut+renesas@gmail.com>",
        "To": "u-boot@lists.denx.de",
        "Date": "Fri, 15 Sep 2017 21:13:55 +0200",
        "Message-Id": "<20170915191359.28712-1-marek.vasut+renesas@gmail.com>",
        "X-Mailer": "git-send-email 2.11.0",
        "X-Mailman-Approved-At": "Fri, 15 Sep 2017 19:22:46 +0000",
        "Cc": "Marek Vasut <marek.vasut+renesas@gmail.com>",
        "Subject": "[U-Boot] [PATCH 1/5] pinctrl: rmobile: Add Renesas RCar pincontrol\n\tdriver",
        "X-BeenThere": "u-boot@lists.denx.de",
        "X-Mailman-Version": "2.1.18",
        "Precedence": "list",
        "List-Id": "U-Boot discussion <u-boot.lists.denx.de>",
        "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>",
        "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>",
        "List-Post": "<mailto:u-boot@lists.denx.de>",
        "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>",
        "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain; charset=\"utf-8\"",
        "Content-Transfer-Encoding": "base64",
        "Errors-To": "u-boot-bounces@lists.denx.de",
        "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>"
    },
    "content": "Add PFC pincontrol driver for the Renesas RCar Gen3 R8A7795 and R8A7796\nSoCs. This driver uses the PFC pin tables from Linux, thus letting us\nshare the occassional fixes to those tables. This driver also has a DT\nsupport, so the pinmux is configured from DT instead of the ad-hoc setup\nin board file.\n\nThis driver is meant to replace the pinmux part of SH_GPIO_PFC driver.\n\nSigned-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>\nCc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>\n---\n drivers/pinctrl/Kconfig               |    1 +\n drivers/pinctrl/Makefile              |    1 +\n drivers/pinctrl/renesas/Kconfig       |   31 +\n drivers/pinctrl/renesas/Makefile      |    3 +\n drivers/pinctrl/renesas/pfc-r8a7795.c | 4898 ++++++++++++++++++++++++++++\n drivers/pinctrl/renesas/pfc-r8a7796.c | 5728 +++++++++++++++++++++++++++++++++\n drivers/pinctrl/renesas/pfc.c         |  565 ++++\n drivers/pinctrl/renesas/sh_pfc.h      |  575 ++++\n 8 files changed, 11802 insertions(+)\n create mode 100644 drivers/pinctrl/renesas/Kconfig\n create mode 100644 drivers/pinctrl/renesas/Makefile\n create mode 100644 drivers/pinctrl/renesas/pfc-r8a7795.c\n create mode 100644 drivers/pinctrl/renesas/pfc-r8a7796.c\n create mode 100644 drivers/pinctrl/renesas/pfc.c\n create mode 100644 drivers/pinctrl/renesas/sh_pfc.h",
    "diff": "diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig\nindex bcbe4a18c1..afca56dff1 100644\n--- a/drivers/pinctrl/Kconfig\n+++ b/drivers/pinctrl/Kconfig\n@@ -292,6 +292,7 @@ endif\n \n source \"drivers/pinctrl/meson/Kconfig\"\n source \"drivers/pinctrl/nxp/Kconfig\"\n+source \"drivers/pinctrl/renesas/Kconfig\"\n source \"drivers/pinctrl/uniphier/Kconfig\"\n source \"drivers/pinctrl/exynos/Kconfig\"\n source \"drivers/pinctrl/mvebu/Kconfig\"\ndiff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile\nindex 64da7c608b..8c04028dfb 100644\n--- a/drivers/pinctrl/Makefile\n+++ b/drivers/pinctrl/Makefile\n@@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL_AT91PIO4)\t\t+= pinctrl-at91-pio4.o\n obj-y\t\t\t\t\t+= nxp/\n obj-$(CONFIG_ARCH_ASPEED) += aspeed/\n obj-$(CONFIG_ARCH_ATH79) += ath79/\n+obj-$(CONFIG_ARCH_RMOBILE) += renesas/\n obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/\n obj-$(CONFIG_PINCTRL_SANDBOX)\t+= pinctrl-sandbox.o\n \ndiff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig\nnew file mode 100644\nindex 0000000000..016ed38529\n--- /dev/null\n+++ b/drivers/pinctrl/renesas/Kconfig\n@@ -0,0 +1,31 @@\n+if ARCH_RMOBILE\n+\n+config PINCTRL_PFC\n+\tbool \"Renesas pin control drivers\"\n+\tdepends on DM && ARCH_RMOBILE\n+\thelp\n+\t  Enable support for clock present on Renesas RCar SoCs.\n+\n+config PINCTRL_PFC_R8A7795\n+\tbool \"Renesas RCar Gen3 R8A7795 pin control driver\"\n+\tdef_bool y if R8A7795\n+\tdepends on PINCTRL_PFC\n+\thelp\n+\t  Support pin multiplexing control on Renesas RCar Gen3 R8A7795 SoCs.\n+\n+\t  The driver is controlled by a device tree node which contains both\n+\t  the GPIO definitions and pin control functions for each available\n+\t  multiplex function.\n+\n+config PINCTRL_PFC_R8A7796\n+\tbool \"Renesas RCar Gen3 R8A7796 pin control driver\"\n+\tdef_bool y if R8A7796\n+\tdepends on PINCTRL_PFC\n+\thelp\n+\t  Support pin multiplexing control on Renesas RCar Gen3 R8A7796 SoCs.\n+\n+\t  The driver is controlled by a device tree node which contains both\n+\t  the GPIO definitions and pin control functions for each available\n+\t  multiplex function.\n+\n+endif\ndiff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile\nnew file mode 100644\nindex 0000000000..ebf80acd71\n--- /dev/null\n+++ b/drivers/pinctrl/renesas/Makefile\n@@ -0,0 +1,3 @@\n+obj-$(CONFIG_PINCTRL_PFC) += pfc.o\n+obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o\n+obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o\ndiff --git a/drivers/pinctrl/renesas/pfc-r8a7795.c b/drivers/pinctrl/renesas/pfc-r8a7795.c\nnew file mode 100644\nindex 0000000000..43eef69025\n--- /dev/null\n+++ b/drivers/pinctrl/renesas/pfc-r8a7795.c\n@@ -0,0 +1,4898 @@\n+/*\n+ * R8A7795 ES2.0+ processor support - PFC hardware block.\n+ *\n+ * Copyright (C) 2015-2016 Renesas Electronics Corporation\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#include <common.h>\n+#include <dm.h>\n+#include <errno.h>\n+#include <dm/pinctrl.h>\n+#include <linux/kernel.h>\n+\n+#include \"sh_pfc.h\"\n+\n+#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \\\n+\t\t   SH_PFC_PIN_CFG_PULL_UP | \\\n+\t\t   SH_PFC_PIN_CFG_PULL_DOWN)\n+\n+#define CPU_ALL_PORT(fn, sfx)\t\t\t\t\t\t\\\n+\tPORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),\t\\\n+\tPORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS),\t\\\n+\tPORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),\t\\\n+\tPORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),\t\\\n+\tPORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),\t\\\n+\tPORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),\t\\\n+\tPORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),\t\\\n+\tPORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),\t\\\n+\tPORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),\t\\\n+\tPORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),\t\\\n+\tPORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),\t\\\n+\tPORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)\n+/*\n+ * F_() : just information\n+ * FM() : macro for FN_xxx / xxx_MARK\n+ */\n+\n+/* GPSR0 */\n+#define GPSR0_15\tF_(D15,\t\t\tIP7_11_8)\n+#define GPSR0_14\tF_(D14,\t\t\tIP7_7_4)\n+#define GPSR0_13\tF_(D13,\t\t\tIP7_3_0)\n+#define GPSR0_12\tF_(D12,\t\t\tIP6_31_28)\n+#define GPSR0_11\tF_(D11,\t\t\tIP6_27_24)\n+#define GPSR0_10\tF_(D10,\t\t\tIP6_23_20)\n+#define GPSR0_9\t\tF_(D9,\t\t\tIP6_19_16)\n+#define GPSR0_8\t\tF_(D8,\t\t\tIP6_15_12)\n+#define GPSR0_7\t\tF_(D7,\t\t\tIP6_11_8)\n+#define GPSR0_6\t\tF_(D6,\t\t\tIP6_7_4)\n+#define GPSR0_5\t\tF_(D5,\t\t\tIP6_3_0)\n+#define GPSR0_4\t\tF_(D4,\t\t\tIP5_31_28)\n+#define GPSR0_3\t\tF_(D3,\t\t\tIP5_27_24)\n+#define GPSR0_2\t\tF_(D2,\t\t\tIP5_23_20)\n+#define GPSR0_1\t\tF_(D1,\t\t\tIP5_19_16)\n+#define GPSR0_0\t\tF_(D0,\t\t\tIP5_15_12)\n+\n+/* GPSR1 */\n+#define GPSR1_27\tF_(EX_WAIT0_A,\t\tIP5_11_8)\n+#define GPSR1_26\tF_(WE1_N,\t\tIP5_7_4)\n+#define GPSR1_25\tF_(WE0_N,\t\tIP5_3_0)\n+#define GPSR1_24\tF_(RD_WR_N,\t\tIP4_31_28)\n+#define GPSR1_23\tF_(RD_N,\t\tIP4_27_24)\n+#define GPSR1_22\tF_(BS_N,\t\tIP4_23_20)\n+#define GPSR1_21\tF_(CS1_N,\t\tIP4_19_16)\n+#define GPSR1_20\tF_(CS0_N,\t\tIP4_15_12)\n+#define GPSR1_19\tF_(A19,\t\t\tIP4_11_8)\n+#define GPSR1_18\tF_(A18,\t\t\tIP4_7_4)\n+#define GPSR1_17\tF_(A17,\t\t\tIP4_3_0)\n+#define GPSR1_16\tF_(A16,\t\t\tIP3_31_28)\n+#define GPSR1_15\tF_(A15,\t\t\tIP3_27_24)\n+#define GPSR1_14\tF_(A14,\t\t\tIP3_23_20)\n+#define GPSR1_13\tF_(A13,\t\t\tIP3_19_16)\n+#define GPSR1_12\tF_(A12,\t\t\tIP3_15_12)\n+#define GPSR1_11\tF_(A11,\t\t\tIP3_11_8)\n+#define GPSR1_10\tF_(A10,\t\t\tIP3_7_4)\n+#define GPSR1_9\t\tF_(A9,\t\t\tIP3_3_0)\n+#define GPSR1_8\t\tF_(A8,\t\t\tIP2_31_28)\n+#define GPSR1_7\t\tF_(A7,\t\t\tIP2_27_24)\n+#define GPSR1_6\t\tF_(A6,\t\t\tIP2_23_20)\n+#define GPSR1_5\t\tF_(A5,\t\t\tIP2_19_16)\n+#define GPSR1_4\t\tF_(A4,\t\t\tIP2_15_12)\n+#define GPSR1_3\t\tF_(A3,\t\t\tIP2_11_8)\n+#define GPSR1_2\t\tF_(A2,\t\t\tIP2_7_4)\n+#define GPSR1_1\t\tF_(A1,\t\t\tIP2_3_0)\n+#define GPSR1_0\t\tF_(A0,\t\t\tIP1_31_28)\n+\n+/* GPSR2 */\n+#define GPSR2_14\tF_(AVB_AVTP_CAPTURE_A,\tIP0_23_20)\n+#define GPSR2_13\tF_(AVB_AVTP_MATCH_A,\tIP0_19_16)\n+#define GPSR2_12\tF_(AVB_LINK,\t\tIP0_15_12)\n+#define GPSR2_11\tF_(AVB_PHY_INT,\t\tIP0_11_8)\n+#define GPSR2_10\tF_(AVB_MAGIC,\t\tIP0_7_4)\n+#define GPSR2_9\t\tF_(AVB_MDC,\t\tIP0_3_0)\n+#define GPSR2_8\t\tF_(PWM2_A,\t\tIP1_27_24)\n+#define GPSR2_7\t\tF_(PWM1_A,\t\tIP1_23_20)\n+#define GPSR2_6\t\tF_(PWM0,\t\tIP1_19_16)\n+#define GPSR2_5\t\tF_(IRQ5,\t\tIP1_15_12)\n+#define GPSR2_4\t\tF_(IRQ4,\t\tIP1_11_8)\n+#define GPSR2_3\t\tF_(IRQ3,\t\tIP1_7_4)\n+#define GPSR2_2\t\tF_(IRQ2,\t\tIP1_3_0)\n+#define GPSR2_1\t\tF_(IRQ1,\t\tIP0_31_28)\n+#define GPSR2_0\t\tF_(IRQ0,\t\tIP0_27_24)\n+\n+/* GPSR3 */\n+#define GPSR3_15\tF_(SD1_WP,\t\tIP11_23_20)\n+#define GPSR3_14\tF_(SD1_CD,\t\tIP11_19_16)\n+#define GPSR3_13\tF_(SD0_WP,\t\tIP11_15_12)\n+#define GPSR3_12\tF_(SD0_CD,\t\tIP11_11_8)\n+#define GPSR3_11\tF_(SD1_DAT3,\t\tIP8_31_28)\n+#define GPSR3_10\tF_(SD1_DAT2,\t\tIP8_27_24)\n+#define GPSR3_9\t\tF_(SD1_DAT1,\t\tIP8_23_20)\n+#define GPSR3_8\t\tF_(SD1_DAT0,\t\tIP8_19_16)\n+#define GPSR3_7\t\tF_(SD1_CMD,\t\tIP8_15_12)\n+#define GPSR3_6\t\tF_(SD1_CLK,\t\tIP8_11_8)\n+#define GPSR3_5\t\tF_(SD0_DAT3,\t\tIP8_7_4)\n+#define GPSR3_4\t\tF_(SD0_DAT2,\t\tIP8_3_0)\n+#define GPSR3_3\t\tF_(SD0_DAT1,\t\tIP7_31_28)\n+#define GPSR3_2\t\tF_(SD0_DAT0,\t\tIP7_27_24)\n+#define GPSR3_1\t\tF_(SD0_CMD,\t\tIP7_23_20)\n+#define GPSR3_0\t\tF_(SD0_CLK,\t\tIP7_19_16)\n+\n+/* GPSR4 */\n+#define GPSR4_17\tF_(SD3_DS,\t\tIP11_7_4)\n+#define GPSR4_16\tF_(SD3_DAT7,\t\tIP11_3_0)\n+#define GPSR4_15\tF_(SD3_DAT6,\t\tIP10_31_28)\n+#define GPSR4_14\tF_(SD3_DAT5,\t\tIP10_27_24)\n+#define GPSR4_13\tF_(SD3_DAT4,\t\tIP10_23_20)\n+#define GPSR4_12\tF_(SD3_DAT3,\t\tIP10_19_16)\n+#define GPSR4_11\tF_(SD3_DAT2,\t\tIP10_15_12)\n+#define GPSR4_10\tF_(SD3_DAT1,\t\tIP10_11_8)\n+#define GPSR4_9\t\tF_(SD3_DAT0,\t\tIP10_7_4)\n+#define GPSR4_8\t\tF_(SD3_CMD,\t\tIP10_3_0)\n+#define GPSR4_7\t\tF_(SD3_CLK,\t\tIP9_31_28)\n+#define GPSR4_6\t\tF_(SD2_DS,\t\tIP9_27_24)\n+#define GPSR4_5\t\tF_(SD2_DAT3,\t\tIP9_23_20)\n+#define GPSR4_4\t\tF_(SD2_DAT2,\t\tIP9_19_16)\n+#define GPSR4_3\t\tF_(SD2_DAT1,\t\tIP9_15_12)\n+#define GPSR4_2\t\tF_(SD2_DAT0,\t\tIP9_11_8)\n+#define GPSR4_1\t\tF_(SD2_CMD,\t\tIP9_7_4)\n+#define GPSR4_0\t\tF_(SD2_CLK,\t\tIP9_3_0)\n+\n+/* GPSR5 */\n+#define GPSR5_25\tF_(MLB_DAT,\t\tIP14_19_16)\n+#define GPSR5_24\tF_(MLB_SIG,\t\tIP14_15_12)\n+#define GPSR5_23\tF_(MLB_CLK,\t\tIP14_11_8)\n+#define GPSR5_22\tFM(MSIOF0_RXD)\n+#define GPSR5_21\tF_(MSIOF0_SS2,\t\tIP14_7_4)\n+#define GPSR5_20\tFM(MSIOF0_TXD)\n+#define GPSR5_19\tF_(MSIOF0_SS1,\t\tIP14_3_0)\n+#define GPSR5_18\tF_(MSIOF0_SYNC,\t\tIP13_31_28)\n+#define GPSR5_17\tFM(MSIOF0_SCK)\n+#define GPSR5_16\tF_(HRTS0_N,\t\tIP13_27_24)\n+#define GPSR5_15\tF_(HCTS0_N,\t\tIP13_23_20)\n+#define GPSR5_14\tF_(HTX0,\t\tIP13_19_16)\n+#define GPSR5_13\tF_(HRX0,\t\tIP13_15_12)\n+#define GPSR5_12\tF_(HSCK0,\t\tIP13_11_8)\n+#define GPSR5_11\tF_(RX2_A,\t\tIP13_7_4)\n+#define GPSR5_10\tF_(TX2_A,\t\tIP13_3_0)\n+#define GPSR5_9\t\tF_(SCK2,\t\tIP12_31_28)\n+#define GPSR5_8\t\tF_(RTS1_N_TANS,\t\tIP12_27_24)\n+#define GPSR5_7\t\tF_(CTS1_N,\t\tIP12_23_20)\n+#define GPSR5_6\t\tF_(TX1_A,\t\tIP12_19_16)\n+#define GPSR5_5\t\tF_(RX1_A,\t\tIP12_15_12)\n+#define GPSR5_4\t\tF_(RTS0_N_TANS,\t\tIP12_11_8)\n+#define GPSR5_3\t\tF_(CTS0_N,\t\tIP12_7_4)\n+#define GPSR5_2\t\tF_(TX0,\t\t\tIP12_3_0)\n+#define GPSR5_1\t\tF_(RX0,\t\t\tIP11_31_28)\n+#define GPSR5_0\t\tF_(SCK0,\t\tIP11_27_24)\n+\n+/* GPSR6 */\n+#define GPSR6_31\tF_(USB2_CH3_OVC,\tIP18_7_4)\n+#define GPSR6_30\tF_(USB2_CH3_PWEN,\tIP18_3_0)\n+#define GPSR6_29\tF_(USB30_OVC,\t\tIP17_31_28)\n+#define GPSR6_28\tF_(USB30_PWEN,\t\tIP17_27_24)\n+#define GPSR6_27\tF_(USB1_OVC,\t\tIP17_23_20)\n+#define GPSR6_26\tF_(USB1_PWEN,\t\tIP17_19_16)\n+#define GPSR6_25\tF_(USB0_OVC,\t\tIP17_15_12)\n+#define GPSR6_24\tF_(USB0_PWEN,\t\tIP17_11_8)\n+#define GPSR6_23\tF_(AUDIO_CLKB_B,\tIP17_7_4)\n+#define GPSR6_22\tF_(AUDIO_CLKA_A,\tIP17_3_0)\n+#define GPSR6_21\tF_(SSI_SDATA9_A,\tIP16_31_28)\n+#define GPSR6_20\tF_(SSI_SDATA8,\t\tIP16_27_24)\n+#define GPSR6_19\tF_(SSI_SDATA7,\t\tIP16_23_20)\n+#define GPSR6_18\tF_(SSI_WS78,\t\tIP16_19_16)\n+#define GPSR6_17\tF_(SSI_SCK78,\t\tIP16_15_12)\n+#define GPSR6_16\tF_(SSI_SDATA6,\t\tIP16_11_8)\n+#define GPSR6_15\tF_(SSI_WS6,\t\tIP16_7_4)\n+#define GPSR6_14\tF_(SSI_SCK6,\t\tIP16_3_0)\n+#define GPSR6_13\tFM(SSI_SDATA5)\n+#define GPSR6_12\tFM(SSI_WS5)\n+#define GPSR6_11\tFM(SSI_SCK5)\n+#define GPSR6_10\tF_(SSI_SDATA4,\t\tIP15_31_28)\n+#define GPSR6_9\t\tF_(SSI_WS4,\t\tIP15_27_24)\n+#define GPSR6_8\t\tF_(SSI_SCK4,\t\tIP15_23_20)\n+#define GPSR6_7\t\tF_(SSI_SDATA3,\t\tIP15_19_16)\n+#define GPSR6_6\t\tF_(SSI_WS349,\t\tIP15_15_12)\n+#define GPSR6_5\t\tF_(SSI_SCK349,\t\tIP15_11_8)\n+#define GPSR6_4\t\tF_(SSI_SDATA2_A,\tIP15_7_4)\n+#define GPSR6_3\t\tF_(SSI_SDATA1_A,\tIP15_3_0)\n+#define GPSR6_2\t\tF_(SSI_SDATA0,\t\tIP14_31_28)\n+#define GPSR6_1\t\tF_(SSI_WS01239,\t\tIP14_27_24)\n+#define GPSR6_0\t\tF_(SSI_SCK01239,\t\tIP14_23_20)\n+\n+/* GPSR7 */\n+#define GPSR7_3\t\tFM(HDMI1_CEC)\n+#define GPSR7_2\t\tFM(HDMI0_CEC)\n+#define GPSR7_1\t\tFM(AVS2)\n+#define GPSR7_0\t\tFM(AVS1)\n+\n+\n+/* IPSRx */\t\t/* 0 */\t\t\t/* 1 */\t\t/* 2 */\t\t\t/* 3 */\t\t\t\t/* 4 */\t\t/* 5 */\t\t/* 6 */\t\t\t/* 7 */\t\t/* 8 */\t\t\t/* 9 */\t\t/* A */\t\t/* B */\t\t/* C - F */\n+#define IP0_3_0\t\tFM(AVB_MDC)\t\tF_(0, 0)\tFM(MSIOF2_SS2_C)\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP0_7_4\t\tFM(AVB_MAGIC)\t\tF_(0, 0)\tFM(MSIOF2_SS1_C)\tFM(SCK4_A)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP0_11_8\tFM(AVB_PHY_INT)\t\tF_(0, 0)\tFM(MSIOF2_SYNC_C)\tFM(RX4_A)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP0_15_12\tFM(AVB_LINK)\t\tF_(0, 0)\tFM(MSIOF2_SCK_C)\tFM(TX4_A)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP0_19_16\tFM(AVB_AVTP_MATCH_A)\tF_(0, 0)\tFM(MSIOF2_RXD_C)\tFM(CTS4_N_A)\t\t\tF_(0, 0)\tFM(FSCLKST2_N_A) F_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP0_23_20\tFM(AVB_AVTP_CAPTURE_A)\tF_(0, 0)\tFM(MSIOF2_TXD_C)\tFM(RTS4_N_TANS_A)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP0_27_24\tFM(IRQ0)\t\tFM(QPOLB)\tF_(0, 0)\t\tFM(DU_CDE)\t\t\tFM(VI4_DATA0_B) FM(CAN0_TX_B)\tFM(CANFD0_TX_B)\t\tFM(MSIOF3_SS2_E) F_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP0_31_28\tFM(IRQ1)\t\tFM(QPOLA)\tF_(0, 0)\t\tFM(DU_DISP)\t\t\tFM(VI4_DATA1_B) FM(CAN0_RX_B)\tFM(CANFD0_RX_B)\t\tFM(MSIOF3_SS1_E) F_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP1_3_0\t\tFM(IRQ2)\t\tFM(QCPV_QDE)\tF_(0, 0)\t\tFM(DU_EXODDF_DU_ODDF_DISP_CDE)\tFM(VI4_DATA2_B) F_(0, 0)\tF_(0, 0)\t\tFM(MSIOF3_SYNC_E) F_(0, 0)\t\tFM(PWM3_B)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP1_7_4\t\tFM(IRQ3)\t\tFM(QSTVB_QVE)\tFM(A25)\t\t\tFM(DU_DOTCLKOUT1)\t\tFM(VI4_DATA3_B) F_(0, 0)\tF_(0, 0)\t\tFM(MSIOF3_SCK_E) F_(0, 0)\t\tFM(PWM4_B)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP1_11_8\tFM(IRQ4)\t\tFM(QSTH_QHS)\tFM(A24)\t\t\tFM(DU_EXHSYNC_DU_HSYNC)\t\tFM(VI4_DATA4_B) F_(0, 0)\tF_(0, 0)\t\tFM(MSIOF3_RXD_E) F_(0, 0)\t\tFM(PWM5_B)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP1_15_12\tFM(IRQ5)\t\tFM(QSTB_QHE)\tFM(A23)\t\t\tFM(DU_EXVSYNC_DU_VSYNC)\t\tFM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0)\t\tFM(MSIOF3_TXD_E) F_(0, 0)\t\tFM(PWM6_B)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP1_19_16\tFM(PWM0)\t\tFM(AVB_AVTP_PPS)FM(A22)\t\t\tF_(0, 0)\t\t\tFM(VI4_DATA6_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(IECLK_B)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP1_23_20\tFM(PWM1_A)\t\tF_(0, 0)\tFM(A21)\t\t\tFM(HRX3_D)\t\t\tFM(VI4_DATA7_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(IERX_B)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP1_27_24\tFM(PWM2_A)\t\tF_(0, 0)\tFM(A20)\t\t\tFM(HTX3_D)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(IETX_B)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP1_31_28\tFM(A0)\t\t\tFM(LCDOUT16)\tFM(MSIOF3_SYNC_B)\tF_(0, 0)\t\t\tFM(VI4_DATA8)\tF_(0, 0)\tFM(DU_DB0)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(PWM3_A)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP2_3_0\t\tFM(A1)\t\t\tFM(LCDOUT17)\tFM(MSIOF3_TXD_B)\tF_(0, 0)\t\t\tFM(VI4_DATA9)\tF_(0, 0)\tFM(DU_DB1)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(PWM4_A)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP2_7_4\t\tFM(A2)\t\t\tFM(LCDOUT18)\tFM(MSIOF3_SCK_B)\tF_(0, 0)\t\t\tFM(VI4_DATA10)\tF_(0, 0)\tFM(DU_DB2)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(PWM5_A)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP2_11_8\tFM(A3)\t\t\tFM(LCDOUT19)\tFM(MSIOF3_RXD_B)\tF_(0, 0)\t\t\tFM(VI4_DATA11)\tF_(0, 0)\tFM(DU_DB3)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(PWM6_A)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+\n+/* IPSRx */\t\t/* 0 */\t\t\t/* 1 */\t\t/* 2 */\t\t\t/* 3 */\t\t\t\t/* 4 */\t\t/* 5 */\t\t/* 6 */\t\t\t/* 7 */\t\t/* 8 */\t\t\t/* 9 */\t\t/* A */\t\t/* B */\t\t/* C - F */\n+#define IP2_15_12\tFM(A4)\t\t\tFM(LCDOUT20)\tFM(MSIOF3_SS1_B)\tF_(0, 0)\t\t\tFM(VI4_DATA12)\tFM(VI5_DATA12)\tFM(DU_DB4)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP2_19_16\tFM(A5)\t\t\tFM(LCDOUT21)\tFM(MSIOF3_SS2_B)\tFM(SCK4_B)\t\t\tFM(VI4_DATA13)\tFM(VI5_DATA13)\tFM(DU_DB5)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP2_23_20\tFM(A6)\t\t\tFM(LCDOUT22)\tFM(MSIOF2_SS1_A)\tFM(RX4_B)\t\t\tFM(VI4_DATA14)\tFM(VI5_DATA14)\tFM(DU_DB6)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP2_27_24\tFM(A7)\t\t\tFM(LCDOUT23)\tFM(MSIOF2_SS2_A)\tFM(TX4_B)\t\t\tFM(VI4_DATA15)\tFM(VI5_DATA15)\tFM(DU_DB7)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP2_31_28\tFM(A8)\t\t\tFM(RX3_B)\tFM(MSIOF2_SYNC_A)\tFM(HRX4_B)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tFM(SDA6_A)\tFM(AVB_AVTP_MATCH_B)\tFM(PWM1_B)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP3_3_0\t\tFM(A9)\t\t\tF_(0, 0)\tFM(MSIOF2_SCK_A)\tFM(CTS4_N_B)\t\t\tF_(0, 0)\tFM(VI5_VSYNC_N)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP3_7_4\t\tFM(A10)\t\t\tF_(0, 0)\tFM(MSIOF2_RXD_A)\tFM(RTS4_N_TANS_B)\t\tF_(0, 0)\tFM(VI5_HSYNC_N)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP3_11_8\tFM(A11)\t\t\tFM(TX3_B)\tFM(MSIOF2_TXD_A)\tFM(HTX4_B)\t\t\tFM(HSCK4)\tFM(VI5_FIELD)\tF_(0, 0)\t\tFM(SCL6_A)\tFM(AVB_AVTP_CAPTURE_B)\tFM(PWM2_B)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP3_15_12\tFM(A12)\t\t\tFM(LCDOUT12)\tFM(MSIOF3_SCK_C)\tF_(0, 0)\t\t\tFM(HRX4_A)\tFM(VI5_DATA8)\tFM(DU_DG4)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP3_19_16\tFM(A13)\t\t\tFM(LCDOUT13)\tFM(MSIOF3_SYNC_C)\tF_(0, 0)\t\t\tFM(HTX4_A)\tFM(VI5_DATA9)\tFM(DU_DG5)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP3_23_20\tFM(A14)\t\t\tFM(LCDOUT14)\tFM(MSIOF3_RXD_C)\tF_(0, 0)\t\t\tFM(HCTS4_N)\tFM(VI5_DATA10)\tFM(DU_DG6)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP3_27_24\tFM(A15)\t\t\tFM(LCDOUT15)\tFM(MSIOF3_TXD_C)\tF_(0, 0)\t\t\tFM(HRTS4_N)\tFM(VI5_DATA11)\tFM(DU_DG7)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP3_31_28\tFM(A16)\t\t\tFM(LCDOUT8)\tF_(0, 0)\t\tF_(0, 0)\t\t\tFM(VI4_FIELD)\tF_(0, 0)\tFM(DU_DG0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP4_3_0\t\tFM(A17)\t\t\tFM(LCDOUT9)\tF_(0, 0)\t\tF_(0, 0)\t\t\tFM(VI4_VSYNC_N)\tF_(0, 0)\tFM(DU_DG1)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP4_7_4\t\tFM(A18)\t\t\tFM(LCDOUT10)\tF_(0, 0)\t\tF_(0, 0)\t\t\tFM(VI4_HSYNC_N)\tF_(0, 0)\tFM(DU_DG2)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP4_11_8\tFM(A19)\t\t\tFM(LCDOUT11)\tF_(0, 0)\t\tF_(0, 0)\t\t\tFM(VI4_CLKENB)\tF_(0, 0)\tFM(DU_DG3)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP4_15_12\tFM(CS0_N)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tFM(VI5_CLKENB)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP4_19_16\tFM(CS1_N)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tFM(VI5_CLK)\tF_(0, 0)\t\tFM(EX_WAIT0_B)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP4_23_20\tFM(BS_N)\t\tFM(QSTVA_QVS)\tFM(MSIOF3_SCK_D)\tFM(SCK3)\t\t\tFM(HSCK3)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tFM(CAN1_TX)\t\tFM(CANFD1_TX)\tFM(IETX_A)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP4_27_24\tFM(RD_N)\t\tF_(0, 0)\tFM(MSIOF3_SYNC_D)\tFM(RX3_A)\t\t\tFM(HRX3_A)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tFM(CAN0_TX_A)\t\tFM(CANFD0_TX_A)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP4_31_28\tFM(RD_WR_N)\t\tF_(0, 0)\tFM(MSIOF3_RXD_D)\tFM(TX3_A)\t\t\tFM(HTX3_A)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tFM(CAN0_RX_A)\t\tFM(CANFD0_RX_A)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP5_3_0\t\tFM(WE0_N)\t\tF_(0, 0)\tFM(MSIOF3_TXD_D)\tFM(CTS3_N)\t\t\tFM(HCTS3_N)\tF_(0, 0)\tF_(0, 0)\t\tFM(SCL6_B)\tFM(CAN_CLK)\t\tF_(0, 0)\tFM(IECLK_A)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP5_7_4\t\tFM(WE1_N)\t\tF_(0, 0)\tFM(MSIOF3_SS1_D)\tFM(RTS3_N_TANS)\t\t\tFM(HRTS3_N)\tF_(0, 0)\tF_(0, 0)\t\tFM(SDA6_B)\tFM(CAN1_RX)\t\tFM(CANFD1_RX)\tFM(IERX_A)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP5_11_8\tFM(EX_WAIT0_A)\t\tFM(QCLK)\tF_(0, 0)\t\tF_(0, 0)\t\t\tFM(VI4_CLK)\tF_(0, 0)\tFM(DU_DOTCLKOUT0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP5_15_12\tFM(D0)\t\t\tFM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)\tF_(0, 0)\t\t\tFM(VI4_DATA16)\tFM(VI5_DATA0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP5_19_16\tFM(D1)\t\t\tFM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)\tF_(0, 0)\t\t\tFM(VI4_DATA17)\tFM(VI5_DATA1)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP5_23_20\tFM(D2)\t\t\tF_(0, 0)\tFM(MSIOF3_RXD_A)\tF_(0, 0)\t\t\tFM(VI4_DATA18)\tFM(VI5_DATA2)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP5_27_24\tFM(D3)\t\t\tF_(0, 0)\tFM(MSIOF3_TXD_A)\tF_(0, 0)\t\t\tFM(VI4_DATA19)\tFM(VI5_DATA3)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP5_31_28\tFM(D4)\t\t\tFM(MSIOF2_SCK_B)F_(0, 0)\t\tF_(0, 0)\t\t\tFM(VI4_DATA20)\tFM(VI5_DATA4)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP6_3_0\t\tFM(D5)\t\t\tFM(MSIOF2_SYNC_B)F_(0, 0)\t\tF_(0, 0)\t\t\tFM(VI4_DATA21)\tFM(VI5_DATA5)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP6_7_4\t\tFM(D6)\t\t\tFM(MSIOF2_RXD_B)F_(0, 0)\t\tF_(0, 0)\t\t\tFM(VI4_DATA22)\tFM(VI5_DATA6)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP6_11_8\tFM(D7)\t\t\tFM(MSIOF2_TXD_B)F_(0, 0)\t\tF_(0, 0)\t\t\tFM(VI4_DATA23)\tFM(VI5_DATA7)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP6_15_12\tFM(D8)\t\t\tFM(LCDOUT0)\tFM(MSIOF2_SCK_D)\tFM(SCK4_C)\t\t\tFM(VI4_DATA0_A)\tF_(0, 0)\tFM(DU_DR0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP6_19_16\tFM(D9)\t\t\tFM(LCDOUT1)\tFM(MSIOF2_SYNC_D)\tF_(0, 0)\t\t\tFM(VI4_DATA1_A)\tF_(0, 0)\tFM(DU_DR1)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP6_23_20\tFM(D10)\t\t\tFM(LCDOUT2)\tFM(MSIOF2_RXD_D)\tFM(HRX3_B)\t\t\tFM(VI4_DATA2_A)\tFM(CTS4_N_C)\tFM(DU_DR2)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP6_27_24\tFM(D11)\t\t\tFM(LCDOUT3)\tFM(MSIOF2_TXD_D)\tFM(HTX3_B)\t\t\tFM(VI4_DATA3_A)\tFM(RTS4_N_TANS_C)FM(DU_DR3)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP6_31_28\tFM(D12)\t\t\tFM(LCDOUT4)\tFM(MSIOF2_SS1_D)\tFM(RX4_C)\t\t\tFM(VI4_DATA4_A)\tF_(0, 0)\tFM(DU_DR4)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP7_3_0\t\tFM(D13)\t\t\tFM(LCDOUT5)\tFM(MSIOF2_SS2_D)\tFM(TX4_C)\t\t\tFM(VI4_DATA5_A)\tF_(0, 0)\tFM(DU_DR5)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP7_7_4\t\tFM(D14)\t\t\tFM(LCDOUT6)\tFM(MSIOF3_SS1_A)\tFM(HRX3_C)\t\t\tFM(VI4_DATA6_A)\tF_(0, 0)\tFM(DU_DR6)\t\tFM(SCL6_C)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP7_11_8\tFM(D15)\t\t\tFM(LCDOUT7)\tFM(MSIOF3_SS2_A)\tFM(HTX3_C)\t\t\tFM(VI4_DATA7_A)\tF_(0, 0)\tFM(DU_DR7)\t\tFM(SDA6_C)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP7_19_16\tFM(SD0_CLK)\t\tF_(0, 0)\tFM(MSIOF1_SCK_E)\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tFM(STP_OPWM_0_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+\n+/* IPSRx */\t\t/* 0 */\t\t\t/* 1 */\t\t/* 2 */\t\t\t/* 3 */\t\t\t\t/* 4 */\t\t/* 5 */\t\t/* 6 */\t\t\t/* 7 */\t\t/* 8 */\t\t\t/* 9 */\t\t/* A */\t\t/* B */\t\t/* C - F */\n+#define IP7_23_20\tFM(SD0_CMD)\t\tF_(0, 0)\tFM(MSIOF1_SYNC_E)\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tFM(STP_IVCXO27_0_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP7_27_24\tFM(SD0_DAT0)\t\tF_(0, 0)\tFM(MSIOF1_RXD_E)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SCK0_B)\tFM(STP_ISCLK_0_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP7_31_28\tFM(SD0_DAT1)\t\tF_(0, 0)\tFM(MSIOF1_TXD_E)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP8_3_0\t\tFM(SD0_DAT2)\t\tF_(0, 0)\tFM(MSIOF1_SS1_E)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDAT0_B)\tFM(STP_ISD_0_B)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP8_7_4\t\tFM(SD0_DAT3)\t\tF_(0, 0)\tFM(MSIOF1_SS2_E)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDEN0_B)\tFM(STP_ISEN_0_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP8_11_8\tFM(SD1_CLK)\t\tF_(0, 0)\tFM(MSIOF1_SCK_G)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(SIM0_CLK_A)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP8_15_12\tFM(SD1_CMD)\t\tF_(0, 0)\tFM(MSIOF1_SYNC_G)\tFM(NFCE_N_B)\t\t\tF_(0, 0)\tFM(SIM0_D_A)\tFM(STP_IVCXO27_1_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP8_19_16\tFM(SD1_DAT0)\t\tFM(SD2_DAT4)\tFM(MSIOF1_RXD_G)\tFM(NFWP_N_B)\t\t\tF_(0, 0)\tFM(TS_SCK1_B)\tFM(STP_ISCLK_1_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP8_23_20\tFM(SD1_DAT1)\t\tFM(SD2_DAT5)\tFM(MSIOF1_TXD_G)\tFM(NFDATA14_B)\t\t\tF_(0, 0)\tFM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP8_27_24\tFM(SD1_DAT2)\t\tFM(SD2_DAT6)\tFM(MSIOF1_SS1_G)\tFM(NFDATA15_B)\t\t\tF_(0, 0)\tFM(TS_SDAT1_B)\tFM(STP_ISD_1_B)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP8_31_28\tFM(SD1_DAT3)\t\tFM(SD2_DAT7)\tFM(MSIOF1_SS2_G)\tFM(NFRB_N_B)\t\t\tF_(0, 0)\tFM(TS_SDEN1_B)\tFM(STP_ISEN_1_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP9_3_0\t\tFM(SD2_CLK)\t\tF_(0, 0)\tFM(NFDATA8)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP9_7_4\t\tFM(SD2_CMD)\t\tF_(0, 0)\tFM(NFDATA9)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP9_11_8\tFM(SD2_DAT0)\t\tF_(0, 0)\tFM(NFDATA10)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP9_15_12\tFM(SD2_DAT1)\t\tF_(0, 0)\tFM(NFDATA11)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP9_19_16\tFM(SD2_DAT2)\t\tF_(0, 0)\tFM(NFDATA12)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP9_23_20\tFM(SD2_DAT3)\t\tF_(0, 0)\tFM(NFDATA13)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP9_27_24\tFM(SD2_DS)\t\tF_(0, 0)\tFM(NFALE)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tFM(SATA_DEVSLP_B)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP9_31_28\tFM(SD3_CLK)\t\tF_(0, 0)\tFM(NFWE_N)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP10_3_0\tFM(SD3_CMD)\t\tF_(0, 0)\tFM(NFRE_N)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP10_7_4\tFM(SD3_DAT0)\t\tF_(0, 0)\tFM(NFDATA0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP10_11_8\tFM(SD3_DAT1)\t\tF_(0, 0)\tFM(NFDATA1)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP10_15_12\tFM(SD3_DAT2)\t\tF_(0, 0)\tFM(NFDATA2)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP10_19_16\tFM(SD3_DAT3)\t\tF_(0, 0)\tFM(NFDATA3)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP10_23_20\tFM(SD3_DAT4)\t\tFM(SD2_CD_A)\tFM(NFDATA4)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP10_27_24\tFM(SD3_DAT5)\t\tFM(SD2_WP_A)\tFM(NFDATA5)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP10_31_28\tFM(SD3_DAT6)\t\tFM(SD3_CD)\tFM(NFDATA6)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP11_3_0\tFM(SD3_DAT7)\t\tFM(SD3_WP)\tFM(NFDATA7)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP11_7_4\tFM(SD3_DS)\t\tF_(0, 0)\tFM(NFCLE)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP11_11_8\tFM(SD0_CD)\t\tF_(0, 0)\tFM(NFDATA14_A)\t\tF_(0, 0)\t\t\tFM(SCL2_B)\tFM(SIM0_RST_A)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+\n+/* IPSRx */\t\t/* 0 */\t\t\t/* 1 */\t\t/* 2 */\t\t\t/* 3 */\t\t\t\t/* 4 */\t\t/* 5 */\t\t/* 6 */\t\t\t/* 7 */\t\t/* 8 */\t\t\t/* 9 */\t\t/* A */\t\t/* B */\t\t/* C - F */\n+#define IP11_15_12\tFM(SD0_WP)\t\tF_(0, 0)\tFM(NFDATA15_A)\t\tF_(0, 0)\t\t\tFM(SDA2_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP11_19_16\tFM(SD1_CD)\t\tF_(0, 0)\tFM(NFRB_N_A)\t\tF_(0, 0)\t\t\tF_(0, 0)\tFM(SIM0_CLK_B)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP11_23_20\tFM(SD1_WP)\t\tF_(0, 0)\tFM(NFCE_N_A)\t\tF_(0, 0)\t\t\tF_(0, 0)\tFM(SIM0_D_B)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP11_27_24\tFM(SCK0)\t\tFM(HSCK1_B)\tFM(MSIOF1_SS2_B)\tFM(AUDIO_CLKC_B)\t\tFM(SDA2_A)\tFM(SIM0_RST_B)\tFM(STP_OPWM_0_C)\tFM(RIF0_CLK_B)\tF_(0, 0)\t\tFM(ADICHS2)\tFM(SCK5_B)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP11_31_28\tFM(RX0)\t\t\tFM(HRX1_B)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SCK0_C)\tFM(STP_ISCLK_0_C)\tFM(RIF0_D0_B)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP12_3_0\tFM(TX0)\t\t\tFM(HTX1_B)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)\tFM(RIF0_D1_B)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP12_7_4\tFM(CTS0_N)\t\tFM(HCTS1_N_B)\tFM(MSIOF1_SYNC_B)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)\tFM(RIF1_SYNC_B)\tFM(AUDIO_CLKOUT_C)\tFM(ADICS_SAMP)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP12_11_8\tFM(RTS0_N_TANS)\t\tFM(HRTS1_N_B)\tFM(MSIOF1_SS1_B)\tFM(AUDIO_CLKA_B)\t\tFM(SCL2_A)\tF_(0, 0)\tFM(STP_IVCXO27_1_C)\tFM(RIF0_SYNC_B)\tF_(0, 0)\t\tFM(ADICHS1)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP12_15_12\tFM(RX1_A)\t\tFM(HRX1_A)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDAT0_C)\tFM(STP_ISD_0_C)\t\tFM(RIF1_CLK_C)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP12_19_16\tFM(TX1_A)\t\tFM(HTX1_A)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDEN0_C)\tFM(STP_ISEN_0_C)\tFM(RIF1_D0_C)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP12_23_20\tFM(CTS1_N)\t\tFM(HCTS1_N_A)\tFM(MSIOF1_RXD_B)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDEN1_C)\tFM(STP_ISEN_1_C)\tFM(RIF1_D0_B)\tF_(0, 0)\t\tFM(ADIDATA)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP12_27_24\tFM(RTS1_N_TANS)\t\tFM(HRTS1_N_A)\tFM(MSIOF1_TXD_B)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDAT1_C)\tFM(STP_ISD_1_C)\t\tFM(RIF1_D1_B)\tF_(0, 0)\t\tFM(ADICHS0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP12_31_28\tFM(SCK2)\t\tFM(SCIF_CLK_B)\tFM(MSIOF1_SCK_B)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SCK1_C)\tFM(STP_ISCLK_1_C)\tFM(RIF1_CLK_B)\tF_(0, 0)\t\tFM(ADICLK)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP13_3_0\tFM(TX2_A)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(SD2_CD_B)\t\t\tFM(SCL1_A)\tF_(0, 0)\tFM(FMCLK_A)\t\tFM(RIF1_D1_C)\tF_(0, 0)\t\tFM(FSO_CFE_0_N)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP13_7_4\tFM(RX2_A)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(SD2_WP_B)\t\t\tFM(SDA1_A)\tF_(0, 0)\tFM(FMIN_A)\t\tFM(RIF1_SYNC_C)\tF_(0, 0)\t\tFM(FSO_CFE_1_N)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP13_11_8\tFM(HSCK0)\t\tF_(0, 0)\tFM(MSIOF1_SCK_D)\tFM(AUDIO_CLKB_A)\t\tFM(SSI_SDATA1_B)FM(TS_SCK0_D)\tFM(STP_ISCLK_0_D)\tFM(RIF0_CLK_C)\tF_(0, 0)\t\tF_(0, 0)\tFM(RX5_B)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP13_15_12\tFM(HRX0)\t\tF_(0, 0)\tFM(MSIOF1_RXD_D)\tF_(0, 0)\t\t\tFM(SSI_SDATA2_B)FM(TS_SDEN0_D)\tFM(STP_ISEN_0_D)\tFM(RIF0_D0_C)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP13_19_16\tFM(HTX0)\t\tF_(0, 0)\tFM(MSIOF1_TXD_D)\tF_(0, 0)\t\t\tFM(SSI_SDATA9_B)FM(TS_SDAT0_D)\tFM(STP_ISD_0_D)\t\tFM(RIF0_D1_C)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP13_23_20\tFM(HCTS0_N)\t\tFM(RX2_B)\tFM(MSIOF1_SYNC_D)\tF_(0, 0)\t\t\tFM(SSI_SCK9_A)\tFM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)\tFM(RIF0_SYNC_C)\tFM(AUDIO_CLKOUT1_A)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP13_27_24\tFM(HRTS0_N)\t\tFM(TX2_B)\tFM(MSIOF1_SS1_D)\tF_(0, 0)\t\t\tFM(SSI_WS9_A)\tF_(0, 0)\tFM(STP_IVCXO27_0_D)\tFM(BPFCLK_A)\tFM(AUDIO_CLKOUT2_A)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP13_31_28\tFM(MSIOF0_SYNC)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tFM(AUDIO_CLKOUT_A)\tF_(0, 0)\tFM(TX5_B)\tF_(0, 0)\tF_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)\n+#define IP14_3_0\tFM(MSIOF0_SS1)\t\tFM(RX5_A)\tFM(NFWP_N_A)\t\tFM(AUDIO_CLKA_C)\t\tFM(SSI_SCK2_A)\tF_(0, 0)\tFM(STP_IVCXO27_0_C)\tF_(0, 0)\tFM(AUDIO_CLKOUT3_A)\tF_(0, 0)\tFM(TCLK1_B)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP14_7_4\tFM(MSIOF0_SS2)\t\tFM(TX5_A)\tFM(MSIOF1_SS2_D)\tFM(AUDIO_CLKC_A)\t\tFM(SSI_WS2_A)\tF_(0, 0)\tFM(STP_OPWM_0_D)\tF_(0, 0)\tFM(AUDIO_CLKOUT_D)\tF_(0, 0)\tFM(SPEEDIN_B)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP14_11_8\tFM(MLB_CLK)\t\tF_(0, 0)\tFM(MSIOF1_SCK_F)\tF_(0, 0)\t\t\tFM(SCL1_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP14_15_12\tFM(MLB_SIG)\t\tFM(RX1_B)\tFM(MSIOF1_SYNC_F)\tF_(0, 0)\t\t\tFM(SDA1_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP14_19_16\tFM(MLB_DAT)\t\tFM(TX1_B)\tFM(MSIOF1_RXD_F)\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP14_23_20\tFM(SSI_SCK01239)\tF_(0, 0)\tFM(MSIOF1_TXD_F)\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP14_27_24\tFM(SSI_WS01239)\t\tF_(0, 0)\tFM(MSIOF1_SS1_F)\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+\n+/* IPSRx */\t\t/* 0 */\t\t\t/* 1 */\t\t/* 2 */\t\t\t/* 3 */\t\t\t\t/* 4 */\t\t/* 5 */\t\t/* 6 */\t\t\t/* 7 */\t\t/* 8 */\t\t\t/* 9 */\t\t/* A */\t\t/* B */\t\t/* C - F */\n+#define IP14_31_28\tFM(SSI_SDATA0)\t\tF_(0, 0)\tFM(MSIOF1_SS2_F)\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP15_3_0\tFM(SSI_SDATA1_A)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP15_7_4\tFM(SSI_SDATA2_A)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\t\t\tFM(SSI_SCK1_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP15_11_8\tFM(SSI_SCK349)\t\tF_(0, 0)\tFM(MSIOF1_SS1_A)\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tFM(STP_OPWM_0_A)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP15_15_12\tFM(SSI_WS349)\t\tFM(HCTS2_N_A)\tFM(MSIOF1_SS2_A)\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tFM(STP_IVCXO27_0_A)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP15_19_16\tFM(SSI_SDATA3)\t\tFM(HRTS2_N_A)\tFM(MSIOF1_TXD_A)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SCK0_A)\tFM(STP_ISCLK_0_A)\tFM(RIF0_D1_A)\tFM(RIF2_D0_A)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP15_23_20\tFM(SSI_SCK4)\t\tFM(HRX2_A)\tFM(MSIOF1_SCK_A)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDAT0_A)\tFM(STP_ISD_0_A)\t\tFM(RIF0_CLK_A)\tFM(RIF2_CLK_A)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP15_27_24\tFM(SSI_WS4)\t\tFM(HTX2_A)\tFM(MSIOF1_SYNC_A)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDEN0_A)\tFM(STP_ISEN_0_A)\tFM(RIF0_SYNC_A)\tFM(RIF2_SYNC_A)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP15_31_28\tFM(SSI_SDATA4)\t\tFM(HSCK2_A)\tFM(MSIOF1_RXD_A)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)\tFM(RIF0_D0_A)\tFM(RIF2_D1_A)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP16_3_0\tFM(SSI_SCK6)\t\tFM(USB2_PWEN)\tF_(0, 0)\t\tFM(SIM0_RST_D)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP16_7_4\tFM(SSI_WS6)\t\tFM(USB2_OVC)\tF_(0, 0)\t\tFM(SIM0_D_D)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP16_11_8\tFM(SSI_SDATA6)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(SIM0_CLK_D)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tFM(SATA_DEVSLP_A)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP16_15_12\tFM(SSI_SCK78)\t\tFM(HRX2_B)\tFM(MSIOF1_SCK_C)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SCK1_A)\tFM(STP_ISCLK_1_A)\tFM(RIF1_CLK_A)\tFM(RIF3_CLK_A)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP16_19_16\tFM(SSI_WS78)\t\tFM(HTX2_B)\tFM(MSIOF1_SYNC_C)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDAT1_A)\tFM(STP_ISD_1_A)\t\tFM(RIF1_SYNC_A)\tFM(RIF3_SYNC_A)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP16_23_20\tFM(SSI_SDATA7)\t\tFM(HCTS2_N_B)\tFM(MSIOF1_RXD_C)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDEN1_A)\tFM(STP_ISEN_1_A)\tFM(RIF1_D0_A)\tFM(RIF3_D0_A)\t\tF_(0, 0)\tFM(TCLK2_A)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP16_27_24\tFM(SSI_SDATA8)\t\tFM(HRTS2_N_B)\tFM(MSIOF1_TXD_C)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)\tFM(RIF1_D1_A)\tFM(RIF3_D1_A)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP16_31_28\tFM(SSI_SDATA9_A)\tFM(HSCK2_B)\tFM(MSIOF1_SS1_C)\tFM(HSCK1_A)\t\t\tFM(SSI_WS1_B)\tFM(SCK1)\tFM(STP_IVCXO27_1_A)\tFM(SCK5_A)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP17_3_0\tFM(AUDIO_CLKA_A)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tFM(CC5_OSCOUT)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP17_7_4\tFM(AUDIO_CLKB_B)\tFM(SCIF_CLK_A)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tFM(STP_IVCXO27_1_D)\tFM(REMOCON_A)\tF_(0, 0)\t\tF_(0, 0)\tFM(TCLK1_A)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP17_11_8\tFM(USB0_PWEN)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(SIM0_RST_C)\t\t\tF_(0, 0)\tFM(TS_SCK1_D)\tFM(STP_ISCLK_1_D)\tFM(BPFCLK_B)\tFM(RIF3_CLK_B)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)\n+#define IP17_15_12\tFM(USB0_OVC)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(SIM0_D_C)\t\t\tF_(0, 0)\tFM(TS_SDAT1_D)\tFM(STP_ISD_1_D)\t\tF_(0, 0)\tFM(RIF3_SYNC_B)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)\n+#define IP17_19_16\tFM(USB1_PWEN)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(SIM0_CLK_C)\t\t\tFM(SSI_SCK1_A)\tFM(TS_SCK0_E)\tFM(STP_ISCLK_0_E)\tFM(FMCLK_B)\tFM(RIF2_CLK_B)\t\tF_(0, 0)\tFM(SPEEDIN_A)\tF_(0, 0)\tF_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)\n+#define IP17_23_20\tFM(USB1_OVC)\t\tF_(0, 0)\tFM(MSIOF1_SS2_C)\tF_(0, 0)\t\t\tFM(SSI_WS1_A)\tFM(TS_SDAT0_E)\tFM(STP_ISD_0_E)\t\tFM(FMIN_B)\tFM(RIF2_SYNC_B)\t\tF_(0, 0)\tFM(REMOCON_B)\tF_(0, 0)\tF_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)\n+#define IP17_27_24\tFM(USB30_PWEN)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(AUDIO_CLKOUT_B)\t\tFM(SSI_SCK2_B)\tFM(TS_SDEN1_D)\tFM(STP_ISEN_1_D)\tFM(STP_OPWM_0_E)FM(RIF3_D0_B)\t\tF_(0, 0)\tFM(TCLK2_B)\tFM(TPU0TO0)\tFM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)\n+#define IP17_31_28\tFM(USB30_OVC)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(AUDIO_CLKOUT1_B)\t\tFM(SSI_WS2_B)\tFM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)\tFM(STP_IVCXO27_0_E)FM(RIF3_D1_B)\tF_(0, 0)\tFM(FSO_TOE_N)\tFM(TPU0TO1)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP18_3_0\tFM(USB2_CH3_PWEN)\tF_(0, 0)\tF_(0, 0)\t\tFM(AUDIO_CLKOUT2_B)\t\tFM(SSI_SCK9_B)\tFM(TS_SDEN0_E)\tFM(STP_ISEN_0_E)\tF_(0, 0)\tFM(RIF2_D0_B)\t\tF_(0, 0)\tF_(0, 0)\tFM(TPU0TO2)\tFM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)\n+#define IP18_7_4\tFM(USB2_CH3_OVC)\tF_(0, 0)\tF_(0, 0)\t\tFM(AUDIO_CLKOUT3_B)\t\tFM(SSI_WS9_B)\tFM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)\tF_(0, 0)\tFM(RIF2_D1_B)\t\tF_(0, 0)\tF_(0, 0)\tFM(TPU0TO3)\tFM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)\n+\n+#define PINMUX_GPSR\t\\\n+\\\n+\t\t\t\t\t\t\t\t\t\t\t\tGPSR6_31 \\\n+\t\t\t\t\t\t\t\t\t\t\t\tGPSR6_30 \\\n+\t\t\t\t\t\t\t\t\t\t\t\tGPSR6_29 \\\n+\t\t\t\t\t\t\t\t\t\t\t\tGPSR6_28 \\\n+\t\tGPSR1_27\t\t\t\t\t\t\t\t\tGPSR6_27 \\\n+\t\tGPSR1_26\t\t\t\t\t\t\t\t\tGPSR6_26 \\\n+\t\tGPSR1_25\t\t\t\t\t\t\tGPSR5_25\tGPSR6_25 \\\n+\t\tGPSR1_24\t\t\t\t\t\t\tGPSR5_24\tGPSR6_24 \\\n+\t\tGPSR1_23\t\t\t\t\t\t\tGPSR5_23\tGPSR6_23 \\\n+\t\tGPSR1_22\t\t\t\t\t\t\tGPSR5_22\tGPSR6_22 \\\n+\t\tGPSR1_21\t\t\t\t\t\t\tGPSR5_21\tGPSR6_21 \\\n+\t\tGPSR1_20\t\t\t\t\t\t\tGPSR5_20\tGPSR6_20 \\\n+\t\tGPSR1_19\t\t\t\t\t\t\tGPSR5_19\tGPSR6_19 \\\n+\t\tGPSR1_18\t\t\t\t\t\t\tGPSR5_18\tGPSR6_18 \\\n+\t\tGPSR1_17\t\t\t\t\tGPSR4_17\tGPSR5_17\tGPSR6_17 \\\n+\t\tGPSR1_16\t\t\t\t\tGPSR4_16\tGPSR5_16\tGPSR6_16 \\\n+GPSR0_15\tGPSR1_15\t\t\tGPSR3_15\tGPSR4_15\tGPSR5_15\tGPSR6_15 \\\n+GPSR0_14\tGPSR1_14\tGPSR2_14\tGPSR3_14\tGPSR4_14\tGPSR5_14\tGPSR6_14 \\\n+GPSR0_13\tGPSR1_13\tGPSR2_13\tGPSR3_13\tGPSR4_13\tGPSR5_13\tGPSR6_13 \\\n+GPSR0_12\tGPSR1_12\tGPSR2_12\tGPSR3_12\tGPSR4_12\tGPSR5_12\tGPSR6_12 \\\n+GPSR0_11\tGPSR1_11\tGPSR2_11\tGPSR3_11\tGPSR4_11\tGPSR5_11\tGPSR6_11 \\\n+GPSR0_10\tGPSR1_10\tGPSR2_10\tGPSR3_10\tGPSR4_10\tGPSR5_10\tGPSR6_10 \\\n+GPSR0_9\t\tGPSR1_9\t\tGPSR2_9\t\tGPSR3_9\t\tGPSR4_9\t\tGPSR5_9\t\tGPSR6_9 \\\n+GPSR0_8\t\tGPSR1_8\t\tGPSR2_8\t\tGPSR3_8\t\tGPSR4_8\t\tGPSR5_8\t\tGPSR6_8 \\\n+GPSR0_7\t\tGPSR1_7\t\tGPSR2_7\t\tGPSR3_7\t\tGPSR4_7\t\tGPSR5_7\t\tGPSR6_7 \\\n+GPSR0_6\t\tGPSR1_6\t\tGPSR2_6\t\tGPSR3_6\t\tGPSR4_6\t\tGPSR5_6\t\tGPSR6_6 \\\n+GPSR0_5\t\tGPSR1_5\t\tGPSR2_5\t\tGPSR3_5\t\tGPSR4_5\t\tGPSR5_5\t\tGPSR6_5 \\\n+GPSR0_4\t\tGPSR1_4\t\tGPSR2_4\t\tGPSR3_4\t\tGPSR4_4\t\tGPSR5_4\t\tGPSR6_4 \\\n+GPSR0_3\t\tGPSR1_3\t\tGPSR2_3\t\tGPSR3_3\t\tGPSR4_3\t\tGPSR5_3\t\tGPSR6_3\t\tGPSR7_3 \\\n+GPSR0_2\t\tGPSR1_2\t\tGPSR2_2\t\tGPSR3_2\t\tGPSR4_2\t\tGPSR5_2\t\tGPSR6_2\t\tGPSR7_2 \\\n+GPSR0_1\t\tGPSR1_1\t\tGPSR2_1\t\tGPSR3_1\t\tGPSR4_1\t\tGPSR5_1\t\tGPSR6_1\t\tGPSR7_1 \\\n+GPSR0_0\t\tGPSR1_0\t\tGPSR2_0\t\tGPSR3_0\t\tGPSR4_0\t\tGPSR5_0\t\tGPSR6_0\t\tGPSR7_0\n+\n+#define PINMUX_IPSR\t\t\t\t\\\n+\\\n+FM(IP0_3_0)\tIP0_3_0\t\tFM(IP1_3_0)\tIP1_3_0\t\tFM(IP2_3_0)\tIP2_3_0\t\tFM(IP3_3_0)\tIP3_3_0 \\\n+FM(IP0_7_4)\tIP0_7_4\t\tFM(IP1_7_4)\tIP1_7_4\t\tFM(IP2_7_4)\tIP2_7_4\t\tFM(IP3_7_4)\tIP3_7_4 \\\n+FM(IP0_11_8)\tIP0_11_8\tFM(IP1_11_8)\tIP1_11_8\tFM(IP2_11_8)\tIP2_11_8\tFM(IP3_11_8)\tIP3_11_8 \\\n+FM(IP0_15_12)\tIP0_15_12\tFM(IP1_15_12)\tIP1_15_12\tFM(IP2_15_12)\tIP2_15_12\tFM(IP3_15_12)\tIP3_15_12 \\\n+FM(IP0_19_16)\tIP0_19_16\tFM(IP1_19_16)\tIP1_19_16\tFM(IP2_19_16)\tIP2_19_16\tFM(IP3_19_16)\tIP3_19_16 \\\n+FM(IP0_23_20)\tIP0_23_20\tFM(IP1_23_20)\tIP1_23_20\tFM(IP2_23_20)\tIP2_23_20\tFM(IP3_23_20)\tIP3_23_20 \\\n+FM(IP0_27_24)\tIP0_27_24\tFM(IP1_27_24)\tIP1_27_24\tFM(IP2_27_24)\tIP2_27_24\tFM(IP3_27_24)\tIP3_27_24 \\\n+FM(IP0_31_28)\tIP0_31_28\tFM(IP1_31_28)\tIP1_31_28\tFM(IP2_31_28)\tIP2_31_28\tFM(IP3_31_28)\tIP3_31_28 \\\n+\\\n+FM(IP4_3_0)\tIP4_3_0\t\tFM(IP5_3_0)\tIP5_3_0\t\tFM(IP6_3_0)\tIP6_3_0\t\tFM(IP7_3_0)\tIP7_3_0 \\\n+FM(IP4_7_4)\tIP4_7_4\t\tFM(IP5_7_4)\tIP5_7_4\t\tFM(IP6_7_4)\tIP6_7_4\t\tFM(IP7_7_4)\tIP7_7_4 \\\n+FM(IP4_11_8)\tIP4_11_8\tFM(IP5_11_8)\tIP5_11_8\tFM(IP6_11_8)\tIP6_11_8\tFM(IP7_11_8)\tIP7_11_8 \\\n+FM(IP4_15_12)\tIP4_15_12\tFM(IP5_15_12)\tIP5_15_12\tFM(IP6_15_12)\tIP6_15_12 \\\n+FM(IP4_19_16)\tIP4_19_16\tFM(IP5_19_16)\tIP5_19_16\tFM(IP6_19_16)\tIP6_19_16\tFM(IP7_19_16)\tIP7_19_16 \\\n+FM(IP4_23_20)\tIP4_23_20\tFM(IP5_23_20)\tIP5_23_20\tFM(IP6_23_20)\tIP6_23_20\tFM(IP7_23_20)\tIP7_23_20 \\\n+FM(IP4_27_24)\tIP4_27_24\tFM(IP5_27_24)\tIP5_27_24\tFM(IP6_27_24)\tIP6_27_24\tFM(IP7_27_24)\tIP7_27_24 \\\n+FM(IP4_31_28)\tIP4_31_28\tFM(IP5_31_28)\tIP5_31_28\tFM(IP6_31_28)\tIP6_31_28\tFM(IP7_31_28)\tIP7_31_28 \\\n+\\\n+FM(IP8_3_0)\tIP8_3_0\t\tFM(IP9_3_0)\tIP9_3_0\t\tFM(IP10_3_0)\tIP10_3_0\tFM(IP11_3_0)\tIP11_3_0 \\\n+FM(IP8_7_4)\tIP8_7_4\t\tFM(IP9_7_4)\tIP9_7_4\t\tFM(IP10_7_4)\tIP10_7_4\tFM(IP11_7_4)\tIP11_7_4 \\\n+FM(IP8_11_8)\tIP8_11_8\tFM(IP9_11_8)\tIP9_11_8\tFM(IP10_11_8)\tIP10_11_8\tFM(IP11_11_8)\tIP11_11_8 \\\n+FM(IP8_15_12)\tIP8_15_12\tFM(IP9_15_12)\tIP9_15_12\tFM(IP10_15_12)\tIP10_15_12\tFM(IP11_15_12)\tIP11_15_12 \\\n+FM(IP8_19_16)\tIP8_19_16\tFM(IP9_19_16)\tIP9_19_16\tFM(IP10_19_16)\tIP10_19_16\tFM(IP11_19_16)\tIP11_19_16 \\\n+FM(IP8_23_20)\tIP8_23_20\tFM(IP9_23_20)\tIP9_23_20\tFM(IP10_23_20)\tIP10_23_20\tFM(IP11_23_20)\tIP11_23_20 \\\n+FM(IP8_27_24)\tIP8_27_24\tFM(IP9_27_24)\tIP9_27_24\tFM(IP10_27_24)\tIP10_27_24\tFM(IP11_27_24)\tIP11_27_24 \\\n+FM(IP8_31_28)\tIP8_31_28\tFM(IP9_31_28)\tIP9_31_28\tFM(IP10_31_28)\tIP10_31_28\tFM(IP11_31_28)\tIP11_31_28 \\\n+\\\n+FM(IP12_3_0)\tIP12_3_0\tFM(IP13_3_0)\tIP13_3_0\tFM(IP14_3_0)\tIP14_3_0\tFM(IP15_3_0)\tIP15_3_0 \\\n+FM(IP12_7_4)\tIP12_7_4\tFM(IP13_7_4)\tIP13_7_4\tFM(IP14_7_4)\tIP14_7_4\tFM(IP15_7_4)\tIP15_7_4 \\\n+FM(IP12_11_8)\tIP12_11_8\tFM(IP13_11_8)\tIP13_11_8\tFM(IP14_11_8)\tIP14_11_8\tFM(IP15_11_8)\tIP15_11_8 \\\n+FM(IP12_15_12)\tIP12_15_12\tFM(IP13_15_12)\tIP13_15_12\tFM(IP14_15_12)\tIP14_15_12\tFM(IP15_15_12)\tIP15_15_12 \\\n+FM(IP12_19_16)\tIP12_19_16\tFM(IP13_19_16)\tIP13_19_16\tFM(IP14_19_16)\tIP14_19_16\tFM(IP15_19_16)\tIP15_19_16 \\\n+FM(IP12_23_20)\tIP12_23_20\tFM(IP13_23_20)\tIP13_23_20\tFM(IP14_23_20)\tIP14_23_20\tFM(IP15_23_20)\tIP15_23_20 \\\n+FM(IP12_27_24)\tIP12_27_24\tFM(IP13_27_24)\tIP13_27_24\tFM(IP14_27_24)\tIP14_27_24\tFM(IP15_27_24)\tIP15_27_24 \\\n+FM(IP12_31_28)\tIP12_31_28\tFM(IP13_31_28)\tIP13_31_28\tFM(IP14_31_28)\tIP14_31_28\tFM(IP15_31_28)\tIP15_31_28 \\\n+\\\n+FM(IP16_3_0)\tIP16_3_0\tFM(IP17_3_0)\tIP17_3_0\tFM(IP18_3_0)\tIP18_3_0 \\\n+FM(IP16_7_4)\tIP16_7_4\tFM(IP17_7_4)\tIP17_7_4\tFM(IP18_7_4)\tIP18_7_4 \\\n+FM(IP16_11_8)\tIP16_11_8\tFM(IP17_11_8)\tIP17_11_8 \\\n+FM(IP16_15_12)\tIP16_15_12\tFM(IP17_15_12)\tIP17_15_12 \\\n+FM(IP16_19_16)\tIP16_19_16\tFM(IP17_19_16)\tIP17_19_16 \\\n+FM(IP16_23_20)\tIP16_23_20\tFM(IP17_23_20)\tIP17_23_20 \\\n+FM(IP16_27_24)\tIP16_27_24\tFM(IP17_27_24)\tIP17_27_24 \\\n+FM(IP16_31_28)\tIP16_31_28\tFM(IP17_31_28)\tIP17_31_28\n+\n+/* MOD_SEL0 */\t\t\t/* 0 */\t\t\t/* 1 */\t\t\t/* 2 */\t\t\t/* 3 */\t\t\t/* 4 */\t\t\t/* 5 */\t\t\t/* 6 */\t\t\t/* 7 */\n+#define MOD_SEL0_31_30_29\tFM(SEL_MSIOF3_0)\tFM(SEL_MSIOF3_1)\tFM(SEL_MSIOF3_2)\tFM(SEL_MSIOF3_3)\tFM(SEL_MSIOF3_4)\tF_(0, 0)\t\tF_(0, 0)\t\tF_(0, 0)\n+#define MOD_SEL0_28_27\t\tFM(SEL_MSIOF2_0)\tFM(SEL_MSIOF2_1)\tFM(SEL_MSIOF2_2)\tFM(SEL_MSIOF2_3)\n+#define MOD_SEL0_26_25_24\tFM(SEL_MSIOF1_0)\tFM(SEL_MSIOF1_1)\tFM(SEL_MSIOF1_2)\tFM(SEL_MSIOF1_3)\tFM(SEL_MSIOF1_4)\tFM(SEL_MSIOF1_5)\tFM(SEL_MSIOF1_6)\tF_(0, 0)\n+#define MOD_SEL0_23\t\tFM(SEL_LBSC_0)\t\tFM(SEL_LBSC_1)\n+#define MOD_SEL0_22\t\tFM(SEL_IEBUS_0)\t\tFM(SEL_IEBUS_1)\n+#define MOD_SEL0_21\t\tFM(SEL_I2C2_0)\t\tFM(SEL_I2C2_1)\n+#define MOD_SEL0_20\t\tFM(SEL_I2C1_0)\t\tFM(SEL_I2C1_1)\n+#define MOD_SEL0_19\t\tFM(SEL_HSCIF4_0)\tFM(SEL_HSCIF4_1)\n+#define MOD_SEL0_18_17\t\tFM(SEL_HSCIF3_0)\tFM(SEL_HSCIF3_1)\tFM(SEL_HSCIF3_2)\tFM(SEL_HSCIF3_3)\n+#define MOD_SEL0_16\t\tFM(SEL_HSCIF1_0)\tFM(SEL_HSCIF1_1)\n+#define MOD_SEL0_14_13\t\tFM(SEL_HSCIF2_0)\tFM(SEL_HSCIF2_1)\tFM(SEL_HSCIF2_2)\tF_(0, 0)\n+#define MOD_SEL0_12\t\tFM(SEL_ETHERAVB_0)\tFM(SEL_ETHERAVB_1)\n+#define MOD_SEL0_11\t\tFM(SEL_DRIF3_0)\t\tFM(SEL_DRIF3_1)\n+#define MOD_SEL0_10\t\tFM(SEL_DRIF2_0)\t\tFM(SEL_DRIF2_1)\n+#define MOD_SEL0_9_8\t\tFM(SEL_DRIF1_0)\t\tFM(SEL_DRIF1_1)\t\tFM(SEL_DRIF1_2)\t\tF_(0, 0)\n+#define MOD_SEL0_7_6\t\tFM(SEL_DRIF0_0)\t\tFM(SEL_DRIF0_1)\t\tFM(SEL_DRIF0_2)\t\tF_(0, 0)\n+#define MOD_SEL0_5\t\tFM(SEL_CANFD0_0)\tFM(SEL_CANFD0_1)\n+#define MOD_SEL0_4_3\t\tFM(SEL_ADG_A_0)\t\tFM(SEL_ADG_A_1)\t\tFM(SEL_ADG_A_2)\t\tFM(SEL_ADG_A_3)\n+\n+/* MOD_SEL1 */\t\t\t/* 0 */\t\t\t/* 1 */\t\t\t/* 2 */\t\t\t/* 3 */\t\t\t/* 4 */\t\t\t/* 5 */\t\t\t/* 6 */\t\t\t/* 7 */\n+#define MOD_SEL1_31_30\t\tFM(SEL_TSIF1_0)\t\tFM(SEL_TSIF1_1)\t\tFM(SEL_TSIF1_2)\t\tFM(SEL_TSIF1_3)\n+#define MOD_SEL1_29_28_27\tFM(SEL_TSIF0_0)\t\tFM(SEL_TSIF0_1)\t\tFM(SEL_TSIF0_2)\t\tFM(SEL_TSIF0_3)\t\tFM(SEL_TSIF0_4)\t\tF_(0, 0)\t\tF_(0, 0)\t\tF_(0, 0)\n+#define MOD_SEL1_26\t\tFM(SEL_TIMER_TMU1_0)\tFM(SEL_TIMER_TMU1_1)\n+#define MOD_SEL1_25_24\t\tFM(SEL_SSP1_1_0)\tFM(SEL_SSP1_1_1)\tFM(SEL_SSP1_1_2)\tFM(SEL_SSP1_1_3)\n+#define MOD_SEL1_23_22_21\tFM(SEL_SSP1_0_0)\tFM(SEL_SSP1_0_1)\tFM(SEL_SSP1_0_2)\tFM(SEL_SSP1_0_3)\tFM(SEL_SSP1_0_4)\tF_(0, 0)\t\tF_(0, 0)\t\tF_(0, 0)\n+#define MOD_SEL1_20\t\tFM(SEL_SSI_0)\t\tFM(SEL_SSI_1)\n+#define MOD_SEL1_19\t\tFM(SEL_SPEED_PULSE_0)\tFM(SEL_SPEED_PULSE_1)\n+#define MOD_SEL1_18_17\t\tFM(SEL_SIMCARD_0)\tFM(SEL_SIMCARD_1)\tFM(SEL_SIMCARD_2)\tFM(SEL_SIMCARD_3)\n+#define MOD_SEL1_16\t\tFM(SEL_SDHI2_0)\t\tFM(SEL_SDHI2_1)\n+#define MOD_SEL1_15_14\t\tFM(SEL_SCIF4_0)\t\tFM(SEL_SCIF4_1)\t\tFM(SEL_SCIF4_2)\t\tF_(0, 0)\n+#define MOD_SEL1_13\t\tFM(SEL_SCIF3_0)\t\tFM(SEL_SCIF3_1)\n+#define MOD_SEL1_12\t\tFM(SEL_SCIF2_0)\t\tFM(SEL_SCIF2_1)\n+#define MOD_SEL1_11\t\tFM(SEL_SCIF1_0)\t\tFM(SEL_SCIF1_1)\n+#define MOD_SEL1_10\t\tFM(SEL_SCIF_0)\t\tFM(SEL_SCIF_1)\n+#define MOD_SEL1_9\t\tFM(SEL_REMOCON_0)\tFM(SEL_REMOCON_1)\n+#define MOD_SEL1_6\t\tFM(SEL_RCAN0_0)\t\tFM(SEL_RCAN0_1)\n+#define MOD_SEL1_5\t\tFM(SEL_PWM6_0)\t\tFM(SEL_PWM6_1)\n+#define MOD_SEL1_4\t\tFM(SEL_PWM5_0)\t\tFM(SEL_PWM5_1)\n+#define MOD_SEL1_3\t\tFM(SEL_PWM4_0)\t\tFM(SEL_PWM4_1)\n+#define MOD_SEL1_2\t\tFM(SEL_PWM3_0)\t\tFM(SEL_PWM3_1)\n+#define MOD_SEL1_1\t\tFM(SEL_PWM2_0)\t\tFM(SEL_PWM2_1)\n+#define MOD_SEL1_0\t\tFM(SEL_PWM1_0)\t\tFM(SEL_PWM1_1)\n+\n+/* MOD_SEL2 */\t\t\t/* 0 */\t\t\t/* 1 */\t\t\t/* 2 */\t\t\t/* 3 */\n+#define MOD_SEL2_31\t\tFM(I2C_SEL_5_0)\t\tFM(I2C_SEL_5_1)\n+#define MOD_SEL2_30\t\tFM(I2C_SEL_3_0)\t\tFM(I2C_SEL_3_1)\n+#define MOD_SEL2_29\t\tFM(I2C_SEL_0_0)\t\tFM(I2C_SEL_0_1)\n+#define MOD_SEL2_28_27\t\tFM(SEL_FM_0)\t\tFM(SEL_FM_1)\t\tFM(SEL_FM_2)\t\tFM(SEL_FM_3)\n+#define MOD_SEL2_26\t\tFM(SEL_SCIF5_0)\t\tFM(SEL_SCIF5_1)\n+#define MOD_SEL2_25_24_23\tFM(SEL_I2C6_0)\t\tFM(SEL_I2C6_1)\t\tFM(SEL_I2C6_2)\t\tF_(0, 0)\t\tF_(0, 0)\t\tF_(0, 0)\t\tF_(0, 0)\t\tF_(0, 0)\n+#define MOD_SEL2_21\t\tFM(SEL_SSI2_0)\t\tFM(SEL_SSI2_1)\n+#define MOD_SEL2_20\t\tFM(SEL_SSI9_0)\t\tFM(SEL_SSI9_1)\n+#define MOD_SEL2_19\t\tFM(SEL_TIMER_TMU2_0)\tFM(SEL_TIMER_TMU2_1)\n+#define MOD_SEL2_18\t\tFM(SEL_ADG_B_0)\t\tFM(SEL_ADG_B_1)\n+#define MOD_SEL2_17\t\tFM(SEL_ADG_C_0)\t\tFM(SEL_ADG_C_1)\n+#define MOD_SEL2_0\t\tFM(SEL_VIN4_0)\t\tFM(SEL_VIN4_1)\n+\n+#define PINMUX_MOD_SELS\t\\\n+\\\n+MOD_SEL0_31_30_29\tMOD_SEL1_31_30\t\tMOD_SEL2_31 \\\n+\t\t\t\t\t\tMOD_SEL2_30 \\\n+\t\t\tMOD_SEL1_29_28_27\tMOD_SEL2_29 \\\n+MOD_SEL0_28_27\t\t\t\t\tMOD_SEL2_28_27 \\\n+MOD_SEL0_26_25_24\tMOD_SEL1_26\t\tMOD_SEL2_26 \\\n+\t\t\tMOD_SEL1_25_24\t\tMOD_SEL2_25_24_23 \\\n+MOD_SEL0_23\t\tMOD_SEL1_23_22_21 \\\n+MOD_SEL0_22 \\\n+MOD_SEL0_21\t\t\t\t\tMOD_SEL2_21 \\\n+MOD_SEL0_20\t\tMOD_SEL1_20\t\tMOD_SEL2_20 \\\n+MOD_SEL0_19\t\tMOD_SEL1_19\t\tMOD_SEL2_19 \\\n+MOD_SEL0_18_17\t\tMOD_SEL1_18_17\t\tMOD_SEL2_18 \\\n+\t\t\t\t\t\tMOD_SEL2_17 \\\n+MOD_SEL0_16\t\tMOD_SEL1_16 \\\n+\t\t\tMOD_SEL1_15_14 \\\n+MOD_SEL0_14_13 \\\n+\t\t\tMOD_SEL1_13 \\\n+MOD_SEL0_12\t\tMOD_SEL1_12 \\\n+MOD_SEL0_11\t\tMOD_SEL1_11 \\\n+MOD_SEL0_10\t\tMOD_SEL1_10 \\\n+MOD_SEL0_9_8\t\tMOD_SEL1_9 \\\n+MOD_SEL0_7_6 \\\n+\t\t\tMOD_SEL1_6 \\\n+MOD_SEL0_5\t\tMOD_SEL1_5 \\\n+MOD_SEL0_4_3\t\tMOD_SEL1_4 \\\n+\t\t\tMOD_SEL1_3 \\\n+\t\t\tMOD_SEL1_2 \\\n+\t\t\tMOD_SEL1_1 \\\n+\t\t\tMOD_SEL1_0\t\tMOD_SEL2_0\n+\n+/*\n+ * These pins are not able to be muxed but have other properties\n+ * that can be set, such as drive-strength or pull-up/pull-down enable.\n+ */\n+#define PINMUX_STATIC \\\n+\tFM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \\\n+\tFM(QSPI0_IO2) FM(QSPI0_IO3) \\\n+\tFM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \\\n+\tFM(QSPI1_IO2) FM(QSPI1_IO3) \\\n+\tFM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \\\n+\tFM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \\\n+\tFM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \\\n+\tFM(AVB_TXCREFCLK) FM(AVB_MDIO) \\\n+\tFM(CLKOUT) FM(PRESETOUT) \\\n+\tFM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \\\n+\tFM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)\n+\n+enum {\n+\tPINMUX_RESERVED = 0,\n+\n+\tPINMUX_DATA_BEGIN,\n+\tGP_ALL(DATA),\n+\tPINMUX_DATA_END,\n+\n+#define F_(x, y)\n+#define FM(x)\tFN_##x,\n+\tPINMUX_FUNCTION_BEGIN,\n+\tGP_ALL(FN),\n+\tPINMUX_GPSR\n+\tPINMUX_IPSR\n+\tPINMUX_MOD_SELS\n+\tPINMUX_FUNCTION_END,\n+#undef F_\n+#undef FM\n+\n+#define F_(x, y)\n+#define FM(x)\tx##_MARK,\n+\tPINMUX_MARK_BEGIN,\n+\tPINMUX_GPSR\n+\tPINMUX_IPSR\n+\tPINMUX_MOD_SELS\n+\tPINMUX_STATIC\n+\tPINMUX_MARK_END,\n+#undef F_\n+#undef FM\n+};\n+\n+static const u16 pinmux_data[] = {\n+\tPINMUX_DATA_GP_ALL(),\n+\n+\tPINMUX_SINGLE(AVS1),\n+\tPINMUX_SINGLE(AVS2),\n+\tPINMUX_SINGLE(HDMI0_CEC),\n+\tPINMUX_SINGLE(HDMI1_CEC),\n+\tPINMUX_SINGLE(I2C_SEL_0_1),\n+\tPINMUX_SINGLE(I2C_SEL_3_1),\n+\tPINMUX_SINGLE(I2C_SEL_5_1),\n+\tPINMUX_SINGLE(MSIOF0_RXD),\n+\tPINMUX_SINGLE(MSIOF0_SCK),\n+\tPINMUX_SINGLE(MSIOF0_TXD),\n+\tPINMUX_SINGLE(SSI_SCK5),\n+\tPINMUX_SINGLE(SSI_SDATA5),\n+\tPINMUX_SINGLE(SSI_WS5),\n+\n+\t/* IPSR0 */\n+\tPINMUX_IPSR_GPSR(IP0_3_0,\tAVB_MDC),\n+\tPINMUX_IPSR_MSEL(IP0_3_0,\tMSIOF2_SS2_C,\t\tSEL_MSIOF2_2),\n+\n+\tPINMUX_IPSR_GPSR(IP0_7_4,\tAVB_MAGIC),\n+\tPINMUX_IPSR_MSEL(IP0_7_4,\tMSIOF2_SS1_C,\t\tSEL_MSIOF2_2),\n+\tPINMUX_IPSR_MSEL(IP0_7_4,\tSCK4_A,\t\t\tSEL_SCIF4_0),\n+\n+\tPINMUX_IPSR_GPSR(IP0_11_8,\tAVB_PHY_INT),\n+\tPINMUX_IPSR_MSEL(IP0_11_8,\tMSIOF2_SYNC_C,\t\tSEL_MSIOF2_2),\n+\tPINMUX_IPSR_MSEL(IP0_11_8,\tRX4_A,\t\t\tSEL_SCIF4_0),\n+\n+\tPINMUX_IPSR_GPSR(IP0_15_12,\tAVB_LINK),\n+\tPINMUX_IPSR_MSEL(IP0_15_12,\tMSIOF2_SCK_C,\t\tSEL_MSIOF2_2),\n+\tPINMUX_IPSR_MSEL(IP0_15_12,\tTX4_A,\t\t\tSEL_SCIF4_0),\n+\n+\tPINMUX_IPSR_MSEL(IP0_19_16,\tAVB_AVTP_MATCH_A,\tSEL_ETHERAVB_0),\n+\tPINMUX_IPSR_MSEL(IP0_19_16,\tMSIOF2_RXD_C,\t\tSEL_MSIOF2_2),\n+\tPINMUX_IPSR_MSEL(IP0_19_16,\tCTS4_N_A,\t\tSEL_SCIF4_0),\n+\tPINMUX_IPSR_GPSR(IP0_19_16,\tFSCLKST2_N_A),\n+\n+\tPINMUX_IPSR_MSEL(IP0_23_20,\tAVB_AVTP_CAPTURE_A,\tSEL_ETHERAVB_0),\n+\tPINMUX_IPSR_MSEL(IP0_23_20,\tMSIOF2_TXD_C,\t\tSEL_MSIOF2_2),\n+\tPINMUX_IPSR_MSEL(IP0_23_20,\tRTS4_N_TANS_A,\t\tSEL_SCIF4_0),\n+\n+\tPINMUX_IPSR_GPSR(IP0_27_24,\tIRQ0),\n+\tPINMUX_IPSR_GPSR(IP0_27_24,\tQPOLB),\n+\tPINMUX_IPSR_GPSR(IP0_27_24,\tDU_CDE),\n+\tPINMUX_IPSR_MSEL(IP0_27_24,\tVI4_DATA0_B,\t\tSEL_VIN4_1),\n+\tPINMUX_IPSR_MSEL(IP0_27_24,\tCAN0_TX_B,\t\tSEL_RCAN0_1),\n+\tPINMUX_IPSR_MSEL(IP0_27_24,\tCANFD0_TX_B,\t\tSEL_CANFD0_1),\n+\tPINMUX_IPSR_MSEL(IP0_27_24,\tMSIOF3_SS2_E,\t\tSEL_MSIOF3_4),\n+\n+\tPINMUX_IPSR_GPSR(IP0_31_28,\tIRQ1),\n+\tPINMUX_IPSR_GPSR(IP0_31_28,\tQPOLA),\n+\tPINMUX_IPSR_GPSR(IP0_31_28,\tDU_DISP),\n+\tPINMUX_IPSR_MSEL(IP0_31_28,\tVI4_DATA1_B,\t\tSEL_VIN4_1),\n+\tPINMUX_IPSR_MSEL(IP0_31_28,\tCAN0_RX_B,\t\tSEL_RCAN0_1),\n+\tPINMUX_IPSR_MSEL(IP0_31_28,\tCANFD0_RX_B,\t\tSEL_CANFD0_1),\n+\tPINMUX_IPSR_MSEL(IP0_31_28,\tMSIOF3_SS1_E,\t\tSEL_MSIOF3_4),\n+\n+\t/* IPSR1 */\n+\tPINMUX_IPSR_GPSR(IP1_3_0,\tIRQ2),\n+\tPINMUX_IPSR_GPSR(IP1_3_0,\tQCPV_QDE),\n+\tPINMUX_IPSR_GPSR(IP1_3_0,\tDU_EXODDF_DU_ODDF_DISP_CDE),\n+\tPINMUX_IPSR_MSEL(IP1_3_0,\tVI4_DATA2_B,\t\tSEL_VIN4_1),\n+\tPINMUX_IPSR_MSEL(IP1_3_0,\tPWM3_B,\t\t\tSEL_PWM3_1),\n+\tPINMUX_IPSR_MSEL(IP1_3_0,\tMSIOF3_SYNC_E,\t\tSEL_MSIOF3_4),\n+\n+\tPINMUX_IPSR_GPSR(IP1_7_4,\tIRQ3),\n+\tPINMUX_IPSR_GPSR(IP1_7_4,\tQSTVB_QVE),\n+\tPINMUX_IPSR_GPSR(IP1_7_4,\tA25),\n+\tPINMUX_IPSR_GPSR(IP1_7_4,\tDU_DOTCLKOUT1),\n+\tPINMUX_IPSR_MSEL(IP1_7_4,\tVI4_DATA3_B,\t\tSEL_VIN4_1),\n+\tPINMUX_IPSR_MSEL(IP1_7_4,\tPWM4_B,\t\t\tSEL_PWM4_1),\n+\tPINMUX_IPSR_MSEL(IP1_7_4,\tMSIOF3_SCK_E,\t\tSEL_MSIOF3_4),\n+\n+\tPINMUX_IPSR_GPSR(IP1_11_8,\tIRQ4),\n+\tPINMUX_IPSR_GPSR(IP1_11_8,\tQSTH_QHS),\n+\tPINMUX_IPSR_GPSR(IP1_11_8,\tA24),\n+\tPINMUX_IPSR_GPSR(IP1_11_8,\tDU_EXHSYNC_DU_HSYNC),\n+\tPINMUX_IPSR_MSEL(IP1_11_8,\tVI4_DATA4_B,\t\tSEL_VIN4_1),\n+\tPINMUX_IPSR_MSEL(IP1_11_8,\tPWM5_B,\t\t\tSEL_PWM5_1),\n+\tPINMUX_IPSR_MSEL(IP1_11_8,\tMSIOF3_RXD_E,\t\tSEL_MSIOF3_4),\n+\n+\tPINMUX_IPSR_GPSR(IP1_15_12,\tIRQ5),\n+\tPINMUX_IPSR_GPSR(IP1_15_12,\tQSTB_QHE),\n+\tPINMUX_IPSR_GPSR(IP1_15_12,\tA23),\n+\tPINMUX_IPSR_GPSR(IP1_15_12,\tDU_EXVSYNC_DU_VSYNC),\n+\tPINMUX_IPSR_MSEL(IP1_15_12,\tVI4_DATA5_B,\t\tSEL_VIN4_1),\n+\tPINMUX_IPSR_MSEL(IP1_15_12,\tPWM6_B,\t\t\tSEL_PWM6_1),\n+\tPINMUX_IPSR_GPSR(IP1_15_12,\tFSCLKST2_N_B),\n+\tPINMUX_IPSR_MSEL(IP1_15_12,\tMSIOF3_TXD_E,\t\tSEL_MSIOF3_4),\n+\n+\tPINMUX_IPSR_GPSR(IP1_19_16,\tPWM0),\n+\tPINMUX_IPSR_GPSR(IP1_19_16,\tAVB_AVTP_PPS),\n+\tPINMUX_IPSR_GPSR(IP1_19_16,\tA22),\n+\tPINMUX_IPSR_MSEL(IP1_19_16,\tVI4_DATA6_B,\t\tSEL_VIN4_1),\n+\tPINMUX_IPSR_MSEL(IP1_19_16,\tIECLK_B,\t\tSEL_IEBUS_1),\n+\n+\tPINMUX_IPSR_MSEL(IP1_23_20,\tPWM1_A,\t\t\tSEL_PWM1_0),\n+\tPINMUX_IPSR_GPSR(IP1_23_20,\tA21),\n+\tPINMUX_IPSR_MSEL(IP1_23_20,\tHRX3_D,\t\t\tSEL_HSCIF3_3),\n+\tPINMUX_IPSR_MSEL(IP1_23_20,\tVI4_DATA7_B,\t\tSEL_VIN4_1),\n+\tPINMUX_IPSR_MSEL(IP1_23_20,\tIERX_B,\t\t\tSEL_IEBUS_1),\n+\n+\tPINMUX_IPSR_MSEL(IP1_27_24,\tPWM2_A,\t\t\tSEL_PWM2_0),\n+\tPINMUX_IPSR_GPSR(IP1_27_24,\tA20),\n+\tPINMUX_IPSR_MSEL(IP1_27_24,\tHTX3_D,\t\t\tSEL_HSCIF3_3),\n+\tPINMUX_IPSR_MSEL(IP1_27_24,\tIETX_B,\t\t\tSEL_IEBUS_1),\n+\n+\tPINMUX_IPSR_GPSR(IP1_31_28,\tA0),\n+\tPINMUX_IPSR_GPSR(IP1_31_28,\tLCDOUT16),\n+\tPINMUX_IPSR_MSEL(IP1_31_28,\tMSIOF3_SYNC_B,\t\tSEL_MSIOF3_1),\n+\tPINMUX_IPSR_GPSR(IP1_31_28,\tVI4_DATA8),\n+\tPINMUX_IPSR_GPSR(IP1_31_28,\tDU_DB0),\n+\tPINMUX_IPSR_MSEL(IP1_31_28,\tPWM3_A,\t\t\tSEL_PWM3_0),\n+\n+\t/* IPSR2 */\n+\tPINMUX_IPSR_GPSR(IP2_3_0,\tA1),\n+\tPINMUX_IPSR_GPSR(IP2_3_0,\tLCDOUT17),\n+\tPINMUX_IPSR_MSEL(IP2_3_0,\tMSIOF3_TXD_B,\t\tSEL_MSIOF3_1),\n+\tPINMUX_IPSR_GPSR(IP2_3_0,\tVI4_DATA9),\n+\tPINMUX_IPSR_GPSR(IP2_3_0,\tDU_DB1),\n+\tPINMUX_IPSR_MSEL(IP2_3_0,\tPWM4_A,\t\t\tSEL_PWM4_0),\n+\n+\tPINMUX_IPSR_GPSR(IP2_7_4,\tA2),\n+\tPINMUX_IPSR_GPSR(IP2_7_4,\tLCDOUT18),\n+\tPINMUX_IPSR_MSEL(IP2_7_4,\tMSIOF3_SCK_B,\t\tSEL_MSIOF3_1),\n+\tPINMUX_IPSR_GPSR(IP2_7_4,\tVI4_DATA10),\n+\tPINMUX_IPSR_GPSR(IP2_7_4,\tDU_DB2),\n+\tPINMUX_IPSR_MSEL(IP2_7_4,\tPWM5_A,\t\t\tSEL_PWM5_0),\n+\n+\tPINMUX_IPSR_GPSR(IP2_11_8,\tA3),\n+\tPINMUX_IPSR_GPSR(IP2_11_8,\tLCDOUT19),\n+\tPINMUX_IPSR_MSEL(IP2_11_8,\tMSIOF3_RXD_B,\t\tSEL_MSIOF3_1),\n+\tPINMUX_IPSR_GPSR(IP2_11_8,\tVI4_DATA11),\n+\tPINMUX_IPSR_GPSR(IP2_11_8,\tDU_DB3),\n+\tPINMUX_IPSR_MSEL(IP2_11_8,\tPWM6_A,\t\t\tSEL_PWM6_0),\n+\n+\tPINMUX_IPSR_GPSR(IP2_15_12,\tA4),\n+\tPINMUX_IPSR_GPSR(IP2_15_12,\tLCDOUT20),\n+\tPINMUX_IPSR_MSEL(IP2_15_12,\tMSIOF3_SS1_B,\t\tSEL_MSIOF3_1),\n+\tPINMUX_IPSR_GPSR(IP2_15_12,\tVI4_DATA12),\n+\tPINMUX_IPSR_GPSR(IP2_15_12,\tVI5_DATA12),\n+\tPINMUX_IPSR_GPSR(IP2_15_12,\tDU_DB4),\n+\n+\tPINMUX_IPSR_GPSR(IP2_19_16,\tA5),\n+\tPINMUX_IPSR_GPSR(IP2_19_16,\tLCDOUT21),\n+\tPINMUX_IPSR_MSEL(IP2_19_16,\tMSIOF3_SS2_B,\t\tSEL_MSIOF3_1),\n+\tPINMUX_IPSR_MSEL(IP2_19_16,\tSCK4_B,\t\t\tSEL_SCIF4_1),\n+\tPINMUX_IPSR_GPSR(IP2_19_16,\tVI4_DATA13),\n+\tPINMUX_IPSR_GPSR(IP2_19_16,\tVI5_DATA13),\n+\tPINMUX_IPSR_GPSR(IP2_19_16,\tDU_DB5),\n+\n+\tPINMUX_IPSR_GPSR(IP2_23_20,\tA6),\n+\tPINMUX_IPSR_GPSR(IP2_23_20,\tLCDOUT22),\n+\tPINMUX_IPSR_MSEL(IP2_23_20,\tMSIOF2_SS1_A,\t\tSEL_MSIOF2_0),\n+\tPINMUX_IPSR_MSEL(IP2_23_20,\tRX4_B,\t\t\tSEL_SCIF4_1),\n+\tPINMUX_IPSR_GPSR(IP2_23_20,\tVI4_DATA14),\n+\tPINMUX_IPSR_GPSR(IP2_23_20,\tVI5_DATA14),\n+\tPINMUX_IPSR_GPSR(IP2_23_20,\tDU_DB6),\n+\n+\tPINMUX_IPSR_GPSR(IP2_27_24,\tA7),\n+\tPINMUX_IPSR_GPSR(IP2_27_24,\tLCDOUT23),\n+\tPINMUX_IPSR_MSEL(IP2_27_24,\tMSIOF2_SS2_A,\t\tSEL_MSIOF2_0),\n+\tPINMUX_IPSR_MSEL(IP2_27_24,\tTX4_B,\t\t\tSEL_SCIF4_1),\n+\tPINMUX_IPSR_GPSR(IP2_27_24,\tVI4_DATA15),\n+\tPINMUX_IPSR_GPSR(IP2_27_24,\tVI5_DATA15),\n+\tPINMUX_IPSR_GPSR(IP2_27_24,\tDU_DB7),\n+\n+\tPINMUX_IPSR_GPSR(IP2_31_28,\tA8),\n+\tPINMUX_IPSR_MSEL(IP2_31_28,\tRX3_B,\t\t\tSEL_SCIF3_1),\n+\tPINMUX_IPSR_MSEL(IP2_31_28,\tMSIOF2_SYNC_A,\t\tSEL_MSIOF2_0),\n+\tPINMUX_IPSR_MSEL(IP2_31_28,\tHRX4_B,\t\t\tSEL_HSCIF4_1),\n+\tPINMUX_IPSR_MSEL(IP2_31_28,\tSDA6_A,\t\t\tSEL_I2C6_0),\n+\tPINMUX_IPSR_MSEL(IP2_31_28,\tAVB_AVTP_MATCH_B,\tSEL_ETHERAVB_1),\n+\tPINMUX_IPSR_MSEL(IP2_31_28,\tPWM1_B,\t\t\tSEL_PWM1_1),\n+\n+\t/* IPSR3 */\n+\tPINMUX_IPSR_GPSR(IP3_3_0,\tA9),\n+\tPINMUX_IPSR_MSEL(IP3_3_0,\tMSIOF2_SCK_A,\t\tSEL_MSIOF2_0),\n+\tPINMUX_IPSR_MSEL(IP3_3_0,\tCTS4_N_B,\t\tSEL_SCIF4_1),\n+\tPINMUX_IPSR_GPSR(IP3_3_0,\tVI5_VSYNC_N),\n+\n+\tPINMUX_IPSR_GPSR(IP3_7_4,\tA10),\n+\tPINMUX_IPSR_MSEL(IP3_7_4,\tMSIOF2_RXD_A,\t\tSEL_MSIOF2_0),\n+\tPINMUX_IPSR_MSEL(IP3_7_4,\tRTS4_N_TANS_B,\t\tSEL_SCIF4_1),\n+\tPINMUX_IPSR_GPSR(IP3_7_4,\tVI5_HSYNC_N),\n+\n+\tPINMUX_IPSR_GPSR(IP3_11_8,\tA11),\n+\tPINMUX_IPSR_MSEL(IP3_11_8,\tTX3_B,\t\t\tSEL_SCIF3_1),\n+\tPINMUX_IPSR_MSEL(IP3_11_8,\tMSIOF2_TXD_A,\t\tSEL_MSIOF2_0),\n+\tPINMUX_IPSR_MSEL(IP3_11_8,\tHTX4_B,\t\t\tSEL_HSCIF4_1),\n+\tPINMUX_IPSR_GPSR(IP3_11_8,\tHSCK4),\n+\tPINMUX_IPSR_GPSR(IP3_11_8,\tVI5_FIELD),\n+\tPINMUX_IPSR_MSEL(IP3_11_8,\tSCL6_A,\t\t\tSEL_I2C6_0),\n+\tPINMUX_IPSR_MSEL(IP3_11_8,\tAVB_AVTP_CAPTURE_B,\tSEL_ETHERAVB_1),\n+\tPINMUX_IPSR_MSEL(IP3_11_8,\tPWM2_B,\t\t\tSEL_PWM2_1),\n+\n+\tPINMUX_IPSR_GPSR(IP3_15_12,\tA12),\n+\tPINMUX_IPSR_GPSR(IP3_15_12,\tLCDOUT12),\n+\tPINMUX_IPSR_MSEL(IP3_15_12,\tMSIOF3_SCK_C,\t\tSEL_MSIOF3_2),\n+\tPINMUX_IPSR_MSEL(IP3_15_12,\tHRX4_A,\t\t\tSEL_HSCIF4_0),\n+\tPINMUX_IPSR_GPSR(IP3_15_12,\tVI5_DATA8),\n+\tPINMUX_IPSR_GPSR(IP3_15_12,\tDU_DG4),\n+\n+\tPINMUX_IPSR_GPSR(IP3_19_16,\tA13),\n+\tPINMUX_IPSR_GPSR(IP3_19_16,\tLCDOUT13),\n+\tPINMUX_IPSR_MSEL(IP3_19_16,\tMSIOF3_SYNC_C,\t\tSEL_MSIOF3_2),\n+\tPINMUX_IPSR_MSEL(IP3_19_16,\tHTX4_A,\t\t\tSEL_HSCIF4_0),\n+\tPINMUX_IPSR_GPSR(IP3_19_16,\tVI5_DATA9),\n+\tPINMUX_IPSR_GPSR(IP3_19_16,\tDU_DG5),\n+\n+\tPINMUX_IPSR_GPSR(IP3_23_20,\tA14),\n+\tPINMUX_IPSR_GPSR(IP3_23_20,\tLCDOUT14),\n+\tPINMUX_IPSR_MSEL(IP3_23_20,\tMSIOF3_RXD_C,\t\tSEL_MSIOF3_2),\n+\tPINMUX_IPSR_GPSR(IP3_23_20,\tHCTS4_N),\n+\tPINMUX_IPSR_GPSR(IP3_23_20,\tVI5_DATA10),\n+\tPINMUX_IPSR_GPSR(IP3_23_20,\tDU_DG6),\n+\n+\tPINMUX_IPSR_GPSR(IP3_27_24,\tA15),\n+\tPINMUX_IPSR_GPSR(IP3_27_24,\tLCDOUT15),\n+\tPINMUX_IPSR_MSEL(IP3_27_24,\tMSIOF3_TXD_C,\t\tSEL_MSIOF3_2),\n+\tPINMUX_IPSR_GPSR(IP3_27_24,\tHRTS4_N),\n+\tPINMUX_IPSR_GPSR(IP3_27_24,\tVI5_DATA11),\n+\tPINMUX_IPSR_GPSR(IP3_27_24,\tDU_DG7),\n+\n+\tPINMUX_IPSR_GPSR(IP3_31_28,\tA16),\n+\tPINMUX_IPSR_GPSR(IP3_31_28,\tLCDOUT8),\n+\tPINMUX_IPSR_GPSR(IP3_31_28,\tVI4_FIELD),\n+\tPINMUX_IPSR_GPSR(IP3_31_28,\tDU_DG0),\n+\n+\t/* IPSR4 */\n+\tPINMUX_IPSR_GPSR(IP4_3_0,\tA17),\n+\tPINMUX_IPSR_GPSR(IP4_3_0,\tLCDOUT9),\n+\tPINMUX_IPSR_GPSR(IP4_3_0,\tVI4_VSYNC_N),\n+\tPINMUX_IPSR_GPSR(IP4_3_0,\tDU_DG1),\n+\n+\tPINMUX_IPSR_GPSR(IP4_7_4,\tA18),\n+\tPINMUX_IPSR_GPSR(IP4_7_4,\tLCDOUT10),\n+\tPINMUX_IPSR_GPSR(IP4_7_4,\tVI4_HSYNC_N),\n+\tPINMUX_IPSR_GPSR(IP4_7_4,\tDU_DG2),\n+\n+\tPINMUX_IPSR_GPSR(IP4_11_8,\tA19),\n+\tPINMUX_IPSR_GPSR(IP4_11_8,\tLCDOUT11),\n+\tPINMUX_IPSR_GPSR(IP4_11_8,\tVI4_CLKENB),\n+\tPINMUX_IPSR_GPSR(IP4_11_8,\tDU_DG3),\n+\n+\tPINMUX_IPSR_GPSR(IP4_15_12,\tCS0_N),\n+\tPINMUX_IPSR_GPSR(IP4_15_12,\tVI5_CLKENB),\n+\n+\tPINMUX_IPSR_GPSR(IP4_19_16,\tCS1_N),\n+\tPINMUX_IPSR_GPSR(IP4_19_16,\tVI5_CLK),\n+\tPINMUX_IPSR_MSEL(IP4_19_16,\tEX_WAIT0_B,\t\tSEL_LBSC_1),\n+\n+\tPINMUX_IPSR_GPSR(IP4_23_20,\tBS_N),\n+\tPINMUX_IPSR_GPSR(IP4_23_20,\tQSTVA_QVS),\n+\tPINMUX_IPSR_MSEL(IP4_23_20,\tMSIOF3_SCK_D,\t\tSEL_MSIOF3_3),\n+\tPINMUX_IPSR_GPSR(IP4_23_20,\tSCK3),\n+\tPINMUX_IPSR_GPSR(IP4_23_20,\tHSCK3),\n+\tPINMUX_IPSR_GPSR(IP4_23_20,\tCAN1_TX),\n+\tPINMUX_IPSR_GPSR(IP4_23_20,\tCANFD1_TX),\n+\tPINMUX_IPSR_MSEL(IP4_23_20,\tIETX_A,\t\t\tSEL_IEBUS_0),\n+\n+\tPINMUX_IPSR_GPSR(IP4_27_24,\tRD_N),\n+\tPINMUX_IPSR_MSEL(IP4_27_24,\tMSIOF3_SYNC_D,\t\tSEL_MSIOF3_3),\n+\tPINMUX_IPSR_MSEL(IP4_27_24,\tRX3_A,\t\t\tSEL_SCIF3_0),\n+\tPINMUX_IPSR_MSEL(IP4_27_24,\tHRX3_A,\t\t\tSEL_HSCIF3_0),\n+\tPINMUX_IPSR_MSEL(IP4_27_24,\tCAN0_TX_A,\t\tSEL_RCAN0_0),\n+\tPINMUX_IPSR_MSEL(IP4_27_24,\tCANFD0_TX_A,\t\tSEL_CANFD0_0),\n+\n+\tPINMUX_IPSR_GPSR(IP4_31_28,\tRD_WR_N),\n+\tPINMUX_IPSR_MSEL(IP4_31_28,\tMSIOF3_RXD_D,\t\tSEL_MSIOF3_3),\n+\tPINMUX_IPSR_MSEL(IP4_31_28,\tTX3_A,\t\t\tSEL_SCIF3_0),\n+\tPINMUX_IPSR_MSEL(IP4_31_28,\tHTX3_A,\t\t\tSEL_HSCIF3_0),\n+\tPINMUX_IPSR_MSEL(IP4_31_28,\tCAN0_RX_A,\t\tSEL_RCAN0_0),\n+\tPINMUX_IPSR_MSEL(IP4_31_28,\tCANFD0_RX_A,\t\tSEL_CANFD0_0),\n+\n+\t/* IPSR5 */\n+\tPINMUX_IPSR_GPSR(IP5_3_0,\tWE0_N),\n+\tPINMUX_IPSR_MSEL(IP5_3_0,\tMSIOF3_TXD_D,\t\tSEL_MSIOF3_3),\n+\tPINMUX_IPSR_GPSR(IP5_3_0,\tCTS3_N),\n+\tPINMUX_IPSR_GPSR(IP5_3_0,\tHCTS3_N),\n+\tPINMUX_IPSR_MSEL(IP5_3_0,\tSCL6_B,\t\t\tSEL_I2C6_1),\n+\tPINMUX_IPSR_GPSR(IP5_3_0,\tCAN_CLK),\n+\tPINMUX_IPSR_MSEL(IP5_3_0,\tIECLK_A,\t\tSEL_IEBUS_0),\n+\n+\tPINMUX_IPSR_GPSR(IP5_7_4,\tWE1_N),\n+\tPINMUX_IPSR_MSEL(IP5_7_4,\tMSIOF3_SS1_D,\t\tSEL_MSIOF3_3),\n+\tPINMUX_IPSR_GPSR(IP5_7_4,\tRTS3_N_TANS),\n+\tPINMUX_IPSR_GPSR(IP5_7_4,\tHRTS3_N),\n+\tPINMUX_IPSR_MSEL(IP5_7_4,\tSDA6_B,\t\t\tSEL_I2C6_1),\n+\tPINMUX_IPSR_GPSR(IP5_7_4,\tCAN1_RX),\n+\tPINMUX_IPSR_GPSR(IP5_7_4,\tCANFD1_RX),\n+\tPINMUX_IPSR_MSEL(IP5_7_4,\tIERX_A,\t\t\tSEL_IEBUS_0),\n+\n+\tPINMUX_IPSR_MSEL(IP5_11_8,\tEX_WAIT0_A,\t\tSEL_LBSC_0),\n+\tPINMUX_IPSR_GPSR(IP5_11_8,\tQCLK),\n+\tPINMUX_IPSR_GPSR(IP5_11_8,\tVI4_CLK),\n+\tPINMUX_IPSR_GPSR(IP5_11_8,\tDU_DOTCLKOUT0),\n+\n+\tPINMUX_IPSR_GPSR(IP5_15_12,\tD0),\n+\tPINMUX_IPSR_MSEL(IP5_15_12,\tMSIOF2_SS1_B,\t\tSEL_MSIOF2_1),\n+\tPINMUX_IPSR_MSEL(IP5_15_12,\tMSIOF3_SCK_A,\t\tSEL_MSIOF3_0),\n+\tPINMUX_IPSR_GPSR(IP5_15_12,\tVI4_DATA16),\n+\tPINMUX_IPSR_GPSR(IP5_15_12,\tVI5_DATA0),\n+\n+\tPINMUX_IPSR_GPSR(IP5_19_16,\tD1),\n+\tPINMUX_IPSR_MSEL(IP5_19_16,\tMSIOF2_SS2_B,\t\tSEL_MSIOF2_1),\n+\tPINMUX_IPSR_MSEL(IP5_19_16,\tMSIOF3_SYNC_A,\t\tSEL_MSIOF3_0),\n+\tPINMUX_IPSR_GPSR(IP5_19_16,\tVI4_DATA17),\n+\tPINMUX_IPSR_GPSR(IP5_19_16,\tVI5_DATA1),\n+\n+\tPINMUX_IPSR_GPSR(IP5_23_20,\tD2),\n+\tPINMUX_IPSR_MSEL(IP5_23_20,\tMSIOF3_RXD_A,\t\tSEL_MSIOF3_0),\n+\tPINMUX_IPSR_GPSR(IP5_23_20,\tVI4_DATA18),\n+\tPINMUX_IPSR_GPSR(IP5_23_20,\tVI5_DATA2),\n+\n+\tPINMUX_IPSR_GPSR(IP5_27_24,\tD3),\n+\tPINMUX_IPSR_MSEL(IP5_27_24,\tMSIOF3_TXD_A,\t\tSEL_MSIOF3_0),\n+\tPINMUX_IPSR_GPSR(IP5_27_24,\tVI4_DATA19),\n+\tPINMUX_IPSR_GPSR(IP5_27_24,\tVI5_DATA3),\n+\n+\tPINMUX_IPSR_GPSR(IP5_31_28,\tD4),\n+\tPINMUX_IPSR_MSEL(IP5_31_28,\tMSIOF2_SCK_B,\t\tSEL_MSIOF2_1),\n+\tPINMUX_IPSR_GPSR(IP5_31_28,\tVI4_DATA20),\n+\tPINMUX_IPSR_GPSR(IP5_31_28,\tVI5_DATA4),\n+\n+\t/* IPSR6 */\n+\tPINMUX_IPSR_GPSR(IP6_3_0,\tD5),\n+\tPINMUX_IPSR_MSEL(IP6_3_0,\tMSIOF2_SYNC_B,\t\tSEL_MSIOF2_1),\n+\tPINMUX_IPSR_GPSR(IP6_3_0,\tVI4_DATA21),\n+\tPINMUX_IPSR_GPSR(IP6_3_0,\tVI5_DATA5),\n+\n+\tPINMUX_IPSR_GPSR(IP6_7_4,\tD6),\n+\tPINMUX_IPSR_MSEL(IP6_7_4,\tMSIOF2_RXD_B,\t\tSEL_MSIOF2_1),\n+\tPINMUX_IPSR_GPSR(IP6_7_4,\tVI4_DATA22),\n+\tPINMUX_IPSR_GPSR(IP6_7_4,\tVI5_DATA6),\n+\n+\tPINMUX_IPSR_GPSR(IP6_11_8,\tD7),\n+\tPINMUX_IPSR_MSEL(IP6_11_8,\tMSIOF2_TXD_B,\t\tSEL_MSIOF2_1),\n+\tPINMUX_IPSR_GPSR(IP6_11_8,\tVI4_DATA23),\n+\tPINMUX_IPSR_GPSR(IP6_11_8,\tVI5_DATA7),\n+\n+\tPINMUX_IPSR_GPSR(IP6_15_12,\tD8),\n+\tPINMUX_IPSR_GPSR(IP6_15_12,\tLCDOUT0),\n+\tPINMUX_IPSR_MSEL(IP6_15_12,\tMSIOF2_SCK_D,\t\tSEL_MSIOF2_3),\n+\tPINMUX_IPSR_MSEL(IP6_15_12,\tSCK4_C,\t\t\tSEL_SCIF4_2),\n+\tPINMUX_IPSR_MSEL(IP6_15_12,\tVI4_DATA0_A,\t\tSEL_VIN4_0),\n+\tPINMUX_IPSR_GPSR(IP6_15_12,\tDU_DR0),\n+\n+\tPINMUX_IPSR_GPSR(IP6_19_16,\tD9),\n+\tPINMUX_IPSR_GPSR(IP6_19_16,\tLCDOUT1),\n+\tPINMUX_IPSR_MSEL(IP6_19_16,\tMSIOF2_SYNC_D,\t\tSEL_MSIOF2_3),\n+\tPINMUX_IPSR_MSEL(IP6_19_16,\tVI4_DATA1_A,\t\tSEL_VIN4_0),\n+\tPINMUX_IPSR_GPSR(IP6_19_16,\tDU_DR1),\n+\n+\tPINMUX_IPSR_GPSR(IP6_23_20,\tD10),\n+\tPINMUX_IPSR_GPSR(IP6_23_20,\tLCDOUT2),\n+\tPINMUX_IPSR_MSEL(IP6_23_20,\tMSIOF2_RXD_D,\t\tSEL_MSIOF2_3),\n+\tPINMUX_IPSR_MSEL(IP6_23_20,\tHRX3_B,\t\t\tSEL_HSCIF3_1),\n+\tPINMUX_IPSR_MSEL(IP6_23_20,\tVI4_DATA2_A,\t\tSEL_VIN4_0),\n+\tPINMUX_IPSR_MSEL(IP6_23_20,\tCTS4_N_C,\t\tSEL_SCIF4_2),\n+\tPINMUX_IPSR_GPSR(IP6_23_20,\tDU_DR2),\n+\n+\tPINMUX_IPSR_GPSR(IP6_27_24,\tD11),\n+\tPINMUX_IPSR_GPSR(IP6_27_24,\tLCDOUT3),\n+\tPINMUX_IPSR_MSEL(IP6_27_24,\tMSIOF2_TXD_D,\t\tSEL_MSIOF2_3),\n+\tPINMUX_IPSR_MSEL(IP6_27_24,\tHTX3_B,\t\t\tSEL_HSCIF3_1),\n+\tPINMUX_IPSR_MSEL(IP6_27_24,\tVI4_DATA3_A,\t\tSEL_VIN4_0),\n+\tPINMUX_IPSR_MSEL(IP6_27_24,\tRTS4_N_TANS_C,\t\tSEL_SCIF4_2),\n+\tPINMUX_IPSR_GPSR(IP6_27_24,\tDU_DR3),\n+\n+\tPINMUX_IPSR_GPSR(IP6_31_28,\tD12),\n+\tPINMUX_IPSR_GPSR(IP6_31_28,\tLCDOUT4),\n+\tPINMUX_IPSR_MSEL(IP6_31_28,\tMSIOF2_SS1_D,\t\tSEL_MSIOF2_3),\n+\tPINMUX_IPSR_MSEL(IP6_31_28,\tRX4_C,\t\t\tSEL_SCIF4_2),\n+\tPINMUX_IPSR_MSEL(IP6_31_28,\tVI4_DATA4_A,\t\tSEL_VIN4_0),\n+\tPINMUX_IPSR_GPSR(IP6_31_28,\tDU_DR4),\n+\n+\t/* IPSR7 */\n+\tPINMUX_IPSR_GPSR(IP7_3_0,\tD13),\n+\tPINMUX_IPSR_GPSR(IP7_3_0,\tLCDOUT5),\n+\tPINMUX_IPSR_MSEL(IP7_3_0,\tMSIOF2_SS2_D,\t\tSEL_MSIOF2_3),\n+\tPINMUX_IPSR_MSEL(IP7_3_0,\tTX4_C,\t\t\tSEL_SCIF4_2),\n+\tPINMUX_IPSR_MSEL(IP7_3_0,\tVI4_DATA5_A,\t\tSEL_VIN4_0),\n+\tPINMUX_IPSR_GPSR(IP7_3_0,\tDU_DR5),\n+\n+\tPINMUX_IPSR_GPSR(IP7_7_4,\tD14),\n+\tPINMUX_IPSR_GPSR(IP7_7_4,\tLCDOUT6),\n+\tPINMUX_IPSR_MSEL(IP7_7_4,\tMSIOF3_SS1_A,\t\tSEL_MSIOF3_0),\n+\tPINMUX_IPSR_MSEL(IP7_7_4,\tHRX3_C,\t\t\tSEL_HSCIF3_2),\n+\tPINMUX_IPSR_MSEL(IP7_7_4,\tVI4_DATA6_A,\t\tSEL_VIN4_0),\n+\tPINMUX_IPSR_GPSR(IP7_7_4,\tDU_DR6),\n+\tPINMUX_IPSR_MSEL(IP7_7_4,\tSCL6_C,\t\t\tSEL_I2C6_2),\n+\n+\tPINMUX_IPSR_GPSR(IP7_11_8,\tD15),\n+\tPINMUX_IPSR_GPSR(IP7_11_8,\tLCDOUT7),\n+\tPINMUX_IPSR_MSEL(IP7_11_8,\tMSIOF3_SS2_A,\t\tSEL_MSIOF3_0),\n+\tPINMUX_IPSR_MSEL(IP7_11_8,\tHTX3_C,\t\t\tSEL_HSCIF3_2),\n+\tPINMUX_IPSR_MSEL(IP7_11_8,\tVI4_DATA7_A,\t\tSEL_VIN4_0),\n+\tPINMUX_IPSR_GPSR(IP7_11_8,\tDU_DR7),\n+\tPINMUX_IPSR_MSEL(IP7_11_8,\tSDA6_C,\t\t\tSEL_I2C6_2),\n+\n+\tPINMUX_IPSR_GPSR(IP7_19_16,\tSD0_CLK),\n+\tPINMUX_IPSR_MSEL(IP7_19_16,\tMSIOF1_SCK_E,\t\tSEL_MSIOF1_4),\n+\tPINMUX_IPSR_MSEL(IP7_19_16,\tSTP_OPWM_0_B,\t\tSEL_SSP1_0_1),\n+\n+\tPINMUX_IPSR_GPSR(IP7_23_20,\tSD0_CMD),\n+\tPINMUX_IPSR_MSEL(IP7_23_20,\tMSIOF1_SYNC_E,\t\tSEL_MSIOF1_4),\n+\tPINMUX_IPSR_MSEL(IP7_23_20,\tSTP_IVCXO27_0_B,\tSEL_SSP1_0_1),\n+\n+\tPINMUX_IPSR_GPSR(IP7_27_24,\tSD0_DAT0),\n+\tPINMUX_IPSR_MSEL(IP7_27_24,\tMSIOF1_RXD_E,\t\tSEL_MSIOF1_4),\n+\tPINMUX_IPSR_MSEL(IP7_27_24,\tTS_SCK0_B,\t\tSEL_TSIF0_1),\n+\tPINMUX_IPSR_MSEL(IP7_27_24,\tSTP_ISCLK_0_B,\t\tSEL_SSP1_0_1),\n+\n+\tPINMUX_IPSR_GPSR(IP7_31_28,\tSD0_DAT1),\n+\tPINMUX_IPSR_MSEL(IP7_31_28,\tMSIOF1_TXD_E,\t\tSEL_MSIOF1_4),\n+\tPINMUX_IPSR_MSEL(IP7_31_28,\tTS_SPSYNC0_B,\t\tSEL_TSIF0_1),\n+\tPINMUX_IPSR_MSEL(IP7_31_28,\tSTP_ISSYNC_0_B,\t\tSEL_SSP1_0_1),\n+\n+\t/* IPSR8 */\n+\tPINMUX_IPSR_GPSR(IP8_3_0,\tSD0_DAT2),\n+\tPINMUX_IPSR_MSEL(IP8_3_0,\tMSIOF1_SS1_E,\t\tSEL_MSIOF1_4),\n+\tPINMUX_IPSR_MSEL(IP8_3_0,\tTS_SDAT0_B,\t\tSEL_TSIF0_1),\n+\tPINMUX_IPSR_MSEL(IP8_3_0,\tSTP_ISD_0_B,\t\tSEL_SSP1_0_1),\n+\n+\tPINMUX_IPSR_GPSR(IP8_7_4,\tSD0_DAT3),\n+\tPINMUX_IPSR_MSEL(IP8_7_4,\tMSIOF1_SS2_E,\t\tSEL_MSIOF1_4),\n+\tPINMUX_IPSR_MSEL(IP8_7_4,\tTS_SDEN0_B,\t\tSEL_TSIF0_1),\n+\tPINMUX_IPSR_MSEL(IP8_7_4,\tSTP_ISEN_0_B,\t\tSEL_SSP1_0_1),\n+\n+\tPINMUX_IPSR_GPSR(IP8_11_8,\tSD1_CLK),\n+\tPINMUX_IPSR_MSEL(IP8_11_8,\tMSIOF1_SCK_G,\t\tSEL_MSIOF1_6),\n+\tPINMUX_IPSR_MSEL(IP8_11_8,\tSIM0_CLK_A,\t\tSEL_SIMCARD_0),\n+\n+\tPINMUX_IPSR_GPSR(IP8_15_12,\tSD1_CMD),\n+\tPINMUX_IPSR_MSEL(IP8_15_12,\tMSIOF1_SYNC_G,\t\tSEL_MSIOF1_6),\n+\tPINMUX_IPSR_GPSR(IP8_15_12,\tNFCE_N_B),\n+\tPINMUX_IPSR_MSEL(IP8_15_12,\tSIM0_D_A,\t\tSEL_SIMCARD_0),\n+\tPINMUX_IPSR_MSEL(IP8_15_12,\tSTP_IVCXO27_1_B,\tSEL_SSP1_1_1),\n+\n+\tPINMUX_IPSR_GPSR(IP8_19_16,\tSD1_DAT0),\n+\tPINMUX_IPSR_GPSR(IP8_19_16,\tSD2_DAT4),\n+\tPINMUX_IPSR_MSEL(IP8_19_16,\tMSIOF1_RXD_G,\t\tSEL_MSIOF1_6),\n+\tPINMUX_IPSR_GPSR(IP8_19_16,\tNFWP_N_B),\n+\tPINMUX_IPSR_MSEL(IP8_19_16,\tTS_SCK1_B,\t\tSEL_TSIF1_1),\n+\tPINMUX_IPSR_MSEL(IP8_19_16,\tSTP_ISCLK_1_B,\t\tSEL_SSP1_1_1),\n+\n+\tPINMUX_IPSR_GPSR(IP8_23_20,\tSD1_DAT1),\n+\tPINMUX_IPSR_GPSR(IP8_23_20,\tSD2_DAT5),\n+\tPINMUX_IPSR_MSEL(IP8_23_20,\tMSIOF1_TXD_G,\t\tSEL_MSIOF1_6),\n+\tPINMUX_IPSR_GPSR(IP8_23_20,\tNFDATA14_B),\n+\tPINMUX_IPSR_MSEL(IP8_23_20,\tTS_SPSYNC1_B,\t\tSEL_TSIF1_1),\n+\tPINMUX_IPSR_MSEL(IP8_23_20,\tSTP_ISSYNC_1_B,\t\tSEL_SSP1_1_1),\n+\n+\tPINMUX_IPSR_GPSR(IP8_27_24,\tSD1_DAT2),\n+\tPINMUX_IPSR_GPSR(IP8_27_24,\tSD2_DAT6),\n+\tPINMUX_IPSR_MSEL(IP8_27_24,\tMSIOF1_SS1_G,\t\tSEL_MSIOF1_6),\n+\tPINMUX_IPSR_GPSR(IP8_27_24,\tNFDATA15_B),\n+\tPINMUX_IPSR_MSEL(IP8_27_24,\tTS_SDAT1_B,\t\tSEL_TSIF1_1),\n+\tPINMUX_IPSR_MSEL(IP8_27_24,\tSTP_ISD_1_B,\t\tSEL_SSP1_1_1),\n+\n+\tPINMUX_IPSR_GPSR(IP8_31_28,\tSD1_DAT3),\n+\tPINMUX_IPSR_GPSR(IP8_31_28,\tSD2_DAT7),\n+\tPINMUX_IPSR_MSEL(IP8_31_28,\tMSIOF1_SS2_G,\t\tSEL_MSIOF1_6),\n+\tPINMUX_IPSR_GPSR(IP8_31_28,\tNFRB_N_B),\n+\tPINMUX_IPSR_MSEL(IP8_31_28,\tTS_SDEN1_B,\t\tSEL_TSIF1_1),\n+\tPINMUX_IPSR_MSEL(IP8_31_28,\tSTP_ISEN_1_B,\t\tSEL_SSP1_1_1),\n+\n+\t/* IPSR9 */\n+\tPINMUX_IPSR_GPSR(IP9_3_0,\tSD2_CLK),\n+\tPINMUX_IPSR_GPSR(IP9_3_0,\tNFDATA8),\n+\n+\tPINMUX_IPSR_GPSR(IP9_7_4,\tSD2_CMD),\n+\tPINMUX_IPSR_GPSR(IP9_7_4,\tNFDATA9),\n+\n+\tPINMUX_IPSR_GPSR(IP9_11_8,\tSD2_DAT0),\n+\tPINMUX_IPSR_GPSR(IP9_11_8,\tNFDATA10),\n+\n+\tPINMUX_IPSR_GPSR(IP9_15_12,\tSD2_DAT1),\n+\tPINMUX_IPSR_GPSR(IP9_15_12,\tNFDATA11),\n+\n+\tPINMUX_IPSR_GPSR(IP9_19_16,\tSD2_DAT2),\n+\tPINMUX_IPSR_GPSR(IP9_19_16,\tNFDATA12),\n+\n+\tPINMUX_IPSR_GPSR(IP9_23_20,\tSD2_DAT3),\n+\tPINMUX_IPSR_GPSR(IP9_23_20,\tNFDATA13),\n+\n+\tPINMUX_IPSR_GPSR(IP9_27_24,\tSD2_DS),\n+\tPINMUX_IPSR_GPSR(IP9_27_24,\tNFALE),\n+\tPINMUX_IPSR_GPSR(IP9_27_24,\tSATA_DEVSLP_B),\n+\n+\tPINMUX_IPSR_GPSR(IP9_31_28,\tSD3_CLK),\n+\tPINMUX_IPSR_GPSR(IP9_31_28,\tNFWE_N),\n+\n+\t/* IPSR10 */\n+\tPINMUX_IPSR_GPSR(IP10_3_0,\tSD3_CMD),\n+\tPINMUX_IPSR_GPSR(IP10_3_0,\tNFRE_N),\n+\n+\tPINMUX_IPSR_GPSR(IP10_7_4,\tSD3_DAT0),\n+\tPINMUX_IPSR_GPSR(IP10_7_4,\tNFDATA0),\n+\n+\tPINMUX_IPSR_GPSR(IP10_11_8,\tSD3_DAT1),\n+\tPINMUX_IPSR_GPSR(IP10_11_8,\tNFDATA1),\n+\n+\tPINMUX_IPSR_GPSR(IP10_15_12,\tSD3_DAT2),\n+\tPINMUX_IPSR_GPSR(IP10_15_12,\tNFDATA2),\n+\n+\tPINMUX_IPSR_GPSR(IP10_19_16,\tSD3_DAT3),\n+\tPINMUX_IPSR_GPSR(IP10_19_16,\tNFDATA3),\n+\n+\tPINMUX_IPSR_GPSR(IP10_23_20,\tSD3_DAT4),\n+\tPINMUX_IPSR_MSEL(IP10_23_20,\tSD2_CD_A,\t\tSEL_SDHI2_0),\n+\tPINMUX_IPSR_GPSR(IP10_23_20,\tNFDATA4),\n+\n+\tPINMUX_IPSR_GPSR(IP10_27_24,\tSD3_DAT5),\n+\tPINMUX_IPSR_MSEL(IP10_27_24,\tSD2_WP_A,\t\tSEL_SDHI2_0),\n+\tPINMUX_IPSR_GPSR(IP10_27_24,\tNFDATA5),\n+\n+\tPINMUX_IPSR_GPSR(IP10_31_28,\tSD3_DAT6),\n+\tPINMUX_IPSR_GPSR(IP10_31_28,\tSD3_CD),\n+\tPINMUX_IPSR_GPSR(IP10_31_28,\tNFDATA6),\n+\n+\t/* IPSR11 */\n+\tPINMUX_IPSR_GPSR(IP11_3_0,\tSD3_DAT7),\n+\tPINMUX_IPSR_GPSR(IP11_3_0,\tSD3_WP),\n+\tPINMUX_IPSR_GPSR(IP11_3_0,\tNFDATA7),\n+\n+\tPINMUX_IPSR_GPSR(IP11_7_4,\tSD3_DS),\n+\tPINMUX_IPSR_GPSR(IP11_7_4,\tNFCLE),\n+\n+\tPINMUX_IPSR_GPSR(IP11_11_8,\tSD0_CD),\n+\tPINMUX_IPSR_MSEL(IP11_11_8,\tSCL2_B,\t\t\tSEL_I2C2_1),\n+\tPINMUX_IPSR_MSEL(IP11_11_8,\tSIM0_RST_A,\t\tSEL_SIMCARD_0),\n+\n+\tPINMUX_IPSR_GPSR(IP11_15_12,\tSD0_WP),\n+\tPINMUX_IPSR_MSEL(IP11_15_12,\tSDA2_B,\t\t\tSEL_I2C2_1),\n+\n+\tPINMUX_IPSR_GPSR(IP11_19_16,\tSD1_CD),\n+\tPINMUX_IPSR_MSEL(IP11_19_16,\tSIM0_CLK_B,\t\tSEL_SIMCARD_1),\n+\n+\tPINMUX_IPSR_GPSR(IP11_23_20,\tSD1_WP),\n+\tPINMUX_IPSR_MSEL(IP11_23_20,\tSIM0_D_B,\t\tSEL_SIMCARD_1),\n+\n+\tPINMUX_IPSR_GPSR(IP11_27_24,\tSCK0),\n+\tPINMUX_IPSR_MSEL(IP11_27_24,\tHSCK1_B,\t\tSEL_HSCIF1_1),\n+\tPINMUX_IPSR_MSEL(IP11_27_24,\tMSIOF1_SS2_B,\t\tSEL_MSIOF1_1),\n+\tPINMUX_IPSR_MSEL(IP11_27_24,\tAUDIO_CLKC_B,\t\tSEL_ADG_C_1),\n+\tPINMUX_IPSR_MSEL(IP11_27_24,\tSDA2_A,\t\t\tSEL_I2C2_0),\n+\tPINMUX_IPSR_MSEL(IP11_27_24,\tSIM0_RST_B,\t\tSEL_SIMCARD_1),\n+\tPINMUX_IPSR_MSEL(IP11_27_24,\tSTP_OPWM_0_C,\t\tSEL_SSP1_0_2),\n+\tPINMUX_IPSR_MSEL(IP11_27_24,\tRIF0_CLK_B,\t\tSEL_DRIF0_1),\n+\tPINMUX_IPSR_GPSR(IP11_27_24,\tADICHS2),\n+\tPINMUX_IPSR_MSEL(IP11_27_24,\tSCK5_B,\t\t\tSEL_SCIF5_1),\n+\n+\tPINMUX_IPSR_GPSR(IP11_31_28,\tRX0),\n+\tPINMUX_IPSR_MSEL(IP11_31_28,\tHRX1_B,\t\t\tSEL_HSCIF1_1),\n+\tPINMUX_IPSR_MSEL(IP11_31_28,\tTS_SCK0_C,\t\tSEL_TSIF0_2),\n+\tPINMUX_IPSR_MSEL(IP11_31_28,\tSTP_ISCLK_0_C,\t\tSEL_SSP1_0_2),\n+\tPINMUX_IPSR_MSEL(IP11_31_28,\tRIF0_D0_B,\t\tSEL_DRIF0_1),\n+\n+\t/* IPSR12 */\n+\tPINMUX_IPSR_GPSR(IP12_3_0,\tTX0),\n+\tPINMUX_IPSR_MSEL(IP12_3_0,\tHTX1_B,\t\t\tSEL_HSCIF1_1),\n+\tPINMUX_IPSR_MSEL(IP12_3_0,\tTS_SPSYNC0_C,\t\tSEL_TSIF0_2),\n+\tPINMUX_IPSR_MSEL(IP12_3_0,\tSTP_ISSYNC_0_C,\t\tSEL_SSP1_0_2),\n+\tPINMUX_IPSR_MSEL(IP12_3_0,\tRIF0_D1_B,\t\tSEL_DRIF0_1),\n+\n+\tPINMUX_IPSR_GPSR(IP12_7_4,\tCTS0_N),\n+\tPINMUX_IPSR_MSEL(IP12_7_4,\tHCTS1_N_B,\t\tSEL_HSCIF1_1),\n+\tPINMUX_IPSR_MSEL(IP12_7_4,\tMSIOF1_SYNC_B,\t\tSEL_MSIOF1_1),\n+\tPINMUX_IPSR_MSEL(IP12_7_4,\tTS_SPSYNC1_C,\t\tSEL_TSIF1_2),\n+\tPINMUX_IPSR_MSEL(IP12_7_4,\tSTP_ISSYNC_1_C,\t\tSEL_SSP1_1_2),\n+\tPINMUX_IPSR_MSEL(IP12_7_4,\tRIF1_SYNC_B,\t\tSEL_DRIF1_1),\n+\tPINMUX_IPSR_GPSR(IP12_7_4,\tAUDIO_CLKOUT_C),\n+\tPINMUX_IPSR_GPSR(IP12_7_4,\tADICS_SAMP),\n+\n+\tPINMUX_IPSR_GPSR(IP12_11_8,\tRTS0_N_TANS),\n+\tPINMUX_IPSR_MSEL(IP12_11_8,\tHRTS1_N_B,\t\tSEL_HSCIF1_1),\n+\tPINMUX_IPSR_MSEL(IP12_11_8,\tMSIOF1_SS1_B,\t\tSEL_MSIOF1_1),\n+\tPINMUX_IPSR_MSEL(IP12_11_8,\tAUDIO_CLKA_B,\t\tSEL_ADG_A_1),\n+\tPINMUX_IPSR_MSEL(IP12_11_8,\tSCL2_A,\t\t\tSEL_I2C2_0),\n+\tPINMUX_IPSR_MSEL(IP12_11_8,\tSTP_IVCXO27_1_C,\tSEL_SSP1_1_2),\n+\tPINMUX_IPSR_MSEL(IP12_11_8,\tRIF0_SYNC_B,\t\tSEL_DRIF0_1),\n+\tPINMUX_IPSR_GPSR(IP12_11_8,\tADICHS1),\n+\n+\tPINMUX_IPSR_MSEL(IP12_15_12,\tRX1_A,\t\t\tSEL_SCIF1_0),\n+\tPINMUX_IPSR_MSEL(IP12_15_12,\tHRX1_A,\t\t\tSEL_HSCIF1_0),\n+\tPINMUX_IPSR_MSEL(IP12_15_12,\tTS_SDAT0_C,\t\tSEL_TSIF0_2),\n+\tPINMUX_IPSR_MSEL(IP12_15_12,\tSTP_ISD_0_C,\t\tSEL_SSP1_0_2),\n+\tPINMUX_IPSR_MSEL(IP12_15_12,\tRIF1_CLK_C,\t\tSEL_DRIF1_2),\n+\n+\tPINMUX_IPSR_MSEL(IP12_19_16,\tTX1_A,\t\t\tSEL_SCIF1_0),\n+\tPINMUX_IPSR_MSEL(IP12_19_16,\tHTX1_A,\t\t\tSEL_HSCIF1_0),\n+\tPINMUX_IPSR_MSEL(IP12_19_16,\tTS_SDEN0_C,\t\tSEL_TSIF0_2),\n+\tPINMUX_IPSR_MSEL(IP12_19_16,\tSTP_ISEN_0_C,\t\tSEL_SSP1_0_2),\n+\tPINMUX_IPSR_MSEL(IP12_19_16,\tRIF1_D0_C,\t\tSEL_DRIF1_2),\n+\n+\tPINMUX_IPSR_GPSR(IP12_23_20,\tCTS1_N),\n+\tPINMUX_IPSR_MSEL(IP12_23_20,\tHCTS1_N_A,\t\tSEL_HSCIF1_0),\n+\tPINMUX_IPSR_MSEL(IP12_23_20,\tMSIOF1_RXD_B,\t\tSEL_MSIOF1_1),\n+\tPINMUX_IPSR_MSEL(IP12_23_20,\tTS_SDEN1_C,\t\tSEL_TSIF1_2),\n+\tPINMUX_IPSR_MSEL(IP12_23_20,\tSTP_ISEN_1_C,\t\tSEL_SSP1_1_2),\n+\tPINMUX_IPSR_MSEL(IP12_23_20,\tRIF1_D0_B,\t\tSEL_DRIF1_1),\n+\tPINMUX_IPSR_GPSR(IP12_23_20,\tADIDATA),\n+\n+\tPINMUX_IPSR_GPSR(IP12_27_24,\tRTS1_N_TANS),\n+\tPINMUX_IPSR_MSEL(IP12_27_24,\tHRTS1_N_A,\t\tSEL_HSCIF1_0),\n+\tPINMUX_IPSR_MSEL(IP12_27_24,\tMSIOF1_TXD_B,\t\tSEL_MSIOF1_1),\n+\tPINMUX_IPSR_MSEL(IP12_27_24,\tTS_SDAT1_C,\t\tSEL_TSIF1_2),\n+\tPINMUX_IPSR_MSEL(IP12_27_24,\tSTP_ISD_1_C,\t\tSEL_SSP1_1_2),\n+\tPINMUX_IPSR_MSEL(IP12_27_24,\tRIF1_D1_B,\t\tSEL_DRIF1_1),\n+\tPINMUX_IPSR_GPSR(IP12_27_24,\tADICHS0),\n+\n+\tPINMUX_IPSR_GPSR(IP12_31_28,\tSCK2),\n+\tPINMUX_IPSR_MSEL(IP12_31_28,\tSCIF_CLK_B,\t\tSEL_SCIF_1),\n+\tPINMUX_IPSR_MSEL(IP12_31_28,\tMSIOF1_SCK_B,\t\tSEL_MSIOF1_1),\n+\tPINMUX_IPSR_MSEL(IP12_31_28,\tTS_SCK1_C,\t\tSEL_TSIF1_2),\n+\tPINMUX_IPSR_MSEL(IP12_31_28,\tSTP_ISCLK_1_C,\t\tSEL_SSP1_1_2),\n+\tPINMUX_IPSR_MSEL(IP12_31_28,\tRIF1_CLK_B,\t\tSEL_DRIF1_1),\n+\tPINMUX_IPSR_GPSR(IP12_31_28,\tADICLK),\n+\n+\t/* IPSR13 */\n+\tPINMUX_IPSR_MSEL(IP13_3_0,\tTX2_A,\t\t\tSEL_SCIF2_0),\n+\tPINMUX_IPSR_MSEL(IP13_3_0,\tSD2_CD_B,\t\tSEL_SDHI2_1),\n+\tPINMUX_IPSR_MSEL(IP13_3_0,\tSCL1_A,\t\t\tSEL_I2C1_0),\n+\tPINMUX_IPSR_MSEL(IP13_3_0,\tFMCLK_A,\t\tSEL_FM_0),\n+\tPINMUX_IPSR_MSEL(IP13_3_0,\tRIF1_D1_C,\t\tSEL_DRIF1_2),\n+\tPINMUX_IPSR_GPSR(IP13_3_0,\tFSO_CFE_0_N),\n+\n+\tPINMUX_IPSR_MSEL(IP13_7_4,\tRX2_A,\t\t\tSEL_SCIF2_0),\n+\tPINMUX_IPSR_MSEL(IP13_7_4,\tSD2_WP_B,\t\tSEL_SDHI2_1),\n+\tPINMUX_IPSR_MSEL(IP13_7_4,\tSDA1_A,\t\t\tSEL_I2C1_0),\n+\tPINMUX_IPSR_MSEL(IP13_7_4,\tFMIN_A,\t\t\tSEL_FM_0),\n+\tPINMUX_IPSR_MSEL(IP13_7_4,\tRIF1_SYNC_C,\t\tSEL_DRIF1_2),\n+\tPINMUX_IPSR_GPSR(IP13_7_4,\tFSO_CFE_1_N),\n+\n+\tPINMUX_IPSR_GPSR(IP13_11_8,\tHSCK0),\n+\tPINMUX_IPSR_MSEL(IP13_11_8,\tMSIOF1_SCK_D,\t\tSEL_MSIOF1_3),\n+\tPINMUX_IPSR_MSEL(IP13_11_8,\tAUDIO_CLKB_A,\t\tSEL_ADG_B_0),\n+\tPINMUX_IPSR_MSEL(IP13_11_8,\tSSI_SDATA1_B,\t\tSEL_SSI_1),\n+\tPINMUX_IPSR_MSEL(IP13_11_8,\tTS_SCK0_D,\t\tSEL_TSIF0_3),\n+\tPINMUX_IPSR_MSEL(IP13_11_8,\tSTP_ISCLK_0_D,\t\tSEL_SSP1_0_3),\n+\tPINMUX_IPSR_MSEL(IP13_11_8,\tRIF0_CLK_C,\t\tSEL_DRIF0_2),\n+\tPINMUX_IPSR_MSEL(IP13_11_8,\tRX5_B,\t\t\tSEL_SCIF5_1),\n+\n+\tPINMUX_IPSR_GPSR(IP13_15_12,\tHRX0),\n+\tPINMUX_IPSR_MSEL(IP13_15_12,\tMSIOF1_RXD_D,\t\tSEL_MSIOF1_3),\n+\tPINMUX_IPSR_MSEL(IP13_15_12,\tSSI_SDATA2_B,\t\tSEL_SSI_1),\n+\tPINMUX_IPSR_MSEL(IP13_15_12,\tTS_SDEN0_D,\t\tSEL_TSIF0_3),\n+\tPINMUX_IPSR_MSEL(IP13_15_12,\tSTP_ISEN_0_D,\t\tSEL_SSP1_0_3),\n+\tPINMUX_IPSR_MSEL(IP13_15_12,\tRIF0_D0_C,\t\tSEL_DRIF0_2),\n+\n+\tPINMUX_IPSR_GPSR(IP13_19_16,\tHTX0),\n+\tPINMUX_IPSR_MSEL(IP13_19_16,\tMSIOF1_TXD_D,\t\tSEL_MSIOF1_3),\n+\tPINMUX_IPSR_MSEL(IP13_19_16,\tSSI_SDATA9_B,\t\tSEL_SSI_1),\n+\tPINMUX_IPSR_MSEL(IP13_19_16,\tTS_SDAT0_D,\t\tSEL_TSIF0_3),\n+\tPINMUX_IPSR_MSEL(IP13_19_16,\tSTP_ISD_0_D,\t\tSEL_SSP1_0_3),\n+\tPINMUX_IPSR_MSEL(IP13_19_16,\tRIF0_D1_C,\t\tSEL_DRIF0_2),\n+\n+\tPINMUX_IPSR_GPSR(IP13_23_20,\tHCTS0_N),\n+\tPINMUX_IPSR_MSEL(IP13_23_20,\tRX2_B,\t\t\tSEL_SCIF2_1),\n+\tPINMUX_IPSR_MSEL(IP13_23_20,\tMSIOF1_SYNC_D,\t\tSEL_MSIOF1_3),\n+\tPINMUX_IPSR_MSEL(IP13_23_20,\tSSI_SCK9_A,\t\tSEL_SSI_0),\n+\tPINMUX_IPSR_MSEL(IP13_23_20,\tTS_SPSYNC0_D,\t\tSEL_TSIF0_3),\n+\tPINMUX_IPSR_MSEL(IP13_23_20,\tSTP_ISSYNC_0_D,\t\tSEL_SSP1_0_3),\n+\tPINMUX_IPSR_MSEL(IP13_23_20,\tRIF0_SYNC_C,\t\tSEL_DRIF0_2),\n+\tPINMUX_IPSR_GPSR(IP13_23_20,\tAUDIO_CLKOUT1_A),\n+\n+\tPINMUX_IPSR_GPSR(IP13_27_24,\tHRTS0_N),\n+\tPINMUX_IPSR_MSEL(IP13_27_24,\tTX2_B,\t\t\tSEL_SCIF2_1),\n+\tPINMUX_IPSR_MSEL(IP13_27_24,\tMSIOF1_SS1_D,\t\tSEL_MSIOF1_3),\n+\tPINMUX_IPSR_MSEL(IP13_27_24,\tSSI_WS9_A,\t\tSEL_SSI_0),\n+\tPINMUX_IPSR_MSEL(IP13_27_24,\tSTP_IVCXO27_0_D,\tSEL_SSP1_0_3),\n+\tPINMUX_IPSR_MSEL(IP13_27_24,\tBPFCLK_A,\t\tSEL_FM_0),\n+\tPINMUX_IPSR_GPSR(IP13_27_24,\tAUDIO_CLKOUT2_A),\n+\n+\tPINMUX_IPSR_GPSR(IP13_31_28,\tMSIOF0_SYNC),\n+\tPINMUX_IPSR_GPSR(IP13_31_28,\tAUDIO_CLKOUT_A),\n+\tPINMUX_IPSR_MSEL(IP13_31_28,\tTX5_B,\t\t\tSEL_SCIF5_1),\n+\tPINMUX_IPSR_MSEL(IP13_31_28,\tBPFCLK_D,\t\tSEL_FM_3),\n+\n+\t/* IPSR14 */\n+\tPINMUX_IPSR_GPSR(IP14_3_0,\tMSIOF0_SS1),\n+\tPINMUX_IPSR_MSEL(IP14_3_0,\tRX5_A,\t\t\tSEL_SCIF5_0),\n+\tPINMUX_IPSR_GPSR(IP14_3_0,\tNFWP_N_A),\n+\tPINMUX_IPSR_MSEL(IP14_3_0,\tAUDIO_CLKA_C,\t\tSEL_ADG_A_2),\n+\tPINMUX_IPSR_MSEL(IP14_3_0,\tSSI_SCK2_A,\t\tSEL_SSI_0),\n+\tPINMUX_IPSR_MSEL(IP14_3_0,\tSTP_IVCXO27_0_C,\tSEL_SSP1_0_2),\n+\tPINMUX_IPSR_GPSR(IP14_3_0,\tAUDIO_CLKOUT3_A),\n+\tPINMUX_IPSR_MSEL(IP14_3_0,\tTCLK1_B,\t\tSEL_TIMER_TMU1_1),\n+\n+\tPINMUX_IPSR_GPSR(IP14_7_4,\tMSIOF0_SS2),\n+\tPINMUX_IPSR_MSEL(IP14_7_4,\tTX5_A,\t\t\tSEL_SCIF5_0),\n+\tPINMUX_IPSR_MSEL(IP14_7_4,\tMSIOF1_SS2_D,\t\tSEL_MSIOF1_3),\n+\tPINMUX_IPSR_MSEL(IP14_7_4,\tAUDIO_CLKC_A,\t\tSEL_ADG_C_0),\n+\tPINMUX_IPSR_MSEL(IP14_7_4,\tSSI_WS2_A,\t\tSEL_SSI_0),\n+\tPINMUX_IPSR_MSEL(IP14_7_4,\tSTP_OPWM_0_D,\t\tSEL_SSP1_0_3),\n+\tPINMUX_IPSR_GPSR(IP14_7_4,\tAUDIO_CLKOUT_D),\n+\tPINMUX_IPSR_MSEL(IP14_7_4,\tSPEEDIN_B,\t\tSEL_SPEED_PULSE_1),\n+\n+\tPINMUX_IPSR_GPSR(IP14_11_8,\tMLB_CLK),\n+\tPINMUX_IPSR_MSEL(IP14_11_8,\tMSIOF1_SCK_F,\t\tSEL_MSIOF1_5),\n+\tPINMUX_IPSR_MSEL(IP14_11_8,\tSCL1_B,\t\t\tSEL_I2C1_1),\n+\n+\tPINMUX_IPSR_GPSR(IP14_15_12,\tMLB_SIG),\n+\tPINMUX_IPSR_MSEL(IP14_15_12,\tRX1_B,\t\t\tSEL_SCIF1_1),\n+\tPINMUX_IPSR_MSEL(IP14_15_12,\tMSIOF1_SYNC_F,\t\tSEL_MSIOF1_5),\n+\tPINMUX_IPSR_MSEL(IP14_15_12,\tSDA1_B,\t\t\tSEL_I2C1_1),\n+\n+\tPINMUX_IPSR_GPSR(IP14_19_16,\tMLB_DAT),\n+\tPINMUX_IPSR_MSEL(IP14_19_16,\tTX1_B,\t\t\tSEL_SCIF1_1),\n+\tPINMUX_IPSR_MSEL(IP14_19_16,\tMSIOF1_RXD_F,\t\tSEL_MSIOF1_5),\n+\n+\tPINMUX_IPSR_GPSR(IP14_23_20,\tSSI_SCK01239),\n+\tPINMUX_IPSR_MSEL(IP14_23_20,\tMSIOF1_TXD_F,\t\tSEL_MSIOF1_5),\n+\n+\tPINMUX_IPSR_GPSR(IP14_27_24,\tSSI_WS01239),\n+\tPINMUX_IPSR_MSEL(IP14_27_24,\tMSIOF1_SS1_F,\t\tSEL_MSIOF1_5),\n+\n+\tPINMUX_IPSR_GPSR(IP14_31_28,\tSSI_SDATA0),\n+\tPINMUX_IPSR_MSEL(IP14_31_28,\tMSIOF1_SS2_F,\t\tSEL_MSIOF1_5),\n+\n+\t/* IPSR15 */\n+\tPINMUX_IPSR_MSEL(IP15_3_0,\tSSI_SDATA1_A,\t\tSEL_SSI_0),\n+\n+\tPINMUX_IPSR_MSEL(IP15_7_4,\tSSI_SDATA2_A,\t\tSEL_SSI_0),\n+\tPINMUX_IPSR_MSEL(IP15_7_4,\tSSI_SCK1_B,\t\tSEL_SSI_1),\n+\n+\tPINMUX_IPSR_GPSR(IP15_11_8,\tSSI_SCK349),\n+\tPINMUX_IPSR_MSEL(IP15_11_8,\tMSIOF1_SS1_A,\t\tSEL_MSIOF1_0),\n+\tPINMUX_IPSR_MSEL(IP15_11_8,\tSTP_OPWM_0_A,\t\tSEL_SSP1_0_0),\n+\n+\tPINMUX_IPSR_GPSR(IP15_15_12,\tSSI_WS349),\n+\tPINMUX_IPSR_MSEL(IP15_15_12,\tHCTS2_N_A,\t\tSEL_HSCIF2_0),\n+\tPINMUX_IPSR_MSEL(IP15_15_12,\tMSIOF1_SS2_A,\t\tSEL_MSIOF1_0),\n+\tPINMUX_IPSR_MSEL(IP15_15_12,\tSTP_IVCXO27_0_A,\tSEL_SSP1_0_0),\n+\n+\tPINMUX_IPSR_GPSR(IP15_19_16,\tSSI_SDATA3),\n+\tPINMUX_IPSR_MSEL(IP15_19_16,\tHRTS2_N_A,\t\tSEL_HSCIF2_0),\n+\tPINMUX_IPSR_MSEL(IP15_19_16,\tMSIOF1_TXD_A,\t\tSEL_MSIOF1_0),\n+\tPINMUX_IPSR_MSEL(IP15_19_16,\tTS_SCK0_A,\t\tSEL_TSIF0_0),\n+\tPINMUX_IPSR_MSEL(IP15_19_16,\tSTP_ISCLK_0_A,\t\tSEL_SSP1_0_0),\n+\tPINMUX_IPSR_MSEL(IP15_19_16,\tRIF0_D1_A,\t\tSEL_DRIF0_0),\n+\tPINMUX_IPSR_MSEL(IP15_19_16,\tRIF2_D0_A,\t\tSEL_DRIF2_0),\n+\n+\tPINMUX_IPSR_GPSR(IP15_23_20,\tSSI_SCK4),\n+\tPINMUX_IPSR_MSEL(IP15_23_20,\tHRX2_A,\t\t\tSEL_HSCIF2_0),\n+\tPINMUX_IPSR_MSEL(IP15_23_20,\tMSIOF1_SCK_A,\t\tSEL_MSIOF1_0),\n+\tPINMUX_IPSR_MSEL(IP15_23_20,\tTS_SDAT0_A,\t\tSEL_TSIF0_0),\n+\tPINMUX_IPSR_MSEL(IP15_23_20,\tSTP_ISD_0_A,\t\tSEL_SSP1_0_0),\n+\tPINMUX_IPSR_MSEL(IP15_23_20,\tRIF0_CLK_A,\t\tSEL_DRIF0_0),\n+\tPINMUX_IPSR_MSEL(IP15_23_20,\tRIF2_CLK_A,\t\tSEL_DRIF2_0),\n+\n+\tPINMUX_IPSR_GPSR(IP15_27_24,\tSSI_WS4),\n+\tPINMUX_IPSR_MSEL(IP15_27_24,\tHTX2_A,\t\t\tSEL_HSCIF2_0),\n+\tPINMUX_IPSR_MSEL(IP15_27_24,\tMSIOF1_SYNC_A,\t\tSEL_MSIOF1_0),\n+\tPINMUX_IPSR_MSEL(IP15_27_24,\tTS_SDEN0_A,\t\tSEL_TSIF0_0),\n+\tPINMUX_IPSR_MSEL(IP15_27_24,\tSTP_ISEN_0_A,\t\tSEL_SSP1_0_0),\n+\tPINMUX_IPSR_MSEL(IP15_27_24,\tRIF0_SYNC_A,\t\tSEL_DRIF0_0),\n+\tPINMUX_IPSR_MSEL(IP15_27_24,\tRIF2_SYNC_A,\t\tSEL_DRIF2_0),\n+\n+\tPINMUX_IPSR_GPSR(IP15_31_28,\tSSI_SDATA4),\n+\tPINMUX_IPSR_MSEL(IP15_31_28,\tHSCK2_A,\t\tSEL_HSCIF2_0),\n+\tPINMUX_IPSR_MSEL(IP15_31_28,\tMSIOF1_RXD_A,\t\tSEL_MSIOF1_0),\n+\tPINMUX_IPSR_MSEL(IP15_31_28,\tTS_SPSYNC0_A,\t\tSEL_TSIF0_0),\n+\tPINMUX_IPSR_MSEL(IP15_31_28,\tSTP_ISSYNC_0_A,\t\tSEL_SSP1_0_0),\n+\tPINMUX_IPSR_MSEL(IP15_31_28,\tRIF0_D0_A,\t\tSEL_DRIF0_0),\n+\tPINMUX_IPSR_MSEL(IP15_31_28,\tRIF2_D1_A,\t\tSEL_DRIF2_0),\n+\n+\t/* IPSR16 */\n+\tPINMUX_IPSR_GPSR(IP16_3_0,\tSSI_SCK6),\n+\tPINMUX_IPSR_GPSR(IP16_3_0,\tUSB2_PWEN),\n+\tPINMUX_IPSR_MSEL(IP16_3_0,\tSIM0_RST_D,\t\tSEL_SIMCARD_3),\n+\n+\tPINMUX_IPSR_GPSR(IP16_7_4,\tSSI_WS6),\n+\tPINMUX_IPSR_GPSR(IP16_7_4,\tUSB2_OVC),\n+\tPINMUX_IPSR_MSEL(IP16_7_4,\tSIM0_D_D,\t\tSEL_SIMCARD_3),\n+\n+\tPINMUX_IPSR_GPSR(IP16_11_8,\tSSI_SDATA6),\n+\tPINMUX_IPSR_MSEL(IP16_11_8,\tSIM0_CLK_D,\t\tSEL_SIMCARD_3),\n+\tPINMUX_IPSR_GPSR(IP16_11_8,\tSATA_DEVSLP_A),\n+\n+\tPINMUX_IPSR_GPSR(IP16_15_12,\tSSI_SCK78),\n+\tPINMUX_IPSR_MSEL(IP16_15_12,\tHRX2_B,\t\t\tSEL_HSCIF2_1),\n+\tPINMUX_IPSR_MSEL(IP16_15_12,\tMSIOF1_SCK_C,\t\tSEL_MSIOF1_2),\n+\tPINMUX_IPSR_MSEL(IP16_15_12,\tTS_SCK1_A,\t\tSEL_TSIF1_0),\n+\tPINMUX_IPSR_MSEL(IP16_15_12,\tSTP_ISCLK_1_A,\t\tSEL_SSP1_1_0),\n+\tPINMUX_IPSR_MSEL(IP16_15_12,\tRIF1_CLK_A,\t\tSEL_DRIF1_0),\n+\tPINMUX_IPSR_MSEL(IP16_15_12,\tRIF3_CLK_A,\t\tSEL_DRIF3_0),\n+\n+\tPINMUX_IPSR_GPSR(IP16_19_16,\tSSI_WS78),\n+\tPINMUX_IPSR_MSEL(IP16_19_16,\tHTX2_B,\t\t\tSEL_HSCIF2_1),\n+\tPINMUX_IPSR_MSEL(IP16_19_16,\tMSIOF1_SYNC_C,\t\tSEL_MSIOF1_2),\n+\tPINMUX_IPSR_MSEL(IP16_19_16,\tTS_SDAT1_A,\t\tSEL_TSIF1_0),\n+\tPINMUX_IPSR_MSEL(IP16_19_16,\tSTP_ISD_1_A,\t\tSEL_SSP1_1_0),\n+\tPINMUX_IPSR_MSEL(IP16_19_16,\tRIF1_SYNC_A,\t\tSEL_DRIF1_0),\n+\tPINMUX_IPSR_MSEL(IP16_19_16,\tRIF3_SYNC_A,\t\tSEL_DRIF3_0),\n+\n+\tPINMUX_IPSR_GPSR(IP16_23_20,\tSSI_SDATA7),\n+\tPINMUX_IPSR_MSEL(IP16_23_20,\tHCTS2_N_B,\t\tSEL_HSCIF2_1),\n+\tPINMUX_IPSR_MSEL(IP16_23_20,\tMSIOF1_RXD_C,\t\tSEL_MSIOF1_2),\n+\tPINMUX_IPSR_MSEL(IP16_23_20,\tTS_SDEN1_A,\t\tSEL_TSIF1_0),\n+\tPINMUX_IPSR_MSEL(IP16_23_20,\tSTP_ISEN_1_A,\t\tSEL_SSP1_1_0),\n+\tPINMUX_IPSR_MSEL(IP16_23_20,\tRIF1_D0_A,\t\tSEL_DRIF1_0),\n+\tPINMUX_IPSR_MSEL(IP16_23_20,\tRIF3_D0_A,\t\tSEL_DRIF3_0),\n+\tPINMUX_IPSR_MSEL(IP16_23_20,\tTCLK2_A,\t\tSEL_TIMER_TMU2_0),\n+\n+\tPINMUX_IPSR_GPSR(IP16_27_24,\tSSI_SDATA8),\n+\tPINMUX_IPSR_MSEL(IP16_27_24,\tHRTS2_N_B,\t\tSEL_HSCIF2_1),\n+\tPINMUX_IPSR_MSEL(IP16_27_24,\tMSIOF1_TXD_C,\t\tSEL_MSIOF1_2),\n+\tPINMUX_IPSR_MSEL(IP16_27_24,\tTS_SPSYNC1_A,\t\tSEL_TSIF1_0),\n+\tPINMUX_IPSR_MSEL(IP16_27_24,\tSTP_ISSYNC_1_A,\t\tSEL_SSP1_1_0),\n+\tPINMUX_IPSR_MSEL(IP16_27_24,\tRIF1_D1_A,\t\tSEL_DRIF1_0),\n+\tPINMUX_IPSR_MSEL(IP16_27_24,\tRIF3_D1_A,\t\tSEL_DRIF3_0),\n+\n+\tPINMUX_IPSR_MSEL(IP16_31_28,\tSSI_SDATA9_A,\t\tSEL_SSI_0),\n+\tPINMUX_IPSR_MSEL(IP16_31_28,\tHSCK2_B,\t\tSEL_HSCIF2_1),\n+\tPINMUX_IPSR_MSEL(IP16_31_28,\tMSIOF1_SS1_C,\t\tSEL_MSIOF1_2),\n+\tPINMUX_IPSR_MSEL(IP16_31_28,\tHSCK1_A,\t\tSEL_HSCIF1_0),\n+\tPINMUX_IPSR_MSEL(IP16_31_28,\tSSI_WS1_B,\t\tSEL_SSI_1),\n+\tPINMUX_IPSR_GPSR(IP16_31_28,\tSCK1),\n+\tPINMUX_IPSR_MSEL(IP16_31_28,\tSTP_IVCXO27_1_A,\tSEL_SSP1_1_0),\n+\tPINMUX_IPSR_MSEL(IP16_31_28,\tSCK5_A,\t\t\tSEL_SCIF5_0),\n+\n+\t/* IPSR17 */\n+\tPINMUX_IPSR_MSEL(IP17_3_0,\tAUDIO_CLKA_A,\t\tSEL_ADG_A_0),\n+\tPINMUX_IPSR_GPSR(IP17_3_0,\tCC5_OSCOUT),\n+\n+\tPINMUX_IPSR_MSEL(IP17_7_4,\tAUDIO_CLKB_B,\t\tSEL_ADG_B_1),\n+\tPINMUX_IPSR_MSEL(IP17_7_4,\tSCIF_CLK_A,\t\tSEL_SCIF_0),\n+\tPINMUX_IPSR_MSEL(IP17_7_4,\tSTP_IVCXO27_1_D,\tSEL_SSP1_1_3),\n+\tPINMUX_IPSR_MSEL(IP17_7_4,\tREMOCON_A,\t\tSEL_REMOCON_0),\n+\tPINMUX_IPSR_MSEL(IP17_7_4,\tTCLK1_A,\t\tSEL_TIMER_TMU1_0),\n+\n+\tPINMUX_IPSR_GPSR(IP17_11_8,\tUSB0_PWEN),\n+\tPINMUX_IPSR_MSEL(IP17_11_8,\tSIM0_RST_C,\t\tSEL_SIMCARD_2),\n+\tPINMUX_IPSR_MSEL(IP17_11_8,\tTS_SCK1_D,\t\tSEL_TSIF1_3),\n+\tPINMUX_IPSR_MSEL(IP17_11_8,\tSTP_ISCLK_1_D,\t\tSEL_SSP1_1_3),\n+\tPINMUX_IPSR_MSEL(IP17_11_8,\tBPFCLK_B,\t\tSEL_FM_1),\n+\tPINMUX_IPSR_MSEL(IP17_11_8,\tRIF3_CLK_B,\t\tSEL_DRIF3_1),\n+\tPINMUX_IPSR_MSEL(IP17_11_8,\tHSCK2_C,\t\tSEL_HSCIF2_2),\n+\n+\tPINMUX_IPSR_GPSR(IP17_15_12,\tUSB0_OVC),\n+\tPINMUX_IPSR_MSEL(IP17_15_12,\tSIM0_D_C,\t\tSEL_SIMCARD_2),\n+\tPINMUX_IPSR_MSEL(IP17_15_12,\tTS_SDAT1_D,\t\tSEL_TSIF1_3),\n+\tPINMUX_IPSR_MSEL(IP17_15_12,\tSTP_ISD_1_D,\t\tSEL_SSP1_1_3),\n+\tPINMUX_IPSR_MSEL(IP17_15_12,\tRIF3_SYNC_B,\t\tSEL_DRIF3_1),\n+\tPINMUX_IPSR_MSEL(IP17_15_12,\tHRX2_C,\t\t\tSEL_HSCIF2_2),\n+\n+\tPINMUX_IPSR_GPSR(IP17_19_16,\tUSB1_PWEN),\n+\tPINMUX_IPSR_MSEL(IP17_19_16,\tSIM0_CLK_C,\t\tSEL_SIMCARD_2),\n+\tPINMUX_IPSR_MSEL(IP17_19_16,\tSSI_SCK1_A,\t\tSEL_SSI_0),\n+\tPINMUX_IPSR_MSEL(IP17_19_16,\tTS_SCK0_E,\t\tSEL_TSIF0_4),\n+\tPINMUX_IPSR_MSEL(IP17_19_16,\tSTP_ISCLK_0_E,\t\tSEL_SSP1_0_4),\n+\tPINMUX_IPSR_MSEL(IP17_19_16,\tFMCLK_B,\t\tSEL_FM_1),\n+\tPINMUX_IPSR_MSEL(IP17_19_16,\tRIF2_CLK_B,\t\tSEL_DRIF2_1),\n+\tPINMUX_IPSR_MSEL(IP17_19_16,\tSPEEDIN_A,\t\tSEL_SPEED_PULSE_0),\n+\tPINMUX_IPSR_MSEL(IP17_19_16,\tHTX2_C,\t\t\tSEL_HSCIF2_2),\n+\n+\tPINMUX_IPSR_GPSR(IP17_23_20,\tUSB1_OVC),\n+\tPINMUX_IPSR_MSEL(IP17_23_20,\tMSIOF1_SS2_C,\t\tSEL_MSIOF1_2),\n+\tPINMUX_IPSR_MSEL(IP17_23_20,\tSSI_WS1_A,\t\tSEL_SSI_0),\n+\tPINMUX_IPSR_MSEL(IP17_23_20,\tTS_SDAT0_E,\t\tSEL_TSIF0_4),\n+\tPINMUX_IPSR_MSEL(IP17_23_20,\tSTP_ISD_0_E,\t\tSEL_SSP1_0_4),\n+\tPINMUX_IPSR_MSEL(IP17_23_20,\tFMIN_B,\t\t\tSEL_FM_1),\n+\tPINMUX_IPSR_MSEL(IP17_23_20,\tRIF2_SYNC_B,\t\tSEL_DRIF2_1),\n+\tPINMUX_IPSR_MSEL(IP17_23_20,\tREMOCON_B,\t\tSEL_REMOCON_1),\n+\tPINMUX_IPSR_MSEL(IP17_23_20,\tHCTS2_N_C,\t\tSEL_HSCIF2_2),\n+\n+\tPINMUX_IPSR_GPSR(IP17_27_24,\tUSB30_PWEN),\n+\tPINMUX_IPSR_GPSR(IP17_27_24,\tAUDIO_CLKOUT_B),\n+\tPINMUX_IPSR_MSEL(IP17_27_24,\tSSI_SCK2_B,\t\tSEL_SSI_1),\n+\tPINMUX_IPSR_MSEL(IP17_27_24,\tTS_SDEN1_D,\t\tSEL_TSIF1_3),\n+\tPINMUX_IPSR_MSEL(IP17_27_24,\tSTP_ISEN_1_D,\t\tSEL_SSP1_1_3),\n+\tPINMUX_IPSR_MSEL(IP17_27_24,\tSTP_OPWM_0_E,\t\tSEL_SSP1_0_4),\n+\tPINMUX_IPSR_MSEL(IP17_27_24,\tRIF3_D0_B,\t\tSEL_DRIF3_1),\n+\tPINMUX_IPSR_MSEL(IP17_27_24,\tTCLK2_B,\t\tSEL_TIMER_TMU2_1),\n+\tPINMUX_IPSR_GPSR(IP17_27_24,\tTPU0TO0),\n+\tPINMUX_IPSR_MSEL(IP17_27_24,\tBPFCLK_C,\t\tSEL_FM_2),\n+\tPINMUX_IPSR_MSEL(IP17_27_24,\tHRTS2_N_C,\t\tSEL_HSCIF2_2),\n+\n+\tPINMUX_IPSR_GPSR(IP17_31_28,\tUSB30_OVC),\n+\tPINMUX_IPSR_GPSR(IP17_31_28,\tAUDIO_CLKOUT1_B),\n+\tPINMUX_IPSR_MSEL(IP17_31_28,\tSSI_WS2_B,\t\tSEL_SSI_1),\n+\tPINMUX_IPSR_MSEL(IP17_31_28,\tTS_SPSYNC1_D,\t\tSEL_TSIF1_3),\n+\tPINMUX_IPSR_MSEL(IP17_31_28,\tSTP_ISSYNC_1_D,\t\tSEL_SSP1_1_3),\n+\tPINMUX_IPSR_MSEL(IP17_31_28,\tSTP_IVCXO27_0_E,\tSEL_SSP1_0_4),\n+\tPINMUX_IPSR_MSEL(IP17_31_28,\tRIF3_D1_B,\t\tSEL_DRIF3_1),\n+\tPINMUX_IPSR_GPSR(IP17_31_28,\tFSO_TOE_N),\n+\tPINMUX_IPSR_GPSR(IP17_31_28,\tTPU0TO1),\n+\n+\t/* IPSR18 */\n+\tPINMUX_IPSR_GPSR(IP18_3_0,\tUSB2_CH3_PWEN),\n+\tPINMUX_IPSR_GPSR(IP18_3_0,\tAUDIO_CLKOUT2_B),\n+\tPINMUX_IPSR_MSEL(IP18_3_0,\tSSI_SCK9_B,\t\tSEL_SSI_1),\n+\tPINMUX_IPSR_MSEL(IP18_3_0,\tTS_SDEN0_E,\t\tSEL_TSIF0_4),\n+\tPINMUX_IPSR_MSEL(IP18_3_0,\tSTP_ISEN_0_E,\t\tSEL_SSP1_0_4),\n+\tPINMUX_IPSR_MSEL(IP18_3_0,\tRIF2_D0_B,\t\tSEL_DRIF2_1),\n+\tPINMUX_IPSR_GPSR(IP18_3_0,\tTPU0TO2),\n+\tPINMUX_IPSR_MSEL(IP18_3_0,\tFMCLK_C,\t\tSEL_FM_2),\n+\tPINMUX_IPSR_MSEL(IP18_3_0,\tFMCLK_D,\t\tSEL_FM_3),\n+\n+\tPINMUX_IPSR_GPSR(IP18_7_4,\tUSB2_CH3_OVC),\n+\tPINMUX_IPSR_GPSR(IP18_7_4,\tAUDIO_CLKOUT3_B),\n+\tPINMUX_IPSR_MSEL(IP18_7_4,\tSSI_WS9_B,\t\tSEL_SSI_1),\n+\tPINMUX_IPSR_MSEL(IP18_7_4,\tTS_SPSYNC0_E,\t\tSEL_TSIF0_4),\n+\tPINMUX_IPSR_MSEL(IP18_7_4,\tSTP_ISSYNC_0_E,\t\tSEL_SSP1_0_4),\n+\tPINMUX_IPSR_MSEL(IP18_7_4,\tRIF2_D1_B,\t\tSEL_DRIF2_1),\n+\tPINMUX_IPSR_GPSR(IP18_7_4,\tTPU0TO3),\n+\tPINMUX_IPSR_MSEL(IP18_7_4,\tFMIN_C,\t\t\tSEL_FM_2),\n+\tPINMUX_IPSR_MSEL(IP18_7_4,\tFMIN_D,\t\t\tSEL_FM_3),\n+\n+/*\n+ * Static pins can not be muxed between different functions but\n+ * still needs a mark entry in the pinmux list. Add each static\n+ * pin to the list without an associated function. The sh-pfc\n+ * core will do the right thing and skip trying to mux then pin\n+ * while still applying configuration to it\n+ */\n+#define FM(x)\tPINMUX_DATA(x##_MARK, 0),\n+\tPINMUX_STATIC\n+#undef FM\n+};\n+\n+/*\n+ * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs.\n+ * Physical layout rows: A - AW, cols: 1 - 39.\n+ */\n+#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))\n+#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)\n+#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)\n+\n+static const struct sh_pfc_pin pinmux_pins[] = {\n+\tPINMUX_GPIO_GP_ALL(),\n+\n+\t/*\n+\t * Pins not associated with a GPIO port.\n+\t *\n+\t * The pin positions are different between different r8a7795\n+\t * packages, all that is needed for the pfc driver is a unique\n+\t * number for each pin. To this end use the pin layout from\n+\t * R-Car H3SiP to calculate a unique number for each pin.\n+\t */\n+\tSH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('F',  1, CLKOUT, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  7, DU_DOTCLKIN2, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN3, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),\n+};\n+\n+/* - EtherAVB --------------------------------------------------------------- */\n+static const unsigned int avb_link_pins[] = {\n+\t/* AVB_LINK */\n+\tRCAR_GP_PIN(2, 12),\n+};\n+static const unsigned int avb_link_mux[] = {\n+\tAVB_LINK_MARK,\n+};\n+static const unsigned int avb_magic_pins[] = {\n+\t/* AVB_MAGIC_ */\n+\tRCAR_GP_PIN(2, 10),\n+};\n+static const unsigned int avb_magic_mux[] = {\n+\tAVB_MAGIC_MARK,\n+};\n+static const unsigned int avb_phy_int_pins[] = {\n+\t/* AVB_PHY_INT */\n+\tRCAR_GP_PIN(2, 11),\n+};\n+static const unsigned int avb_phy_int_mux[] = {\n+\tAVB_PHY_INT_MARK,\n+};\n+static const unsigned int avb_mdc_pins[] = {\n+\t/* AVB_MDC, AVB_MDIO */\n+\tRCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),\n+};\n+static const unsigned int avb_mdc_mux[] = {\n+\tAVB_MDC_MARK, AVB_MDIO_MARK,\n+};\n+static const unsigned int avb_mii_pins[] = {\n+\t/*\n+\t * AVB_TX_CTL, AVB_TXC, AVB_TD0,\n+\t * AVB_TD1, AVB_TD2, AVB_TD3,\n+\t * AVB_RX_CTL, AVB_RXC, AVB_RD0,\n+\t * AVB_RD1, AVB_RD2, AVB_RD3,\n+\t * AVB_TXCREFCLK\n+\t */\n+\tPIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),\n+\tPIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),\n+\tPIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),\n+\tPIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),\n+\tPIN_NUMBER('A', 12),\n+\n+};\n+static const unsigned int avb_mii_mux[] = {\n+\tAVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,\n+\tAVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,\n+\tAVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,\n+\tAVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,\n+\tAVB_TXCREFCLK_MARK,\n+};\n+static const unsigned int avb_avtp_pps_pins[] = {\n+\t/* AVB_AVTP_PPS */\n+\tRCAR_GP_PIN(2, 6),\n+};\n+static const unsigned int avb_avtp_pps_mux[] = {\n+\tAVB_AVTP_PPS_MARK,\n+};\n+static const unsigned int avb_avtp_match_a_pins[] = {\n+\t/* AVB_AVTP_MATCH_A */\n+\tRCAR_GP_PIN(2, 13),\n+};\n+static const unsigned int avb_avtp_match_a_mux[] = {\n+\tAVB_AVTP_MATCH_A_MARK,\n+};\n+static const unsigned int avb_avtp_capture_a_pins[] = {\n+\t/* AVB_AVTP_CAPTURE_A */\n+\tRCAR_GP_PIN(2, 14),\n+};\n+static const unsigned int avb_avtp_capture_a_mux[] = {\n+\tAVB_AVTP_CAPTURE_A_MARK,\n+};\n+static const unsigned int avb_avtp_match_b_pins[] = {\n+\t/*  AVB_AVTP_MATCH_B */\n+\tRCAR_GP_PIN(1, 8),\n+};\n+static const unsigned int avb_avtp_match_b_mux[] = {\n+\tAVB_AVTP_MATCH_B_MARK,\n+};\n+static const unsigned int avb_avtp_capture_b_pins[] = {\n+\t/* AVB_AVTP_CAPTURE_B */\n+\tRCAR_GP_PIN(1, 11),\n+};\n+static const unsigned int avb_avtp_capture_b_mux[] = {\n+\tAVB_AVTP_CAPTURE_B_MARK,\n+};\n+\n+/* - DRIF0 --------------------------------------------------------------- */\n+static const unsigned int drif0_ctrl_a_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),\n+};\n+static const unsigned int drif0_ctrl_a_mux[] = {\n+\tRIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,\n+};\n+static const unsigned int drif0_data0_a_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(6, 10),\n+};\n+static const unsigned int drif0_data0_a_mux[] = {\n+\tRIF0_D0_A_MARK,\n+};\n+static const unsigned int drif0_data1_a_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(6, 7),\n+};\n+static const unsigned int drif0_data1_a_mux[] = {\n+\tRIF0_D1_A_MARK,\n+};\n+static const unsigned int drif0_ctrl_b_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),\n+};\n+static const unsigned int drif0_ctrl_b_mux[] = {\n+\tRIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,\n+};\n+static const unsigned int drif0_data0_b_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(5, 1),\n+};\n+static const unsigned int drif0_data0_b_mux[] = {\n+\tRIF0_D0_B_MARK,\n+};\n+static const unsigned int drif0_data1_b_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(5, 2),\n+};\n+static const unsigned int drif0_data1_b_mux[] = {\n+\tRIF0_D1_B_MARK,\n+};\n+static const unsigned int drif0_ctrl_c_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),\n+};\n+static const unsigned int drif0_ctrl_c_mux[] = {\n+\tRIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,\n+};\n+static const unsigned int drif0_data0_c_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(5, 13),\n+};\n+static const unsigned int drif0_data0_c_mux[] = {\n+\tRIF0_D0_C_MARK,\n+};\n+static const unsigned int drif0_data1_c_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(5, 14),\n+};\n+static const unsigned int drif0_data1_c_mux[] = {\n+\tRIF0_D1_C_MARK,\n+};\n+/* - DRIF1 --------------------------------------------------------------- */\n+static const unsigned int drif1_ctrl_a_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),\n+};\n+static const unsigned int drif1_ctrl_a_mux[] = {\n+\tRIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,\n+};\n+static const unsigned int drif1_data0_a_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(6, 19),\n+};\n+static const unsigned int drif1_data0_a_mux[] = {\n+\tRIF1_D0_A_MARK,\n+};\n+static const unsigned int drif1_data1_a_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(6, 20),\n+};\n+static const unsigned int drif1_data1_a_mux[] = {\n+\tRIF1_D1_A_MARK,\n+};\n+static const unsigned int drif1_ctrl_b_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),\n+};\n+static const unsigned int drif1_ctrl_b_mux[] = {\n+\tRIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,\n+};\n+static const unsigned int drif1_data0_b_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(5, 7),\n+};\n+static const unsigned int drif1_data0_b_mux[] = {\n+\tRIF1_D0_B_MARK,\n+};\n+static const unsigned int drif1_data1_b_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(5, 8),\n+};\n+static const unsigned int drif1_data1_b_mux[] = {\n+\tRIF1_D1_B_MARK,\n+};\n+static const unsigned int drif1_ctrl_c_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),\n+};\n+static const unsigned int drif1_ctrl_c_mux[] = {\n+\tRIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,\n+};\n+static const unsigned int drif1_data0_c_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(5, 6),\n+};\n+static const unsigned int drif1_data0_c_mux[] = {\n+\tRIF1_D0_C_MARK,\n+};\n+static const unsigned int drif1_data1_c_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(5, 10),\n+};\n+static const unsigned int drif1_data1_c_mux[] = {\n+\tRIF1_D1_C_MARK,\n+};\n+/* - DRIF2 --------------------------------------------------------------- */\n+static const unsigned int drif2_ctrl_a_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),\n+};\n+static const unsigned int drif2_ctrl_a_mux[] = {\n+\tRIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,\n+};\n+static const unsigned int drif2_data0_a_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(6, 7),\n+};\n+static const unsigned int drif2_data0_a_mux[] = {\n+\tRIF2_D0_A_MARK,\n+};\n+static const unsigned int drif2_data1_a_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(6, 10),\n+};\n+static const unsigned int drif2_data1_a_mux[] = {\n+\tRIF2_D1_A_MARK,\n+};\n+static const unsigned int drif2_ctrl_b_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),\n+};\n+static const unsigned int drif2_ctrl_b_mux[] = {\n+\tRIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,\n+};\n+static const unsigned int drif2_data0_b_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(6, 30),\n+};\n+static const unsigned int drif2_data0_b_mux[] = {\n+\tRIF2_D0_B_MARK,\n+};\n+static const unsigned int drif2_data1_b_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(6, 31),\n+};\n+static const unsigned int drif2_data1_b_mux[] = {\n+\tRIF2_D1_B_MARK,\n+};\n+/* - DRIF3 --------------------------------------------------------------- */\n+static const unsigned int drif3_ctrl_a_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),\n+};\n+static const unsigned int drif3_ctrl_a_mux[] = {\n+\tRIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,\n+};\n+static const unsigned int drif3_data0_a_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(6, 19),\n+};\n+static const unsigned int drif3_data0_a_mux[] = {\n+\tRIF3_D0_A_MARK,\n+};\n+static const unsigned int drif3_data1_a_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(6, 20),\n+};\n+static const unsigned int drif3_data1_a_mux[] = {\n+\tRIF3_D1_A_MARK,\n+};\n+static const unsigned int drif3_ctrl_b_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),\n+};\n+static const unsigned int drif3_ctrl_b_mux[] = {\n+\tRIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,\n+};\n+static const unsigned int drif3_data0_b_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(6, 28),\n+};\n+static const unsigned int drif3_data0_b_mux[] = {\n+\tRIF3_D0_B_MARK,\n+};\n+static const unsigned int drif3_data1_b_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(6, 29),\n+};\n+static const unsigned int drif3_data1_b_mux[] = {\n+\tRIF3_D1_B_MARK,\n+};\n+\n+/* - DU --------------------------------------------------------------------- */\n+static const unsigned int du_rgb666_pins[] = {\n+\t/* R[7:2], G[7:2], B[7:2] */\n+\tRCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),\n+\tRCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),\n+\tRCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),\n+\tRCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),\n+\tRCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),\n+\tRCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),\n+};\n+static const unsigned int du_rgb666_mux[] = {\n+\tDU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,\n+\tDU_DR3_MARK, DU_DR2_MARK,\n+\tDU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,\n+\tDU_DG3_MARK, DU_DG2_MARK,\n+\tDU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,\n+\tDU_DB3_MARK, DU_DB2_MARK,\n+};\n+static const unsigned int du_rgb888_pins[] = {\n+\t/* R[7:0], G[7:0], B[7:0] */\n+\tRCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),\n+\tRCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),\n+\tRCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),\n+\tRCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),\n+\tRCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),\n+\tRCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),\n+\tRCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),\n+\tRCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),\n+\tRCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),\n+};\n+static const unsigned int du_rgb888_mux[] = {\n+\tDU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,\n+\tDU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,\n+\tDU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,\n+\tDU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,\n+\tDU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,\n+\tDU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,\n+};\n+static const unsigned int du_clk_out_0_pins[] = {\n+\t/* CLKOUT */\n+\tRCAR_GP_PIN(1, 27),\n+};\n+static const unsigned int du_clk_out_0_mux[] = {\n+\tDU_DOTCLKOUT0_MARK\n+};\n+static const unsigned int du_clk_out_1_pins[] = {\n+\t/* CLKOUT */\n+\tRCAR_GP_PIN(2, 3),\n+};\n+static const unsigned int du_clk_out_1_mux[] = {\n+\tDU_DOTCLKOUT1_MARK\n+};\n+static const unsigned int du_sync_pins[] = {\n+\t/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */\n+\tRCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),\n+};\n+static const unsigned int du_sync_mux[] = {\n+\tDU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK\n+};\n+static const unsigned int du_oddf_pins[] = {\n+\t/* EXDISP/EXODDF/EXCDE */\n+\tRCAR_GP_PIN(2, 2),\n+};\n+static const unsigned int du_oddf_mux[] = {\n+\tDU_EXODDF_DU_ODDF_DISP_CDE_MARK,\n+};\n+static const unsigned int du_cde_pins[] = {\n+\t/* CDE */\n+\tRCAR_GP_PIN(2, 0),\n+};\n+static const unsigned int du_cde_mux[] = {\n+\tDU_CDE_MARK,\n+};\n+static const unsigned int du_disp_pins[] = {\n+\t/* DISP */\n+\tRCAR_GP_PIN(2, 1),\n+};\n+static const unsigned int du_disp_mux[] = {\n+\tDU_DISP_MARK,\n+};\n+\n+/* - MSIOF0 ----------------------------------------------------------------- */\n+static const unsigned int msiof0_clk_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(5, 17),\n+};\n+static const unsigned int msiof0_clk_mux[] = {\n+\tMSIOF0_SCK_MARK,\n+};\n+static const unsigned int msiof0_sync_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(5, 18),\n+};\n+static const unsigned int msiof0_sync_mux[] = {\n+\tMSIOF0_SYNC_MARK,\n+};\n+static const unsigned int msiof0_ss1_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(5, 19),\n+};\n+static const unsigned int msiof0_ss1_mux[] = {\n+\tMSIOF0_SS1_MARK,\n+};\n+static const unsigned int msiof0_ss2_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(5, 21),\n+};\n+static const unsigned int msiof0_ss2_mux[] = {\n+\tMSIOF0_SS2_MARK,\n+};\n+static const unsigned int msiof0_txd_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(5, 20),\n+};\n+static const unsigned int msiof0_txd_mux[] = {\n+\tMSIOF0_TXD_MARK,\n+};\n+static const unsigned int msiof0_rxd_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(5, 22),\n+};\n+static const unsigned int msiof0_rxd_mux[] = {\n+\tMSIOF0_RXD_MARK,\n+};\n+/* - MSIOF1 ----------------------------------------------------------------- */\n+static const unsigned int msiof1_clk_a_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(6, 8),\n+};\n+static const unsigned int msiof1_clk_a_mux[] = {\n+\tMSIOF1_SCK_A_MARK,\n+};\n+static const unsigned int msiof1_sync_a_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(6, 9),\n+};\n+static const unsigned int msiof1_sync_a_mux[] = {\n+\tMSIOF1_SYNC_A_MARK,\n+};\n+static const unsigned int msiof1_ss1_a_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(6, 5),\n+};\n+static const unsigned int msiof1_ss1_a_mux[] = {\n+\tMSIOF1_SS1_A_MARK,\n+};\n+static const unsigned int msiof1_ss2_a_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(6, 6),\n+};\n+static const unsigned int msiof1_ss2_a_mux[] = {\n+\tMSIOF1_SS2_A_MARK,\n+};\n+static const unsigned int msiof1_txd_a_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(6, 7),\n+};\n+static const unsigned int msiof1_txd_a_mux[] = {\n+\tMSIOF1_TXD_A_MARK,\n+};\n+static const unsigned int msiof1_rxd_a_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(6, 10),\n+};\n+static const unsigned int msiof1_rxd_a_mux[] = {\n+\tMSIOF1_RXD_A_MARK,\n+};\n+static const unsigned int msiof1_clk_b_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(5, 9),\n+};\n+static const unsigned int msiof1_clk_b_mux[] = {\n+\tMSIOF1_SCK_B_MARK,\n+};\n+static const unsigned int msiof1_sync_b_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(5, 3),\n+};\n+static const unsigned int msiof1_sync_b_mux[] = {\n+\tMSIOF1_SYNC_B_MARK,\n+};\n+static const unsigned int msiof1_ss1_b_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(5, 4),\n+};\n+static const unsigned int msiof1_ss1_b_mux[] = {\n+\tMSIOF1_SS1_B_MARK,\n+};\n+static const unsigned int msiof1_ss2_b_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(5, 0),\n+};\n+static const unsigned int msiof1_ss2_b_mux[] = {\n+\tMSIOF1_SS2_B_MARK,\n+};\n+static const unsigned int msiof1_txd_b_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(5, 8),\n+};\n+static const unsigned int msiof1_txd_b_mux[] = {\n+\tMSIOF1_TXD_B_MARK,\n+};\n+static const unsigned int msiof1_rxd_b_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(5, 7),\n+};\n+static const unsigned int msiof1_rxd_b_mux[] = {\n+\tMSIOF1_RXD_B_MARK,\n+};\n+static const unsigned int msiof1_clk_c_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(6, 17),\n+};\n+static const unsigned int msiof1_clk_c_mux[] = {\n+\tMSIOF1_SCK_C_MARK,\n+};\n+static const unsigned int msiof1_sync_c_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(6, 18),\n+};\n+static const unsigned int msiof1_sync_c_mux[] = {\n+\tMSIOF1_SYNC_C_MARK,\n+};\n+static const unsigned int msiof1_ss1_c_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(6, 21),\n+};\n+static const unsigned int msiof1_ss1_c_mux[] = {\n+\tMSIOF1_SS1_C_MARK,\n+};\n+static const unsigned int msiof1_ss2_c_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(6, 27),\n+};\n+static const unsigned int msiof1_ss2_c_mux[] = {\n+\tMSIOF1_SS2_C_MARK,\n+};\n+static const unsigned int msiof1_txd_c_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(6, 20),\n+};\n+static const unsigned int msiof1_txd_c_mux[] = {\n+\tMSIOF1_TXD_C_MARK,\n+};\n+static const unsigned int msiof1_rxd_c_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(6, 19),\n+};\n+static const unsigned int msiof1_rxd_c_mux[] = {\n+\tMSIOF1_RXD_C_MARK,\n+};\n+static const unsigned int msiof1_clk_d_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(5, 12),\n+};\n+static const unsigned int msiof1_clk_d_mux[] = {\n+\tMSIOF1_SCK_D_MARK,\n+};\n+static const unsigned int msiof1_sync_d_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(5, 15),\n+};\n+static const unsigned int msiof1_sync_d_mux[] = {\n+\tMSIOF1_SYNC_D_MARK,\n+};\n+static const unsigned int msiof1_ss1_d_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(5, 16),\n+};\n+static const unsigned int msiof1_ss1_d_mux[] = {\n+\tMSIOF1_SS1_D_MARK,\n+};\n+static const unsigned int msiof1_ss2_d_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(5, 21),\n+};\n+static const unsigned int msiof1_ss2_d_mux[] = {\n+\tMSIOF1_SS2_D_MARK,\n+};\n+static const unsigned int msiof1_txd_d_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(5, 14),\n+};\n+static const unsigned int msiof1_txd_d_mux[] = {\n+\tMSIOF1_TXD_D_MARK,\n+};\n+static const unsigned int msiof1_rxd_d_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(5, 13),\n+};\n+static const unsigned int msiof1_rxd_d_mux[] = {\n+\tMSIOF1_RXD_D_MARK,\n+};\n+static const unsigned int msiof1_clk_e_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(3, 0),\n+};\n+static const unsigned int msiof1_clk_e_mux[] = {\n+\tMSIOF1_SCK_E_MARK,\n+};\n+static const unsigned int msiof1_sync_e_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(3, 1),\n+};\n+static const unsigned int msiof1_sync_e_mux[] = {\n+\tMSIOF1_SYNC_E_MARK,\n+};\n+static const unsigned int msiof1_ss1_e_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(3, 4),\n+};\n+static const unsigned int msiof1_ss1_e_mux[] = {\n+\tMSIOF1_SS1_E_MARK,\n+};\n+static const unsigned int msiof1_ss2_e_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(3, 5),\n+};\n+static const unsigned int msiof1_ss2_e_mux[] = {\n+\tMSIOF1_SS2_E_MARK,\n+};\n+static const unsigned int msiof1_txd_e_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(3, 3),\n+};\n+static const unsigned int msiof1_txd_e_mux[] = {\n+\tMSIOF1_TXD_E_MARK,\n+};\n+static const unsigned int msiof1_rxd_e_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(3, 2),\n+};\n+static const unsigned int msiof1_rxd_e_mux[] = {\n+\tMSIOF1_RXD_E_MARK,\n+};\n+static const unsigned int msiof1_clk_f_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(5, 23),\n+};\n+static const unsigned int msiof1_clk_f_mux[] = {\n+\tMSIOF1_SCK_F_MARK,\n+};\n+static const unsigned int msiof1_sync_f_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(5, 24),\n+};\n+static const unsigned int msiof1_sync_f_mux[] = {\n+\tMSIOF1_SYNC_F_MARK,\n+};\n+static const unsigned int msiof1_ss1_f_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(6, 1),\n+};\n+static const unsigned int msiof1_ss1_f_mux[] = {\n+\tMSIOF1_SS1_F_MARK,\n+};\n+static const unsigned int msiof1_ss2_f_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(6, 2),\n+};\n+static const unsigned int msiof1_ss2_f_mux[] = {\n+\tMSIOF1_SS2_F_MARK,\n+};\n+static const unsigned int msiof1_txd_f_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(6, 0),\n+};\n+static const unsigned int msiof1_txd_f_mux[] = {\n+\tMSIOF1_TXD_F_MARK,\n+};\n+static const unsigned int msiof1_rxd_f_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(5, 25),\n+};\n+static const unsigned int msiof1_rxd_f_mux[] = {\n+\tMSIOF1_RXD_F_MARK,\n+};\n+static const unsigned int msiof1_clk_g_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(3, 6),\n+};\n+static const unsigned int msiof1_clk_g_mux[] = {\n+\tMSIOF1_SCK_G_MARK,\n+};\n+static const unsigned int msiof1_sync_g_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(3, 7),\n+};\n+static const unsigned int msiof1_sync_g_mux[] = {\n+\tMSIOF1_SYNC_G_MARK,\n+};\n+static const unsigned int msiof1_ss1_g_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(3, 10),\n+};\n+static const unsigned int msiof1_ss1_g_mux[] = {\n+\tMSIOF1_SS1_G_MARK,\n+};\n+static const unsigned int msiof1_ss2_g_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(3, 11),\n+};\n+static const unsigned int msiof1_ss2_g_mux[] = {\n+\tMSIOF1_SS2_G_MARK,\n+};\n+static const unsigned int msiof1_txd_g_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(3, 9),\n+};\n+static const unsigned int msiof1_txd_g_mux[] = {\n+\tMSIOF1_TXD_G_MARK,\n+};\n+static const unsigned int msiof1_rxd_g_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(3, 8),\n+};\n+static const unsigned int msiof1_rxd_g_mux[] = {\n+\tMSIOF1_RXD_G_MARK,\n+};\n+/* - MSIOF2 ----------------------------------------------------------------- */\n+static const unsigned int msiof2_clk_a_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(1, 9),\n+};\n+static const unsigned int msiof2_clk_a_mux[] = {\n+\tMSIOF2_SCK_A_MARK,\n+};\n+static const unsigned int msiof2_sync_a_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(1, 8),\n+};\n+static const unsigned int msiof2_sync_a_mux[] = {\n+\tMSIOF2_SYNC_A_MARK,\n+};\n+static const unsigned int msiof2_ss1_a_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(1, 6),\n+};\n+static const unsigned int msiof2_ss1_a_mux[] = {\n+\tMSIOF2_SS1_A_MARK,\n+};\n+static const unsigned int msiof2_ss2_a_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(1, 7),\n+};\n+static const unsigned int msiof2_ss2_a_mux[] = {\n+\tMSIOF2_SS2_A_MARK,\n+};\n+static const unsigned int msiof2_txd_a_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(1, 11),\n+};\n+static const unsigned int msiof2_txd_a_mux[] = {\n+\tMSIOF2_TXD_A_MARK,\n+};\n+static const unsigned int msiof2_rxd_a_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(1, 10),\n+};\n+static const unsigned int msiof2_rxd_a_mux[] = {\n+\tMSIOF2_RXD_A_MARK,\n+};\n+static const unsigned int msiof2_clk_b_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(0, 4),\n+};\n+static const unsigned int msiof2_clk_b_mux[] = {\n+\tMSIOF2_SCK_B_MARK,\n+};\n+static const unsigned int msiof2_sync_b_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(0, 5),\n+};\n+static const unsigned int msiof2_sync_b_mux[] = {\n+\tMSIOF2_SYNC_B_MARK,\n+};\n+static const unsigned int msiof2_ss1_b_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(0, 0),\n+};\n+static const unsigned int msiof2_ss1_b_mux[] = {\n+\tMSIOF2_SS1_B_MARK,\n+};\n+static const unsigned int msiof2_ss2_b_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(0, 1),\n+};\n+static const unsigned int msiof2_ss2_b_mux[] = {\n+\tMSIOF2_SS2_B_MARK,\n+};\n+static const unsigned int msiof2_txd_b_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(0, 7),\n+};\n+static const unsigned int msiof2_txd_b_mux[] = {\n+\tMSIOF2_TXD_B_MARK,\n+};\n+static const unsigned int msiof2_rxd_b_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(0, 6),\n+};\n+static const unsigned int msiof2_rxd_b_mux[] = {\n+\tMSIOF2_RXD_B_MARK,\n+};\n+static const unsigned int msiof2_clk_c_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(2, 12),\n+};\n+static const unsigned int msiof2_clk_c_mux[] = {\n+\tMSIOF2_SCK_C_MARK,\n+};\n+static const unsigned int msiof2_sync_c_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(2, 11),\n+};\n+static const unsigned int msiof2_sync_c_mux[] = {\n+\tMSIOF2_SYNC_C_MARK,\n+};\n+static const unsigned int msiof2_ss1_c_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(2, 10),\n+};\n+static const unsigned int msiof2_ss1_c_mux[] = {\n+\tMSIOF2_SS1_C_MARK,\n+};\n+static const unsigned int msiof2_ss2_c_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(2, 9),\n+};\n+static const unsigned int msiof2_ss2_c_mux[] = {\n+\tMSIOF2_SS2_C_MARK,\n+};\n+static const unsigned int msiof2_txd_c_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(2, 14),\n+};\n+static const unsigned int msiof2_txd_c_mux[] = {\n+\tMSIOF2_TXD_C_MARK,\n+};\n+static const unsigned int msiof2_rxd_c_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(2, 13),\n+};\n+static const unsigned int msiof2_rxd_c_mux[] = {\n+\tMSIOF2_RXD_C_MARK,\n+};\n+static const unsigned int msiof2_clk_d_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(0, 8),\n+};\n+static const unsigned int msiof2_clk_d_mux[] = {\n+\tMSIOF2_SCK_D_MARK,\n+};\n+static const unsigned int msiof2_sync_d_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(0, 9),\n+};\n+static const unsigned int msiof2_sync_d_mux[] = {\n+\tMSIOF2_SYNC_D_MARK,\n+};\n+static const unsigned int msiof2_ss1_d_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(0, 12),\n+};\n+static const unsigned int msiof2_ss1_d_mux[] = {\n+\tMSIOF2_SS1_D_MARK,\n+};\n+static const unsigned int msiof2_ss2_d_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(0, 13),\n+};\n+static const unsigned int msiof2_ss2_d_mux[] = {\n+\tMSIOF2_SS2_D_MARK,\n+};\n+static const unsigned int msiof2_txd_d_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(0, 11),\n+};\n+static const unsigned int msiof2_txd_d_mux[] = {\n+\tMSIOF2_TXD_D_MARK,\n+};\n+static const unsigned int msiof2_rxd_d_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(0, 10),\n+};\n+static const unsigned int msiof2_rxd_d_mux[] = {\n+\tMSIOF2_RXD_D_MARK,\n+};\n+/* - MSIOF3 ----------------------------------------------------------------- */\n+static const unsigned int msiof3_clk_a_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(0, 0),\n+};\n+static const unsigned int msiof3_clk_a_mux[] = {\n+\tMSIOF3_SCK_A_MARK,\n+};\n+static const unsigned int msiof3_sync_a_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(0, 1),\n+};\n+static const unsigned int msiof3_sync_a_mux[] = {\n+\tMSIOF3_SYNC_A_MARK,\n+};\n+static const unsigned int msiof3_ss1_a_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(0, 14),\n+};\n+static const unsigned int msiof3_ss1_a_mux[] = {\n+\tMSIOF3_SS1_A_MARK,\n+};\n+static const unsigned int msiof3_ss2_a_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(0, 15),\n+};\n+static const unsigned int msiof3_ss2_a_mux[] = {\n+\tMSIOF3_SS2_A_MARK,\n+};\n+static const unsigned int msiof3_txd_a_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(0, 3),\n+};\n+static const unsigned int msiof3_txd_a_mux[] = {\n+\tMSIOF3_TXD_A_MARK,\n+};\n+static const unsigned int msiof3_rxd_a_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(0, 2),\n+};\n+static const unsigned int msiof3_rxd_a_mux[] = {\n+\tMSIOF3_RXD_A_MARK,\n+};\n+static const unsigned int msiof3_clk_b_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(1, 2),\n+};\n+static const unsigned int msiof3_clk_b_mux[] = {\n+\tMSIOF3_SCK_B_MARK,\n+};\n+static const unsigned int msiof3_sync_b_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(1, 0),\n+};\n+static const unsigned int msiof3_sync_b_mux[] = {\n+\tMSIOF3_SYNC_B_MARK,\n+};\n+static const unsigned int msiof3_ss1_b_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(1, 4),\n+};\n+static const unsigned int msiof3_ss1_b_mux[] = {\n+\tMSIOF3_SS1_B_MARK,\n+};\n+static const unsigned int msiof3_ss2_b_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(1, 5),\n+};\n+static const unsigned int msiof3_ss2_b_mux[] = {\n+\tMSIOF3_SS2_B_MARK,\n+};\n+static const unsigned int msiof3_txd_b_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(1, 1),\n+};\n+static const unsigned int msiof3_txd_b_mux[] = {\n+\tMSIOF3_TXD_B_MARK,\n+};\n+static const unsigned int msiof3_rxd_b_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(1, 3),\n+};\n+static const unsigned int msiof3_rxd_b_mux[] = {\n+\tMSIOF3_RXD_B_MARK,\n+};\n+static const unsigned int msiof3_clk_c_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(1, 12),\n+};\n+static const unsigned int msiof3_clk_c_mux[] = {\n+\tMSIOF3_SCK_C_MARK,\n+};\n+static const unsigned int msiof3_sync_c_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(1, 13),\n+};\n+static const unsigned int msiof3_sync_c_mux[] = {\n+\tMSIOF3_SYNC_C_MARK,\n+};\n+static const unsigned int msiof3_txd_c_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(1, 15),\n+};\n+static const unsigned int msiof3_txd_c_mux[] = {\n+\tMSIOF3_TXD_C_MARK,\n+};\n+static const unsigned int msiof3_rxd_c_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(1, 14),\n+};\n+static const unsigned int msiof3_rxd_c_mux[] = {\n+\tMSIOF3_RXD_C_MARK,\n+};\n+static const unsigned int msiof3_clk_d_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(1, 22),\n+};\n+static const unsigned int msiof3_clk_d_mux[] = {\n+\tMSIOF3_SCK_D_MARK,\n+};\n+static const unsigned int msiof3_sync_d_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(1, 23),\n+};\n+static const unsigned int msiof3_sync_d_mux[] = {\n+\tMSIOF3_SYNC_D_MARK,\n+};\n+static const unsigned int msiof3_ss1_d_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(1, 26),\n+};\n+static const unsigned int msiof3_ss1_d_mux[] = {\n+\tMSIOF3_SS1_D_MARK,\n+};\n+static const unsigned int msiof3_txd_d_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(1, 25),\n+};\n+static const unsigned int msiof3_txd_d_mux[] = {\n+\tMSIOF3_TXD_D_MARK,\n+};\n+static const unsigned int msiof3_rxd_d_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(1, 24),\n+};\n+static const unsigned int msiof3_rxd_d_mux[] = {\n+\tMSIOF3_RXD_D_MARK,\n+};\n+static const unsigned int msiof3_clk_e_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(2, 3),\n+};\n+static const unsigned int msiof3_clk_e_mux[] = {\n+\tMSIOF3_SCK_E_MARK,\n+};\n+static const unsigned int msiof3_sync_e_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(2, 2),\n+};\n+static const unsigned int msiof3_sync_e_mux[] = {\n+\tMSIOF3_SYNC_E_MARK,\n+};\n+static const unsigned int msiof3_ss1_e_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(2, 1),\n+};\n+static const unsigned int msiof3_ss1_e_mux[] = {\n+\tMSIOF3_SS1_E_MARK,\n+};\n+static const unsigned int msiof3_ss2_e_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(2, 0),\n+};\n+static const unsigned int msiof3_ss2_e_mux[] = {\n+\tMSIOF3_SS2_E_MARK,\n+};\n+static const unsigned int msiof3_txd_e_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(2, 5),\n+};\n+static const unsigned int msiof3_txd_e_mux[] = {\n+\tMSIOF3_TXD_E_MARK,\n+};\n+static const unsigned int msiof3_rxd_e_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(2, 4),\n+};\n+static const unsigned int msiof3_rxd_e_mux[] = {\n+\tMSIOF3_RXD_E_MARK,\n+};\n+\n+/* - PWM0 --------------------------------------------------------------------*/\n+static const unsigned int pwm0_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(2, 6),\n+};\n+static const unsigned int pwm0_mux[] = {\n+\tPWM0_MARK,\n+};\n+/* - PWM1 --------------------------------------------------------------------*/\n+static const unsigned int pwm1_a_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(2, 7),\n+};\n+static const unsigned int pwm1_a_mux[] = {\n+\tPWM1_A_MARK,\n+};\n+static const unsigned int pwm1_b_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(1, 8),\n+};\n+static const unsigned int pwm1_b_mux[] = {\n+\tPWM1_B_MARK,\n+};\n+/* - PWM2 --------------------------------------------------------------------*/\n+static const unsigned int pwm2_a_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(2, 8),\n+};\n+static const unsigned int pwm2_a_mux[] = {\n+\tPWM2_A_MARK,\n+};\n+static const unsigned int pwm2_b_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(1, 11),\n+};\n+static const unsigned int pwm2_b_mux[] = {\n+\tPWM2_B_MARK,\n+};\n+/* - PWM3 --------------------------------------------------------------------*/\n+static const unsigned int pwm3_a_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(1, 0),\n+};\n+static const unsigned int pwm3_a_mux[] = {\n+\tPWM3_A_MARK,\n+};\n+static const unsigned int pwm3_b_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(2, 2),\n+};\n+static const unsigned int pwm3_b_mux[] = {\n+\tPWM3_B_MARK,\n+};\n+/* - PWM4 --------------------------------------------------------------------*/\n+static const unsigned int pwm4_a_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(1, 1),\n+};\n+static const unsigned int pwm4_a_mux[] = {\n+\tPWM4_A_MARK,\n+};\n+static const unsigned int pwm4_b_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(2, 3),\n+};\n+static const unsigned int pwm4_b_mux[] = {\n+\tPWM4_B_MARK,\n+};\n+/* - PWM5 --------------------------------------------------------------------*/\n+static const unsigned int pwm5_a_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(1, 2),\n+};\n+static const unsigned int pwm5_a_mux[] = {\n+\tPWM5_A_MARK,\n+};\n+static const unsigned int pwm5_b_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(2, 4),\n+};\n+static const unsigned int pwm5_b_mux[] = {\n+\tPWM5_B_MARK,\n+};\n+/* - PWM6 --------------------------------------------------------------------*/\n+static const unsigned int pwm6_a_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(1, 3),\n+};\n+static const unsigned int pwm6_a_mux[] = {\n+\tPWM6_A_MARK,\n+};\n+static const unsigned int pwm6_b_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(2, 5),\n+};\n+static const unsigned int pwm6_b_mux[] = {\n+\tPWM6_B_MARK,\n+};\n+\n+/* - SCIF0 ------------------------------------------------------------------ */\n+static const unsigned int scif0_data_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),\n+};\n+static const unsigned int scif0_data_mux[] = {\n+\tRX0_MARK, TX0_MARK,\n+};\n+static const unsigned int scif0_clk_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(5, 0),\n+};\n+static const unsigned int scif0_clk_mux[] = {\n+\tSCK0_MARK,\n+};\n+static const unsigned int scif0_ctrl_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),\n+};\n+static const unsigned int scif0_ctrl_mux[] = {\n+\tRTS0_N_TANS_MARK, CTS0_N_MARK,\n+};\n+/* - SCIF1 ------------------------------------------------------------------ */\n+static const unsigned int scif1_data_a_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),\n+};\n+static const unsigned int scif1_data_a_mux[] = {\n+\tRX1_A_MARK, TX1_A_MARK,\n+};\n+static const unsigned int scif1_clk_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(6, 21),\n+};\n+static const unsigned int scif1_clk_mux[] = {\n+\tSCK1_MARK,\n+};\n+static const unsigned int scif1_ctrl_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),\n+};\n+static const unsigned int scif1_ctrl_mux[] = {\n+\tRTS1_N_TANS_MARK, CTS1_N_MARK,\n+};\n+\n+static const unsigned int scif1_data_b_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),\n+};\n+static const unsigned int scif1_data_b_mux[] = {\n+\tRX1_B_MARK, TX1_B_MARK,\n+};\n+/* - SCIF2 ------------------------------------------------------------------ */\n+static const unsigned int scif2_data_a_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),\n+};\n+static const unsigned int scif2_data_a_mux[] = {\n+\tRX2_A_MARK, TX2_A_MARK,\n+};\n+static const unsigned int scif2_clk_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(5, 9),\n+};\n+static const unsigned int scif2_clk_mux[] = {\n+\tSCK2_MARK,\n+};\n+static const unsigned int scif2_data_b_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),\n+};\n+static const unsigned int scif2_data_b_mux[] = {\n+\tRX2_B_MARK, TX2_B_MARK,\n+};\n+/* - SCIF3 ------------------------------------------------------------------ */\n+static const unsigned int scif3_data_a_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),\n+};\n+static const unsigned int scif3_data_a_mux[] = {\n+\tRX3_A_MARK, TX3_A_MARK,\n+};\n+static const unsigned int scif3_clk_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(1, 22),\n+};\n+static const unsigned int scif3_clk_mux[] = {\n+\tSCK3_MARK,\n+};\n+static const unsigned int scif3_ctrl_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),\n+};\n+static const unsigned int scif3_ctrl_mux[] = {\n+\tRTS3_N_TANS_MARK, CTS3_N_MARK,\n+};\n+static const unsigned int scif3_data_b_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),\n+};\n+static const unsigned int scif3_data_b_mux[] = {\n+\tRX3_B_MARK, TX3_B_MARK,\n+};\n+/* - SCIF4 ------------------------------------------------------------------ */\n+static const unsigned int scif4_data_a_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),\n+};\n+static const unsigned int scif4_data_a_mux[] = {\n+\tRX4_A_MARK, TX4_A_MARK,\n+};\n+static const unsigned int scif4_clk_a_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(2, 10),\n+};\n+static const unsigned int scif4_clk_a_mux[] = {\n+\tSCK4_A_MARK,\n+};\n+static const unsigned int scif4_ctrl_a_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),\n+};\n+static const unsigned int scif4_ctrl_a_mux[] = {\n+\tRTS4_N_TANS_A_MARK, CTS4_N_A_MARK,\n+};\n+static const unsigned int scif4_data_b_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),\n+};\n+static const unsigned int scif4_data_b_mux[] = {\n+\tRX4_B_MARK, TX4_B_MARK,\n+};\n+static const unsigned int scif4_clk_b_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(1, 5),\n+};\n+static const unsigned int scif4_clk_b_mux[] = {\n+\tSCK4_B_MARK,\n+};\n+static const unsigned int scif4_ctrl_b_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),\n+};\n+static const unsigned int scif4_ctrl_b_mux[] = {\n+\tRTS4_N_TANS_B_MARK, CTS4_N_B_MARK,\n+};\n+static const unsigned int scif4_data_c_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),\n+};\n+static const unsigned int scif4_data_c_mux[] = {\n+\tRX4_C_MARK, TX4_C_MARK,\n+};\n+static const unsigned int scif4_clk_c_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(0, 8),\n+};\n+static const unsigned int scif4_clk_c_mux[] = {\n+\tSCK4_C_MARK,\n+};\n+static const unsigned int scif4_ctrl_c_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),\n+};\n+static const unsigned int scif4_ctrl_c_mux[] = {\n+\tRTS4_N_TANS_C_MARK, CTS4_N_C_MARK,\n+};\n+/* - SCIF5 ------------------------------------------------------------------ */\n+static const unsigned int scif5_data_a_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),\n+};\n+static const unsigned int scif5_data_a_mux[] = {\n+\tRX5_A_MARK, TX5_A_MARK,\n+};\n+static const unsigned int scif5_clk_a_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(6, 21),\n+};\n+static const unsigned int scif5_clk_a_mux[] = {\n+\tSCK5_A_MARK,\n+};\n+static const unsigned int scif5_data_b_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),\n+};\n+static const unsigned int scif5_data_b_mux[] = {\n+\tRX5_B_MARK, TX5_B_MARK,\n+};\n+static const unsigned int scif5_clk_b_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(5, 0),\n+};\n+static const unsigned int scif5_clk_b_mux[] = {\n+\tSCK5_B_MARK,\n+};\n+\n+/* - SDHI0 ------------------------------------------------------------------ */\n+static const unsigned int sdhi0_data1_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(3, 2),\n+};\n+static const unsigned int sdhi0_data1_mux[] = {\n+\tSD0_DAT0_MARK,\n+};\n+static const unsigned int sdhi0_data4_pins[] = {\n+\t/* D[0:3] */\n+\tRCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),\n+\tRCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),\n+};\n+static const unsigned int sdhi0_data4_mux[] = {\n+\tSD0_DAT0_MARK, SD0_DAT1_MARK,\n+\tSD0_DAT2_MARK, SD0_DAT3_MARK,\n+};\n+static const unsigned int sdhi0_ctrl_pins[] = {\n+\t/* CLK, CMD */\n+\tRCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),\n+};\n+static const unsigned int sdhi0_ctrl_mux[] = {\n+\tSD0_CLK_MARK, SD0_CMD_MARK,\n+};\n+static const unsigned int sdhi0_cd_pins[] = {\n+\t/* CD */\n+\tRCAR_GP_PIN(3, 12),\n+};\n+static const unsigned int sdhi0_cd_mux[] = {\n+\tSD0_CD_MARK,\n+};\n+static const unsigned int sdhi0_wp_pins[] = {\n+\t/* WP */\n+\tRCAR_GP_PIN(3, 13),\n+};\n+static const unsigned int sdhi0_wp_mux[] = {\n+\tSD0_WP_MARK,\n+};\n+/* - SDHI1 ------------------------------------------------------------------ */\n+static const unsigned int sdhi1_data1_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(3, 8),\n+};\n+static const unsigned int sdhi1_data1_mux[] = {\n+\tSD1_DAT0_MARK,\n+};\n+static const unsigned int sdhi1_data4_pins[] = {\n+\t/* D[0:3] */\n+\tRCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),\n+\tRCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),\n+};\n+static const unsigned int sdhi1_data4_mux[] = {\n+\tSD1_DAT0_MARK, SD1_DAT1_MARK,\n+\tSD1_DAT2_MARK, SD1_DAT3_MARK,\n+};\n+static const unsigned int sdhi1_ctrl_pins[] = {\n+\t/* CLK, CMD */\n+\tRCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),\n+};\n+static const unsigned int sdhi1_ctrl_mux[] = {\n+\tSD1_CLK_MARK, SD1_CMD_MARK,\n+};\n+static const unsigned int sdhi1_cd_pins[] = {\n+\t/* CD */\n+\tRCAR_GP_PIN(3, 14),\n+};\n+static const unsigned int sdhi1_cd_mux[] = {\n+\tSD1_CD_MARK,\n+};\n+static const unsigned int sdhi1_wp_pins[] = {\n+\t/* WP */\n+\tRCAR_GP_PIN(3, 15),\n+};\n+static const unsigned int sdhi1_wp_mux[] = {\n+\tSD1_WP_MARK,\n+};\n+/* - SDHI2 ------------------------------------------------------------------ */\n+static const unsigned int sdhi2_data1_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(4, 2),\n+};\n+static const unsigned int sdhi2_data1_mux[] = {\n+\tSD2_DAT0_MARK,\n+};\n+static const unsigned int sdhi2_data4_pins[] = {\n+\t/* D[0:3] */\n+\tRCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),\n+\tRCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),\n+};\n+static const unsigned int sdhi2_data4_mux[] = {\n+\tSD2_DAT0_MARK, SD2_DAT1_MARK,\n+\tSD2_DAT2_MARK, SD2_DAT3_MARK,\n+};\n+static const unsigned int sdhi2_data8_pins[] = {\n+\t/* D[0:7] */\n+\tRCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),\n+\tRCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),\n+\tRCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),\n+\tRCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),\n+};\n+static const unsigned int sdhi2_data8_mux[] = {\n+\tSD2_DAT0_MARK, SD2_DAT1_MARK,\n+\tSD2_DAT2_MARK, SD2_DAT3_MARK,\n+\tSD2_DAT4_MARK, SD2_DAT5_MARK,\n+\tSD2_DAT6_MARK, SD2_DAT7_MARK,\n+};\n+static const unsigned int sdhi2_ctrl_pins[] = {\n+\t/* CLK, CMD */\n+\tRCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),\n+};\n+static const unsigned int sdhi2_ctrl_mux[] = {\n+\tSD2_CLK_MARK, SD2_CMD_MARK,\n+};\n+static const unsigned int sdhi2_cd_a_pins[] = {\n+\t/* CD */\n+\tRCAR_GP_PIN(4, 13),\n+};\n+static const unsigned int sdhi2_cd_a_mux[] = {\n+\tSD2_CD_A_MARK,\n+};\n+static const unsigned int sdhi2_cd_b_pins[] = {\n+\t/* CD */\n+\tRCAR_GP_PIN(5, 10),\n+};\n+static const unsigned int sdhi2_cd_b_mux[] = {\n+\tSD2_CD_B_MARK,\n+};\n+static const unsigned int sdhi2_wp_a_pins[] = {\n+\t/* WP */\n+\tRCAR_GP_PIN(4, 14),\n+};\n+static const unsigned int sdhi2_wp_a_mux[] = {\n+\tSD2_WP_A_MARK,\n+};\n+static const unsigned int sdhi2_wp_b_pins[] = {\n+\t/* WP */\n+\tRCAR_GP_PIN(5, 11),\n+};\n+static const unsigned int sdhi2_wp_b_mux[] = {\n+\tSD2_WP_B_MARK,\n+};\n+static const unsigned int sdhi2_ds_pins[] = {\n+\t/* DS */\n+\tRCAR_GP_PIN(4, 6),\n+};\n+static const unsigned int sdhi2_ds_mux[] = {\n+\tSD2_DS_MARK,\n+};\n+/* - SDHI3 ------------------------------------------------------------------ */\n+static const unsigned int sdhi3_data1_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(4, 9),\n+};\n+static const unsigned int sdhi3_data1_mux[] = {\n+\tSD3_DAT0_MARK,\n+};\n+static const unsigned int sdhi3_data4_pins[] = {\n+\t/* D[0:3] */\n+\tRCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),\n+\tRCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),\n+};\n+static const unsigned int sdhi3_data4_mux[] = {\n+\tSD3_DAT0_MARK, SD3_DAT1_MARK,\n+\tSD3_DAT2_MARK, SD3_DAT3_MARK,\n+};\n+static const unsigned int sdhi3_data8_pins[] = {\n+\t/* D[0:7] */\n+\tRCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),\n+\tRCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),\n+\tRCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),\n+\tRCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),\n+};\n+static const unsigned int sdhi3_data8_mux[] = {\n+\tSD3_DAT0_MARK, SD3_DAT1_MARK,\n+\tSD3_DAT2_MARK, SD3_DAT3_MARK,\n+\tSD3_DAT4_MARK, SD3_DAT5_MARK,\n+\tSD3_DAT6_MARK, SD3_DAT7_MARK,\n+};\n+static const unsigned int sdhi3_ctrl_pins[] = {\n+\t/* CLK, CMD */\n+\tRCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),\n+};\n+static const unsigned int sdhi3_ctrl_mux[] = {\n+\tSD3_CLK_MARK, SD3_CMD_MARK,\n+};\n+static const unsigned int sdhi3_cd_pins[] = {\n+\t/* CD */\n+\tRCAR_GP_PIN(4, 15),\n+};\n+static const unsigned int sdhi3_cd_mux[] = {\n+\tSD3_CD_MARK,\n+};\n+static const unsigned int sdhi3_wp_pins[] = {\n+\t/* WP */\n+\tRCAR_GP_PIN(4, 16),\n+};\n+static const unsigned int sdhi3_wp_mux[] = {\n+\tSD3_WP_MARK,\n+};\n+static const unsigned int sdhi3_ds_pins[] = {\n+\t/* DS */\n+\tRCAR_GP_PIN(4, 17),\n+};\n+static const unsigned int sdhi3_ds_mux[] = {\n+\tSD3_DS_MARK,\n+};\n+\n+/* - SCIF Clock ------------------------------------------------------------- */\n+static const unsigned int scif_clk_a_pins[] = {\n+\t/* SCIF_CLK */\n+\tRCAR_GP_PIN(6, 23),\n+};\n+static const unsigned int scif_clk_a_mux[] = {\n+\tSCIF_CLK_A_MARK,\n+};\n+static const unsigned int scif_clk_b_pins[] = {\n+\t/* SCIF_CLK */\n+\tRCAR_GP_PIN(5, 9),\n+};\n+static const unsigned int scif_clk_b_mux[] = {\n+\tSCIF_CLK_B_MARK,\n+};\n+\n+/* - USB0 ------------------------------------------------------------------- */\n+static const unsigned int usb0_pins[] = {\n+\t/* PWEN, OVC */\n+\tRCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),\n+};\n+static const unsigned int usb0_mux[] = {\n+\tUSB0_PWEN_MARK, USB0_OVC_MARK,\n+};\n+/* - USB1 ------------------------------------------------------------------- */\n+static const unsigned int usb1_pins[] = {\n+\t/* PWEN, OVC */\n+\tRCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),\n+};\n+static const unsigned int usb1_mux[] = {\n+\tUSB1_PWEN_MARK, USB1_OVC_MARK,\n+};\n+/* - USB2 ------------------------------------------------------------------- */\n+static const unsigned int usb2_pins[] = {\n+\t/* PWEN, OVC */\n+\tRCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),\n+};\n+static const unsigned int usb2_mux[] = {\n+\tUSB2_PWEN_MARK, USB2_OVC_MARK,\n+};\n+/* - USB2_CH3 --------------------------------------------------------------- */\n+static const unsigned int usb2_ch3_pins[] = {\n+\t/* PWEN, OVC */\n+\tRCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),\n+};\n+static const unsigned int usb2_ch3_mux[] = {\n+\tUSB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,\n+};\n+\n+static const struct sh_pfc_pin_group pinmux_groups[] = {\n+\tSH_PFC_PIN_GROUP(avb_link),\n+\tSH_PFC_PIN_GROUP(avb_magic),\n+\tSH_PFC_PIN_GROUP(avb_phy_int),\n+\tSH_PFC_PIN_GROUP(avb_mdc),\n+\tSH_PFC_PIN_GROUP(avb_mii),\n+\tSH_PFC_PIN_GROUP(avb_avtp_pps),\n+\tSH_PFC_PIN_GROUP(avb_avtp_match_a),\n+\tSH_PFC_PIN_GROUP(avb_avtp_capture_a),\n+\tSH_PFC_PIN_GROUP(avb_avtp_match_b),\n+\tSH_PFC_PIN_GROUP(avb_avtp_capture_b),\n+\tSH_PFC_PIN_GROUP(drif0_ctrl_a),\n+\tSH_PFC_PIN_GROUP(drif0_data0_a),\n+\tSH_PFC_PIN_GROUP(drif0_data1_a),\n+\tSH_PFC_PIN_GROUP(drif0_ctrl_b),\n+\tSH_PFC_PIN_GROUP(drif0_data0_b),\n+\tSH_PFC_PIN_GROUP(drif0_data1_b),\n+\tSH_PFC_PIN_GROUP(drif0_ctrl_c),\n+\tSH_PFC_PIN_GROUP(drif0_data0_c),\n+\tSH_PFC_PIN_GROUP(drif0_data1_c),\n+\tSH_PFC_PIN_GROUP(drif1_ctrl_a),\n+\tSH_PFC_PIN_GROUP(drif1_data0_a),\n+\tSH_PFC_PIN_GROUP(drif1_data1_a),\n+\tSH_PFC_PIN_GROUP(drif1_ctrl_b),\n+\tSH_PFC_PIN_GROUP(drif1_data0_b),\n+\tSH_PFC_PIN_GROUP(drif1_data1_b),\n+\tSH_PFC_PIN_GROUP(drif1_ctrl_c),\n+\tSH_PFC_PIN_GROUP(drif1_data0_c),\n+\tSH_PFC_PIN_GROUP(drif1_data1_c),\n+\tSH_PFC_PIN_GROUP(drif2_ctrl_a),\n+\tSH_PFC_PIN_GROUP(drif2_data0_a),\n+\tSH_PFC_PIN_GROUP(drif2_data1_a),\n+\tSH_PFC_PIN_GROUP(drif2_ctrl_b),\n+\tSH_PFC_PIN_GROUP(drif2_data0_b),\n+\tSH_PFC_PIN_GROUP(drif2_data1_b),\n+\tSH_PFC_PIN_GROUP(drif3_ctrl_a),\n+\tSH_PFC_PIN_GROUP(drif3_data0_a),\n+\tSH_PFC_PIN_GROUP(drif3_data1_a),\n+\tSH_PFC_PIN_GROUP(drif3_ctrl_b),\n+\tSH_PFC_PIN_GROUP(drif3_data0_b),\n+\tSH_PFC_PIN_GROUP(drif3_data1_b),\n+\tSH_PFC_PIN_GROUP(du_rgb666),\n+\tSH_PFC_PIN_GROUP(du_rgb888),\n+\tSH_PFC_PIN_GROUP(du_clk_out_0),\n+\tSH_PFC_PIN_GROUP(du_clk_out_1),\n+\tSH_PFC_PIN_GROUP(du_sync),\n+\tSH_PFC_PIN_GROUP(du_oddf),\n+\tSH_PFC_PIN_GROUP(du_cde),\n+\tSH_PFC_PIN_GROUP(du_disp),\n+\tSH_PFC_PIN_GROUP(msiof0_clk),\n+\tSH_PFC_PIN_GROUP(msiof0_sync),\n+\tSH_PFC_PIN_GROUP(msiof0_ss1),\n+\tSH_PFC_PIN_GROUP(msiof0_ss2),\n+\tSH_PFC_PIN_GROUP(msiof0_txd),\n+\tSH_PFC_PIN_GROUP(msiof0_rxd),\n+\tSH_PFC_PIN_GROUP(msiof1_clk_a),\n+\tSH_PFC_PIN_GROUP(msiof1_sync_a),\n+\tSH_PFC_PIN_GROUP(msiof1_ss1_a),\n+\tSH_PFC_PIN_GROUP(msiof1_ss2_a),\n+\tSH_PFC_PIN_GROUP(msiof1_txd_a),\n+\tSH_PFC_PIN_GROUP(msiof1_rxd_a),\n+\tSH_PFC_PIN_GROUP(msiof1_clk_b),\n+\tSH_PFC_PIN_GROUP(msiof1_sync_b),\n+\tSH_PFC_PIN_GROUP(msiof1_ss1_b),\n+\tSH_PFC_PIN_GROUP(msiof1_ss2_b),\n+\tSH_PFC_PIN_GROUP(msiof1_txd_b),\n+\tSH_PFC_PIN_GROUP(msiof1_rxd_b),\n+\tSH_PFC_PIN_GROUP(msiof1_clk_c),\n+\tSH_PFC_PIN_GROUP(msiof1_sync_c),\n+\tSH_PFC_PIN_GROUP(msiof1_ss1_c),\n+\tSH_PFC_PIN_GROUP(msiof1_ss2_c),\n+\tSH_PFC_PIN_GROUP(msiof1_txd_c),\n+\tSH_PFC_PIN_GROUP(msiof1_rxd_c),\n+\tSH_PFC_PIN_GROUP(msiof1_clk_d),\n+\tSH_PFC_PIN_GROUP(msiof1_sync_d),\n+\tSH_PFC_PIN_GROUP(msiof1_ss1_d),\n+\tSH_PFC_PIN_GROUP(msiof1_ss2_d),\n+\tSH_PFC_PIN_GROUP(msiof1_txd_d),\n+\tSH_PFC_PIN_GROUP(msiof1_rxd_d),\n+\tSH_PFC_PIN_GROUP(msiof1_clk_e),\n+\tSH_PFC_PIN_GROUP(msiof1_sync_e),\n+\tSH_PFC_PIN_GROUP(msiof1_ss1_e),\n+\tSH_PFC_PIN_GROUP(msiof1_ss2_e),\n+\tSH_PFC_PIN_GROUP(msiof1_txd_e),\n+\tSH_PFC_PIN_GROUP(msiof1_rxd_e),\n+\tSH_PFC_PIN_GROUP(msiof1_clk_f),\n+\tSH_PFC_PIN_GROUP(msiof1_sync_f),\n+\tSH_PFC_PIN_GROUP(msiof1_ss1_f),\n+\tSH_PFC_PIN_GROUP(msiof1_ss2_f),\n+\tSH_PFC_PIN_GROUP(msiof1_txd_f),\n+\tSH_PFC_PIN_GROUP(msiof1_rxd_f),\n+\tSH_PFC_PIN_GROUP(msiof1_clk_g),\n+\tSH_PFC_PIN_GROUP(msiof1_sync_g),\n+\tSH_PFC_PIN_GROUP(msiof1_ss1_g),\n+\tSH_PFC_PIN_GROUP(msiof1_ss2_g),\n+\tSH_PFC_PIN_GROUP(msiof1_txd_g),\n+\tSH_PFC_PIN_GROUP(msiof1_rxd_g),\n+\tSH_PFC_PIN_GROUP(msiof2_clk_a),\n+\tSH_PFC_PIN_GROUP(msiof2_sync_a),\n+\tSH_PFC_PIN_GROUP(msiof2_ss1_a),\n+\tSH_PFC_PIN_GROUP(msiof2_ss2_a),\n+\tSH_PFC_PIN_GROUP(msiof2_txd_a),\n+\tSH_PFC_PIN_GROUP(msiof2_rxd_a),\n+\tSH_PFC_PIN_GROUP(msiof2_clk_b),\n+\tSH_PFC_PIN_GROUP(msiof2_sync_b),\n+\tSH_PFC_PIN_GROUP(msiof2_ss1_b),\n+\tSH_PFC_PIN_GROUP(msiof2_ss2_b),\n+\tSH_PFC_PIN_GROUP(msiof2_txd_b),\n+\tSH_PFC_PIN_GROUP(msiof2_rxd_b),\n+\tSH_PFC_PIN_GROUP(msiof2_clk_c),\n+\tSH_PFC_PIN_GROUP(msiof2_sync_c),\n+\tSH_PFC_PIN_GROUP(msiof2_ss1_c),\n+\tSH_PFC_PIN_GROUP(msiof2_ss2_c),\n+\tSH_PFC_PIN_GROUP(msiof2_txd_c),\n+\tSH_PFC_PIN_GROUP(msiof2_rxd_c),\n+\tSH_PFC_PIN_GROUP(msiof2_clk_d),\n+\tSH_PFC_PIN_GROUP(msiof2_sync_d),\n+\tSH_PFC_PIN_GROUP(msiof2_ss1_d),\n+\tSH_PFC_PIN_GROUP(msiof2_ss2_d),\n+\tSH_PFC_PIN_GROUP(msiof2_txd_d),\n+\tSH_PFC_PIN_GROUP(msiof2_rxd_d),\n+\tSH_PFC_PIN_GROUP(msiof3_clk_a),\n+\tSH_PFC_PIN_GROUP(msiof3_sync_a),\n+\tSH_PFC_PIN_GROUP(msiof3_ss1_a),\n+\tSH_PFC_PIN_GROUP(msiof3_ss2_a),\n+\tSH_PFC_PIN_GROUP(msiof3_txd_a),\n+\tSH_PFC_PIN_GROUP(msiof3_rxd_a),\n+\tSH_PFC_PIN_GROUP(msiof3_clk_b),\n+\tSH_PFC_PIN_GROUP(msiof3_sync_b),\n+\tSH_PFC_PIN_GROUP(msiof3_ss1_b),\n+\tSH_PFC_PIN_GROUP(msiof3_ss2_b),\n+\tSH_PFC_PIN_GROUP(msiof3_txd_b),\n+\tSH_PFC_PIN_GROUP(msiof3_rxd_b),\n+\tSH_PFC_PIN_GROUP(msiof3_clk_c),\n+\tSH_PFC_PIN_GROUP(msiof3_sync_c),\n+\tSH_PFC_PIN_GROUP(msiof3_txd_c),\n+\tSH_PFC_PIN_GROUP(msiof3_rxd_c),\n+\tSH_PFC_PIN_GROUP(msiof3_clk_d),\n+\tSH_PFC_PIN_GROUP(msiof3_sync_d),\n+\tSH_PFC_PIN_GROUP(msiof3_ss1_d),\n+\tSH_PFC_PIN_GROUP(msiof3_txd_d),\n+\tSH_PFC_PIN_GROUP(msiof3_rxd_d),\n+\tSH_PFC_PIN_GROUP(msiof3_clk_e),\n+\tSH_PFC_PIN_GROUP(msiof3_sync_e),\n+\tSH_PFC_PIN_GROUP(msiof3_ss1_e),\n+\tSH_PFC_PIN_GROUP(msiof3_ss2_e),\n+\tSH_PFC_PIN_GROUP(msiof3_txd_e),\n+\tSH_PFC_PIN_GROUP(msiof3_rxd_e),\n+\tSH_PFC_PIN_GROUP(pwm0),\n+\tSH_PFC_PIN_GROUP(pwm1_a),\n+\tSH_PFC_PIN_GROUP(pwm1_b),\n+\tSH_PFC_PIN_GROUP(pwm2_a),\n+\tSH_PFC_PIN_GROUP(pwm2_b),\n+\tSH_PFC_PIN_GROUP(pwm3_a),\n+\tSH_PFC_PIN_GROUP(pwm3_b),\n+\tSH_PFC_PIN_GROUP(pwm4_a),\n+\tSH_PFC_PIN_GROUP(pwm4_b),\n+\tSH_PFC_PIN_GROUP(pwm5_a),\n+\tSH_PFC_PIN_GROUP(pwm5_b),\n+\tSH_PFC_PIN_GROUP(pwm6_a),\n+\tSH_PFC_PIN_GROUP(pwm6_b),\n+\tSH_PFC_PIN_GROUP(scif0_data),\n+\tSH_PFC_PIN_GROUP(scif0_clk),\n+\tSH_PFC_PIN_GROUP(scif0_ctrl),\n+\tSH_PFC_PIN_GROUP(scif1_data_a),\n+\tSH_PFC_PIN_GROUP(scif1_clk),\n+\tSH_PFC_PIN_GROUP(scif1_ctrl),\n+\tSH_PFC_PIN_GROUP(scif1_data_b),\n+\tSH_PFC_PIN_GROUP(scif2_data_a),\n+\tSH_PFC_PIN_GROUP(scif2_clk),\n+\tSH_PFC_PIN_GROUP(scif2_data_b),\n+\tSH_PFC_PIN_GROUP(scif3_data_a),\n+\tSH_PFC_PIN_GROUP(scif3_clk),\n+\tSH_PFC_PIN_GROUP(scif3_ctrl),\n+\tSH_PFC_PIN_GROUP(scif3_data_b),\n+\tSH_PFC_PIN_GROUP(scif4_data_a),\n+\tSH_PFC_PIN_GROUP(scif4_clk_a),\n+\tSH_PFC_PIN_GROUP(scif4_ctrl_a),\n+\tSH_PFC_PIN_GROUP(scif4_data_b),\n+\tSH_PFC_PIN_GROUP(scif4_clk_b),\n+\tSH_PFC_PIN_GROUP(scif4_ctrl_b),\n+\tSH_PFC_PIN_GROUP(scif4_data_c),\n+\tSH_PFC_PIN_GROUP(scif4_clk_c),\n+\tSH_PFC_PIN_GROUP(scif4_ctrl_c),\n+\tSH_PFC_PIN_GROUP(scif5_data_a),\n+\tSH_PFC_PIN_GROUP(scif5_clk_a),\n+\tSH_PFC_PIN_GROUP(scif5_data_b),\n+\tSH_PFC_PIN_GROUP(scif5_clk_b),\n+\tSH_PFC_PIN_GROUP(scif_clk_a),\n+\tSH_PFC_PIN_GROUP(scif_clk_b),\n+\tSH_PFC_PIN_GROUP(sdhi0_data1),\n+\tSH_PFC_PIN_GROUP(sdhi0_data4),\n+\tSH_PFC_PIN_GROUP(sdhi0_ctrl),\n+\tSH_PFC_PIN_GROUP(sdhi0_cd),\n+\tSH_PFC_PIN_GROUP(sdhi0_wp),\n+\tSH_PFC_PIN_GROUP(sdhi1_data1),\n+\tSH_PFC_PIN_GROUP(sdhi1_data4),\n+\tSH_PFC_PIN_GROUP(sdhi1_ctrl),\n+\tSH_PFC_PIN_GROUP(sdhi1_cd),\n+\tSH_PFC_PIN_GROUP(sdhi1_wp),\n+\tSH_PFC_PIN_GROUP(sdhi2_data1),\n+\tSH_PFC_PIN_GROUP(sdhi2_data4),\n+\tSH_PFC_PIN_GROUP(sdhi2_data8),\n+\tSH_PFC_PIN_GROUP(sdhi2_ctrl),\n+\tSH_PFC_PIN_GROUP(sdhi2_cd_a),\n+\tSH_PFC_PIN_GROUP(sdhi2_wp_a),\n+\tSH_PFC_PIN_GROUP(sdhi2_cd_b),\n+\tSH_PFC_PIN_GROUP(sdhi2_wp_b),\n+\tSH_PFC_PIN_GROUP(sdhi2_ds),\n+\tSH_PFC_PIN_GROUP(sdhi3_data1),\n+\tSH_PFC_PIN_GROUP(sdhi3_data4),\n+\tSH_PFC_PIN_GROUP(sdhi3_data8),\n+\tSH_PFC_PIN_GROUP(sdhi3_ctrl),\n+\tSH_PFC_PIN_GROUP(sdhi3_cd),\n+\tSH_PFC_PIN_GROUP(sdhi3_wp),\n+\tSH_PFC_PIN_GROUP(sdhi3_ds),\n+\tSH_PFC_PIN_GROUP(usb0),\n+\tSH_PFC_PIN_GROUP(usb1),\n+\tSH_PFC_PIN_GROUP(usb2),\n+\tSH_PFC_PIN_GROUP(usb2_ch3),\n+};\n+\n+static const char * const avb_groups[] = {\n+\t\"avb_link\",\n+\t\"avb_magic\",\n+\t\"avb_phy_int\",\n+\t\"avb_mdc\",\n+\t\"avb_mii\",\n+\t\"avb_avtp_pps\",\n+\t\"avb_avtp_match_a\",\n+\t\"avb_avtp_capture_a\",\n+\t\"avb_avtp_match_b\",\n+\t\"avb_avtp_capture_b\",\n+};\n+\n+static const char * const drif0_groups[] = {\n+\t\"drif0_ctrl_a\",\n+\t\"drif0_data0_a\",\n+\t\"drif0_data1_a\",\n+\t\"drif0_ctrl_b\",\n+\t\"drif0_data0_b\",\n+\t\"drif0_data1_b\",\n+\t\"drif0_ctrl_c\",\n+\t\"drif0_data0_c\",\n+\t\"drif0_data1_c\",\n+};\n+\n+static const char * const drif1_groups[] = {\n+\t\"drif1_ctrl_a\",\n+\t\"drif1_data0_a\",\n+\t\"drif1_data1_a\",\n+\t\"drif1_ctrl_b\",\n+\t\"drif1_data0_b\",\n+\t\"drif1_data1_b\",\n+\t\"drif1_ctrl_c\",\n+\t\"drif1_data0_c\",\n+\t\"drif1_data1_c\",\n+};\n+\n+static const char * const drif2_groups[] = {\n+\t\"drif2_ctrl_a\",\n+\t\"drif2_data0_a\",\n+\t\"drif2_data1_a\",\n+\t\"drif2_ctrl_b\",\n+\t\"drif2_data0_b\",\n+\t\"drif2_data1_b\",\n+};\n+\n+static const char * const drif3_groups[] = {\n+\t\"drif3_ctrl_a\",\n+\t\"drif3_data0_a\",\n+\t\"drif3_data1_a\",\n+\t\"drif3_ctrl_b\",\n+\t\"drif3_data0_b\",\n+\t\"drif3_data1_b\",\n+};\n+\n+static const char * const du_groups[] = {\n+\t\"du_rgb666\",\n+\t\"du_rgb888\",\n+\t\"du_clk_out_0\",\n+\t\"du_clk_out_1\",\n+\t\"du_sync\",\n+\t\"du_oddf\",\n+\t\"du_cde\",\n+\t\"du_disp\",\n+};\n+\n+static const char * const msiof0_groups[] = {\n+\t\"msiof0_clk\",\n+\t\"msiof0_sync\",\n+\t\"msiof0_ss1\",\n+\t\"msiof0_ss2\",\n+\t\"msiof0_txd\",\n+\t\"msiof0_rxd\",\n+};\n+\n+static const char * const msiof1_groups[] = {\n+\t\"msiof1_clk_a\",\n+\t\"msiof1_sync_a\",\n+\t\"msiof1_ss1_a\",\n+\t\"msiof1_ss2_a\",\n+\t\"msiof1_txd_a\",\n+\t\"msiof1_rxd_a\",\n+\t\"msiof1_clk_b\",\n+\t\"msiof1_sync_b\",\n+\t\"msiof1_ss1_b\",\n+\t\"msiof1_ss2_b\",\n+\t\"msiof1_txd_b\",\n+\t\"msiof1_rxd_b\",\n+\t\"msiof1_clk_c\",\n+\t\"msiof1_sync_c\",\n+\t\"msiof1_ss1_c\",\n+\t\"msiof1_ss2_c\",\n+\t\"msiof1_txd_c\",\n+\t\"msiof1_rxd_c\",\n+\t\"msiof1_clk_d\",\n+\t\"msiof1_sync_d\",\n+\t\"msiof1_ss1_d\",\n+\t\"msiof1_ss2_d\",\n+\t\"msiof1_txd_d\",\n+\t\"msiof1_rxd_d\",\n+\t\"msiof1_clk_e\",\n+\t\"msiof1_sync_e\",\n+\t\"msiof1_ss1_e\",\n+\t\"msiof1_ss2_e\",\n+\t\"msiof1_txd_e\",\n+\t\"msiof1_rxd_e\",\n+\t\"msiof1_clk_f\",\n+\t\"msiof1_sync_f\",\n+\t\"msiof1_ss1_f\",\n+\t\"msiof1_ss2_f\",\n+\t\"msiof1_txd_f\",\n+\t\"msiof1_rxd_f\",\n+\t\"msiof1_clk_g\",\n+\t\"msiof1_sync_g\",\n+\t\"msiof1_ss1_g\",\n+\t\"msiof1_ss2_g\",\n+\t\"msiof1_txd_g\",\n+\t\"msiof1_rxd_g\",\n+};\n+\n+static const char * const msiof2_groups[] = {\n+\t\"msiof2_clk_a\",\n+\t\"msiof2_sync_a\",\n+\t\"msiof2_ss1_a\",\n+\t\"msiof2_ss2_a\",\n+\t\"msiof2_txd_a\",\n+\t\"msiof2_rxd_a\",\n+\t\"msiof2_clk_b\",\n+\t\"msiof2_sync_b\",\n+\t\"msiof2_ss1_b\",\n+\t\"msiof2_ss2_b\",\n+\t\"msiof2_txd_b\",\n+\t\"msiof2_rxd_b\",\n+\t\"msiof2_clk_c\",\n+\t\"msiof2_sync_c\",\n+\t\"msiof2_ss1_c\",\n+\t\"msiof2_ss2_c\",\n+\t\"msiof2_txd_c\",\n+\t\"msiof2_rxd_c\",\n+\t\"msiof2_clk_d\",\n+\t\"msiof2_sync_d\",\n+\t\"msiof2_ss1_d\",\n+\t\"msiof2_ss2_d\",\n+\t\"msiof2_txd_d\",\n+\t\"msiof2_rxd_d\",\n+};\n+\n+static const char * const msiof3_groups[] = {\n+\t\"msiof3_clk_a\",\n+\t\"msiof3_sync_a\",\n+\t\"msiof3_ss1_a\",\n+\t\"msiof3_ss2_a\",\n+\t\"msiof3_txd_a\",\n+\t\"msiof3_rxd_a\",\n+\t\"msiof3_clk_b\",\n+\t\"msiof3_sync_b\",\n+\t\"msiof3_ss1_b\",\n+\t\"msiof3_ss2_b\",\n+\t\"msiof3_txd_b\",\n+\t\"msiof3_rxd_b\",\n+\t\"msiof3_clk_c\",\n+\t\"msiof3_sync_c\",\n+\t\"msiof3_txd_c\",\n+\t\"msiof3_rxd_c\",\n+\t\"msiof3_clk_d\",\n+\t\"msiof3_sync_d\",\n+\t\"msiof3_ss1_d\",\n+\t\"msiof3_txd_d\",\n+\t\"msiof3_rxd_d\",\n+\t\"msiof3_clk_e\",\n+\t\"msiof3_sync_e\",\n+\t\"msiof3_ss1_e\",\n+\t\"msiof3_ss2_e\",\n+\t\"msiof3_txd_e\",\n+\t\"msiof3_rxd_e\",\n+};\n+\n+static const char * const pwm0_groups[] = {\n+\t\"pwm0\",\n+};\n+\n+static const char * const pwm1_groups[] = {\n+\t\"pwm1_a\",\n+\t\"pwm1_b\",\n+};\n+\n+static const char * const pwm2_groups[] = {\n+\t\"pwm2_a\",\n+\t\"pwm2_b\",\n+};\n+\n+static const char * const pwm3_groups[] = {\n+\t\"pwm3_a\",\n+\t\"pwm3_b\",\n+};\n+\n+static const char * const pwm4_groups[] = {\n+\t\"pwm4_a\",\n+\t\"pwm4_b\",\n+};\n+\n+static const char * const pwm5_groups[] = {\n+\t\"pwm5_a\",\n+\t\"pwm5_b\",\n+};\n+\n+static const char * const pwm6_groups[] = {\n+\t\"pwm6_a\",\n+\t\"pwm6_b\",\n+};\n+\n+static const char * const scif0_groups[] = {\n+\t\"scif0_data\",\n+\t\"scif0_clk\",\n+\t\"scif0_ctrl\",\n+};\n+\n+static const char * const scif1_groups[] = {\n+\t\"scif1_data_a\",\n+\t\"scif1_clk\",\n+\t\"scif1_ctrl\",\n+\t\"scif1_data_b\",\n+};\n+\n+static const char * const scif2_groups[] = {\n+\t\"scif2_data_a\",\n+\t\"scif2_clk\",\n+\t\"scif2_data_b\",\n+};\n+\n+static const char * const scif3_groups[] = {\n+\t\"scif3_data_a\",\n+\t\"scif3_clk\",\n+\t\"scif3_ctrl\",\n+\t\"scif3_data_b\",\n+};\n+\n+static const char * const scif4_groups[] = {\n+\t\"scif4_data_a\",\n+\t\"scif4_clk_a\",\n+\t\"scif4_ctrl_a\",\n+\t\"scif4_data_b\",\n+\t\"scif4_clk_b\",\n+\t\"scif4_ctrl_b\",\n+\t\"scif4_data_c\",\n+\t\"scif4_clk_c\",\n+\t\"scif4_ctrl_c\",\n+};\n+\n+static const char * const scif5_groups[] = {\n+\t\"scif5_data_a\",\n+\t\"scif5_clk_a\",\n+\t\"scif5_data_b\",\n+\t\"scif5_clk_b\",\n+};\n+\n+static const char * const scif_clk_groups[] = {\n+\t\"scif_clk_a\",\n+\t\"scif_clk_b\",\n+};\n+\n+static const char * const sdhi0_groups[] = {\n+\t\"sdhi0_data1\",\n+\t\"sdhi0_data4\",\n+\t\"sdhi0_ctrl\",\n+\t\"sdhi0_cd\",\n+\t\"sdhi0_wp\",\n+};\n+\n+static const char * const sdhi1_groups[] = {\n+\t\"sdhi1_data1\",\n+\t\"sdhi1_data4\",\n+\t\"sdhi1_ctrl\",\n+\t\"sdhi1_cd\",\n+\t\"sdhi1_wp\",\n+};\n+\n+static const char * const sdhi2_groups[] = {\n+\t\"sdhi2_data1\",\n+\t\"sdhi2_data4\",\n+\t\"sdhi2_data8\",\n+\t\"sdhi2_ctrl\",\n+\t\"sdhi2_cd_a\",\n+\t\"sdhi2_wp_a\",\n+\t\"sdhi2_cd_b\",\n+\t\"sdhi2_wp_b\",\n+\t\"sdhi2_ds\",\n+};\n+\n+static const char * const sdhi3_groups[] = {\n+\t\"sdhi3_data1\",\n+\t\"sdhi3_data4\",\n+\t\"sdhi3_data8\",\n+\t\"sdhi3_ctrl\",\n+\t\"sdhi3_cd\",\n+\t\"sdhi3_wp\",\n+\t\"sdhi3_ds\",\n+};\n+\n+static const char * const usb0_groups[] = {\n+\t\"usb0\",\n+};\n+\n+static const char * const usb1_groups[] = {\n+\t\"usb1\",\n+};\n+\n+static const char * const usb2_groups[] = {\n+\t\"usb2\",\n+};\n+\n+static const char * const usb2_ch3_groups[] = {\n+\t\"usb2_ch3\",\n+};\n+\n+static const struct sh_pfc_function pinmux_functions[] = {\n+\tSH_PFC_FUNCTION(avb),\n+\tSH_PFC_FUNCTION(drif0),\n+\tSH_PFC_FUNCTION(drif1),\n+\tSH_PFC_FUNCTION(drif2),\n+\tSH_PFC_FUNCTION(drif3),\n+\tSH_PFC_FUNCTION(du),\n+\tSH_PFC_FUNCTION(msiof0),\n+\tSH_PFC_FUNCTION(msiof1),\n+\tSH_PFC_FUNCTION(msiof2),\n+\tSH_PFC_FUNCTION(msiof3),\n+\tSH_PFC_FUNCTION(pwm0),\n+\tSH_PFC_FUNCTION(pwm1),\n+\tSH_PFC_FUNCTION(pwm2),\n+\tSH_PFC_FUNCTION(pwm3),\n+\tSH_PFC_FUNCTION(pwm4),\n+\tSH_PFC_FUNCTION(pwm5),\n+\tSH_PFC_FUNCTION(pwm6),\n+\tSH_PFC_FUNCTION(scif0),\n+\tSH_PFC_FUNCTION(scif1),\n+\tSH_PFC_FUNCTION(scif2),\n+\tSH_PFC_FUNCTION(scif3),\n+\tSH_PFC_FUNCTION(scif4),\n+\tSH_PFC_FUNCTION(scif5),\n+\tSH_PFC_FUNCTION(scif_clk),\n+\tSH_PFC_FUNCTION(sdhi0),\n+\tSH_PFC_FUNCTION(sdhi1),\n+\tSH_PFC_FUNCTION(sdhi2),\n+\tSH_PFC_FUNCTION(sdhi3),\n+\tSH_PFC_FUNCTION(usb0),\n+\tSH_PFC_FUNCTION(usb1),\n+\tSH_PFC_FUNCTION(usb2),\n+\tSH_PFC_FUNCTION(usb2_ch3),\n+};\n+\n+static const struct pinmux_cfg_reg pinmux_config_regs[] = {\n+#define F_(x, y)\tFN_##y\n+#define FM(x)\t\tFN_##x\n+\t{ PINMUX_CFG_REG(\"GPSR0\", 0xe6060100, 32, 1) {\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\tGP_0_15_FN,\tGPSR0_15,\n+\t\tGP_0_14_FN,\tGPSR0_14,\n+\t\tGP_0_13_FN,\tGPSR0_13,\n+\t\tGP_0_12_FN,\tGPSR0_12,\n+\t\tGP_0_11_FN,\tGPSR0_11,\n+\t\tGP_0_10_FN,\tGPSR0_10,\n+\t\tGP_0_9_FN,\tGPSR0_9,\n+\t\tGP_0_8_FN,\tGPSR0_8,\n+\t\tGP_0_7_FN,\tGPSR0_7,\n+\t\tGP_0_6_FN,\tGPSR0_6,\n+\t\tGP_0_5_FN,\tGPSR0_5,\n+\t\tGP_0_4_FN,\tGPSR0_4,\n+\t\tGP_0_3_FN,\tGPSR0_3,\n+\t\tGP_0_2_FN,\tGPSR0_2,\n+\t\tGP_0_1_FN,\tGPSR0_1,\n+\t\tGP_0_0_FN,\tGPSR0_0, }\n+\t},\n+\t{ PINMUX_CFG_REG(\"GPSR1\", 0xe6060104, 32, 1) {\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\tGP_1_27_FN,\tGPSR1_27,\n+\t\tGP_1_26_FN,\tGPSR1_26,\n+\t\tGP_1_25_FN,\tGPSR1_25,\n+\t\tGP_1_24_FN,\tGPSR1_24,\n+\t\tGP_1_23_FN,\tGPSR1_23,\n+\t\tGP_1_22_FN,\tGPSR1_22,\n+\t\tGP_1_21_FN,\tGPSR1_21,\n+\t\tGP_1_20_FN,\tGPSR1_20,\n+\t\tGP_1_19_FN,\tGPSR1_19,\n+\t\tGP_1_18_FN,\tGPSR1_18,\n+\t\tGP_1_17_FN,\tGPSR1_17,\n+\t\tGP_1_16_FN,\tGPSR1_16,\n+\t\tGP_1_15_FN,\tGPSR1_15,\n+\t\tGP_1_14_FN,\tGPSR1_14,\n+\t\tGP_1_13_FN,\tGPSR1_13,\n+\t\tGP_1_12_FN,\tGPSR1_12,\n+\t\tGP_1_11_FN,\tGPSR1_11,\n+\t\tGP_1_10_FN,\tGPSR1_10,\n+\t\tGP_1_9_FN,\tGPSR1_9,\n+\t\tGP_1_8_FN,\tGPSR1_8,\n+\t\tGP_1_7_FN,\tGPSR1_7,\n+\t\tGP_1_6_FN,\tGPSR1_6,\n+\t\tGP_1_5_FN,\tGPSR1_5,\n+\t\tGP_1_4_FN,\tGPSR1_4,\n+\t\tGP_1_3_FN,\tGPSR1_3,\n+\t\tGP_1_2_FN,\tGPSR1_2,\n+\t\tGP_1_1_FN,\tGPSR1_1,\n+\t\tGP_1_0_FN,\tGPSR1_0, }\n+\t},\n+\t{ PINMUX_CFG_REG(\"GPSR2\", 0xe6060108, 32, 1) {\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\tGP_2_14_FN,\tGPSR2_14,\n+\t\tGP_2_13_FN,\tGPSR2_13,\n+\t\tGP_2_12_FN,\tGPSR2_12,\n+\t\tGP_2_11_FN,\tGPSR2_11,\n+\t\tGP_2_10_FN,\tGPSR2_10,\n+\t\tGP_2_9_FN,\tGPSR2_9,\n+\t\tGP_2_8_FN,\tGPSR2_8,\n+\t\tGP_2_7_FN,\tGPSR2_7,\n+\t\tGP_2_6_FN,\tGPSR2_6,\n+\t\tGP_2_5_FN,\tGPSR2_5,\n+\t\tGP_2_4_FN,\tGPSR2_4,\n+\t\tGP_2_3_FN,\tGPSR2_3,\n+\t\tGP_2_2_FN,\tGPSR2_2,\n+\t\tGP_2_1_FN,\tGPSR2_1,\n+\t\tGP_2_0_FN,\tGPSR2_0, }\n+\t},\n+\t{ PINMUX_CFG_REG(\"GPSR3\", 0xe606010c, 32, 1) {\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\tGP_3_15_FN,\tGPSR3_15,\n+\t\tGP_3_14_FN,\tGPSR3_14,\n+\t\tGP_3_13_FN,\tGPSR3_13,\n+\t\tGP_3_12_FN,\tGPSR3_12,\n+\t\tGP_3_11_FN,\tGPSR3_11,\n+\t\tGP_3_10_FN,\tGPSR3_10,\n+\t\tGP_3_9_FN,\tGPSR3_9,\n+\t\tGP_3_8_FN,\tGPSR3_8,\n+\t\tGP_3_7_FN,\tGPSR3_7,\n+\t\tGP_3_6_FN,\tGPSR3_6,\n+\t\tGP_3_5_FN,\tGPSR3_5,\n+\t\tGP_3_4_FN,\tGPSR3_4,\n+\t\tGP_3_3_FN,\tGPSR3_3,\n+\t\tGP_3_2_FN,\tGPSR3_2,\n+\t\tGP_3_1_FN,\tGPSR3_1,\n+\t\tGP_3_0_FN,\tGPSR3_0, }\n+\t},\n+\t{ PINMUX_CFG_REG(\"GPSR4\", 0xe6060110, 32, 1) {\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\tGP_4_17_FN,\tGPSR4_17,\n+\t\tGP_4_16_FN,\tGPSR4_16,\n+\t\tGP_4_15_FN,\tGPSR4_15,\n+\t\tGP_4_14_FN,\tGPSR4_14,\n+\t\tGP_4_13_FN,\tGPSR4_13,\n+\t\tGP_4_12_FN,\tGPSR4_12,\n+\t\tGP_4_11_FN,\tGPSR4_11,\n+\t\tGP_4_10_FN,\tGPSR4_10,\n+\t\tGP_4_9_FN,\tGPSR4_9,\n+\t\tGP_4_8_FN,\tGPSR4_8,\n+\t\tGP_4_7_FN,\tGPSR4_7,\n+\t\tGP_4_6_FN,\tGPSR4_6,\n+\t\tGP_4_5_FN,\tGPSR4_5,\n+\t\tGP_4_4_FN,\tGPSR4_4,\n+\t\tGP_4_3_FN,\tGPSR4_3,\n+\t\tGP_4_2_FN,\tGPSR4_2,\n+\t\tGP_4_1_FN,\tGPSR4_1,\n+\t\tGP_4_0_FN,\tGPSR4_0, }\n+\t},\n+\t{ PINMUX_CFG_REG(\"GPSR5\", 0xe6060114, 32, 1) {\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\tGP_5_25_FN,\tGPSR5_25,\n+\t\tGP_5_24_FN,\tGPSR5_24,\n+\t\tGP_5_23_FN,\tGPSR5_23,\n+\t\tGP_5_22_FN,\tGPSR5_22,\n+\t\tGP_5_21_FN,\tGPSR5_21,\n+\t\tGP_5_20_FN,\tGPSR5_20,\n+\t\tGP_5_19_FN,\tGPSR5_19,\n+\t\tGP_5_18_FN,\tGPSR5_18,\n+\t\tGP_5_17_FN,\tGPSR5_17,\n+\t\tGP_5_16_FN,\tGPSR5_16,\n+\t\tGP_5_15_FN,\tGPSR5_15,\n+\t\tGP_5_14_FN,\tGPSR5_14,\n+\t\tGP_5_13_FN,\tGPSR5_13,\n+\t\tGP_5_12_FN,\tGPSR5_12,\n+\t\tGP_5_11_FN,\tGPSR5_11,\n+\t\tGP_5_10_FN,\tGPSR5_10,\n+\t\tGP_5_9_FN,\tGPSR5_9,\n+\t\tGP_5_8_FN,\tGPSR5_8,\n+\t\tGP_5_7_FN,\tGPSR5_7,\n+\t\tGP_5_6_FN,\tGPSR5_6,\n+\t\tGP_5_5_FN,\tGPSR5_5,\n+\t\tGP_5_4_FN,\tGPSR5_4,\n+\t\tGP_5_3_FN,\tGPSR5_3,\n+\t\tGP_5_2_FN,\tGPSR5_2,\n+\t\tGP_5_1_FN,\tGPSR5_1,\n+\t\tGP_5_0_FN,\tGPSR5_0, }\n+\t},\n+\t{ PINMUX_CFG_REG(\"GPSR6\", 0xe6060118, 32, 1) {\n+\t\tGP_6_31_FN,\tGPSR6_31,\n+\t\tGP_6_30_FN,\tGPSR6_30,\n+\t\tGP_6_29_FN,\tGPSR6_29,\n+\t\tGP_6_28_FN,\tGPSR6_28,\n+\t\tGP_6_27_FN,\tGPSR6_27,\n+\t\tGP_6_26_FN,\tGPSR6_26,\n+\t\tGP_6_25_FN,\tGPSR6_25,\n+\t\tGP_6_24_FN,\tGPSR6_24,\n+\t\tGP_6_23_FN,\tGPSR6_23,\n+\t\tGP_6_22_FN,\tGPSR6_22,\n+\t\tGP_6_21_FN,\tGPSR6_21,\n+\t\tGP_6_20_FN,\tGPSR6_20,\n+\t\tGP_6_19_FN,\tGPSR6_19,\n+\t\tGP_6_18_FN,\tGPSR6_18,\n+\t\tGP_6_17_FN,\tGPSR6_17,\n+\t\tGP_6_16_FN,\tGPSR6_16,\n+\t\tGP_6_15_FN,\tGPSR6_15,\n+\t\tGP_6_14_FN,\tGPSR6_14,\n+\t\tGP_6_13_FN,\tGPSR6_13,\n+\t\tGP_6_12_FN,\tGPSR6_12,\n+\t\tGP_6_11_FN,\tGPSR6_11,\n+\t\tGP_6_10_FN,\tGPSR6_10,\n+\t\tGP_6_9_FN,\tGPSR6_9,\n+\t\tGP_6_8_FN,\tGPSR6_8,\n+\t\tGP_6_7_FN,\tGPSR6_7,\n+\t\tGP_6_6_FN,\tGPSR6_6,\n+\t\tGP_6_5_FN,\tGPSR6_5,\n+\t\tGP_6_4_FN,\tGPSR6_4,\n+\t\tGP_6_3_FN,\tGPSR6_3,\n+\t\tGP_6_2_FN,\tGPSR6_2,\n+\t\tGP_6_1_FN,\tGPSR6_1,\n+\t\tGP_6_0_FN,\tGPSR6_0, }\n+\t},\n+\t{ PINMUX_CFG_REG(\"GPSR7\", 0xe606011c, 32, 1) {\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\tGP_7_3_FN, GPSR7_3,\n+\t\tGP_7_2_FN, GPSR7_2,\n+\t\tGP_7_1_FN, GPSR7_1,\n+\t\tGP_7_0_FN, GPSR7_0, }\n+\t},\n+#undef F_\n+#undef FM\n+\n+#define F_(x, y)\tx,\n+#define FM(x)\t\tFN_##x,\n+\t{ PINMUX_CFG_REG(\"IPSR0\", 0xe6060200, 32, 4) {\n+\t\tIP0_31_28\n+\t\tIP0_27_24\n+\t\tIP0_23_20\n+\t\tIP0_19_16\n+\t\tIP0_15_12\n+\t\tIP0_11_8\n+\t\tIP0_7_4\n+\t\tIP0_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR1\", 0xe6060204, 32, 4) {\n+\t\tIP1_31_28\n+\t\tIP1_27_24\n+\t\tIP1_23_20\n+\t\tIP1_19_16\n+\t\tIP1_15_12\n+\t\tIP1_11_8\n+\t\tIP1_7_4\n+\t\tIP1_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR2\", 0xe6060208, 32, 4) {\n+\t\tIP2_31_28\n+\t\tIP2_27_24\n+\t\tIP2_23_20\n+\t\tIP2_19_16\n+\t\tIP2_15_12\n+\t\tIP2_11_8\n+\t\tIP2_7_4\n+\t\tIP2_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR3\", 0xe606020c, 32, 4) {\n+\t\tIP3_31_28\n+\t\tIP3_27_24\n+\t\tIP3_23_20\n+\t\tIP3_19_16\n+\t\tIP3_15_12\n+\t\tIP3_11_8\n+\t\tIP3_7_4\n+\t\tIP3_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR4\", 0xe6060210, 32, 4) {\n+\t\tIP4_31_28\n+\t\tIP4_27_24\n+\t\tIP4_23_20\n+\t\tIP4_19_16\n+\t\tIP4_15_12\n+\t\tIP4_11_8\n+\t\tIP4_7_4\n+\t\tIP4_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR5\", 0xe6060214, 32, 4) {\n+\t\tIP5_31_28\n+\t\tIP5_27_24\n+\t\tIP5_23_20\n+\t\tIP5_19_16\n+\t\tIP5_15_12\n+\t\tIP5_11_8\n+\t\tIP5_7_4\n+\t\tIP5_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR6\", 0xe6060218, 32, 4) {\n+\t\tIP6_31_28\n+\t\tIP6_27_24\n+\t\tIP6_23_20\n+\t\tIP6_19_16\n+\t\tIP6_15_12\n+\t\tIP6_11_8\n+\t\tIP6_7_4\n+\t\tIP6_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR7\", 0xe606021c, 32, 4) {\n+\t\tIP7_31_28\n+\t\tIP7_27_24\n+\t\tIP7_23_20\n+\t\tIP7_19_16\n+\t\t/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+\t\tIP7_11_8\n+\t\tIP7_7_4\n+\t\tIP7_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR8\", 0xe6060220, 32, 4) {\n+\t\tIP8_31_28\n+\t\tIP8_27_24\n+\t\tIP8_23_20\n+\t\tIP8_19_16\n+\t\tIP8_15_12\n+\t\tIP8_11_8\n+\t\tIP8_7_4\n+\t\tIP8_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR9\", 0xe6060224, 32, 4) {\n+\t\tIP9_31_28\n+\t\tIP9_27_24\n+\t\tIP9_23_20\n+\t\tIP9_19_16\n+\t\tIP9_15_12\n+\t\tIP9_11_8\n+\t\tIP9_7_4\n+\t\tIP9_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR10\", 0xe6060228, 32, 4) {\n+\t\tIP10_31_28\n+\t\tIP10_27_24\n+\t\tIP10_23_20\n+\t\tIP10_19_16\n+\t\tIP10_15_12\n+\t\tIP10_11_8\n+\t\tIP10_7_4\n+\t\tIP10_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR11\", 0xe606022c, 32, 4) {\n+\t\tIP11_31_28\n+\t\tIP11_27_24\n+\t\tIP11_23_20\n+\t\tIP11_19_16\n+\t\tIP11_15_12\n+\t\tIP11_11_8\n+\t\tIP11_7_4\n+\t\tIP11_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR12\", 0xe6060230, 32, 4) {\n+\t\tIP12_31_28\n+\t\tIP12_27_24\n+\t\tIP12_23_20\n+\t\tIP12_19_16\n+\t\tIP12_15_12\n+\t\tIP12_11_8\n+\t\tIP12_7_4\n+\t\tIP12_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR13\", 0xe6060234, 32, 4) {\n+\t\tIP13_31_28\n+\t\tIP13_27_24\n+\t\tIP13_23_20\n+\t\tIP13_19_16\n+\t\tIP13_15_12\n+\t\tIP13_11_8\n+\t\tIP13_7_4\n+\t\tIP13_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR14\", 0xe6060238, 32, 4) {\n+\t\tIP14_31_28\n+\t\tIP14_27_24\n+\t\tIP14_23_20\n+\t\tIP14_19_16\n+\t\tIP14_15_12\n+\t\tIP14_11_8\n+\t\tIP14_7_4\n+\t\tIP14_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR15\", 0xe606023c, 32, 4) {\n+\t\tIP15_31_28\n+\t\tIP15_27_24\n+\t\tIP15_23_20\n+\t\tIP15_19_16\n+\t\tIP15_15_12\n+\t\tIP15_11_8\n+\t\tIP15_7_4\n+\t\tIP15_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR16\", 0xe6060240, 32, 4) {\n+\t\tIP16_31_28\n+\t\tIP16_27_24\n+\t\tIP16_23_20\n+\t\tIP16_19_16\n+\t\tIP16_15_12\n+\t\tIP16_11_8\n+\t\tIP16_7_4\n+\t\tIP16_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR17\", 0xe6060244, 32, 4) {\n+\t\tIP17_31_28\n+\t\tIP17_27_24\n+\t\tIP17_23_20\n+\t\tIP17_19_16\n+\t\tIP17_15_12\n+\t\tIP17_11_8\n+\t\tIP17_7_4\n+\t\tIP17_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR18\", 0xe6060248, 32, 4) {\n+\t\t/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t/* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t/* IP18_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+\t\tIP18_7_4\n+\t\tIP18_3_0 }\n+\t},\n+#undef F_\n+#undef FM\n+\n+#define F_(x, y)\tx,\n+#define FM(x)\t\tFN_##x,\n+\t{ PINMUX_CFG_REG_VAR(\"MOD_SEL0\", 0xe6060500, 32,\n+\t\t\t     3, 2, 3, 1, 1, 1, 1, 1, 2, 1,\n+\t\t\t     1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {\n+\t\tMOD_SEL0_31_30_29\n+\t\tMOD_SEL0_28_27\n+\t\tMOD_SEL0_26_25_24\n+\t\tMOD_SEL0_23\n+\t\tMOD_SEL0_22\n+\t\tMOD_SEL0_21\n+\t\tMOD_SEL0_20\n+\t\tMOD_SEL0_19\n+\t\tMOD_SEL0_18_17\n+\t\tMOD_SEL0_16\n+\t\t0, 0, /* RESERVED 15 */\n+\t\tMOD_SEL0_14_13\n+\t\tMOD_SEL0_12\n+\t\tMOD_SEL0_11\n+\t\tMOD_SEL0_10\n+\t\tMOD_SEL0_9_8\n+\t\tMOD_SEL0_7_6\n+\t\tMOD_SEL0_5\n+\t\tMOD_SEL0_4_3\n+\t\t/* RESERVED 2, 1, 0 */\n+\t\t0, 0, 0, 0, 0, 0, 0, 0 }\n+\t},\n+\t{ PINMUX_CFG_REG_VAR(\"MOD_SEL1\", 0xe6060504, 32,\n+\t\t\t     2, 3, 1, 2, 3, 1, 1, 2, 1,\n+\t\t\t     2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {\n+\t\tMOD_SEL1_31_30\n+\t\tMOD_SEL1_29_28_27\n+\t\tMOD_SEL1_26\n+\t\tMOD_SEL1_25_24\n+\t\tMOD_SEL1_23_22_21\n+\t\tMOD_SEL1_20\n+\t\tMOD_SEL1_19\n+\t\tMOD_SEL1_18_17\n+\t\tMOD_SEL1_16\n+\t\tMOD_SEL1_15_14\n+\t\tMOD_SEL1_13\n+\t\tMOD_SEL1_12\n+\t\tMOD_SEL1_11\n+\t\tMOD_SEL1_10\n+\t\tMOD_SEL1_9\n+\t\t0, 0, 0, 0, /* RESERVED 8, 7 */\n+\t\tMOD_SEL1_6\n+\t\tMOD_SEL1_5\n+\t\tMOD_SEL1_4\n+\t\tMOD_SEL1_3\n+\t\tMOD_SEL1_2\n+\t\tMOD_SEL1_1\n+\t\tMOD_SEL1_0 }\n+\t},\n+\t{ PINMUX_CFG_REG_VAR(\"MOD_SEL2\", 0xe6060508, 32,\n+\t\t\t     1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,\n+\t\t\t     4, 4, 4, 3, 1) {\n+\t\tMOD_SEL2_31\n+\t\tMOD_SEL2_30\n+\t\tMOD_SEL2_29\n+\t\tMOD_SEL2_28_27\n+\t\tMOD_SEL2_26\n+\t\tMOD_SEL2_25_24_23\n+\t\t/* RESERVED 22 */\n+\t\t0, 0,\n+\t\tMOD_SEL2_21\n+\t\tMOD_SEL2_20\n+\t\tMOD_SEL2_19\n+\t\tMOD_SEL2_18\n+\t\tMOD_SEL2_17\n+\t\t/* RESERVED 16 */\n+\t\t0, 0,\n+\t\t/* RESERVED 15, 14, 13, 12 */\n+\t\t0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t/* RESERVED 11, 10, 9, 8 */\n+\t\t0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t/* RESERVED 7, 6, 5, 4 */\n+\t\t0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t/* RESERVED 3, 2, 1 */\n+\t\t0, 0, 0, 0, 0, 0, 0, 0,\n+\t\tMOD_SEL2_0 }\n+\t},\n+\t{ },\n+};\n+\n+static const struct pinmux_drive_reg pinmux_drive_regs[] = {\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL0\", 0xe6060300) {\n+\t\t{ PIN_NUMBER('W', 3),   28, 2 },\t/* QSPI0_SPCLK */\n+\t\t{ PIN_A_NUMBER('C', 5), 24, 2 },\t/* QSPI0_MOSI_IO0 */\n+\t\t{ PIN_A_NUMBER('B', 4), 20, 2 },\t/* QSPI0_MISO_IO1 */\n+\t\t{ PIN_NUMBER('Y', 6),   16, 2 },\t/* QSPI0_IO2 */\n+\t\t{ PIN_A_NUMBER('B', 6), 12, 2 },\t/* QSPI0_IO3 */\n+\t\t{ PIN_NUMBER('Y', 3),    8, 2 },\t/* QSPI0_SSL */\n+\t\t{ PIN_NUMBER('V', 3),    4, 2 },\t/* QSPI1_SPCLK */\n+\t\t{ PIN_A_NUMBER('C', 7),  0, 2 },\t/* QSPI1_MOSI_IO0 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL1\", 0xe6060304) {\n+\t\t{ PIN_A_NUMBER('E', 5), 28, 2 },\t/* QSPI1_MISO_IO1 */\n+\t\t{ PIN_A_NUMBER('E', 4), 24, 2 },\t/* QSPI1_IO2 */\n+\t\t{ PIN_A_NUMBER('C', 3), 20, 2 },\t/* QSPI1_IO3 */\n+\t\t{ PIN_NUMBER('V', 5),   16, 2 },\t/* QSPI1_SSL */\n+\t\t{ PIN_NUMBER('Y', 7),   12, 2 },\t/* RPC_INT# */\n+\t\t{ PIN_NUMBER('V', 6),    8, 2 },\t/* RPC_WP# */\n+\t\t{ PIN_NUMBER('V', 7),    4, 2 },\t/* RPC_RESET# */\n+\t\t{ PIN_NUMBER('A', 16),   0, 3 },\t/* AVB_RX_CTL */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL2\", 0xe6060308) {\n+\t\t{ PIN_NUMBER('B', 19),  28, 3 },\t/* AVB_RXC */\n+\t\t{ PIN_NUMBER('A', 13),  24, 3 },\t/* AVB_RD0 */\n+\t\t{ PIN_NUMBER('B', 13),  20, 3 },\t/* AVB_RD1 */\n+\t\t{ PIN_NUMBER('A', 14),  16, 3 },\t/* AVB_RD2 */\n+\t\t{ PIN_NUMBER('B', 14),  12, 3 },\t/* AVB_RD3 */\n+\t\t{ PIN_NUMBER('A', 8),    8, 3 },\t/* AVB_TX_CTL */\n+\t\t{ PIN_NUMBER('A', 19),   4, 3 },\t/* AVB_TXC */\n+\t\t{ PIN_NUMBER('A', 18),   0, 3 },\t/* AVB_TD0 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL3\", 0xe606030c) {\n+\t\t{ PIN_NUMBER('B', 18),  28, 3 },\t/* AVB_TD1 */\n+\t\t{ PIN_NUMBER('A', 17),  24, 3 },\t/* AVB_TD2 */\n+\t\t{ PIN_NUMBER('B', 17),  20, 3 },\t/* AVB_TD3 */\n+\t\t{ PIN_NUMBER('A', 12),  16, 3 },\t/* AVB_TXCREFCLK */\n+\t\t{ PIN_NUMBER('A', 9),   12, 3 },\t/* AVB_MDIO */\n+\t\t{ RCAR_GP_PIN(2,  9),    8, 3 },\t/* AVB_MDC */\n+\t\t{ RCAR_GP_PIN(2, 10),    4, 3 },\t/* AVB_MAGIC */\n+\t\t{ RCAR_GP_PIN(2, 11),    0, 3 },\t/* AVB_PHY_INT */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL4\", 0xe6060310) {\n+\t\t{ RCAR_GP_PIN(2, 12), 28, 3 },\t/* AVB_LINK */\n+\t\t{ RCAR_GP_PIN(2, 13), 24, 3 },\t/* AVB_AVTP_MATCH */\n+\t\t{ RCAR_GP_PIN(2, 14), 20, 3 },\t/* AVB_AVTP_CAPTURE */\n+\t\t{ RCAR_GP_PIN(2,  0), 16, 3 },\t/* IRQ0 */\n+\t\t{ RCAR_GP_PIN(2,  1), 12, 3 },\t/* IRQ1 */\n+\t\t{ RCAR_GP_PIN(2,  2),  8, 3 },\t/* IRQ2 */\n+\t\t{ RCAR_GP_PIN(2,  3),  4, 3 },\t/* IRQ3 */\n+\t\t{ RCAR_GP_PIN(2,  4),  0, 3 },\t/* IRQ4 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL5\", 0xe6060314) {\n+\t\t{ RCAR_GP_PIN(2,  5), 28, 3 },\t/* IRQ5 */\n+\t\t{ RCAR_GP_PIN(2,  6), 24, 3 },\t/* PWM0 */\n+\t\t{ RCAR_GP_PIN(2,  7), 20, 3 },\t/* PWM1 */\n+\t\t{ RCAR_GP_PIN(2,  8), 16, 3 },\t/* PWM2 */\n+\t\t{ RCAR_GP_PIN(1,  0), 12, 3 },\t/* A0 */\n+\t\t{ RCAR_GP_PIN(1,  1),  8, 3 },\t/* A1 */\n+\t\t{ RCAR_GP_PIN(1,  2),  4, 3 },\t/* A2 */\n+\t\t{ RCAR_GP_PIN(1,  3),  0, 3 },\t/* A3 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL6\", 0xe6060318) {\n+\t\t{ RCAR_GP_PIN(1,  4), 28, 3 },\t/* A4 */\n+\t\t{ RCAR_GP_PIN(1,  5), 24, 3 },\t/* A5 */\n+\t\t{ RCAR_GP_PIN(1,  6), 20, 3 },\t/* A6 */\n+\t\t{ RCAR_GP_PIN(1,  7), 16, 3 },\t/* A7 */\n+\t\t{ RCAR_GP_PIN(1,  8), 12, 3 },\t/* A8 */\n+\t\t{ RCAR_GP_PIN(1,  9),  8, 3 },\t/* A9 */\n+\t\t{ RCAR_GP_PIN(1, 10),  4, 3 },\t/* A10 */\n+\t\t{ RCAR_GP_PIN(1, 11),  0, 3 },\t/* A11 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL7\", 0xe606031c) {\n+\t\t{ RCAR_GP_PIN(1, 12), 28, 3 },\t/* A12 */\n+\t\t{ RCAR_GP_PIN(1, 13), 24, 3 },\t/* A13 */\n+\t\t{ RCAR_GP_PIN(1, 14), 20, 3 },\t/* A14 */\n+\t\t{ RCAR_GP_PIN(1, 15), 16, 3 },\t/* A15 */\n+\t\t{ RCAR_GP_PIN(1, 16), 12, 3 },\t/* A16 */\n+\t\t{ RCAR_GP_PIN(1, 17),  8, 3 },\t/* A17 */\n+\t\t{ RCAR_GP_PIN(1, 18),  4, 3 },\t/* A18 */\n+\t\t{ RCAR_GP_PIN(1, 19),  0, 3 },\t/* A19 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL8\", 0xe6060320) {\n+\t\t{ PIN_NUMBER('F', 1), 28, 3 },\t/* CLKOUT */\n+\t\t{ RCAR_GP_PIN(1, 20), 24, 3 },\t/* CS0 */\n+\t\t{ RCAR_GP_PIN(1, 21), 20, 3 },\t/* CS1_A26 */\n+\t\t{ RCAR_GP_PIN(1, 22), 16, 3 },\t/* BS */\n+\t\t{ RCAR_GP_PIN(1, 23), 12, 3 },\t/* RD */\n+\t\t{ RCAR_GP_PIN(1, 24),  8, 3 },\t/* RD_WR */\n+\t\t{ RCAR_GP_PIN(1, 25),  4, 3 },\t/* WE0 */\n+\t\t{ RCAR_GP_PIN(1, 26),  0, 3 },\t/* WE1 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL9\", 0xe6060324) {\n+\t\t{ RCAR_GP_PIN(1, 27), 28, 3 },\t/* EX_WAIT0 */\n+\t\t{ PIN_NUMBER('C', 1), 24, 3 },\t/* PRESETOUT# */\n+\t\t{ RCAR_GP_PIN(0,  0), 20, 3 },\t/* D0 */\n+\t\t{ RCAR_GP_PIN(0,  1), 16, 3 },\t/* D1 */\n+\t\t{ RCAR_GP_PIN(0,  2), 12, 3 },\t/* D2 */\n+\t\t{ RCAR_GP_PIN(0,  3),  8, 3 },\t/* D3 */\n+\t\t{ RCAR_GP_PIN(0,  4),  4, 3 },\t/* D4 */\n+\t\t{ RCAR_GP_PIN(0,  5),  0, 3 },\t/* D5 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL10\", 0xe6060328) {\n+\t\t{ RCAR_GP_PIN(0,  6), 28, 3 },\t/* D6 */\n+\t\t{ RCAR_GP_PIN(0,  7), 24, 3 },\t/* D7 */\n+\t\t{ RCAR_GP_PIN(0,  8), 20, 3 },\t/* D8 */\n+\t\t{ RCAR_GP_PIN(0,  9), 16, 3 },\t/* D9 */\n+\t\t{ RCAR_GP_PIN(0, 10), 12, 3 },\t/* D10 */\n+\t\t{ RCAR_GP_PIN(0, 11),  8, 3 },\t/* D11 */\n+\t\t{ RCAR_GP_PIN(0, 12),  4, 3 },\t/* D12 */\n+\t\t{ RCAR_GP_PIN(0, 13),  0, 3 },\t/* D13 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL11\", 0xe606032c) {\n+\t\t{ RCAR_GP_PIN(0, 14),   28, 3 },\t/* D14 */\n+\t\t{ RCAR_GP_PIN(0, 15),   24, 3 },\t/* D15 */\n+\t\t{ RCAR_GP_PIN(7,  0),   20, 3 },\t/* AVS1 */\n+\t\t{ RCAR_GP_PIN(7,  1),   16, 3 },\t/* AVS2 */\n+\t\t{ RCAR_GP_PIN(7,  2),   12, 3 },\t/* HDMI0_CEC */\n+\t\t{ RCAR_GP_PIN(7,  3),    8, 3 },\t/* HDMI1_CEC */\n+\t\t{ PIN_A_NUMBER('P', 7),  4, 2 },\t/* DU_DOTCLKIN0 */\n+\t\t{ PIN_A_NUMBER('P', 8),  0, 2 },\t/* DU_DOTCLKIN1 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL12\", 0xe6060330) {\n+\t\t{ PIN_A_NUMBER('R', 7),  28, 2 },\t/* DU_DOTCLKIN2 */\n+\t\t{ PIN_A_NUMBER('R', 8),  24, 2 },\t/* DU_DOTCLKIN3 */\n+\t\t{ PIN_A_NUMBER('D', 38), 20, 2 },\t/* FSCLKST# */\n+\t\t{ PIN_A_NUMBER('R', 30),  4, 2 },\t/* TMS */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL13\", 0xe6060334) {\n+\t\t{ PIN_A_NUMBER('T', 28), 28, 2 },\t/* TDO */\n+\t\t{ PIN_A_NUMBER('T', 30), 24, 2 },\t/* ASEBRK */\n+\t\t{ RCAR_GP_PIN(3,  0),    20, 3 },\t/* SD0_CLK */\n+\t\t{ RCAR_GP_PIN(3,  1),    16, 3 },\t/* SD0_CMD */\n+\t\t{ RCAR_GP_PIN(3,  2),    12, 3 },\t/* SD0_DAT0 */\n+\t\t{ RCAR_GP_PIN(3,  3),     8, 3 },\t/* SD0_DAT1 */\n+\t\t{ RCAR_GP_PIN(3,  4),     4, 3 },\t/* SD0_DAT2 */\n+\t\t{ RCAR_GP_PIN(3,  5),     0, 3 },\t/* SD0_DAT3 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL14\", 0xe6060338) {\n+\t\t{ RCAR_GP_PIN(3,  6), 28, 3 },\t/* SD1_CLK */\n+\t\t{ RCAR_GP_PIN(3,  7), 24, 3 },\t/* SD1_CMD */\n+\t\t{ RCAR_GP_PIN(3,  8), 20, 3 },\t/* SD1_DAT0 */\n+\t\t{ RCAR_GP_PIN(3,  9), 16, 3 },\t/* SD1_DAT1 */\n+\t\t{ RCAR_GP_PIN(3, 10), 12, 3 },\t/* SD1_DAT2 */\n+\t\t{ RCAR_GP_PIN(3, 11),  8, 3 },\t/* SD1_DAT3 */\n+\t\t{ RCAR_GP_PIN(4,  0),  4, 3 },\t/* SD2_CLK */\n+\t\t{ RCAR_GP_PIN(4,  1),  0, 3 },\t/* SD2_CMD */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL15\", 0xe606033c) {\n+\t\t{ RCAR_GP_PIN(4,  2), 28, 3 },\t/* SD2_DAT0 */\n+\t\t{ RCAR_GP_PIN(4,  3), 24, 3 },\t/* SD2_DAT1 */\n+\t\t{ RCAR_GP_PIN(4,  4), 20, 3 },\t/* SD2_DAT2 */\n+\t\t{ RCAR_GP_PIN(4,  5), 16, 3 },\t/* SD2_DAT3 */\n+\t\t{ RCAR_GP_PIN(4,  6), 12, 3 },\t/* SD2_DS */\n+\t\t{ RCAR_GP_PIN(4,  7),  8, 3 },\t/* SD3_CLK */\n+\t\t{ RCAR_GP_PIN(4,  8),  4, 3 },\t/* SD3_CMD */\n+\t\t{ RCAR_GP_PIN(4,  9),  0, 3 },\t/* SD3_DAT0 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL16\", 0xe6060340) {\n+\t\t{ RCAR_GP_PIN(4, 10), 28, 3 },\t/* SD3_DAT1 */\n+\t\t{ RCAR_GP_PIN(4, 11), 24, 3 },\t/* SD3_DAT2 */\n+\t\t{ RCAR_GP_PIN(4, 12), 20, 3 },\t/* SD3_DAT3 */\n+\t\t{ RCAR_GP_PIN(4, 13), 16, 3 },\t/* SD3_DAT4 */\n+\t\t{ RCAR_GP_PIN(4, 14), 12, 3 },\t/* SD3_DAT5 */\n+\t\t{ RCAR_GP_PIN(4, 15),  8, 3 },\t/* SD3_DAT6 */\n+\t\t{ RCAR_GP_PIN(4, 16),  4, 3 },\t/* SD3_DAT7 */\n+\t\t{ RCAR_GP_PIN(4, 17),  0, 3 },\t/* SD3_DS */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL17\", 0xe6060344) {\n+\t\t{ RCAR_GP_PIN(3, 12), 28, 3 },\t/* SD0_CD */\n+\t\t{ RCAR_GP_PIN(3, 13), 24, 3 },\t/* SD0_WP */\n+\t\t{ RCAR_GP_PIN(3, 14), 20, 3 },\t/* SD1_CD */\n+\t\t{ RCAR_GP_PIN(3, 15), 16, 3 },\t/* SD1_WP */\n+\t\t{ RCAR_GP_PIN(5,  0), 12, 3 },\t/* SCK0 */\n+\t\t{ RCAR_GP_PIN(5,  1),  8, 3 },\t/* RX0 */\n+\t\t{ RCAR_GP_PIN(5,  2),  4, 3 },\t/* TX0 */\n+\t\t{ RCAR_GP_PIN(5,  3),  0, 3 },\t/* CTS0 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL18\", 0xe6060348) {\n+\t\t{ RCAR_GP_PIN(5,  4), 28, 3 },\t/* RTS0_TANS */\n+\t\t{ RCAR_GP_PIN(5,  5), 24, 3 },\t/* RX1 */\n+\t\t{ RCAR_GP_PIN(5,  6), 20, 3 },\t/* TX1 */\n+\t\t{ RCAR_GP_PIN(5,  7), 16, 3 },\t/* CTS1 */\n+\t\t{ RCAR_GP_PIN(5,  8), 12, 3 },\t/* RTS1_TANS */\n+\t\t{ RCAR_GP_PIN(5,  9),  8, 3 },\t/* SCK2 */\n+\t\t{ RCAR_GP_PIN(5, 10),  4, 3 },\t/* TX2 */\n+\t\t{ RCAR_GP_PIN(5, 11),  0, 3 },\t/* RX2 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL19\", 0xe606034c) {\n+\t\t{ RCAR_GP_PIN(5, 12), 28, 3 },\t/* HSCK0 */\n+\t\t{ RCAR_GP_PIN(5, 13), 24, 3 },\t/* HRX0 */\n+\t\t{ RCAR_GP_PIN(5, 14), 20, 3 },\t/* HTX0 */\n+\t\t{ RCAR_GP_PIN(5, 15), 16, 3 },\t/* HCTS0 */\n+\t\t{ RCAR_GP_PIN(5, 16), 12, 3 },\t/* HRTS0 */\n+\t\t{ RCAR_GP_PIN(5, 17),  8, 3 },\t/* MSIOF0_SCK */\n+\t\t{ RCAR_GP_PIN(5, 18),  4, 3 },\t/* MSIOF0_SYNC */\n+\t\t{ RCAR_GP_PIN(5, 19),  0, 3 },\t/* MSIOF0_SS1 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL20\", 0xe6060350) {\n+\t\t{ RCAR_GP_PIN(5, 20), 28, 3 },\t/* MSIOF0_TXD */\n+\t\t{ RCAR_GP_PIN(5, 21), 24, 3 },\t/* MSIOF0_SS2 */\n+\t\t{ RCAR_GP_PIN(5, 22), 20, 3 },\t/* MSIOF0_RXD */\n+\t\t{ RCAR_GP_PIN(5, 23), 16, 3 },\t/* MLB_CLK */\n+\t\t{ RCAR_GP_PIN(5, 24), 12, 3 },\t/* MLB_SIG */\n+\t\t{ RCAR_GP_PIN(5, 25),  8, 3 },\t/* MLB_DAT */\n+\t\t{ PIN_NUMBER('H', 37),  4, 3 },\t/* MLB_REF */\n+\t\t{ RCAR_GP_PIN(6,  0),  0, 3 },\t/* SSI_SCK01239 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL21\", 0xe6060354) {\n+\t\t{ RCAR_GP_PIN(6,  1), 28, 3 },\t/* SSI_WS01239 */\n+\t\t{ RCAR_GP_PIN(6,  2), 24, 3 },\t/* SSI_SDATA0 */\n+\t\t{ RCAR_GP_PIN(6,  3), 20, 3 },\t/* SSI_SDATA1 */\n+\t\t{ RCAR_GP_PIN(6,  4), 16, 3 },\t/* SSI_SDATA2 */\n+\t\t{ RCAR_GP_PIN(6,  5), 12, 3 },\t/* SSI_SCK349 */\n+\t\t{ RCAR_GP_PIN(6,  6),  8, 3 },\t/* SSI_WS349 */\n+\t\t{ RCAR_GP_PIN(6,  7),  4, 3 },\t/* SSI_SDATA3 */\n+\t\t{ RCAR_GP_PIN(6,  8),  0, 3 },\t/* SSI_SCK4 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL22\", 0xe6060358) {\n+\t\t{ RCAR_GP_PIN(6,  9), 28, 3 },\t/* SSI_WS4 */\n+\t\t{ RCAR_GP_PIN(6, 10), 24, 3 },\t/* SSI_SDATA4 */\n+\t\t{ RCAR_GP_PIN(6, 11), 20, 3 },\t/* SSI_SCK5 */\n+\t\t{ RCAR_GP_PIN(6, 12), 16, 3 },\t/* SSI_WS5 */\n+\t\t{ RCAR_GP_PIN(6, 13), 12, 3 },\t/* SSI_SDATA5 */\n+\t\t{ RCAR_GP_PIN(6, 14),  8, 3 },\t/* SSI_SCK6 */\n+\t\t{ RCAR_GP_PIN(6, 15),  4, 3 },\t/* SSI_WS6 */\n+\t\t{ RCAR_GP_PIN(6, 16),  0, 3 },\t/* SSI_SDATA6 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL23\", 0xe606035c) {\n+\t\t{ RCAR_GP_PIN(6, 17), 28, 3 },\t/* SSI_SCK78 */\n+\t\t{ RCAR_GP_PIN(6, 18), 24, 3 },\t/* SSI_WS78 */\n+\t\t{ RCAR_GP_PIN(6, 19), 20, 3 },\t/* SSI_SDATA7 */\n+\t\t{ RCAR_GP_PIN(6, 20), 16, 3 },\t/* SSI_SDATA8 */\n+\t\t{ RCAR_GP_PIN(6, 21), 12, 3 },\t/* SSI_SDATA9 */\n+\t\t{ RCAR_GP_PIN(6, 22),  8, 3 },\t/* AUDIO_CLKA */\n+\t\t{ RCAR_GP_PIN(6, 23),  4, 3 },\t/* AUDIO_CLKB */\n+\t\t{ RCAR_GP_PIN(6, 24),  0, 3 },\t/* USB0_PWEN */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL24\", 0xe6060360) {\n+\t\t{ RCAR_GP_PIN(6, 25), 28, 3 },\t/* USB0_OVC */\n+\t\t{ RCAR_GP_PIN(6, 26), 24, 3 },\t/* USB1_PWEN */\n+\t\t{ RCAR_GP_PIN(6, 27), 20, 3 },\t/* USB1_OVC */\n+\t\t{ RCAR_GP_PIN(6, 28), 16, 3 },\t/* USB30_PWEN */\n+\t\t{ RCAR_GP_PIN(6, 29), 12, 3 },\t/* USB30_OVC */\n+\t\t{ RCAR_GP_PIN(6, 30),  8, 3 },\t/* USB2_CH3_PWEN */\n+\t\t{ RCAR_GP_PIN(6, 31),  4, 3 },\t/* USB2_CH3_OVC */\n+\t} },\n+\t{ },\n+};\n+\n+static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)\n+{\n+\tint bit = -EINVAL;\n+\n+\t*pocctrl = 0xe6060380;\n+\n+\tif (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))\n+\t\tbit = pin & 0x1f;\n+\n+\tif (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))\n+\t\tbit = (pin & 0x1f) + 12;\n+\n+\treturn bit;\n+}\n+\n+#define PUEN\t0xe6060400\n+#define PUD\t0xe6060440\n+\n+#define PU0\t0x00\n+#define PU1\t0x04\n+#define PU2\t0x08\n+#define PU3\t0x0c\n+#define PU4\t0x10\n+#define PU5\t0x14\n+#define PU6\t0x18\n+\n+static const struct sh_pfc_bias_info bias_info[] = {\n+\t{ RCAR_GP_PIN(2, 11),    PU0, 31 },\t/* AVB_PHY_INT */\n+\t{ RCAR_GP_PIN(2, 10),    PU0, 30 },\t/* AVB_MAGIC */\n+\t{ RCAR_GP_PIN(2,  9),    PU0, 29 },\t/* AVB_MDC */\n+\t{ PIN_NUMBER('A', 9),    PU0, 28 },\t/* AVB_MDIO */\n+\t{ PIN_NUMBER('A', 12),   PU0, 27 },\t/* AVB_TXCREFCLK */\n+\t{ PIN_NUMBER('B', 17),   PU0, 26 },\t/* AVB_TD3 */\n+\t{ PIN_NUMBER('A', 17),   PU0, 25 },\t/* AVB_TD2 */\n+\t{ PIN_NUMBER('B', 18),   PU0, 24 },\t/* AVB_TD1 */\n+\t{ PIN_NUMBER('A', 18),   PU0, 23 },\t/* AVB_TD0 */\n+\t{ PIN_NUMBER('A', 19),   PU0, 22 },\t/* AVB_TXC */\n+\t{ PIN_NUMBER('A', 8),    PU0, 21 },\t/* AVB_TX_CTL */\n+\t{ PIN_NUMBER('B', 14),   PU0, 20 },\t/* AVB_RD3 */\n+\t{ PIN_NUMBER('A', 14),   PU0, 19 },\t/* AVB_RD2 */\n+\t{ PIN_NUMBER('B', 13),   PU0, 18 },\t/* AVB_RD1 */\n+\t{ PIN_NUMBER('A', 13),   PU0, 17 },\t/* AVB_RD0 */\n+\t{ PIN_NUMBER('B', 19),   PU0, 16 },\t/* AVB_RXC */\n+\t{ PIN_NUMBER('A', 16),   PU0, 15 },\t/* AVB_RX_CTL */\n+\t{ PIN_NUMBER('V', 7),    PU0, 14 },\t/* RPC_RESET# */\n+\t{ PIN_NUMBER('V', 6),    PU0, 13 },\t/* RPC_WP# */\n+\t{ PIN_NUMBER('Y', 7),    PU0, 12 },\t/* RPC_INT# */\n+\t{ PIN_NUMBER('V', 5),    PU0, 11 },\t/* QSPI1_SSL */\n+\t{ PIN_A_NUMBER('C', 3),  PU0, 10 },\t/* QSPI1_IO3 */\n+\t{ PIN_A_NUMBER('E', 4),  PU0,  9 },\t/* QSPI1_IO2 */\n+\t{ PIN_A_NUMBER('E', 5),  PU0,  8 },\t/* QSPI1_MISO_IO1 */\n+\t{ PIN_A_NUMBER('C', 7),  PU0,  7 },\t/* QSPI1_MOSI_IO0 */\n+\t{ PIN_NUMBER('V', 3),    PU0,  6 },\t/* QSPI1_SPCLK */\n+\t{ PIN_NUMBER('Y', 3),    PU0,  5 },\t/* QSPI0_SSL */\n+\t{ PIN_A_NUMBER('B', 6),  PU0,  4 },\t/* QSPI0_IO3 */\n+\t{ PIN_NUMBER('Y', 6),    PU0,  3 },\t/* QSPI0_IO2 */\n+\t{ PIN_A_NUMBER('B', 4),  PU0,  2 },\t/* QSPI0_MISO_IO1 */\n+\t{ PIN_A_NUMBER('C', 5),  PU0,  1 },\t/* QSPI0_MOSI_IO0 */\n+\t{ PIN_NUMBER('W', 3),    PU0,  0 },\t/* QSPI0_SPCLK */\n+\n+\t{ RCAR_GP_PIN(1, 19),    PU1, 31 },\t/* A19 */\n+\t{ RCAR_GP_PIN(1, 18),    PU1, 30 },\t/* A18 */\n+\t{ RCAR_GP_PIN(1, 17),    PU1, 29 },\t/* A17 */\n+\t{ RCAR_GP_PIN(1, 16),    PU1, 28 },\t/* A16 */\n+\t{ RCAR_GP_PIN(1, 15),    PU1, 27 },\t/* A15 */\n+\t{ RCAR_GP_PIN(1, 14),    PU1, 26 },\t/* A14 */\n+\t{ RCAR_GP_PIN(1, 13),    PU1, 25 },\t/* A13 */\n+\t{ RCAR_GP_PIN(1, 12),    PU1, 24 },\t/* A12 */\n+\t{ RCAR_GP_PIN(1, 11),    PU1, 23 },\t/* A11 */\n+\t{ RCAR_GP_PIN(1, 10),    PU1, 22 },\t/* A10 */\n+\t{ RCAR_GP_PIN(1,  9),    PU1, 21 },\t/* A9 */\n+\t{ RCAR_GP_PIN(1,  8),    PU1, 20 },\t/* A8 */\n+\t{ RCAR_GP_PIN(1,  7),    PU1, 19 },\t/* A7 */\n+\t{ RCAR_GP_PIN(1,  6),    PU1, 18 },\t/* A6 */\n+\t{ RCAR_GP_PIN(1,  5),    PU1, 17 },\t/* A5 */\n+\t{ RCAR_GP_PIN(1,  4),    PU1, 16 },\t/* A4 */\n+\t{ RCAR_GP_PIN(1,  3),    PU1, 15 },\t/* A3 */\n+\t{ RCAR_GP_PIN(1,  2),    PU1, 14 },\t/* A2 */\n+\t{ RCAR_GP_PIN(1,  1),    PU1, 13 },\t/* A1 */\n+\t{ RCAR_GP_PIN(1,  0),    PU1, 12 },\t/* A0 */\n+\t{ RCAR_GP_PIN(2,  8),    PU1, 11 },\t/* PWM2_A */\n+\t{ RCAR_GP_PIN(2,  7),    PU1, 10 },\t/* PWM1_A */\n+\t{ RCAR_GP_PIN(2,  6),    PU1,  9 },\t/* PWM0 */\n+\t{ RCAR_GP_PIN(2,  5),    PU1,  8 },\t/* IRQ5 */\n+\t{ RCAR_GP_PIN(2,  4),    PU1,  7 },\t/* IRQ4 */\n+\t{ RCAR_GP_PIN(2,  3),    PU1,  6 },\t/* IRQ3 */\n+\t{ RCAR_GP_PIN(2,  2),    PU1,  5 },\t/* IRQ2 */\n+\t{ RCAR_GP_PIN(2,  1),    PU1,  4 },\t/* IRQ1 */\n+\t{ RCAR_GP_PIN(2,  0),    PU1,  3 },\t/* IRQ0 */\n+\t{ RCAR_GP_PIN(2, 14),    PU1,  2 },\t/* AVB_AVTP_CAPTURE_A */\n+\t{ RCAR_GP_PIN(2, 13),    PU1,  1 },\t/* AVB_AVTP_MATCH_A */\n+\t{ RCAR_GP_PIN(2, 12),    PU1,  0 },\t/* AVB_LINK */\n+\n+\t{ PIN_A_NUMBER('P', 8),  PU2, 31 },\t/* DU_DOTCLKIN1 */\n+\t{ PIN_A_NUMBER('P', 7),  PU2, 30 },\t/* DU_DOTCLKIN0 */\n+\t{ RCAR_GP_PIN(7,  3),    PU2, 29 },\t/* HDMI1_CEC */\n+\t{ RCAR_GP_PIN(7,  2),    PU2, 28 },\t/* HDMI0_CEC */\n+\t{ RCAR_GP_PIN(7,  1),    PU2, 27 },\t/* AVS2 */\n+\t{ RCAR_GP_PIN(7,  0),    PU2, 26 },\t/* AVS1 */\n+\t{ RCAR_GP_PIN(0, 15),    PU2, 25 },\t/* D15 */\n+\t{ RCAR_GP_PIN(0, 14),    PU2, 24 },\t/* D14 */\n+\t{ RCAR_GP_PIN(0, 13),    PU2, 23 },\t/* D13 */\n+\t{ RCAR_GP_PIN(0, 12),    PU2, 22 },\t/* D12 */\n+\t{ RCAR_GP_PIN(0, 11),    PU2, 21 },\t/* D11 */\n+\t{ RCAR_GP_PIN(0, 10),    PU2, 20 },\t/* D10 */\n+\t{ RCAR_GP_PIN(0,  9),    PU2, 19 },\t/* D9 */\n+\t{ RCAR_GP_PIN(0,  8),    PU2, 18 },\t/* D8 */\n+\t{ RCAR_GP_PIN(0,  7),    PU2, 17 },\t/* D7 */\n+\t{ RCAR_GP_PIN(0,  6),    PU2, 16 },\t/* D6 */\n+\t{ RCAR_GP_PIN(0,  5),    PU2, 15 },\t/* D5 */\n+\t{ RCAR_GP_PIN(0,  4),    PU2, 14 },\t/* D4 */\n+\t{ RCAR_GP_PIN(0,  3),    PU2, 13 },\t/* D3 */\n+\t{ RCAR_GP_PIN(0,  2),    PU2, 12 },\t/* D2 */\n+\t{ RCAR_GP_PIN(0,  1),    PU2, 11 },\t/* D1 */\n+\t{ RCAR_GP_PIN(0,  0),    PU2, 10 },\t/* D0 */\n+\t{ PIN_NUMBER('C', 1),    PU2,  9 },\t/* PRESETOUT# */\n+\t{ RCAR_GP_PIN(1, 27),    PU2,  8 },\t/* EX_WAIT0_A */\n+\t{ RCAR_GP_PIN(1, 26),    PU2,  7 },\t/* WE1_N */\n+\t{ RCAR_GP_PIN(1, 25),    PU2,  6 },\t/* WE0_N */\n+\t{ RCAR_GP_PIN(1, 24),    PU2,  5 },\t/* RD_WR_N */\n+\t{ RCAR_GP_PIN(1, 23),    PU2,  4 },\t/* RD_N */\n+\t{ RCAR_GP_PIN(1, 22),    PU2,  3 },\t/* BS_N */\n+\t{ RCAR_GP_PIN(1, 21),    PU2,  2 },\t/* CS1_N */\n+\t{ RCAR_GP_PIN(1, 20),    PU2,  1 },\t/* CS0_N */\n+\t{ PIN_NUMBER('F', 1),    PU2,  0 },\t/* CLKOUT */\n+\n+\t{ RCAR_GP_PIN(4,  9),    PU3, 31 },\t/* SD3_DAT0 */\n+\t{ RCAR_GP_PIN(4,  8),    PU3, 30 },\t/* SD3_CMD */\n+\t{ RCAR_GP_PIN(4,  7),    PU3, 29 },\t/* SD3_CLK */\n+\t{ RCAR_GP_PIN(4,  6),    PU3, 28 },\t/* SD2_DS */\n+\t{ RCAR_GP_PIN(4,  5),    PU3, 27 },\t/* SD2_DAT3 */\n+\t{ RCAR_GP_PIN(4,  4),    PU3, 26 },\t/* SD2_DAT2 */\n+\t{ RCAR_GP_PIN(4,  3),    PU3, 25 },\t/* SD2_DAT1 */\n+\t{ RCAR_GP_PIN(4,  2),    PU3, 24 },\t/* SD2_DAT0 */\n+\t{ RCAR_GP_PIN(4,  1),    PU3, 23 },\t/* SD2_CMD */\n+\t{ RCAR_GP_PIN(4,  0),    PU3, 22 },\t/* SD2_CLK */\n+\t{ RCAR_GP_PIN(3, 11),    PU3, 21 },\t/* SD1_DAT3 */\n+\t{ RCAR_GP_PIN(3, 10),    PU3, 20 },\t/* SD1_DAT2 */\n+\t{ RCAR_GP_PIN(3,  9),    PU3, 19 },\t/* SD1_DAT1 */\n+\t{ RCAR_GP_PIN(3,  8),    PU3, 18 },\t/* SD1_DAT0 */\n+\t{ RCAR_GP_PIN(3,  7),    PU3, 17 },\t/* SD1_CMD */\n+\t{ RCAR_GP_PIN(3,  6),    PU3, 16 },\t/* SD1_CLK */\n+\t{ RCAR_GP_PIN(3,  5),    PU3, 15 },\t/* SD0_DAT3 */\n+\t{ RCAR_GP_PIN(3,  4),    PU3, 14 },\t/* SD0_DAT2 */\n+\t{ RCAR_GP_PIN(3,  3),    PU3, 13 },\t/* SD0_DAT1 */\n+\t{ RCAR_GP_PIN(3,  2),    PU3, 12 },\t/* SD0_DAT0 */\n+\t{ RCAR_GP_PIN(3,  1),    PU3, 11 },\t/* SD0_CMD */\n+\t{ RCAR_GP_PIN(3,  0),    PU3, 10 },\t/* SD0_CLK */\n+\t{ PIN_A_NUMBER('T', 30), PU3,  9 },\t/* ASEBRK */\n+\t/* bit 8 n/a */\n+\t{ PIN_A_NUMBER('R', 29), PU3,  7 },\t/* TDI */\n+\t{ PIN_A_NUMBER('R', 30), PU3,  6 },\t/* TMS */\n+\t{ PIN_A_NUMBER('T', 27), PU3,  5 },\t/* TCK */\n+\t{ PIN_A_NUMBER('R', 26), PU3,  4 },\t/* TRST# */\n+\t{ PIN_A_NUMBER('D', 39), PU3,  3 },\t/* EXTALR*/\n+\t{ PIN_A_NUMBER('D', 38), PU3,  2 },\t/* FSCLKST# */\n+\t{ PIN_A_NUMBER('R', 8),  PU3,  1 },\t/* DU_DOTCLKIN3 */\n+\t{ PIN_A_NUMBER('R', 7),  PU3,  0 },\t/* DU_DOTCLKIN2 */\n+\n+\t{ RCAR_GP_PIN(5, 19),    PU4, 31 },\t/* MSIOF0_SS1 */\n+\t{ RCAR_GP_PIN(5, 18),    PU4, 30 },\t/* MSIOF0_SYNC */\n+\t{ RCAR_GP_PIN(5, 17),    PU4, 29 },\t/* MSIOF0_SCK */\n+\t{ RCAR_GP_PIN(5, 16),    PU4, 28 },\t/* HRTS0_N */\n+\t{ RCAR_GP_PIN(5, 15),    PU4, 27 },\t/* HCTS0_N */\n+\t{ RCAR_GP_PIN(5, 14),    PU4, 26 },\t/* HTX0 */\n+\t{ RCAR_GP_PIN(5, 13),    PU4, 25 },\t/* HRX0 */\n+\t{ RCAR_GP_PIN(5, 12),    PU4, 24 },\t/* HSCK0 */\n+\t{ RCAR_GP_PIN(5, 11),    PU4, 23 },\t/* RX2_A */\n+\t{ RCAR_GP_PIN(5, 10),    PU4, 22 },\t/* TX2_A */\n+\t{ RCAR_GP_PIN(5,  9),    PU4, 21 },\t/* SCK2 */\n+\t{ RCAR_GP_PIN(5,  8),    PU4, 20 },\t/* RTS1_N_TANS */\n+\t{ RCAR_GP_PIN(5,  7),    PU4, 19 },\t/* CTS1_N */\n+\t{ RCAR_GP_PIN(5,  6),    PU4, 18 },\t/* TX1_A */\n+\t{ RCAR_GP_PIN(5,  5),    PU4, 17 },\t/* RX1_A */\n+\t{ RCAR_GP_PIN(5,  4),    PU4, 16 },\t/* RTS0_N_TANS */\n+\t{ RCAR_GP_PIN(5,  3),    PU4, 15 },\t/* CTS0_N */\n+\t{ RCAR_GP_PIN(5,  2),    PU4, 14 },\t/* TX0 */\n+\t{ RCAR_GP_PIN(5,  1),    PU4, 13 },\t/* RX0 */\n+\t{ RCAR_GP_PIN(5,  0),    PU4, 12 },\t/* SCK0 */\n+\t{ RCAR_GP_PIN(3, 15),    PU4, 11 },\t/* SD1_WP */\n+\t{ RCAR_GP_PIN(3, 14),    PU4, 10 },\t/* SD1_CD */\n+\t{ RCAR_GP_PIN(3, 13),    PU4,  9 },\t/* SD0_WP */\n+\t{ RCAR_GP_PIN(3, 12),    PU4,  8 },\t/* SD0_CD */\n+\t{ RCAR_GP_PIN(4, 17),    PU4,  7 },\t/* SD3_DS */\n+\t{ RCAR_GP_PIN(4, 16),    PU4,  6 },\t/* SD3_DAT7 */\n+\t{ RCAR_GP_PIN(4, 15),    PU4,  5 },\t/* SD3_DAT6 */\n+\t{ RCAR_GP_PIN(4, 14),    PU4,  4 },\t/* SD3_DAT5 */\n+\t{ RCAR_GP_PIN(4, 13),    PU4,  3 },\t/* SD3_DAT4 */\n+\t{ RCAR_GP_PIN(4, 12),    PU4,  2 },\t/* SD3_DAT3 */\n+\t{ RCAR_GP_PIN(4, 11),    PU4,  1 },\t/* SD3_DAT2 */\n+\t{ RCAR_GP_PIN(4, 10),    PU4,  0 },\t/* SD3_DAT1 */\n+\n+\t{ RCAR_GP_PIN(6, 24),    PU5, 31 },\t/* USB0_PWEN */\n+\t{ RCAR_GP_PIN(6, 23),    PU5, 30 },\t/* AUDIO_CLKB_B */\n+\t{ RCAR_GP_PIN(6, 22),    PU5, 29 },\t/* AUDIO_CLKA_A */\n+\t{ RCAR_GP_PIN(6, 21),    PU5, 28 },\t/* SSI_SDATA9_A */\n+\t{ RCAR_GP_PIN(6, 20),    PU5, 27 },\t/* SSI_SDATA8 */\n+\t{ RCAR_GP_PIN(6, 19),    PU5, 26 },\t/* SSI_SDATA7 */\n+\t{ RCAR_GP_PIN(6, 18),    PU5, 25 },\t/* SSI_WS78 */\n+\t{ RCAR_GP_PIN(6, 17),    PU5, 24 },\t/* SSI_SCK78 */\n+\t{ RCAR_GP_PIN(6, 16),    PU5, 23 },\t/* SSI_SDATA6 */\n+\t{ RCAR_GP_PIN(6, 15),    PU5, 22 },\t/* SSI_WS6 */\n+\t{ RCAR_GP_PIN(6, 14),    PU5, 21 },\t/* SSI_SCK6 */\n+\t{ RCAR_GP_PIN(6, 13),    PU5, 20 },\t/* SSI_SDATA5 */\n+\t{ RCAR_GP_PIN(6, 12),    PU5, 19 },\t/* SSI_WS5 */\n+\t{ RCAR_GP_PIN(6, 11),    PU5, 18 },\t/* SSI_SCK5 */\n+\t{ RCAR_GP_PIN(6, 10),    PU5, 17 },\t/* SSI_SDATA4 */\n+\t{ RCAR_GP_PIN(6,  9),    PU5, 16 },\t/* SSI_WS4 */\n+\t{ RCAR_GP_PIN(6,  8),    PU5, 15 },\t/* SSI_SCK4 */\n+\t{ RCAR_GP_PIN(6,  7),    PU5, 14 },\t/* SSI_SDATA3 */\n+\t{ RCAR_GP_PIN(6,  6),    PU5, 13 },\t/* SSI_WS349 */\n+\t{ RCAR_GP_PIN(6,  5),    PU5, 12 },\t/* SSI_SCK349 */\n+\t{ RCAR_GP_PIN(6,  4),    PU5, 11 },\t/* SSI_SDATA2_A */\n+\t{ RCAR_GP_PIN(6,  3),    PU5, 10 },\t/* SSI_SDATA1_A */\n+\t{ RCAR_GP_PIN(6,  2),    PU5,  9 },\t/* SSI_SDATA0 */\n+\t{ RCAR_GP_PIN(6,  1),    PU5,  8 },\t/* SSI_WS01239 */\n+\t{ RCAR_GP_PIN(6,  0),    PU5,  7 },\t/* SSI_SCK01239 */\n+\t{ PIN_NUMBER('H', 37),   PU5,  6 },\t/* MLB_REF */\n+\t{ RCAR_GP_PIN(5, 25),    PU5,  5 },\t/* MLB_DAT */\n+\t{ RCAR_GP_PIN(5, 24),    PU5,  4 },\t/* MLB_SIG */\n+\t{ RCAR_GP_PIN(5, 23),    PU5,  3 },\t/* MLB_CLK */\n+\t{ RCAR_GP_PIN(5, 22),    PU5,  2 },\t/* MSIOF0_RXD */\n+\t{ RCAR_GP_PIN(5, 21),    PU5,  1 },\t/* MSIOF0_SS2 */\n+\t{ RCAR_GP_PIN(5, 20),    PU5,  0 },\t/* MSIOF0_TXD */\n+\n+\t{ RCAR_GP_PIN(6, 31),    PU6,  6 },\t/* USB2_CH3_OVC */\n+\t{ RCAR_GP_PIN(6, 30),    PU6,  5 },\t/* USB2_CH3_PWEN */\n+\t{ RCAR_GP_PIN(6, 29),    PU6,  4 },\t/* USB30_OVC */\n+\t{ RCAR_GP_PIN(6, 28),    PU6,  3 },\t/* USB30_PWEN */\n+\t{ RCAR_GP_PIN(6, 27),    PU6,  2 },\t/* USB1_OVC */\n+\t{ RCAR_GP_PIN(6, 26),    PU6,  1 },\t/* USB1_PWEN */\n+\t{ RCAR_GP_PIN(6, 25),    PU6,  0 },\t/* USB0_OVC */\n+};\n+\n+static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,\n+\t\t\t\t\t    unsigned int pin)\n+{\n+\tconst struct sh_pfc_bias_info *info;\n+\tu32 reg;\n+\tu32 bit;\n+\n+\tinfo = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);\n+\tif (!info)\n+\t\treturn PIN_CONFIG_BIAS_DISABLE;\n+\n+\treg = info->reg;\n+\tbit = BIT(info->bit);\n+\n+\tif (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))\n+\t\treturn PIN_CONFIG_BIAS_DISABLE;\n+\telse if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)\n+\t\treturn PIN_CONFIG_BIAS_PULL_UP;\n+\telse\n+\t\treturn PIN_CONFIG_BIAS_PULL_DOWN;\n+}\n+\n+static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,\n+\t\t\t\t   unsigned int bias)\n+{\n+\tconst struct sh_pfc_bias_info *info;\n+\tu32 enable, updown;\n+\tu32 reg;\n+\tu32 bit;\n+\n+\tinfo = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);\n+\tif (!info)\n+\t\treturn;\n+\n+\treg = info->reg;\n+\tbit = BIT(info->bit);\n+\n+\tenable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;\n+\tif (bias != PIN_CONFIG_BIAS_DISABLE)\n+\t\tenable |= bit;\n+\n+\tupdown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;\n+\tif (bias == PIN_CONFIG_BIAS_PULL_UP)\n+\t\tupdown |= bit;\n+\n+\tsh_pfc_write_reg(pfc, PUD + reg, 32, updown);\n+\tsh_pfc_write_reg(pfc, PUEN + reg, 32, enable);\n+}\n+\n+static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {\n+\t.pin_to_pocctrl = r8a7795_pin_to_pocctrl,\n+\t.get_bias = r8a7795_pinmux_get_bias,\n+\t.set_bias = r8a7795_pinmux_set_bias,\n+};\n+\n+const struct sh_pfc_soc_info r8a7795_pinmux_info = {\n+\t.name = \"r8a77951_pfc\",\n+\t.ops = &r8a7795_pinmux_ops,\n+\t.unlock_reg = 0xe6060000, /* PMMR */\n+\n+\t.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },\n+\n+\t.pins = pinmux_pins,\n+\t.nr_pins = ARRAY_SIZE(pinmux_pins),\n+\t.groups = pinmux_groups,\n+\t.nr_groups = ARRAY_SIZE(pinmux_groups),\n+\t.functions = pinmux_functions,\n+\t.nr_functions = ARRAY_SIZE(pinmux_functions),\n+\n+\t.cfg_regs = pinmux_config_regs,\n+\t.drive_regs = pinmux_drive_regs,\n+\n+\t.pinmux_data = pinmux_data,\n+\t.pinmux_data_size = ARRAY_SIZE(pinmux_data),\n+};\ndiff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c\nnew file mode 100644\nindex 0000000000..fa8150be0e\n--- /dev/null\n+++ b/drivers/pinctrl/renesas/pfc-r8a7796.c\n@@ -0,0 +1,5728 @@\n+/*\n+ * R8A7796 processor support - PFC hardware block.\n+ *\n+ * Copyright (C) 2016 Renesas Electronics Corp.\n+ *\n+ * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c\n+ *\n+ * R-Car Gen3 processor support - PFC hardware block.\n+ *\n+ * Copyright (C) 2015  Renesas Electronics Corporation\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#include <common.h>\n+#include <dm.h>\n+#include <errno.h>\n+#include <dm/pinctrl.h>\n+#include <linux/kernel.h>\n+\n+#include \"sh_pfc.h\"\n+\n+#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \\\n+\t\t   SH_PFC_PIN_CFG_PULL_UP | \\\n+\t\t   SH_PFC_PIN_CFG_PULL_DOWN)\n+\n+#define CPU_ALL_PORT(fn, sfx)\t\t\t\t\t\t\\\n+\tPORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),\t\\\n+\tPORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),\t\\\n+\tPORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),\t\\\n+\tPORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),\t\\\n+\tPORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),\t\\\n+\tPORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),\t\\\n+\tPORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),\t\\\n+\tPORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),\t\\\n+\tPORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),\t\\\n+\tPORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),\t\\\n+\tPORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),\t\\\n+\tPORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)\n+/*\n+ * F_() : just information\n+ * FM() : macro for FN_xxx / xxx_MARK\n+ */\n+\n+/* GPSR0 */\n+#define GPSR0_15\tF_(D15,\t\t\tIP7_11_8)\n+#define GPSR0_14\tF_(D14,\t\t\tIP7_7_4)\n+#define GPSR0_13\tF_(D13,\t\t\tIP7_3_0)\n+#define GPSR0_12\tF_(D12,\t\t\tIP6_31_28)\n+#define GPSR0_11\tF_(D11,\t\t\tIP6_27_24)\n+#define GPSR0_10\tF_(D10,\t\t\tIP6_23_20)\n+#define GPSR0_9\t\tF_(D9,\t\t\tIP6_19_16)\n+#define GPSR0_8\t\tF_(D8,\t\t\tIP6_15_12)\n+#define GPSR0_7\t\tF_(D7,\t\t\tIP6_11_8)\n+#define GPSR0_6\t\tF_(D6,\t\t\tIP6_7_4)\n+#define GPSR0_5\t\tF_(D5,\t\t\tIP6_3_0)\n+#define GPSR0_4\t\tF_(D4,\t\t\tIP5_31_28)\n+#define GPSR0_3\t\tF_(D3,\t\t\tIP5_27_24)\n+#define GPSR0_2\t\tF_(D2,\t\t\tIP5_23_20)\n+#define GPSR0_1\t\tF_(D1,\t\t\tIP5_19_16)\n+#define GPSR0_0\t\tF_(D0,\t\t\tIP5_15_12)\n+\n+/* GPSR1 */\n+#define GPSR1_28\tFM(CLKOUT)\n+#define GPSR1_27\tF_(EX_WAIT0_A,\t\tIP5_11_8)\n+#define GPSR1_26\tF_(WE1_N,\t\tIP5_7_4)\n+#define GPSR1_25\tF_(WE0_N,\t\tIP5_3_0)\n+#define GPSR1_24\tF_(RD_WR_N,\t\tIP4_31_28)\n+#define GPSR1_23\tF_(RD_N,\t\tIP4_27_24)\n+#define GPSR1_22\tF_(BS_N,\t\tIP4_23_20)\n+#define GPSR1_21\tF_(CS1_N,\t\tIP4_19_16)\n+#define GPSR1_20\tF_(CS0_N,\t\tIP4_15_12)\n+#define GPSR1_19\tF_(A19,\t\t\tIP4_11_8)\n+#define GPSR1_18\tF_(A18,\t\t\tIP4_7_4)\n+#define GPSR1_17\tF_(A17,\t\t\tIP4_3_0)\n+#define GPSR1_16\tF_(A16,\t\t\tIP3_31_28)\n+#define GPSR1_15\tF_(A15,\t\t\tIP3_27_24)\n+#define GPSR1_14\tF_(A14,\t\t\tIP3_23_20)\n+#define GPSR1_13\tF_(A13,\t\t\tIP3_19_16)\n+#define GPSR1_12\tF_(A12,\t\t\tIP3_15_12)\n+#define GPSR1_11\tF_(A11,\t\t\tIP3_11_8)\n+#define GPSR1_10\tF_(A10,\t\t\tIP3_7_4)\n+#define GPSR1_9\t\tF_(A9,\t\t\tIP3_3_0)\n+#define GPSR1_8\t\tF_(A8,\t\t\tIP2_31_28)\n+#define GPSR1_7\t\tF_(A7,\t\t\tIP2_27_24)\n+#define GPSR1_6\t\tF_(A6,\t\t\tIP2_23_20)\n+#define GPSR1_5\t\tF_(A5,\t\t\tIP2_19_16)\n+#define GPSR1_4\t\tF_(A4,\t\t\tIP2_15_12)\n+#define GPSR1_3\t\tF_(A3,\t\t\tIP2_11_8)\n+#define GPSR1_2\t\tF_(A2,\t\t\tIP2_7_4)\n+#define GPSR1_1\t\tF_(A1,\t\t\tIP2_3_0)\n+#define GPSR1_0\t\tF_(A0,\t\t\tIP1_31_28)\n+\n+/* GPSR2 */\n+#define GPSR2_14\tF_(AVB_AVTP_CAPTURE_A,\tIP0_23_20)\n+#define GPSR2_13\tF_(AVB_AVTP_MATCH_A,\tIP0_19_16)\n+#define GPSR2_12\tF_(AVB_LINK,\t\tIP0_15_12)\n+#define GPSR2_11\tF_(AVB_PHY_INT,\t\tIP0_11_8)\n+#define GPSR2_10\tF_(AVB_MAGIC,\t\tIP0_7_4)\n+#define GPSR2_9\t\tF_(AVB_MDC,\t\tIP0_3_0)\n+#define GPSR2_8\t\tF_(PWM2_A,\t\tIP1_27_24)\n+#define GPSR2_7\t\tF_(PWM1_A,\t\tIP1_23_20)\n+#define GPSR2_6\t\tF_(PWM0,\t\tIP1_19_16)\n+#define GPSR2_5\t\tF_(IRQ5,\t\tIP1_15_12)\n+#define GPSR2_4\t\tF_(IRQ4,\t\tIP1_11_8)\n+#define GPSR2_3\t\tF_(IRQ3,\t\tIP1_7_4)\n+#define GPSR2_2\t\tF_(IRQ2,\t\tIP1_3_0)\n+#define GPSR2_1\t\tF_(IRQ1,\t\tIP0_31_28)\n+#define GPSR2_0\t\tF_(IRQ0,\t\tIP0_27_24)\n+\n+/* GPSR3 */\n+#define GPSR3_15\tF_(SD1_WP,\t\tIP11_23_20)\n+#define GPSR3_14\tF_(SD1_CD,\t\tIP11_19_16)\n+#define GPSR3_13\tF_(SD0_WP,\t\tIP11_15_12)\n+#define GPSR3_12\tF_(SD0_CD,\t\tIP11_11_8)\n+#define GPSR3_11\tF_(SD1_DAT3,\t\tIP8_31_28)\n+#define GPSR3_10\tF_(SD1_DAT2,\t\tIP8_27_24)\n+#define GPSR3_9\t\tF_(SD1_DAT1,\t\tIP8_23_20)\n+#define GPSR3_8\t\tF_(SD1_DAT0,\t\tIP8_19_16)\n+#define GPSR3_7\t\tF_(SD1_CMD,\t\tIP8_15_12)\n+#define GPSR3_6\t\tF_(SD1_CLK,\t\tIP8_11_8)\n+#define GPSR3_5\t\tF_(SD0_DAT3,\t\tIP8_7_4)\n+#define GPSR3_4\t\tF_(SD0_DAT2,\t\tIP8_3_0)\n+#define GPSR3_3\t\tF_(SD0_DAT1,\t\tIP7_31_28)\n+#define GPSR3_2\t\tF_(SD0_DAT0,\t\tIP7_27_24)\n+#define GPSR3_1\t\tF_(SD0_CMD,\t\tIP7_23_20)\n+#define GPSR3_0\t\tF_(SD0_CLK,\t\tIP7_19_16)\n+\n+/* GPSR4 */\n+#define GPSR4_17\tF_(SD3_DS,\t\tIP11_7_4)\n+#define GPSR4_16\tF_(SD3_DAT7,\t\tIP11_3_0)\n+#define GPSR4_15\tF_(SD3_DAT6,\t\tIP10_31_28)\n+#define GPSR4_14\tF_(SD3_DAT5,\t\tIP10_27_24)\n+#define GPSR4_13\tF_(SD3_DAT4,\t\tIP10_23_20)\n+#define GPSR4_12\tF_(SD3_DAT3,\t\tIP10_19_16)\n+#define GPSR4_11\tF_(SD3_DAT2,\t\tIP10_15_12)\n+#define GPSR4_10\tF_(SD3_DAT1,\t\tIP10_11_8)\n+#define GPSR4_9\t\tF_(SD3_DAT0,\t\tIP10_7_4)\n+#define GPSR4_8\t\tF_(SD3_CMD,\t\tIP10_3_0)\n+#define GPSR4_7\t\tF_(SD3_CLK,\t\tIP9_31_28)\n+#define GPSR4_6\t\tF_(SD2_DS,\t\tIP9_27_24)\n+#define GPSR4_5\t\tF_(SD2_DAT3,\t\tIP9_23_20)\n+#define GPSR4_4\t\tF_(SD2_DAT2,\t\tIP9_19_16)\n+#define GPSR4_3\t\tF_(SD2_DAT1,\t\tIP9_15_12)\n+#define GPSR4_2\t\tF_(SD2_DAT0,\t\tIP9_11_8)\n+#define GPSR4_1\t\tF_(SD2_CMD,\t\tIP9_7_4)\n+#define GPSR4_0\t\tF_(SD2_CLK,\t\tIP9_3_0)\n+\n+/* GPSR5 */\n+#define GPSR5_25\tF_(MLB_DAT,\t\tIP14_19_16)\n+#define GPSR5_24\tF_(MLB_SIG,\t\tIP14_15_12)\n+#define GPSR5_23\tF_(MLB_CLK,\t\tIP14_11_8)\n+#define GPSR5_22\tFM(MSIOF0_RXD)\n+#define GPSR5_21\tF_(MSIOF0_SS2,\t\tIP14_7_4)\n+#define GPSR5_20\tFM(MSIOF0_TXD)\n+#define GPSR5_19\tF_(MSIOF0_SS1,\t\tIP14_3_0)\n+#define GPSR5_18\tF_(MSIOF0_SYNC,\t\tIP13_31_28)\n+#define GPSR5_17\tFM(MSIOF0_SCK)\n+#define GPSR5_16\tF_(HRTS0_N,\t\tIP13_27_24)\n+#define GPSR5_15\tF_(HCTS0_N,\t\tIP13_23_20)\n+#define GPSR5_14\tF_(HTX0,\t\tIP13_19_16)\n+#define GPSR5_13\tF_(HRX0,\t\tIP13_15_12)\n+#define GPSR5_12\tF_(HSCK0,\t\tIP13_11_8)\n+#define GPSR5_11\tF_(RX2_A,\t\tIP13_7_4)\n+#define GPSR5_10\tF_(TX2_A,\t\tIP13_3_0)\n+#define GPSR5_9\t\tF_(SCK2,\t\tIP12_31_28)\n+#define GPSR5_8\t\tF_(RTS1_N_TANS,\t\tIP12_27_24)\n+#define GPSR5_7\t\tF_(CTS1_N,\t\tIP12_23_20)\n+#define GPSR5_6\t\tF_(TX1_A,\t\tIP12_19_16)\n+#define GPSR5_5\t\tF_(RX1_A,\t\tIP12_15_12)\n+#define GPSR5_4\t\tF_(RTS0_N_TANS,\t\tIP12_11_8)\n+#define GPSR5_3\t\tF_(CTS0_N,\t\tIP12_7_4)\n+#define GPSR5_2\t\tF_(TX0,\t\t\tIP12_3_0)\n+#define GPSR5_1\t\tF_(RX0,\t\t\tIP11_31_28)\n+#define GPSR5_0\t\tF_(SCK0,\t\tIP11_27_24)\n+\n+/* GPSR6 */\n+#define GPSR6_31\tF_(GP6_31,\t\tIP18_7_4)\n+#define GPSR6_30\tF_(GP6_30,\t\tIP18_3_0)\n+#define GPSR6_29\tF_(USB30_OVC,\t\tIP17_31_28)\n+#define GPSR6_28\tF_(USB30_PWEN,\t\tIP17_27_24)\n+#define GPSR6_27\tF_(USB1_OVC,\t\tIP17_23_20)\n+#define GPSR6_26\tF_(USB1_PWEN,\t\tIP17_19_16)\n+#define GPSR6_25\tF_(USB0_OVC,\t\tIP17_15_12)\n+#define GPSR6_24\tF_(USB0_PWEN,\t\tIP17_11_8)\n+#define GPSR6_23\tF_(AUDIO_CLKB_B,\tIP17_7_4)\n+#define GPSR6_22\tF_(AUDIO_CLKA_A,\tIP17_3_0)\n+#define GPSR6_21\tF_(SSI_SDATA9_A,\tIP16_31_28)\n+#define GPSR6_20\tF_(SSI_SDATA8,\t\tIP16_27_24)\n+#define GPSR6_19\tF_(SSI_SDATA7,\t\tIP16_23_20)\n+#define GPSR6_18\tF_(SSI_WS78,\t\tIP16_19_16)\n+#define GPSR6_17\tF_(SSI_SCK78,\t\tIP16_15_12)\n+#define GPSR6_16\tF_(SSI_SDATA6,\t\tIP16_11_8)\n+#define GPSR6_15\tF_(SSI_WS6,\t\tIP16_7_4)\n+#define GPSR6_14\tF_(SSI_SCK6,\t\tIP16_3_0)\n+#define GPSR6_13\tFM(SSI_SDATA5)\n+#define GPSR6_12\tFM(SSI_WS5)\n+#define GPSR6_11\tFM(SSI_SCK5)\n+#define GPSR6_10\tF_(SSI_SDATA4,\t\tIP15_31_28)\n+#define GPSR6_9\t\tF_(SSI_WS4,\t\tIP15_27_24)\n+#define GPSR6_8\t\tF_(SSI_SCK4,\t\tIP15_23_20)\n+#define GPSR6_7\t\tF_(SSI_SDATA3,\t\tIP15_19_16)\n+#define GPSR6_6\t\tF_(SSI_WS349,\t\tIP15_15_12)\n+#define GPSR6_5\t\tF_(SSI_SCK349,\t\tIP15_11_8)\n+#define GPSR6_4\t\tF_(SSI_SDATA2_A,\tIP15_7_4)\n+#define GPSR6_3\t\tF_(SSI_SDATA1_A,\tIP15_3_0)\n+#define GPSR6_2\t\tF_(SSI_SDATA0,\t\tIP14_31_28)\n+#define GPSR6_1\t\tF_(SSI_WS01239,\t\tIP14_27_24)\n+#define GPSR6_0\t\tF_(SSI_SCK01239,\tIP14_23_20)\n+\n+/* GPSR7 */\n+#define GPSR7_3\t\tFM(GP7_03)\n+#define GPSR7_2\t\tFM(HDMI0_CEC)\n+#define GPSR7_1\t\tFM(AVS2)\n+#define GPSR7_0\t\tFM(AVS1)\n+\n+\n+/* IPSRx */\t\t/* 0 */\t\t\t/* 1 */\t\t/* 2 */\t\t\t/* 3 */\t\t\t\t/* 4 */\t\t/* 5 */\t\t/* 6 */\t\t\t/* 7 */\t\t/* 8 */\t\t\t/* 9 */\t\t/* A */\t\t/* B */\t\t/* C - F */\n+#define IP0_3_0\t\tFM(AVB_MDC)\t\tF_(0, 0)\tFM(MSIOF2_SS2_C)\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP0_7_4\t\tFM(AVB_MAGIC)\t\tF_(0, 0)\tFM(MSIOF2_SS1_C)\tFM(SCK4_A)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP0_11_8\tFM(AVB_PHY_INT)\t\tF_(0, 0)\tFM(MSIOF2_SYNC_C)\tFM(RX4_A)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP0_15_12\tFM(AVB_LINK)\t\tF_(0, 0)\tFM(MSIOF2_SCK_C)\tFM(TX4_A)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP0_19_16\tFM(AVB_AVTP_MATCH_A)\tF_(0, 0)\tFM(MSIOF2_RXD_C)\tFM(CTS4_N_A)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP0_23_20\tFM(AVB_AVTP_CAPTURE_A)\tF_(0, 0)\tFM(MSIOF2_TXD_C)\tFM(RTS4_N_TANS_A)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP0_27_24\tFM(IRQ0)\t\tFM(QPOLB)\tF_(0, 0)\t\tFM(DU_CDE)\t\t\tFM(VI4_DATA0_B) FM(CAN0_TX_B)\tFM(CANFD0_TX_B)\t\tFM(MSIOF3_SS2_E) F_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP0_31_28\tFM(IRQ1)\t\tFM(QPOLA)\tF_(0, 0)\t\tFM(DU_DISP)\t\t\tFM(VI4_DATA1_B) FM(CAN0_RX_B)\tFM(CANFD0_RX_B)\t\tFM(MSIOF3_SS1_E) F_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP1_3_0\t\tFM(IRQ2)\t\tFM(QCPV_QDE)\tF_(0, 0)\t\tFM(DU_EXODDF_DU_ODDF_DISP_CDE)\tFM(VI4_DATA2_B) F_(0, 0)\tF_(0, 0)\t\tFM(MSIOF3_SYNC_E) F_(0, 0)\t\tFM(PWM3_B)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP1_7_4\t\tFM(IRQ3)\t\tFM(QSTVB_QVE)\tFM(A25)\t\t\tFM(DU_DOTCLKOUT1)\t\tFM(VI4_DATA3_B) F_(0, 0)\tF_(0, 0)\t\tFM(MSIOF3_SCK_E) F_(0, 0)\t\tFM(PWM4_B)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP1_11_8\tFM(IRQ4)\t\tFM(QSTH_QHS)\tFM(A24)\t\t\tFM(DU_EXHSYNC_DU_HSYNC)\t\tFM(VI4_DATA4_B) F_(0, 0)\tF_(0, 0)\t\tFM(MSIOF3_RXD_E) F_(0, 0)\t\tFM(PWM5_B)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP1_15_12\tFM(IRQ5)\t\tFM(QSTB_QHE)\tFM(A23)\t\t\tFM(DU_EXVSYNC_DU_VSYNC)\t\tFM(VI4_DATA5_B) F_(0, 0)\tF_(0, 0)\t\tFM(MSIOF3_TXD_E) F_(0, 0)\t\tFM(PWM6_B)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP1_19_16\tFM(PWM0)\t\tFM(AVB_AVTP_PPS)FM(A22)\t\t\tF_(0, 0)\t\t\tFM(VI4_DATA6_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(IECLK_B)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP1_23_20\tFM(PWM1_A)\t\tF_(0, 0)\tFM(A21)\t\t\tFM(HRX3_D)\t\t\tFM(VI4_DATA7_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(IERX_B)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP1_27_24\tFM(PWM2_A)\t\tF_(0, 0)\tFM(A20)\t\t\tFM(HTX3_D)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(IETX_B)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP1_31_28\tFM(A0)\t\t\tFM(LCDOUT16)\tFM(MSIOF3_SYNC_B)\tF_(0, 0)\t\t\tFM(VI4_DATA8)\tF_(0, 0)\tFM(DU_DB0)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(PWM3_A)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP2_3_0\t\tFM(A1)\t\t\tFM(LCDOUT17)\tFM(MSIOF3_TXD_B)\tF_(0, 0)\t\t\tFM(VI4_DATA9)\tF_(0, 0)\tFM(DU_DB1)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(PWM4_A)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP2_7_4\t\tFM(A2)\t\t\tFM(LCDOUT18)\tFM(MSIOF3_SCK_B)\tF_(0, 0)\t\t\tFM(VI4_DATA10)\tF_(0, 0)\tFM(DU_DB2)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(PWM5_A)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP2_11_8\tFM(A3)\t\t\tFM(LCDOUT19)\tFM(MSIOF3_RXD_B)\tF_(0, 0)\t\t\tFM(VI4_DATA11)\tF_(0, 0)\tFM(DU_DB3)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(PWM6_A)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP2_15_12\tFM(A4)\t\t\tFM(LCDOUT20)\tFM(MSIOF3_SS1_B)\tF_(0, 0)\t\t\tFM(VI4_DATA12)\tFM(VI5_DATA12)\tFM(DU_DB4)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP2_19_16\tFM(A5)\t\t\tFM(LCDOUT21)\tFM(MSIOF3_SS2_B)\tFM(SCK4_B)\t\t\tFM(VI4_DATA13)\tFM(VI5_DATA13)\tFM(DU_DB5)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP2_23_20\tFM(A6)\t\t\tFM(LCDOUT22)\tFM(MSIOF2_SS1_A)\tFM(RX4_B)\t\t\tFM(VI4_DATA14)\tFM(VI5_DATA14)\tFM(DU_DB6)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP2_27_24\tFM(A7)\t\t\tFM(LCDOUT23)\tFM(MSIOF2_SS2_A)\tFM(TX4_B)\t\t\tFM(VI4_DATA15)\tFM(VI5_DATA15)\tFM(DU_DB7)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP2_31_28\tFM(A8)\t\t\tFM(RX3_B)\tFM(MSIOF2_SYNC_A)\tFM(HRX4_B)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tFM(SDA6_A)\tFM(AVB_AVTP_MATCH_B)\tFM(PWM1_B)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP3_3_0\t\tFM(A9)\t\t\tF_(0, 0)\tFM(MSIOF2_SCK_A)\tFM(CTS4_N_B)\t\t\tF_(0, 0)\tFM(VI5_VSYNC_N)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP3_7_4\t\tFM(A10)\t\t\tF_(0, 0)\tFM(MSIOF2_RXD_A)\tFM(RTS4_N_TANS_B)\t\tF_(0, 0)\tFM(VI5_HSYNC_N)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP3_11_8\tFM(A11)\t\t\tFM(TX3_B)\tFM(MSIOF2_TXD_A)\tFM(HTX4_B)\t\t\tFM(HSCK4)\tFM(VI5_FIELD)\tF_(0, 0)\t\tFM(SCL6_A)\tFM(AVB_AVTP_CAPTURE_B)\tFM(PWM2_B)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+\n+/* IPSRx */\t\t/* 0 */\t\t\t/* 1 */\t\t/* 2 */\t\t\t/* 3 */\t\t\t\t/* 4 */\t\t/* 5 */\t\t/* 6 */\t\t\t/* 7 */\t\t/* 8 */\t\t\t/* 9 */\t\t/* A */\t\t/* B */\t\t/* C - F */\n+#define IP3_15_12\tFM(A12)\t\t\tFM(LCDOUT12)\tFM(MSIOF3_SCK_C)\tF_(0, 0)\t\t\tFM(HRX4_A)\tFM(VI5_DATA8)\tFM(DU_DG4)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP3_19_16\tFM(A13)\t\t\tFM(LCDOUT13)\tFM(MSIOF3_SYNC_C)\tF_(0, 0)\t\t\tFM(HTX4_A)\tFM(VI5_DATA9)\tFM(DU_DG5)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP3_23_20\tFM(A14)\t\t\tFM(LCDOUT14)\tFM(MSIOF3_RXD_C)\tF_(0, 0)\t\t\tFM(HCTS4_N)\tFM(VI5_DATA10)\tFM(DU_DG6)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP3_27_24\tFM(A15)\t\t\tFM(LCDOUT15)\tFM(MSIOF3_TXD_C)\tF_(0, 0)\t\t\tFM(HRTS4_N)\tFM(VI5_DATA11)\tFM(DU_DG7)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP3_31_28\tFM(A16)\t\t\tFM(LCDOUT8)\tF_(0, 0)\t\tF_(0, 0)\t\t\tFM(VI4_FIELD)\tF_(0, 0)\tFM(DU_DG0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP4_3_0\t\tFM(A17)\t\t\tFM(LCDOUT9)\tF_(0, 0)\t\tF_(0, 0)\t\t\tFM(VI4_VSYNC_N)\tF_(0, 0)\tFM(DU_DG1)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP4_7_4\t\tFM(A18)\t\t\tFM(LCDOUT10)\tF_(0, 0)\t\tF_(0, 0)\t\t\tFM(VI4_HSYNC_N)\tF_(0, 0)\tFM(DU_DG2)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP4_11_8\tFM(A19)\t\t\tFM(LCDOUT11)\tF_(0, 0)\t\tF_(0, 0)\t\t\tFM(VI4_CLKENB)\tF_(0, 0)\tFM(DU_DG3)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP4_15_12\tFM(CS0_N)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tFM(VI5_CLKENB)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP4_19_16\tFM(CS1_N)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tFM(VI5_CLK)\tF_(0, 0)\t\tFM(EX_WAIT0_B)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP4_23_20\tFM(BS_N)\t\tFM(QSTVA_QVS)\tFM(MSIOF3_SCK_D)\tFM(SCK3)\t\t\tFM(HSCK3)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tFM(CAN1_TX)\t\tFM(CANFD1_TX)\tFM(IETX_A)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP4_27_24\tFM(RD_N)\t\tF_(0, 0)\tFM(MSIOF3_SYNC_D)\tFM(RX3_A)\t\t\tFM(HRX3_A)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tFM(CAN0_TX_A)\t\tFM(CANFD0_TX_A)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP4_31_28\tFM(RD_WR_N)\t\tF_(0, 0)\tFM(MSIOF3_RXD_D)\tFM(TX3_A)\t\t\tFM(HTX3_A)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tFM(CAN0_RX_A)\t\tFM(CANFD0_RX_A)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP5_3_0\t\tFM(WE0_N)\t\tF_(0, 0)\tFM(MSIOF3_TXD_D)\tFM(CTS3_N)\t\t\tFM(HCTS3_N)\tF_(0, 0)\tF_(0, 0)\t\tFM(SCL6_B)\tFM(CAN_CLK)\t\tF_(0, 0)\tFM(IECLK_A)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP5_7_4\t\tFM(WE1_N)\t\tF_(0, 0)\tFM(MSIOF3_SS1_D)\tFM(RTS3_N_TANS)\t\t\tFM(HRTS3_N)\tF_(0, 0)\tF_(0, 0)\t\tFM(SDA6_B)\tFM(CAN1_RX)\t\tFM(CANFD1_RX)\tFM(IERX_A)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP5_11_8\tFM(EX_WAIT0_A)\t\tFM(QCLK)\tF_(0, 0)\t\tF_(0, 0)\t\t\tFM(VI4_CLK)\tF_(0, 0)\tFM(DU_DOTCLKOUT0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP5_15_12\tFM(D0)\t\t\tFM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)\tF_(0, 0)\t\t\tFM(VI4_DATA16)\tFM(VI5_DATA0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP5_19_16\tFM(D1)\t\t\tFM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)\tF_(0, 0)\t\t\tFM(VI4_DATA17)\tFM(VI5_DATA1)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP5_23_20\tFM(D2)\t\t\tF_(0, 0)\tFM(MSIOF3_RXD_A)\tF_(0, 0)\t\t\tFM(VI4_DATA18)\tFM(VI5_DATA2)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP5_27_24\tFM(D3)\t\t\tF_(0, 0)\tFM(MSIOF3_TXD_A)\tF_(0, 0)\t\t\tFM(VI4_DATA19)\tFM(VI5_DATA3)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP5_31_28\tFM(D4)\t\t\tFM(MSIOF2_SCK_B)F_(0, 0)\t\tF_(0, 0)\t\t\tFM(VI4_DATA20)\tFM(VI5_DATA4)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP6_3_0\t\tFM(D5)\t\t\tFM(MSIOF2_SYNC_B)F_(0, 0)\t\tF_(0, 0)\t\t\tFM(VI4_DATA21)\tFM(VI5_DATA5)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP6_7_4\t\tFM(D6)\t\t\tFM(MSIOF2_RXD_B)F_(0, 0)\t\tF_(0, 0)\t\t\tFM(VI4_DATA22)\tFM(VI5_DATA6)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP6_11_8\tFM(D7)\t\t\tFM(MSIOF2_TXD_B)F_(0, 0)\t\tF_(0, 0)\t\t\tFM(VI4_DATA23)\tFM(VI5_DATA7)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP6_15_12\tFM(D8)\t\t\tFM(LCDOUT0)\tFM(MSIOF2_SCK_D)\tFM(SCK4_C)\t\t\tFM(VI4_DATA0_A)\tF_(0, 0)\tFM(DU_DR0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP6_19_16\tFM(D9)\t\t\tFM(LCDOUT1)\tFM(MSIOF2_SYNC_D)\tF_(0, 0)\t\t\tFM(VI4_DATA1_A)\tF_(0, 0)\tFM(DU_DR1)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP6_23_20\tFM(D10)\t\t\tFM(LCDOUT2)\tFM(MSIOF2_RXD_D)\tFM(HRX3_B)\t\t\tFM(VI4_DATA2_A)\tFM(CTS4_N_C)\tFM(DU_DR2)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP6_27_24\tFM(D11)\t\t\tFM(LCDOUT3)\tFM(MSIOF2_TXD_D)\tFM(HTX3_B)\t\t\tFM(VI4_DATA3_A)\tFM(RTS4_N_TANS_C)FM(DU_DR3)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP6_31_28\tFM(D12)\t\t\tFM(LCDOUT4)\tFM(MSIOF2_SS1_D)\tFM(RX4_C)\t\t\tFM(VI4_DATA4_A)\tF_(0, 0)\tFM(DU_DR4)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+\n+/* IPSRx */\t\t/* 0 */\t\t\t/* 1 */\t\t/* 2 */\t\t\t/* 3 */\t\t\t\t/* 4 */\t\t/* 5 */\t\t/* 6 */\t\t\t/* 7 */\t\t/* 8 */\t\t\t/* 9 */\t\t/* A */\t\t/* B */\t\t/* C - F */\n+#define IP7_3_0\t\tFM(D13)\t\t\tFM(LCDOUT5)\tFM(MSIOF2_SS2_D)\tFM(TX4_C)\t\t\tFM(VI4_DATA5_A)\tF_(0, 0)\tFM(DU_DR5)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP7_7_4\t\tFM(D14)\t\t\tFM(LCDOUT6)\tFM(MSIOF3_SS1_A)\tFM(HRX3_C)\t\t\tFM(VI4_DATA6_A)\tF_(0, 0)\tFM(DU_DR6)\t\tFM(SCL6_C)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP7_11_8\tFM(D15)\t\t\tFM(LCDOUT7)\tFM(MSIOF3_SS2_A)\tFM(HTX3_C)\t\t\tFM(VI4_DATA7_A)\tF_(0, 0)\tFM(DU_DR7)\t\tFM(SDA6_C)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP7_19_16\tFM(SD0_CLK)\t\tF_(0, 0)\tFM(MSIOF1_SCK_E)\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tFM(STP_OPWM_0_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP7_23_20\tFM(SD0_CMD)\t\tF_(0, 0)\tFM(MSIOF1_SYNC_E)\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tFM(STP_IVCXO27_0_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP7_27_24\tFM(SD0_DAT0)\t\tF_(0, 0)\tFM(MSIOF1_RXD_E)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SCK0_B)\tFM(STP_ISCLK_0_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP7_31_28\tFM(SD0_DAT1)\t\tF_(0, 0)\tFM(MSIOF1_TXD_E)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP8_3_0\t\tFM(SD0_DAT2)\t\tF_(0, 0)\tFM(MSIOF1_SS1_E)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDAT0_B)\tFM(STP_ISD_0_B)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP8_7_4\t\tFM(SD0_DAT3)\t\tF_(0, 0)\tFM(MSIOF1_SS2_E)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDEN0_B)\tFM(STP_ISEN_0_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP8_11_8\tFM(SD1_CLK)\t\tF_(0, 0)\tFM(MSIOF1_SCK_G)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(SIM0_CLK_A)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP8_15_12\tFM(SD1_CMD)\t\tF_(0, 0)\tFM(MSIOF1_SYNC_G)\tFM(NFCE_N_B)\t\t\tF_(0, 0)\tFM(SIM0_D_A)\tFM(STP_IVCXO27_1_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP8_19_16\tFM(SD1_DAT0)\t\tFM(SD2_DAT4)\tFM(MSIOF1_RXD_G)\tFM(NFWP_N_B)\t\t\tF_(0, 0)\tFM(TS_SCK1_B)\tFM(STP_ISCLK_1_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP8_23_20\tFM(SD1_DAT1)\t\tFM(SD2_DAT5)\tFM(MSIOF1_TXD_G)\tFM(NFDATA14_B)\t\t\tF_(0, 0)\tFM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP8_27_24\tFM(SD1_DAT2)\t\tFM(SD2_DAT6)\tFM(MSIOF1_SS1_G)\tFM(NFDATA15_B)\t\t\tF_(0, 0)\tFM(TS_SDAT1_B)\tFM(STP_ISD_1_B)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP8_31_28\tFM(SD1_DAT3)\t\tFM(SD2_DAT7)\tFM(MSIOF1_SS2_G)\tFM(NFRB_N_B)\t\t\tF_(0, 0)\tFM(TS_SDEN1_B)\tFM(STP_ISEN_1_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP9_3_0\t\tFM(SD2_CLK)\t\tF_(0, 0)\tFM(NFDATA8)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP9_7_4\t\tFM(SD2_CMD)\t\tF_(0, 0)\tFM(NFDATA9)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP9_11_8\tFM(SD2_DAT0)\t\tF_(0, 0)\tFM(NFDATA10)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP9_15_12\tFM(SD2_DAT1)\t\tF_(0, 0)\tFM(NFDATA11)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP9_19_16\tFM(SD2_DAT2)\t\tF_(0, 0)\tFM(NFDATA12)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP9_23_20\tFM(SD2_DAT3)\t\tF_(0, 0)\tFM(NFDATA13)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP9_27_24\tFM(SD2_DS)\t\tF_(0, 0)\tFM(NFALE)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP9_31_28\tFM(SD3_CLK)\t\tF_(0, 0)\tFM(NFWE_N)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP10_3_0\tFM(SD3_CMD)\t\tF_(0, 0)\tFM(NFRE_N)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP10_7_4\tFM(SD3_DAT0)\t\tF_(0, 0)\tFM(NFDATA0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP10_11_8\tFM(SD3_DAT1)\t\tF_(0, 0)\tFM(NFDATA1)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP10_15_12\tFM(SD3_DAT2)\t\tF_(0, 0)\tFM(NFDATA2)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP10_19_16\tFM(SD3_DAT3)\t\tF_(0, 0)\tFM(NFDATA3)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP10_23_20\tFM(SD3_DAT4)\t\tFM(SD2_CD_A)\tFM(NFDATA4)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP10_27_24\tFM(SD3_DAT5)\t\tFM(SD2_WP_A)\tFM(NFDATA5)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP10_31_28\tFM(SD3_DAT6)\t\tFM(SD3_CD)\tFM(NFDATA6)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP11_3_0\tFM(SD3_DAT7)\t\tFM(SD3_WP)\tFM(NFDATA7)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP11_7_4\tFM(SD3_DS)\t\tF_(0, 0)\tFM(NFCLE)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP11_11_8\tFM(SD0_CD)\t\tF_(0, 0)\tFM(NFDATA14_A)\t\tF_(0, 0)\t\t\tFM(SCL2_B)\tFM(SIM0_RST_A)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+\n+/* IPSRx */\t\t/* 0 */\t\t\t/* 1 */\t\t/* 2 */\t\t\t/* 3 */\t\t\t\t/* 4 */\t\t/* 5 */\t\t/* 6 */\t\t\t/* 7 */\t\t/* 8 */\t\t\t/* 9 */\t\t/* A */\t\t/* B */\t\t/* C - F */\n+#define IP11_15_12\tFM(SD0_WP)\t\tF_(0, 0)\tFM(NFDATA15_A)\t\tF_(0, 0)\t\t\tFM(SDA2_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP11_19_16\tFM(SD1_CD)\t\tF_(0, 0)\tFM(NFRB_N_A)\t\tF_(0, 0)\t\t\tF_(0, 0)\tFM(SIM0_CLK_B)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP11_23_20\tFM(SD1_WP)\t\tF_(0, 0)\tFM(NFCE_N_A)\t\tF_(0, 0)\t\t\tF_(0, 0)\tFM(SIM0_D_B)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP11_27_24\tFM(SCK0)\t\tFM(HSCK1_B)\tFM(MSIOF1_SS2_B)\tFM(AUDIO_CLKC_B)\t\tFM(SDA2_A)\tFM(SIM0_RST_B)\tFM(STP_OPWM_0_C)\tFM(RIF0_CLK_B)\tF_(0, 0)\t\tFM(ADICHS2)\tFM(SCK5_B)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP11_31_28\tFM(RX0)\t\t\tFM(HRX1_B)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SCK0_C)\tFM(STP_ISCLK_0_C)\tFM(RIF0_D0_B)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP12_3_0\tFM(TX0)\t\t\tFM(HTX1_B)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)\tFM(RIF0_D1_B)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP12_7_4\tFM(CTS0_N)\t\tFM(HCTS1_N_B)\tFM(MSIOF1_SYNC_B)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)\tFM(RIF1_SYNC_B)\tFM(AUDIO_CLKOUT_C)\tFM(ADICS_SAMP)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP12_11_8\tFM(RTS0_N_TANS)\t\tFM(HRTS1_N_B)\tFM(MSIOF1_SS1_B)\tFM(AUDIO_CLKA_B)\t\tFM(SCL2_A)\tF_(0, 0)\tFM(STP_IVCXO27_1_C)\tFM(RIF0_SYNC_B)\tF_(0, 0)\t\tFM(ADICHS1)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP12_15_12\tFM(RX1_A)\t\tFM(HRX1_A)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDAT0_C)\tFM(STP_ISD_0_C)\t\tFM(RIF1_CLK_C)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP12_19_16\tFM(TX1_A)\t\tFM(HTX1_A)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDEN0_C)\tFM(STP_ISEN_0_C)\tFM(RIF1_D0_C)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP12_23_20\tFM(CTS1_N)\t\tFM(HCTS1_N_A)\tFM(MSIOF1_RXD_B)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDEN1_C)\tFM(STP_ISEN_1_C)\tFM(RIF1_D0_B)\tF_(0, 0)\t\tFM(ADIDATA)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP12_27_24\tFM(RTS1_N_TANS)\t\tFM(HRTS1_N_A)\tFM(MSIOF1_TXD_B)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDAT1_C)\tFM(STP_ISD_1_C)\t\tFM(RIF1_D1_B)\tF_(0, 0)\t\tFM(ADICHS0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP12_31_28\tFM(SCK2)\t\tFM(SCIF_CLK_B)\tFM(MSIOF1_SCK_B)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SCK1_C)\tFM(STP_ISCLK_1_C)\tFM(RIF1_CLK_B)\tF_(0, 0)\t\tFM(ADICLK)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP13_3_0\tFM(TX2_A)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(SD2_CD_B)\t\t\tFM(SCL1_A)\tF_(0, 0)\tFM(FMCLK_A)\t\tFM(RIF1_D1_C)\tF_(0, 0)\t\tFM(FSO_CFE_0_N)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP13_7_4\tFM(RX2_A)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(SD2_WP_B)\t\t\tFM(SDA1_A)\tF_(0, 0)\tFM(FMIN_A)\t\tFM(RIF1_SYNC_C)\tF_(0, 0)\t\tFM(FSO_CFE_1_N)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP13_11_8\tFM(HSCK0)\t\tF_(0, 0)\tFM(MSIOF1_SCK_D)\tFM(AUDIO_CLKB_A)\t\tFM(SSI_SDATA1_B)FM(TS_SCK0_D)\tFM(STP_ISCLK_0_D)\tFM(RIF0_CLK_C)\tF_(0, 0)\t\tF_(0, 0)\tFM(RX5_B)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP13_15_12\tFM(HRX0)\t\tF_(0, 0)\tFM(MSIOF1_RXD_D)\tF_(0, 0)\t\t\tFM(SSI_SDATA2_B)FM(TS_SDEN0_D)\tFM(STP_ISEN_0_D)\tFM(RIF0_D0_C)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP13_19_16\tFM(HTX0)\t\tF_(0, 0)\tFM(MSIOF1_TXD_D)\tF_(0, 0)\t\t\tFM(SSI_SDATA9_B)FM(TS_SDAT0_D)\tFM(STP_ISD_0_D)\t\tFM(RIF0_D1_C)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP13_23_20\tFM(HCTS0_N)\t\tFM(RX2_B)\tFM(MSIOF1_SYNC_D)\tF_(0, 0)\t\t\tFM(SSI_SCK9_A)\tFM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)\tFM(RIF0_SYNC_C)\tFM(AUDIO_CLKOUT1_A)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP13_27_24\tFM(HRTS0_N)\t\tFM(TX2_B)\tFM(MSIOF1_SS1_D)\tF_(0, 0)\t\t\tFM(SSI_WS9_A)\tF_(0, 0)\tFM(STP_IVCXO27_0_D)\tFM(BPFCLK_A)\tFM(AUDIO_CLKOUT2_A)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP13_31_28\tFM(MSIOF0_SYNC)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tFM(AUDIO_CLKOUT_A)\tF_(0, 0)\tFM(TX5_B)\tF_(0, 0)\tF_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)\n+#define IP14_3_0\tFM(MSIOF0_SS1)\t\tFM(RX5_A)\tFM(NFWP_N_A)\t\tFM(AUDIO_CLKA_C)\t\tFM(SSI_SCK2_A)\tF_(0, 0)\tFM(STP_IVCXO27_0_C)\tF_(0, 0)\tFM(AUDIO_CLKOUT3_A)\tF_(0, 0)\tFM(TCLK1_B)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP14_7_4\tFM(MSIOF0_SS2)\t\tFM(TX5_A)\tFM(MSIOF1_SS2_D)\tFM(AUDIO_CLKC_A)\t\tFM(SSI_WS2_A)\tF_(0, 0)\tFM(STP_OPWM_0_D)\tF_(0, 0)\tFM(AUDIO_CLKOUT_D)\tF_(0, 0)\tFM(SPEEDIN_B)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP14_11_8\tFM(MLB_CLK)\t\tF_(0, 0)\tFM(MSIOF1_SCK_F)\tF_(0, 0)\t\t\tFM(SCL1_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP14_15_12\tFM(MLB_SIG)\t\tFM(RX1_B)\tFM(MSIOF1_SYNC_F)\tF_(0, 0)\t\t\tFM(SDA1_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP14_19_16\tFM(MLB_DAT)\t\tFM(TX1_B)\tFM(MSIOF1_RXD_F)\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP14_23_20\tFM(SSI_SCK01239)\tF_(0, 0)\tFM(MSIOF1_TXD_F)\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP14_27_24\tFM(SSI_WS01239)\t\tF_(0, 0)\tFM(MSIOF1_SS1_F)\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+\n+/* IPSRx */\t\t/* 0 */\t\t\t/* 1 */\t\t/* 2 */\t\t\t/* 3 */\t\t\t\t/* 4 */\t\t/* 5 */\t\t/* 6 */\t\t\t/* 7 */\t\t/* 8 */\t\t\t/* 9 */\t\t/* A */\t\t/* B */\t\t/* C - F */\n+#define IP14_31_28\tFM(SSI_SDATA0)\t\tF_(0, 0)\tFM(MSIOF1_SS2_F)\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP15_3_0\tFM(SSI_SDATA1_A)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP15_7_4\tFM(SSI_SDATA2_A)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\t\t\tFM(SSI_SCK1_B)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP15_11_8\tFM(SSI_SCK349)\t\tF_(0, 0)\tFM(MSIOF1_SS1_A)\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tFM(STP_OPWM_0_A)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP15_15_12\tFM(SSI_WS349)\t\tFM(HCTS2_N_A)\tFM(MSIOF1_SS2_A)\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tFM(STP_IVCXO27_0_A)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP15_19_16\tFM(SSI_SDATA3)\t\tFM(HRTS2_N_A)\tFM(MSIOF1_TXD_A)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SCK0_A)\tFM(STP_ISCLK_0_A)\tFM(RIF0_D1_A)\tFM(RIF2_D0_A)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP15_23_20\tFM(SSI_SCK4)\t\tFM(HRX2_A)\tFM(MSIOF1_SCK_A)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDAT0_A)\tFM(STP_ISD_0_A)\t\tFM(RIF0_CLK_A)\tFM(RIF2_CLK_A)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP15_27_24\tFM(SSI_WS4)\t\tFM(HTX2_A)\tFM(MSIOF1_SYNC_A)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDEN0_A)\tFM(STP_ISEN_0_A)\tFM(RIF0_SYNC_A)\tFM(RIF2_SYNC_A)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP15_31_28\tFM(SSI_SDATA4)\t\tFM(HSCK2_A)\tFM(MSIOF1_RXD_A)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)\tFM(RIF0_D0_A)\tFM(RIF2_D1_A)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP16_3_0\tFM(SSI_SCK6)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(SIM0_RST_D)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP16_7_4\tFM(SSI_WS6)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(SIM0_D_D)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP16_11_8\tFM(SSI_SDATA6)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(SIM0_CLK_D)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP16_15_12\tFM(SSI_SCK78)\t\tFM(HRX2_B)\tFM(MSIOF1_SCK_C)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SCK1_A)\tFM(STP_ISCLK_1_A)\tFM(RIF1_CLK_A)\tFM(RIF3_CLK_A)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP16_19_16\tFM(SSI_WS78)\t\tFM(HTX2_B)\tFM(MSIOF1_SYNC_C)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDAT1_A)\tFM(STP_ISD_1_A)\t\tFM(RIF1_SYNC_A)\tFM(RIF3_SYNC_A)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP16_23_20\tFM(SSI_SDATA7)\t\tFM(HCTS2_N_B)\tFM(MSIOF1_RXD_C)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SDEN1_A)\tFM(STP_ISEN_1_A)\tFM(RIF1_D0_A)\tFM(RIF3_D0_A)\t\tF_(0, 0)\tFM(TCLK2_A)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP16_27_24\tFM(SSI_SDATA8)\t\tFM(HRTS2_N_B)\tFM(MSIOF1_TXD_C)\tF_(0, 0)\t\t\tF_(0, 0)\tFM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)\tFM(RIF1_D1_A)\tFM(RIF3_D1_A)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP16_31_28\tFM(SSI_SDATA9_A)\tFM(HSCK2_B)\tFM(MSIOF1_SS1_C)\tFM(HSCK1_A)\t\t\tFM(SSI_WS1_B)\tFM(SCK1)\tFM(STP_IVCXO27_1_A)\tFM(SCK5_A)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP17_3_0\tFM(AUDIO_CLKA_A)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\t\tF_(0, 0)\tF_(0, 0)\tFM(CC5_OSCOUT)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP17_7_4\tFM(AUDIO_CLKB_B)\tFM(SCIF_CLK_A)\tF_(0, 0)\t\tF_(0, 0)\t\t\tF_(0, 0)\tF_(0, 0)\tFM(STP_IVCXO27_1_D)\tFM(REMOCON_A)\tF_(0, 0)\t\tF_(0, 0)\tFM(TCLK1_A)\tF_(0, 0)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP17_11_8\tFM(USB0_PWEN)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(SIM0_RST_C)\t\t\tF_(0, 0)\tFM(TS_SCK1_D)\tFM(STP_ISCLK_1_D)\tFM(BPFCLK_B)\tFM(RIF3_CLK_B)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)\n+#define IP17_15_12\tFM(USB0_OVC)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(SIM0_D_C)\t\t\tF_(0, 0)\tFM(TS_SDAT1_D)\tFM(STP_ISD_1_D)\t\tF_(0, 0)\tFM(RIF3_SYNC_B)\t\tF_(0, 0)\tF_(0, 0)\tF_(0, 0)\tF_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)\n+#define IP17_19_16\tFM(USB1_PWEN)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(SIM0_CLK_C)\t\t\tFM(SSI_SCK1_A)\tFM(TS_SCK0_E)\tFM(STP_ISCLK_0_E)\tFM(FMCLK_B)\tFM(RIF2_CLK_B)\t\tF_(0, 0)\tFM(SPEEDIN_A)\tF_(0, 0)\tF_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)\n+#define IP17_23_20\tFM(USB1_OVC)\t\tF_(0, 0)\tFM(MSIOF1_SS2_C)\tF_(0, 0)\t\t\tFM(SSI_WS1_A)\tFM(TS_SDAT0_E)\tFM(STP_ISD_0_E)\t\tFM(FMIN_B)\tFM(RIF2_SYNC_B)\t\tF_(0, 0)\tFM(REMOCON_B)\tF_(0, 0)\tF_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)\n+#define IP17_27_24\tFM(USB30_PWEN)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(AUDIO_CLKOUT_B)\t\tFM(SSI_SCK2_B)\tFM(TS_SDEN1_D)\tFM(STP_ISEN_1_D)\tFM(STP_OPWM_0_E)FM(RIF3_D0_B)\t\tF_(0, 0)\tFM(TCLK2_B)\tFM(TPU0TO0)\tFM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)\n+#define IP17_31_28\tFM(USB30_OVC)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(AUDIO_CLKOUT1_B)\t\tFM(SSI_WS2_B)\tFM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)\tFM(STP_IVCXO27_0_E)FM(RIF3_D1_B)\tF_(0, 0)\tFM(FSO_TOE_N)\tFM(TPU0TO1)\tF_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)\n+#define IP18_3_0\tFM(GP6_30)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(AUDIO_CLKOUT2_B)\t\tFM(SSI_SCK9_B)\tFM(TS_SDEN0_E)\tFM(STP_ISEN_0_E)\tF_(0, 0)\tFM(RIF2_D0_B)\t\tF_(0, 0)\tF_(0, 0)\tFM(TPU0TO2)\tFM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)\n+#define IP18_7_4\tFM(GP6_31)\t\tF_(0, 0)\tF_(0, 0)\t\tFM(AUDIO_CLKOUT3_B)\t\tFM(SSI_WS9_B)\tFM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)\tF_(0, 0)\tFM(RIF2_D1_B)\t\tF_(0, 0)\tF_(0, 0)\tFM(TPU0TO3)\tFM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)\n+\n+#define PINMUX_GPSR\t\\\n+\\\n+\t\t\t\t\t\t\t\t\t\t\t\tGPSR6_31 \\\n+\t\t\t\t\t\t\t\t\t\t\t\tGPSR6_30 \\\n+\t\t\t\t\t\t\t\t\t\t\t\tGPSR6_29 \\\n+\t\tGPSR1_28\t\t\t\t\t\t\t\t\tGPSR6_28 \\\n+\t\tGPSR1_27\t\t\t\t\t\t\t\t\tGPSR6_27 \\\n+\t\tGPSR1_26\t\t\t\t\t\t\t\t\tGPSR6_26 \\\n+\t\tGPSR1_25\t\t\t\t\t\t\tGPSR5_25\tGPSR6_25 \\\n+\t\tGPSR1_24\t\t\t\t\t\t\tGPSR5_24\tGPSR6_24 \\\n+\t\tGPSR1_23\t\t\t\t\t\t\tGPSR5_23\tGPSR6_23 \\\n+\t\tGPSR1_22\t\t\t\t\t\t\tGPSR5_22\tGPSR6_22 \\\n+\t\tGPSR1_21\t\t\t\t\t\t\tGPSR5_21\tGPSR6_21 \\\n+\t\tGPSR1_20\t\t\t\t\t\t\tGPSR5_20\tGPSR6_20 \\\n+\t\tGPSR1_19\t\t\t\t\t\t\tGPSR5_19\tGPSR6_19 \\\n+\t\tGPSR1_18\t\t\t\t\t\t\tGPSR5_18\tGPSR6_18 \\\n+\t\tGPSR1_17\t\t\t\t\tGPSR4_17\tGPSR5_17\tGPSR6_17 \\\n+\t\tGPSR1_16\t\t\t\t\tGPSR4_16\tGPSR5_16\tGPSR6_16 \\\n+GPSR0_15\tGPSR1_15\t\t\tGPSR3_15\tGPSR4_15\tGPSR5_15\tGPSR6_15 \\\n+GPSR0_14\tGPSR1_14\tGPSR2_14\tGPSR3_14\tGPSR4_14\tGPSR5_14\tGPSR6_14 \\\n+GPSR0_13\tGPSR1_13\tGPSR2_13\tGPSR3_13\tGPSR4_13\tGPSR5_13\tGPSR6_13 \\\n+GPSR0_12\tGPSR1_12\tGPSR2_12\tGPSR3_12\tGPSR4_12\tGPSR5_12\tGPSR6_12 \\\n+GPSR0_11\tGPSR1_11\tGPSR2_11\tGPSR3_11\tGPSR4_11\tGPSR5_11\tGPSR6_11 \\\n+GPSR0_10\tGPSR1_10\tGPSR2_10\tGPSR3_10\tGPSR4_10\tGPSR5_10\tGPSR6_10 \\\n+GPSR0_9\t\tGPSR1_9\t\tGPSR2_9\t\tGPSR3_9\t\tGPSR4_9\t\tGPSR5_9\t\tGPSR6_9 \\\n+GPSR0_8\t\tGPSR1_8\t\tGPSR2_8\t\tGPSR3_8\t\tGPSR4_8\t\tGPSR5_8\t\tGPSR6_8 \\\n+GPSR0_7\t\tGPSR1_7\t\tGPSR2_7\t\tGPSR3_7\t\tGPSR4_7\t\tGPSR5_7\t\tGPSR6_7 \\\n+GPSR0_6\t\tGPSR1_6\t\tGPSR2_6\t\tGPSR3_6\t\tGPSR4_6\t\tGPSR5_6\t\tGPSR6_6 \\\n+GPSR0_5\t\tGPSR1_5\t\tGPSR2_5\t\tGPSR3_5\t\tGPSR4_5\t\tGPSR5_5\t\tGPSR6_5 \\\n+GPSR0_4\t\tGPSR1_4\t\tGPSR2_4\t\tGPSR3_4\t\tGPSR4_4\t\tGPSR5_4\t\tGPSR6_4 \\\n+GPSR0_3\t\tGPSR1_3\t\tGPSR2_3\t\tGPSR3_3\t\tGPSR4_3\t\tGPSR5_3\t\tGPSR6_3\t\tGPSR7_3 \\\n+GPSR0_2\t\tGPSR1_2\t\tGPSR2_2\t\tGPSR3_2\t\tGPSR4_2\t\tGPSR5_2\t\tGPSR6_2\t\tGPSR7_2 \\\n+GPSR0_1\t\tGPSR1_1\t\tGPSR2_1\t\tGPSR3_1\t\tGPSR4_1\t\tGPSR5_1\t\tGPSR6_1\t\tGPSR7_1 \\\n+GPSR0_0\t\tGPSR1_0\t\tGPSR2_0\t\tGPSR3_0\t\tGPSR4_0\t\tGPSR5_0\t\tGPSR6_0\t\tGPSR7_0\n+\n+#define PINMUX_IPSR\t\t\t\t\\\n+\\\n+FM(IP0_3_0)\tIP0_3_0\t\tFM(IP1_3_0)\tIP1_3_0\t\tFM(IP2_3_0)\tIP2_3_0\t\tFM(IP3_3_0)\tIP3_3_0 \\\n+FM(IP0_7_4)\tIP0_7_4\t\tFM(IP1_7_4)\tIP1_7_4\t\tFM(IP2_7_4)\tIP2_7_4\t\tFM(IP3_7_4)\tIP3_7_4 \\\n+FM(IP0_11_8)\tIP0_11_8\tFM(IP1_11_8)\tIP1_11_8\tFM(IP2_11_8)\tIP2_11_8\tFM(IP3_11_8)\tIP3_11_8 \\\n+FM(IP0_15_12)\tIP0_15_12\tFM(IP1_15_12)\tIP1_15_12\tFM(IP2_15_12)\tIP2_15_12\tFM(IP3_15_12)\tIP3_15_12 \\\n+FM(IP0_19_16)\tIP0_19_16\tFM(IP1_19_16)\tIP1_19_16\tFM(IP2_19_16)\tIP2_19_16\tFM(IP3_19_16)\tIP3_19_16 \\\n+FM(IP0_23_20)\tIP0_23_20\tFM(IP1_23_20)\tIP1_23_20\tFM(IP2_23_20)\tIP2_23_20\tFM(IP3_23_20)\tIP3_23_20 \\\n+FM(IP0_27_24)\tIP0_27_24\tFM(IP1_27_24)\tIP1_27_24\tFM(IP2_27_24)\tIP2_27_24\tFM(IP3_27_24)\tIP3_27_24 \\\n+FM(IP0_31_28)\tIP0_31_28\tFM(IP1_31_28)\tIP1_31_28\tFM(IP2_31_28)\tIP2_31_28\tFM(IP3_31_28)\tIP3_31_28 \\\n+\\\n+FM(IP4_3_0)\tIP4_3_0\t\tFM(IP5_3_0)\tIP5_3_0\t\tFM(IP6_3_0)\tIP6_3_0\t\tFM(IP7_3_0)\tIP7_3_0 \\\n+FM(IP4_7_4)\tIP4_7_4\t\tFM(IP5_7_4)\tIP5_7_4\t\tFM(IP6_7_4)\tIP6_7_4\t\tFM(IP7_7_4)\tIP7_7_4 \\\n+FM(IP4_11_8)\tIP4_11_8\tFM(IP5_11_8)\tIP5_11_8\tFM(IP6_11_8)\tIP6_11_8\tFM(IP7_11_8)\tIP7_11_8 \\\n+FM(IP4_15_12)\tIP4_15_12\tFM(IP5_15_12)\tIP5_15_12\tFM(IP6_15_12)\tIP6_15_12 \\\n+FM(IP4_19_16)\tIP4_19_16\tFM(IP5_19_16)\tIP5_19_16\tFM(IP6_19_16)\tIP6_19_16\tFM(IP7_19_16)\tIP7_19_16 \\\n+FM(IP4_23_20)\tIP4_23_20\tFM(IP5_23_20)\tIP5_23_20\tFM(IP6_23_20)\tIP6_23_20\tFM(IP7_23_20)\tIP7_23_20 \\\n+FM(IP4_27_24)\tIP4_27_24\tFM(IP5_27_24)\tIP5_27_24\tFM(IP6_27_24)\tIP6_27_24\tFM(IP7_27_24)\tIP7_27_24 \\\n+FM(IP4_31_28)\tIP4_31_28\tFM(IP5_31_28)\tIP5_31_28\tFM(IP6_31_28)\tIP6_31_28\tFM(IP7_31_28)\tIP7_31_28 \\\n+\\\n+FM(IP8_3_0)\tIP8_3_0\t\tFM(IP9_3_0)\tIP9_3_0\t\tFM(IP10_3_0)\tIP10_3_0\tFM(IP11_3_0)\tIP11_3_0 \\\n+FM(IP8_7_4)\tIP8_7_4\t\tFM(IP9_7_4)\tIP9_7_4\t\tFM(IP10_7_4)\tIP10_7_4\tFM(IP11_7_4)\tIP11_7_4 \\\n+FM(IP8_11_8)\tIP8_11_8\tFM(IP9_11_8)\tIP9_11_8\tFM(IP10_11_8)\tIP10_11_8\tFM(IP11_11_8)\tIP11_11_8 \\\n+FM(IP8_15_12)\tIP8_15_12\tFM(IP9_15_12)\tIP9_15_12\tFM(IP10_15_12)\tIP10_15_12\tFM(IP11_15_12)\tIP11_15_12 \\\n+FM(IP8_19_16)\tIP8_19_16\tFM(IP9_19_16)\tIP9_19_16\tFM(IP10_19_16)\tIP10_19_16\tFM(IP11_19_16)\tIP11_19_16 \\\n+FM(IP8_23_20)\tIP8_23_20\tFM(IP9_23_20)\tIP9_23_20\tFM(IP10_23_20)\tIP10_23_20\tFM(IP11_23_20)\tIP11_23_20 \\\n+FM(IP8_27_24)\tIP8_27_24\tFM(IP9_27_24)\tIP9_27_24\tFM(IP10_27_24)\tIP10_27_24\tFM(IP11_27_24)\tIP11_27_24 \\\n+FM(IP8_31_28)\tIP8_31_28\tFM(IP9_31_28)\tIP9_31_28\tFM(IP10_31_28)\tIP10_31_28\tFM(IP11_31_28)\tIP11_31_28 \\\n+\\\n+FM(IP12_3_0)\tIP12_3_0\tFM(IP13_3_0)\tIP13_3_0\tFM(IP14_3_0)\tIP14_3_0\tFM(IP15_3_0)\tIP15_3_0 \\\n+FM(IP12_7_4)\tIP12_7_4\tFM(IP13_7_4)\tIP13_7_4\tFM(IP14_7_4)\tIP14_7_4\tFM(IP15_7_4)\tIP15_7_4 \\\n+FM(IP12_11_8)\tIP12_11_8\tFM(IP13_11_8)\tIP13_11_8\tFM(IP14_11_8)\tIP14_11_8\tFM(IP15_11_8)\tIP15_11_8 \\\n+FM(IP12_15_12)\tIP12_15_12\tFM(IP13_15_12)\tIP13_15_12\tFM(IP14_15_12)\tIP14_15_12\tFM(IP15_15_12)\tIP15_15_12 \\\n+FM(IP12_19_16)\tIP12_19_16\tFM(IP13_19_16)\tIP13_19_16\tFM(IP14_19_16)\tIP14_19_16\tFM(IP15_19_16)\tIP15_19_16 \\\n+FM(IP12_23_20)\tIP12_23_20\tFM(IP13_23_20)\tIP13_23_20\tFM(IP14_23_20)\tIP14_23_20\tFM(IP15_23_20)\tIP15_23_20 \\\n+FM(IP12_27_24)\tIP12_27_24\tFM(IP13_27_24)\tIP13_27_24\tFM(IP14_27_24)\tIP14_27_24\tFM(IP15_27_24)\tIP15_27_24 \\\n+FM(IP12_31_28)\tIP12_31_28\tFM(IP13_31_28)\tIP13_31_28\tFM(IP14_31_28)\tIP14_31_28\tFM(IP15_31_28)\tIP15_31_28 \\\n+\\\n+FM(IP16_3_0)\tIP16_3_0\tFM(IP17_3_0)\tIP17_3_0\tFM(IP18_3_0)\tIP18_3_0 \\\n+FM(IP16_7_4)\tIP16_7_4\tFM(IP17_7_4)\tIP17_7_4\tFM(IP18_7_4)\tIP18_7_4 \\\n+FM(IP16_11_8)\tIP16_11_8\tFM(IP17_11_8)\tIP17_11_8 \\\n+FM(IP16_15_12)\tIP16_15_12\tFM(IP17_15_12)\tIP17_15_12 \\\n+FM(IP16_19_16)\tIP16_19_16\tFM(IP17_19_16)\tIP17_19_16 \\\n+FM(IP16_23_20)\tIP16_23_20\tFM(IP17_23_20)\tIP17_23_20 \\\n+FM(IP16_27_24)\tIP16_27_24\tFM(IP17_27_24)\tIP17_27_24 \\\n+FM(IP16_31_28)\tIP16_31_28\tFM(IP17_31_28)\tIP17_31_28\n+\n+/* MOD_SEL0 */\t\t\t/* 0 */\t\t\t/* 1 */\t\t\t/* 2 */\t\t\t/* 3 */\t\t\t/* 4 */\t\t\t/* 5 */\t\t\t/* 6 */\t\t\t/* 7 */\n+#define MOD_SEL0_31_30_29\tFM(SEL_MSIOF3_0)\tFM(SEL_MSIOF3_1)\tFM(SEL_MSIOF3_2)\tFM(SEL_MSIOF3_3)\tFM(SEL_MSIOF3_4)\tF_(0, 0)\t\tF_(0, 0)\t\tF_(0, 0)\n+#define MOD_SEL0_28_27\t\tFM(SEL_MSIOF2_0)\tFM(SEL_MSIOF2_1)\tFM(SEL_MSIOF2_2)\tFM(SEL_MSIOF2_3)\n+#define MOD_SEL0_26_25_24\tFM(SEL_MSIOF1_0)\tFM(SEL_MSIOF1_1)\tFM(SEL_MSIOF1_2)\tFM(SEL_MSIOF1_3)\tFM(SEL_MSIOF1_4)\tFM(SEL_MSIOF1_5)\tFM(SEL_MSIOF1_6)\tF_(0, 0)\n+#define MOD_SEL0_23\t\tFM(SEL_LBSC_0)\t\tFM(SEL_LBSC_1)\n+#define MOD_SEL0_22\t\tFM(SEL_IEBUS_0)\t\tFM(SEL_IEBUS_1)\n+#define MOD_SEL0_21\t\tFM(SEL_I2C2_0)\t\tFM(SEL_I2C2_1)\n+#define MOD_SEL0_20\t\tFM(SEL_I2C1_0)\t\tFM(SEL_I2C1_1)\n+#define MOD_SEL0_19\t\tFM(SEL_HSCIF4_0)\tFM(SEL_HSCIF4_1)\n+#define MOD_SEL0_18_17\t\tFM(SEL_HSCIF3_0)\tFM(SEL_HSCIF3_1)\tFM(SEL_HSCIF3_2)\tFM(SEL_HSCIF3_3)\n+#define MOD_SEL0_16\t\tFM(SEL_HSCIF1_0)\tFM(SEL_HSCIF1_1)\n+#define MOD_SEL0_14_13\t\tFM(SEL_HSCIF2_0)\tFM(SEL_HSCIF2_1)\tFM(SEL_HSCIF2_2)\tF_(0, 0)\n+#define MOD_SEL0_12\t\tFM(SEL_ETHERAVB_0)\tFM(SEL_ETHERAVB_1)\n+#define MOD_SEL0_11\t\tFM(SEL_DRIF3_0)\t\tFM(SEL_DRIF3_1)\n+#define MOD_SEL0_10\t\tFM(SEL_DRIF2_0)\t\tFM(SEL_DRIF2_1)\n+#define MOD_SEL0_9_8\t\tFM(SEL_DRIF1_0)\t\tFM(SEL_DRIF1_1)\t\tFM(SEL_DRIF1_2)\t\tF_(0, 0)\n+#define MOD_SEL0_7_6\t\tFM(SEL_DRIF0_0)\t\tFM(SEL_DRIF0_1)\t\tFM(SEL_DRIF0_2)\t\tF_(0, 0)\n+#define MOD_SEL0_5\t\tFM(SEL_CANFD0_0)\tFM(SEL_CANFD0_1)\n+#define MOD_SEL0_4_3\t\tFM(SEL_ADG_A_0)\t\tFM(SEL_ADG_A_1)\t\tFM(SEL_ADG_A_2)\t\tFM(SEL_ADG_A_3)\n+\n+/* MOD_SEL1 */\t\t\t/* 0 */\t\t\t/* 1 */\t\t\t/* 2 */\t\t\t/* 3 */\t\t\t/* 4 */\t\t\t/* 5 */\t\t\t/* 6 */\t\t\t/* 7 */\n+#define MOD_SEL1_31_30\t\tFM(SEL_TSIF1_0)\t\tFM(SEL_TSIF1_1)\t\tFM(SEL_TSIF1_2)\t\tFM(SEL_TSIF1_3)\n+#define MOD_SEL1_29_28_27\tFM(SEL_TSIF0_0)\t\tFM(SEL_TSIF0_1)\t\tFM(SEL_TSIF0_2)\t\tFM(SEL_TSIF0_3)\t\tFM(SEL_TSIF0_4)\t\tF_(0, 0)\t\tF_(0, 0)\t\tF_(0, 0)\n+#define MOD_SEL1_26\t\tFM(SEL_TIMER_TMU_0)\tFM(SEL_TIMER_TMU_1)\n+#define MOD_SEL1_25_24\t\tFM(SEL_SSP1_1_0)\tFM(SEL_SSP1_1_1)\tFM(SEL_SSP1_1_2)\tFM(SEL_SSP1_1_3)\n+#define MOD_SEL1_23_22_21\tFM(SEL_SSP1_0_0)\tFM(SEL_SSP1_0_1)\tFM(SEL_SSP1_0_2)\tFM(SEL_SSP1_0_3)\tFM(SEL_SSP1_0_4)\tF_(0, 0)\t\tF_(0, 0)\t\tF_(0, 0)\n+#define MOD_SEL1_20\t\tFM(SEL_SSI_0)\t\tFM(SEL_SSI_1)\n+#define MOD_SEL1_19\t\tFM(SEL_SPEED_PULSE_0)\tFM(SEL_SPEED_PULSE_1)\n+#define MOD_SEL1_18_17\t\tFM(SEL_SIMCARD_0)\tFM(SEL_SIMCARD_1)\tFM(SEL_SIMCARD_2)\tFM(SEL_SIMCARD_3)\n+#define MOD_SEL1_16\t\tFM(SEL_SDHI2_0)\t\tFM(SEL_SDHI2_1)\n+#define MOD_SEL1_15_14\t\tFM(SEL_SCIF4_0)\t\tFM(SEL_SCIF4_1)\t\tFM(SEL_SCIF4_2)\t\tF_(0, 0)\n+#define MOD_SEL1_13\t\tFM(SEL_SCIF3_0)\t\tFM(SEL_SCIF3_1)\n+#define MOD_SEL1_12\t\tFM(SEL_SCIF2_0)\t\tFM(SEL_SCIF2_1)\n+#define MOD_SEL1_11\t\tFM(SEL_SCIF1_0)\t\tFM(SEL_SCIF1_1)\n+#define MOD_SEL1_10\t\tFM(SEL_SCIF_0)\t\tFM(SEL_SCIF_1)\n+#define MOD_SEL1_9\t\tFM(SEL_REMOCON_0)\tFM(SEL_REMOCON_1)\n+#define MOD_SEL1_6\t\tFM(SEL_RCAN0_0)\t\tFM(SEL_RCAN0_1)\n+#define MOD_SEL1_5\t\tFM(SEL_PWM6_0)\t\tFM(SEL_PWM6_1)\n+#define MOD_SEL1_4\t\tFM(SEL_PWM5_0)\t\tFM(SEL_PWM5_1)\n+#define MOD_SEL1_3\t\tFM(SEL_PWM4_0)\t\tFM(SEL_PWM4_1)\n+#define MOD_SEL1_2\t\tFM(SEL_PWM3_0)\t\tFM(SEL_PWM3_1)\n+#define MOD_SEL1_1\t\tFM(SEL_PWM2_0)\t\tFM(SEL_PWM2_1)\n+#define MOD_SEL1_0\t\tFM(SEL_PWM1_0)\t\tFM(SEL_PWM1_1)\n+\n+/* MOD_SEL1 */\t\t\t/* 0 */\t\t\t/* 1 */\t\t\t/* 2 */\t\t\t/* 3 */\t\t\t/* 4 */\t\t\t/* 5 */\t\t\t/* 6 */\t\t\t/* 7 */\n+#define MOD_SEL2_31\t\tFM(I2C_SEL_5_0)\t\tFM(I2C_SEL_5_1)\n+#define MOD_SEL2_30\t\tFM(I2C_SEL_3_0)\t\tFM(I2C_SEL_3_1)\n+#define MOD_SEL2_29\t\tFM(I2C_SEL_0_0)\t\tFM(I2C_SEL_0_1)\n+#define MOD_SEL2_28_27\t\tFM(SEL_FM_0)\t\tFM(SEL_FM_1)\t\tFM(SEL_FM_2)\t\tFM(SEL_FM_3)\n+#define MOD_SEL2_26\t\tFM(SEL_SCIF5_0)\t\tFM(SEL_SCIF5_1)\n+#define MOD_SEL2_25_24_23\tFM(SEL_I2C6_0)\t\tFM(SEL_I2C6_1)\t\tFM(SEL_I2C6_2)\t\tF_(0, 0)\t\tF_(0, 0)\t\tF_(0, 0)\t\tF_(0, 0)\t\tF_(0, 0)\n+#define MOD_SEL2_22\t\tFM(SEL_NDF_0)\t\tFM(SEL_NDF_1)\n+#define MOD_SEL2_21\t\tFM(SEL_SSI2_0)\t\tFM(SEL_SSI2_1)\n+#define MOD_SEL2_20\t\tFM(SEL_SSI9_0)\t\tFM(SEL_SSI9_1)\n+#define MOD_SEL2_19\t\tFM(SEL_TIMER_TMU2_0)\tFM(SEL_TIMER_TMU2_1)\n+#define MOD_SEL2_18\t\tFM(SEL_ADG_B_0)\t\tFM(SEL_ADG_B_1)\n+#define MOD_SEL2_17\t\tFM(SEL_ADG_C_0)\t\tFM(SEL_ADG_C_1)\n+#define MOD_SEL2_0\t\tFM(SEL_VIN4_0)\t\tFM(SEL_VIN4_1)\n+\n+#define PINMUX_MOD_SELS\t\\\n+\\\n+MOD_SEL0_31_30_29\tMOD_SEL1_31_30\t\tMOD_SEL2_31 \\\n+\t\t\t\t\t\tMOD_SEL2_30 \\\n+\t\t\tMOD_SEL1_29_28_27\tMOD_SEL2_29 \\\n+MOD_SEL0_28_27\t\t\t\t\tMOD_SEL2_28_27 \\\n+MOD_SEL0_26_25_24\tMOD_SEL1_26\t\tMOD_SEL2_26 \\\n+\t\t\tMOD_SEL1_25_24\t\tMOD_SEL2_25_24_23 \\\n+MOD_SEL0_23\t\tMOD_SEL1_23_22_21 \\\n+MOD_SEL0_22\t\t\t\t\tMOD_SEL2_22 \\\n+MOD_SEL0_21\t\t\t\t\tMOD_SEL2_21 \\\n+MOD_SEL0_20\t\tMOD_SEL1_20\t\tMOD_SEL2_20 \\\n+MOD_SEL0_19\t\tMOD_SEL1_19\t\tMOD_SEL2_19 \\\n+MOD_SEL0_18_17\t\tMOD_SEL1_18_17\t\tMOD_SEL2_18 \\\n+\t\t\t\t\t\tMOD_SEL2_17 \\\n+MOD_SEL0_16\t\tMOD_SEL1_16 \\\n+\t\t\tMOD_SEL1_15_14 \\\n+MOD_SEL0_14_13 \\\n+\t\t\tMOD_SEL1_13 \\\n+MOD_SEL0_12\t\tMOD_SEL1_12 \\\n+MOD_SEL0_11\t\tMOD_SEL1_11 \\\n+MOD_SEL0_10\t\tMOD_SEL1_10 \\\n+MOD_SEL0_9_8\t\tMOD_SEL1_9 \\\n+MOD_SEL0_7_6 \\\n+\t\t\tMOD_SEL1_6 \\\n+MOD_SEL0_5\t\tMOD_SEL1_5 \\\n+MOD_SEL0_4_3\t\tMOD_SEL1_4 \\\n+\t\t\tMOD_SEL1_3 \\\n+\t\t\tMOD_SEL1_2 \\\n+\t\t\tMOD_SEL1_1 \\\n+\t\t\tMOD_SEL1_0\t\tMOD_SEL2_0\n+\n+/*\n+ * These pins are not able to be muxed but have other properties\n+ * that can be set, such as drive-strength or pull-up/pull-down enable.\n+ */\n+#define PINMUX_STATIC \\\n+\tFM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \\\n+\tFM(QSPI0_IO2) FM(QSPI0_IO3) \\\n+\tFM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \\\n+\tFM(QSPI1_IO2) FM(QSPI1_IO3) \\\n+\tFM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \\\n+\tFM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \\\n+\tFM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \\\n+\tFM(AVB_TXCREFCLK) FM(AVB_MDIO) \\\n+\tFM(PRESETOUT) \\\n+\tFM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \\\n+\tFM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)\n+\n+enum {\n+\tPINMUX_RESERVED = 0,\n+\n+\tPINMUX_DATA_BEGIN,\n+\tGP_ALL(DATA),\n+\tPINMUX_DATA_END,\n+\n+#define F_(x, y)\n+#define FM(x)\tFN_##x,\n+\tPINMUX_FUNCTION_BEGIN,\n+\tGP_ALL(FN),\n+\tPINMUX_GPSR\n+\tPINMUX_IPSR\n+\tPINMUX_MOD_SELS\n+\tPINMUX_FUNCTION_END,\n+#undef F_\n+#undef FM\n+\n+#define F_(x, y)\n+#define FM(x)\tx##_MARK,\n+\tPINMUX_MARK_BEGIN,\n+\tPINMUX_GPSR\n+\tPINMUX_IPSR\n+\tPINMUX_MOD_SELS\n+\tPINMUX_STATIC\n+\tPINMUX_MARK_END,\n+#undef F_\n+#undef FM\n+};\n+\n+static const u16 pinmux_data[] = {\n+\tPINMUX_DATA_GP_ALL(),\n+\n+\tPINMUX_SINGLE(AVS1),\n+\tPINMUX_SINGLE(AVS2),\n+\tPINMUX_SINGLE(CLKOUT),\n+\tPINMUX_SINGLE(GP7_03),\n+\tPINMUX_SINGLE(HDMI0_CEC),\n+\tPINMUX_SINGLE(MSIOF0_RXD),\n+\tPINMUX_SINGLE(MSIOF0_SCK),\n+\tPINMUX_SINGLE(MSIOF0_TXD),\n+\tPINMUX_SINGLE(SSI_SCK5),\n+\tPINMUX_SINGLE(SSI_SDATA5),\n+\tPINMUX_SINGLE(SSI_WS5),\n+\n+\t/* IPSR0 */\n+\tPINMUX_IPSR_GPSR(IP0_3_0,\tAVB_MDC),\n+\tPINMUX_IPSR_MSEL(IP0_3_0,\tMSIOF2_SS2_C,\t\tSEL_MSIOF2_2),\n+\n+\tPINMUX_IPSR_GPSR(IP0_7_4,\tAVB_MAGIC),\n+\tPINMUX_IPSR_MSEL(IP0_7_4,\tMSIOF2_SS1_C,\t\tSEL_MSIOF2_2),\n+\tPINMUX_IPSR_MSEL(IP0_7_4,\tSCK4_A,\t\t\tSEL_SCIF4_0),\n+\n+\tPINMUX_IPSR_GPSR(IP0_11_8,\tAVB_PHY_INT),\n+\tPINMUX_IPSR_MSEL(IP0_11_8,\tMSIOF2_SYNC_C,\t\tSEL_MSIOF2_2),\n+\tPINMUX_IPSR_MSEL(IP0_11_8,\tRX4_A,\t\t\tSEL_SCIF4_0),\n+\n+\tPINMUX_IPSR_GPSR(IP0_15_12,\tAVB_LINK),\n+\tPINMUX_IPSR_MSEL(IP0_15_12,\tMSIOF2_SCK_C,\t\tSEL_MSIOF2_2),\n+\tPINMUX_IPSR_MSEL(IP0_15_12,\tTX4_A,\t\t\tSEL_SCIF4_0),\n+\n+\tPINMUX_IPSR_MSEL(IP0_19_16,\tAVB_AVTP_MATCH_A,\tSEL_ETHERAVB_0),\n+\tPINMUX_IPSR_MSEL(IP0_19_16,\tMSIOF2_RXD_C,\t\tSEL_MSIOF2_2),\n+\tPINMUX_IPSR_MSEL(IP0_19_16,\tCTS4_N_A,\t\tSEL_SCIF4_0),\n+\n+\tPINMUX_IPSR_MSEL(IP0_23_20,\tAVB_AVTP_CAPTURE_A,\tSEL_ETHERAVB_0),\n+\tPINMUX_IPSR_MSEL(IP0_23_20,\tMSIOF2_TXD_C,\t\tSEL_MSIOF2_2),\n+\tPINMUX_IPSR_MSEL(IP0_23_20,\tRTS4_N_TANS_A,\t\tSEL_SCIF4_0),\n+\n+\tPINMUX_IPSR_GPSR(IP0_27_24,\tIRQ0),\n+\tPINMUX_IPSR_GPSR(IP0_27_24,\tQPOLB),\n+\tPINMUX_IPSR_GPSR(IP0_27_24,\tDU_CDE),\n+\tPINMUX_IPSR_MSEL(IP0_27_24,\tVI4_DATA0_B,\t\tSEL_VIN4_1),\n+\tPINMUX_IPSR_MSEL(IP0_27_24,\tCAN0_TX_B,\t\tSEL_RCAN0_1),\n+\tPINMUX_IPSR_MSEL(IP0_27_24,\tCANFD0_TX_B,\t\tSEL_CANFD0_1),\n+\tPINMUX_IPSR_MSEL(IP0_27_24,\tMSIOF3_SS2_E,\t\tSEL_MSIOF3_4),\n+\n+\tPINMUX_IPSR_GPSR(IP0_31_28,\tIRQ1),\n+\tPINMUX_IPSR_GPSR(IP0_31_28,\tQPOLA),\n+\tPINMUX_IPSR_GPSR(IP0_31_28,\tDU_DISP),\n+\tPINMUX_IPSR_MSEL(IP0_31_28,\tVI4_DATA1_B,\t\tSEL_VIN4_1),\n+\tPINMUX_IPSR_MSEL(IP0_31_28,\tCAN0_RX_B,\t\tSEL_RCAN0_1),\n+\tPINMUX_IPSR_MSEL(IP0_31_28,\tCANFD0_RX_B,\t\tSEL_CANFD0_1),\n+\tPINMUX_IPSR_MSEL(IP0_31_28,\tMSIOF3_SS1_E,\t\tSEL_MSIOF3_4),\n+\n+\t/* IPSR1 */\n+\tPINMUX_IPSR_GPSR(IP1_3_0,\tIRQ2),\n+\tPINMUX_IPSR_GPSR(IP1_3_0,\tQCPV_QDE),\n+\tPINMUX_IPSR_GPSR(IP1_3_0,\tDU_EXODDF_DU_ODDF_DISP_CDE),\n+\tPINMUX_IPSR_MSEL(IP1_3_0,\tVI4_DATA2_B,\t\tSEL_VIN4_1),\n+\tPINMUX_IPSR_MSEL(IP1_3_0,\tPWM3_B,\t\t\tSEL_PWM3_1),\n+\tPINMUX_IPSR_MSEL(IP1_3_0,\tMSIOF3_SYNC_E,\t\tSEL_MSIOF3_4),\n+\n+\tPINMUX_IPSR_GPSR(IP1_7_4,\tIRQ3),\n+\tPINMUX_IPSR_GPSR(IP1_7_4,\tQSTVB_QVE),\n+\tPINMUX_IPSR_GPSR(IP1_7_4,\tA25),\n+\tPINMUX_IPSR_GPSR(IP1_7_4,\tDU_DOTCLKOUT1),\n+\tPINMUX_IPSR_MSEL(IP1_7_4,\tVI4_DATA3_B,\t\tSEL_VIN4_1),\n+\tPINMUX_IPSR_MSEL(IP1_7_4,\tPWM4_B,\t\t\tSEL_PWM4_1),\n+\tPINMUX_IPSR_MSEL(IP1_7_4,\tMSIOF3_SCK_E,\t\tSEL_MSIOF3_4),\n+\n+\tPINMUX_IPSR_GPSR(IP1_11_8,\tIRQ4),\n+\tPINMUX_IPSR_GPSR(IP1_11_8,\tQSTH_QHS),\n+\tPINMUX_IPSR_GPSR(IP1_11_8,\tA24),\n+\tPINMUX_IPSR_GPSR(IP1_11_8,\tDU_EXHSYNC_DU_HSYNC),\n+\tPINMUX_IPSR_MSEL(IP1_11_8,\tVI4_DATA4_B,\t\tSEL_VIN4_1),\n+\tPINMUX_IPSR_MSEL(IP1_11_8,\tPWM5_B,\t\t\tSEL_PWM5_1),\n+\tPINMUX_IPSR_MSEL(IP1_11_8,\tMSIOF3_RXD_E,\t\tSEL_MSIOF3_4),\n+\n+\tPINMUX_IPSR_GPSR(IP1_15_12,\tIRQ5),\n+\tPINMUX_IPSR_GPSR(IP1_15_12,\tQSTB_QHE),\n+\tPINMUX_IPSR_GPSR(IP1_15_12,\tA23),\n+\tPINMUX_IPSR_GPSR(IP1_15_12,\tDU_EXVSYNC_DU_VSYNC),\n+\tPINMUX_IPSR_MSEL(IP1_15_12,\tVI4_DATA5_B,\t\tSEL_VIN4_1),\n+\tPINMUX_IPSR_MSEL(IP1_15_12,\tPWM6_B,\t\t\tSEL_PWM6_1),\n+\tPINMUX_IPSR_MSEL(IP1_15_12,\tMSIOF3_TXD_E,\t\tSEL_MSIOF3_4),\n+\n+\tPINMUX_IPSR_GPSR(IP1_19_16,\tPWM0),\n+\tPINMUX_IPSR_GPSR(IP1_19_16,\tAVB_AVTP_PPS),\n+\tPINMUX_IPSR_GPSR(IP1_19_16,\tA22),\n+\tPINMUX_IPSR_MSEL(IP1_19_16,\tVI4_DATA6_B,\t\tSEL_VIN4_1),\n+\tPINMUX_IPSR_MSEL(IP1_19_16,\tIECLK_B,\t\tSEL_IEBUS_1),\n+\n+\tPINMUX_IPSR_MSEL(IP1_23_20,\tPWM1_A,\t\t\tSEL_PWM1_0),\n+\tPINMUX_IPSR_GPSR(IP1_23_20,\tA21),\n+\tPINMUX_IPSR_MSEL(IP1_23_20,\tHRX3_D,\t\t\tSEL_HSCIF3_3),\n+\tPINMUX_IPSR_MSEL(IP1_23_20,\tVI4_DATA7_B,\t\tSEL_VIN4_1),\n+\tPINMUX_IPSR_MSEL(IP1_23_20,\tIERX_B,\t\t\tSEL_IEBUS_1),\n+\n+\tPINMUX_IPSR_MSEL(IP1_27_24,\tPWM2_A,\t\t\tSEL_PWM2_0),\n+\tPINMUX_IPSR_GPSR(IP1_27_24,\tA20),\n+\tPINMUX_IPSR_MSEL(IP1_27_24,\tHTX3_D,\t\t\tSEL_HSCIF3_3),\n+\tPINMUX_IPSR_MSEL(IP1_27_24,\tIETX_B,\t\t\tSEL_IEBUS_1),\n+\n+\tPINMUX_IPSR_GPSR(IP1_31_28,\tA0),\n+\tPINMUX_IPSR_GPSR(IP1_31_28,\tLCDOUT16),\n+\tPINMUX_IPSR_MSEL(IP1_31_28,\tMSIOF3_SYNC_B,\t\tSEL_MSIOF3_1),\n+\tPINMUX_IPSR_GPSR(IP1_31_28,\tVI4_DATA8),\n+\tPINMUX_IPSR_GPSR(IP1_31_28,\tDU_DB0),\n+\tPINMUX_IPSR_MSEL(IP1_31_28,\tPWM3_A,\t\t\tSEL_PWM3_0),\n+\n+\t/* IPSR2 */\n+\tPINMUX_IPSR_GPSR(IP2_3_0,\tA1),\n+\tPINMUX_IPSR_GPSR(IP2_3_0,\tLCDOUT17),\n+\tPINMUX_IPSR_MSEL(IP2_3_0,\tMSIOF3_TXD_B,\t\tSEL_MSIOF3_1),\n+\tPINMUX_IPSR_GPSR(IP2_3_0,\tVI4_DATA9),\n+\tPINMUX_IPSR_GPSR(IP2_3_0,\tDU_DB1),\n+\tPINMUX_IPSR_MSEL(IP2_3_0,\tPWM4_A,\t\t\tSEL_PWM4_0),\n+\n+\tPINMUX_IPSR_GPSR(IP2_7_4,\tA2),\n+\tPINMUX_IPSR_GPSR(IP2_7_4,\tLCDOUT18),\n+\tPINMUX_IPSR_MSEL(IP2_7_4,\tMSIOF3_SCK_B,\t\tSEL_MSIOF3_1),\n+\tPINMUX_IPSR_GPSR(IP2_7_4,\tVI4_DATA10),\n+\tPINMUX_IPSR_GPSR(IP2_7_4,\tDU_DB2),\n+\tPINMUX_IPSR_MSEL(IP2_7_4,\tPWM5_A,\t\t\tSEL_PWM5_0),\n+\n+\tPINMUX_IPSR_GPSR(IP2_11_8,\tA3),\n+\tPINMUX_IPSR_GPSR(IP2_11_8,\tLCDOUT19),\n+\tPINMUX_IPSR_MSEL(IP2_11_8,\tMSIOF3_RXD_B,\t\tSEL_MSIOF3_1),\n+\tPINMUX_IPSR_GPSR(IP2_11_8,\tVI4_DATA11),\n+\tPINMUX_IPSR_GPSR(IP2_11_8,\tDU_DB3),\n+\tPINMUX_IPSR_MSEL(IP2_11_8,\tPWM6_A,\t\t\tSEL_PWM6_0),\n+\n+\tPINMUX_IPSR_GPSR(IP2_15_12,\tA4),\n+\tPINMUX_IPSR_GPSR(IP2_15_12,\tLCDOUT20),\n+\tPINMUX_IPSR_MSEL(IP2_15_12,\tMSIOF3_SS1_B,\t\tSEL_MSIOF3_1),\n+\tPINMUX_IPSR_GPSR(IP2_15_12,\tVI4_DATA12),\n+\tPINMUX_IPSR_GPSR(IP2_15_12,\tVI5_DATA12),\n+\tPINMUX_IPSR_GPSR(IP2_15_12,\tDU_DB4),\n+\n+\tPINMUX_IPSR_GPSR(IP2_19_16,\tA5),\n+\tPINMUX_IPSR_GPSR(IP2_19_16,\tLCDOUT21),\n+\tPINMUX_IPSR_MSEL(IP2_19_16,\tMSIOF3_SS2_B,\t\tSEL_MSIOF3_1),\n+\tPINMUX_IPSR_MSEL(IP2_19_16,\tSCK4_B,\t\t\tSEL_SCIF4_1),\n+\tPINMUX_IPSR_GPSR(IP2_19_16,\tVI4_DATA13),\n+\tPINMUX_IPSR_GPSR(IP2_19_16,\tVI5_DATA13),\n+\tPINMUX_IPSR_GPSR(IP2_19_16,\tDU_DB5),\n+\n+\tPINMUX_IPSR_GPSR(IP2_23_20,\tA6),\n+\tPINMUX_IPSR_GPSR(IP2_23_20,\tLCDOUT22),\n+\tPINMUX_IPSR_MSEL(IP2_23_20,\tMSIOF2_SS1_A,\t\tSEL_MSIOF2_0),\n+\tPINMUX_IPSR_MSEL(IP2_23_20,\tRX4_B,\t\t\tSEL_SCIF4_1),\n+\tPINMUX_IPSR_GPSR(IP2_23_20,\tVI4_DATA14),\n+\tPINMUX_IPSR_GPSR(IP2_23_20,\tVI5_DATA14),\n+\tPINMUX_IPSR_GPSR(IP2_23_20,\tDU_DB6),\n+\n+\tPINMUX_IPSR_GPSR(IP2_27_24,\tA7),\n+\tPINMUX_IPSR_GPSR(IP2_27_24,\tLCDOUT23),\n+\tPINMUX_IPSR_MSEL(IP2_27_24,\tMSIOF2_SS2_A,\t\tSEL_MSIOF2_0),\n+\tPINMUX_IPSR_MSEL(IP2_27_24,\tTX4_B,\t\t\tSEL_SCIF4_1),\n+\tPINMUX_IPSR_GPSR(IP2_27_24,\tVI4_DATA15),\n+\tPINMUX_IPSR_GPSR(IP2_27_24,\tVI5_DATA15),\n+\tPINMUX_IPSR_GPSR(IP2_27_24,\tDU_DB7),\n+\n+\tPINMUX_IPSR_GPSR(IP2_31_28,\tA8),\n+\tPINMUX_IPSR_MSEL(IP2_31_28,\tRX3_B,\t\t\tSEL_SCIF3_1),\n+\tPINMUX_IPSR_MSEL(IP2_31_28,\tMSIOF2_SYNC_A,\t\tSEL_MSIOF2_0),\n+\tPINMUX_IPSR_MSEL(IP2_31_28,\tHRX4_B,\t\t\tSEL_HSCIF4_1),\n+\tPINMUX_IPSR_MSEL(IP2_31_28,\tSDA6_A,\t\t\tSEL_I2C6_0),\n+\tPINMUX_IPSR_MSEL(IP2_31_28,\tAVB_AVTP_MATCH_B,\tSEL_ETHERAVB_1),\n+\tPINMUX_IPSR_MSEL(IP2_31_28,\tPWM1_B,\t\t\tSEL_PWM1_1),\n+\n+\t/* IPSR3 */\n+\tPINMUX_IPSR_GPSR(IP3_3_0,\tA9),\n+\tPINMUX_IPSR_MSEL(IP3_3_0,\tMSIOF2_SCK_A,\t\tSEL_MSIOF2_0),\n+\tPINMUX_IPSR_MSEL(IP3_3_0,\tCTS4_N_B,\t\tSEL_SCIF4_1),\n+\tPINMUX_IPSR_GPSR(IP3_3_0,\tVI5_VSYNC_N),\n+\n+\tPINMUX_IPSR_GPSR(IP3_7_4,\tA10),\n+\tPINMUX_IPSR_MSEL(IP3_7_4,\tMSIOF2_RXD_A,\t\tSEL_MSIOF2_0),\n+\tPINMUX_IPSR_MSEL(IP3_7_4,\tRTS4_N_TANS_B,\t\tSEL_SCIF4_1),\n+\tPINMUX_IPSR_GPSR(IP3_7_4,\tVI5_HSYNC_N),\n+\n+\tPINMUX_IPSR_GPSR(IP3_11_8,\tA11),\n+\tPINMUX_IPSR_MSEL(IP3_11_8,\tTX3_B,\t\t\tSEL_SCIF3_1),\n+\tPINMUX_IPSR_MSEL(IP3_11_8,\tMSIOF2_TXD_A,\t\tSEL_MSIOF2_0),\n+\tPINMUX_IPSR_MSEL(IP3_11_8,\tHTX4_B,\t\t\tSEL_HSCIF4_1),\n+\tPINMUX_IPSR_GPSR(IP3_11_8,\tHSCK4),\n+\tPINMUX_IPSR_GPSR(IP3_11_8,\tVI5_FIELD),\n+\tPINMUX_IPSR_MSEL(IP3_11_8,\tSCL6_A,\t\t\tSEL_I2C6_0),\n+\tPINMUX_IPSR_MSEL(IP3_11_8,\tAVB_AVTP_CAPTURE_B,\tSEL_ETHERAVB_1),\n+\tPINMUX_IPSR_MSEL(IP3_11_8,\tPWM2_B,\t\t\tSEL_PWM2_1),\n+\n+\tPINMUX_IPSR_GPSR(IP3_15_12,\tA12),\n+\tPINMUX_IPSR_GPSR(IP3_15_12,\tLCDOUT12),\n+\tPINMUX_IPSR_MSEL(IP3_15_12,\tMSIOF3_SCK_C,\t\tSEL_MSIOF3_2),\n+\tPINMUX_IPSR_MSEL(IP3_15_12,\tHRX4_A,\t\t\tSEL_HSCIF4_0),\n+\tPINMUX_IPSR_GPSR(IP3_15_12,\tVI5_DATA8),\n+\tPINMUX_IPSR_GPSR(IP3_15_12,\tDU_DG4),\n+\n+\tPINMUX_IPSR_GPSR(IP3_19_16,\tA13),\n+\tPINMUX_IPSR_GPSR(IP3_19_16,\tLCDOUT13),\n+\tPINMUX_IPSR_MSEL(IP3_19_16,\tMSIOF3_SYNC_C,\t\tSEL_MSIOF3_2),\n+\tPINMUX_IPSR_MSEL(IP3_19_16,\tHTX4_A,\t\t\tSEL_HSCIF4_0),\n+\tPINMUX_IPSR_GPSR(IP3_19_16,\tVI5_DATA9),\n+\tPINMUX_IPSR_GPSR(IP3_19_16,\tDU_DG5),\n+\n+\tPINMUX_IPSR_GPSR(IP3_23_20,\tA14),\n+\tPINMUX_IPSR_GPSR(IP3_23_20,\tLCDOUT14),\n+\tPINMUX_IPSR_MSEL(IP3_23_20,\tMSIOF3_RXD_C,\t\tSEL_MSIOF3_2),\n+\tPINMUX_IPSR_GPSR(IP3_23_20,\tHCTS4_N),\n+\tPINMUX_IPSR_GPSR(IP3_23_20,\tVI5_DATA10),\n+\tPINMUX_IPSR_GPSR(IP3_23_20,\tDU_DG6),\n+\n+\tPINMUX_IPSR_GPSR(IP3_27_24,\tA15),\n+\tPINMUX_IPSR_GPSR(IP3_27_24,\tLCDOUT15),\n+\tPINMUX_IPSR_MSEL(IP3_27_24,\tMSIOF3_TXD_C,\t\tSEL_MSIOF3_2),\n+\tPINMUX_IPSR_GPSR(IP3_27_24,\tHRTS4_N),\n+\tPINMUX_IPSR_GPSR(IP3_27_24,\tVI5_DATA11),\n+\tPINMUX_IPSR_GPSR(IP3_27_24,\tDU_DG7),\n+\n+\tPINMUX_IPSR_GPSR(IP3_31_28,\tA16),\n+\tPINMUX_IPSR_GPSR(IP3_31_28,\tLCDOUT8),\n+\tPINMUX_IPSR_GPSR(IP3_31_28,\tVI4_FIELD),\n+\tPINMUX_IPSR_GPSR(IP3_31_28,\tDU_DG0),\n+\n+\t/* IPSR4 */\n+\tPINMUX_IPSR_GPSR(IP4_3_0,\tA17),\n+\tPINMUX_IPSR_GPSR(IP4_3_0,\tLCDOUT9),\n+\tPINMUX_IPSR_GPSR(IP4_3_0,\tVI4_VSYNC_N),\n+\tPINMUX_IPSR_GPSR(IP4_3_0,\tDU_DG1),\n+\n+\tPINMUX_IPSR_GPSR(IP4_7_4,\tA18),\n+\tPINMUX_IPSR_GPSR(IP4_7_4,\tLCDOUT10),\n+\tPINMUX_IPSR_GPSR(IP4_7_4,\tVI4_HSYNC_N),\n+\tPINMUX_IPSR_GPSR(IP4_7_4,\tDU_DG2),\n+\n+\tPINMUX_IPSR_GPSR(IP4_11_8,\tA19),\n+\tPINMUX_IPSR_GPSR(IP4_11_8,\tLCDOUT11),\n+\tPINMUX_IPSR_GPSR(IP4_11_8,\tVI4_CLKENB),\n+\tPINMUX_IPSR_GPSR(IP4_11_8,\tDU_DG3),\n+\n+\tPINMUX_IPSR_GPSR(IP4_15_12,\tCS0_N),\n+\tPINMUX_IPSR_GPSR(IP4_15_12,\tVI5_CLKENB),\n+\n+\tPINMUX_IPSR_GPSR(IP4_19_16,\tCS1_N),\n+\tPINMUX_IPSR_GPSR(IP4_19_16,\tVI5_CLK),\n+\tPINMUX_IPSR_MSEL(IP4_19_16,\tEX_WAIT0_B,\t\tSEL_LBSC_1),\n+\n+\tPINMUX_IPSR_GPSR(IP4_23_20,\tBS_N),\n+\tPINMUX_IPSR_GPSR(IP4_23_20,\tQSTVA_QVS),\n+\tPINMUX_IPSR_MSEL(IP4_23_20,\tMSIOF3_SCK_D,\t\tSEL_MSIOF3_3),\n+\tPINMUX_IPSR_GPSR(IP4_23_20,\tSCK3),\n+\tPINMUX_IPSR_GPSR(IP4_23_20,\tHSCK3),\n+\tPINMUX_IPSR_GPSR(IP4_23_20,\tCAN1_TX),\n+\tPINMUX_IPSR_GPSR(IP4_23_20,\tCANFD1_TX),\n+\tPINMUX_IPSR_MSEL(IP4_23_20,\tIETX_A,\t\t\tSEL_IEBUS_0),\n+\n+\tPINMUX_IPSR_GPSR(IP4_27_24,\tRD_N),\n+\tPINMUX_IPSR_MSEL(IP4_27_24,\tMSIOF3_SYNC_D,\t\tSEL_MSIOF3_3),\n+\tPINMUX_IPSR_MSEL(IP4_27_24,\tRX3_A,\t\t\tSEL_SCIF3_0),\n+\tPINMUX_IPSR_MSEL(IP4_27_24,\tHRX3_A,\t\t\tSEL_HSCIF3_0),\n+\tPINMUX_IPSR_MSEL(IP4_27_24,\tCAN0_TX_A,\t\tSEL_RCAN0_0),\n+\tPINMUX_IPSR_MSEL(IP4_27_24,\tCANFD0_TX_A,\t\tSEL_CANFD0_0),\n+\n+\tPINMUX_IPSR_GPSR(IP4_31_28,\tRD_WR_N),\n+\tPINMUX_IPSR_MSEL(IP4_31_28,\tMSIOF3_RXD_D,\t\tSEL_MSIOF3_3),\n+\tPINMUX_IPSR_MSEL(IP4_31_28,\tTX3_A,\t\t\tSEL_SCIF3_0),\n+\tPINMUX_IPSR_MSEL(IP4_31_28,\tHTX3_A,\t\t\tSEL_HSCIF3_0),\n+\tPINMUX_IPSR_MSEL(IP4_31_28,\tCAN0_RX_A,\t\tSEL_RCAN0_0),\n+\tPINMUX_IPSR_MSEL(IP4_31_28,\tCANFD0_RX_A,\t\tSEL_CANFD0_0),\n+\n+\t/* IPSR5 */\n+\tPINMUX_IPSR_GPSR(IP5_3_0,\tWE0_N),\n+\tPINMUX_IPSR_MSEL(IP5_3_0,\tMSIOF3_TXD_D,\t\tSEL_MSIOF3_3),\n+\tPINMUX_IPSR_GPSR(IP5_3_0,\tCTS3_N),\n+\tPINMUX_IPSR_GPSR(IP5_3_0,\tHCTS3_N),\n+\tPINMUX_IPSR_MSEL(IP5_3_0,\tSCL6_B,\t\t\tSEL_I2C6_1),\n+\tPINMUX_IPSR_GPSR(IP5_3_0,\tCAN_CLK),\n+\tPINMUX_IPSR_MSEL(IP5_3_0,\tIECLK_A,\t\tSEL_IEBUS_0),\n+\n+\tPINMUX_IPSR_GPSR(IP5_7_4,\tWE1_N),\n+\tPINMUX_IPSR_MSEL(IP5_7_4,\tMSIOF3_SS1_D,\t\tSEL_MSIOF3_3),\n+\tPINMUX_IPSR_GPSR(IP5_7_4,\tRTS3_N_TANS),\n+\tPINMUX_IPSR_GPSR(IP5_7_4,\tHRTS3_N),\n+\tPINMUX_IPSR_MSEL(IP5_7_4,\tSDA6_B,\t\t\tSEL_I2C6_1),\n+\tPINMUX_IPSR_GPSR(IP5_7_4,\tCAN1_RX),\n+\tPINMUX_IPSR_GPSR(IP5_7_4,\tCANFD1_RX),\n+\tPINMUX_IPSR_MSEL(IP5_7_4,\tIERX_A,\t\t\tSEL_IEBUS_0),\n+\n+\tPINMUX_IPSR_MSEL(IP5_11_8,\tEX_WAIT0_A,\t\tSEL_LBSC_0),\n+\tPINMUX_IPSR_GPSR(IP5_11_8,\tQCLK),\n+\tPINMUX_IPSR_GPSR(IP5_11_8,\tVI4_CLK),\n+\tPINMUX_IPSR_GPSR(IP5_11_8,\tDU_DOTCLKOUT0),\n+\n+\tPINMUX_IPSR_GPSR(IP5_15_12,\tD0),\n+\tPINMUX_IPSR_MSEL(IP5_15_12,\tMSIOF2_SS1_B,\t\tSEL_MSIOF2_1),\n+\tPINMUX_IPSR_MSEL(IP5_15_12,\tMSIOF3_SCK_A,\t\tSEL_MSIOF3_0),\n+\tPINMUX_IPSR_GPSR(IP5_15_12,\tVI4_DATA16),\n+\tPINMUX_IPSR_GPSR(IP5_15_12,\tVI5_DATA0),\n+\n+\tPINMUX_IPSR_GPSR(IP5_19_16,\tD1),\n+\tPINMUX_IPSR_MSEL(IP5_19_16,\tMSIOF2_SS2_B,\t\tSEL_MSIOF2_1),\n+\tPINMUX_IPSR_MSEL(IP5_19_16,\tMSIOF3_SYNC_A,\t\tSEL_MSIOF3_0),\n+\tPINMUX_IPSR_GPSR(IP5_19_16,\tVI4_DATA17),\n+\tPINMUX_IPSR_GPSR(IP5_19_16,\tVI5_DATA1),\n+\n+\tPINMUX_IPSR_GPSR(IP5_23_20,\tD2),\n+\tPINMUX_IPSR_MSEL(IP5_23_20,\tMSIOF3_RXD_A,\t\tSEL_MSIOF3_0),\n+\tPINMUX_IPSR_GPSR(IP5_23_20,\tVI4_DATA18),\n+\tPINMUX_IPSR_GPSR(IP5_23_20,\tVI5_DATA2),\n+\n+\tPINMUX_IPSR_GPSR(IP5_27_24,\tD3),\n+\tPINMUX_IPSR_MSEL(IP5_27_24,\tMSIOF3_TXD_A,\t\tSEL_MSIOF3_0),\n+\tPINMUX_IPSR_GPSR(IP5_27_24,\tVI4_DATA19),\n+\tPINMUX_IPSR_GPSR(IP5_27_24,\tVI5_DATA3),\n+\n+\tPINMUX_IPSR_GPSR(IP5_31_28,\tD4),\n+\tPINMUX_IPSR_MSEL(IP5_31_28,\tMSIOF2_SCK_B,\t\tSEL_MSIOF2_1),\n+\tPINMUX_IPSR_GPSR(IP5_31_28,\tVI4_DATA20),\n+\tPINMUX_IPSR_GPSR(IP5_31_28,\tVI5_DATA4),\n+\n+\t/* IPSR6 */\n+\tPINMUX_IPSR_GPSR(IP6_3_0,\tD5),\n+\tPINMUX_IPSR_MSEL(IP6_3_0,\tMSIOF2_SYNC_B,\t\tSEL_MSIOF2_1),\n+\tPINMUX_IPSR_GPSR(IP6_3_0,\tVI4_DATA21),\n+\tPINMUX_IPSR_GPSR(IP6_3_0,\tVI5_DATA5),\n+\n+\tPINMUX_IPSR_GPSR(IP6_7_4,\tD6),\n+\tPINMUX_IPSR_MSEL(IP6_7_4,\tMSIOF2_RXD_B,\t\tSEL_MSIOF2_1),\n+\tPINMUX_IPSR_GPSR(IP6_7_4,\tVI4_DATA22),\n+\tPINMUX_IPSR_GPSR(IP6_7_4,\tVI5_DATA6),\n+\n+\tPINMUX_IPSR_GPSR(IP6_11_8,\tD7),\n+\tPINMUX_IPSR_MSEL(IP6_11_8,\tMSIOF2_TXD_B,\t\tSEL_MSIOF2_1),\n+\tPINMUX_IPSR_GPSR(IP6_11_8,\tVI4_DATA23),\n+\tPINMUX_IPSR_GPSR(IP6_11_8,\tVI5_DATA7),\n+\n+\tPINMUX_IPSR_GPSR(IP6_15_12,\tD8),\n+\tPINMUX_IPSR_GPSR(IP6_15_12,\tLCDOUT0),\n+\tPINMUX_IPSR_MSEL(IP6_15_12,\tMSIOF2_SCK_D,\t\tSEL_MSIOF2_3),\n+\tPINMUX_IPSR_MSEL(IP6_15_12,\tSCK4_C,\t\t\tSEL_SCIF4_2),\n+\tPINMUX_IPSR_MSEL(IP6_15_12,\tVI4_DATA0_A,\t\tSEL_VIN4_0),\n+\tPINMUX_IPSR_GPSR(IP6_15_12,\tDU_DR0),\n+\n+\tPINMUX_IPSR_GPSR(IP6_19_16,\tD9),\n+\tPINMUX_IPSR_GPSR(IP6_19_16,\tLCDOUT1),\n+\tPINMUX_IPSR_MSEL(IP6_19_16,\tMSIOF2_SYNC_D,\t\tSEL_MSIOF2_3),\n+\tPINMUX_IPSR_MSEL(IP6_19_16,\tVI4_DATA1_A,\t\tSEL_VIN4_0),\n+\tPINMUX_IPSR_GPSR(IP6_19_16,\tDU_DR1),\n+\n+\tPINMUX_IPSR_GPSR(IP6_23_20,\tD10),\n+\tPINMUX_IPSR_GPSR(IP6_23_20,\tLCDOUT2),\n+\tPINMUX_IPSR_MSEL(IP6_23_20,\tMSIOF2_RXD_D,\t\tSEL_MSIOF2_3),\n+\tPINMUX_IPSR_MSEL(IP6_23_20,\tHRX3_B,\t\t\tSEL_HSCIF3_1),\n+\tPINMUX_IPSR_MSEL(IP6_23_20,\tVI4_DATA2_A,\t\tSEL_VIN4_0),\n+\tPINMUX_IPSR_MSEL(IP6_23_20,\tCTS4_N_C,\t\tSEL_SCIF4_2),\n+\tPINMUX_IPSR_GPSR(IP6_23_20,\tDU_DR2),\n+\n+\tPINMUX_IPSR_GPSR(IP6_27_24,\tD11),\n+\tPINMUX_IPSR_GPSR(IP6_27_24,\tLCDOUT3),\n+\tPINMUX_IPSR_MSEL(IP6_27_24,\tMSIOF2_TXD_D,\t\tSEL_MSIOF2_3),\n+\tPINMUX_IPSR_MSEL(IP6_27_24,\tHTX3_B,\t\t\tSEL_HSCIF3_1),\n+\tPINMUX_IPSR_MSEL(IP6_27_24,\tVI4_DATA3_A,\t\tSEL_VIN4_0),\n+\tPINMUX_IPSR_MSEL(IP6_27_24,\tRTS4_N_TANS_C,\t\tSEL_SCIF4_2),\n+\tPINMUX_IPSR_GPSR(IP6_27_24,\tDU_DR3),\n+\n+\tPINMUX_IPSR_GPSR(IP6_31_28,\tD12),\n+\tPINMUX_IPSR_GPSR(IP6_31_28,\tLCDOUT4),\n+\tPINMUX_IPSR_MSEL(IP6_31_28,\tMSIOF2_SS1_D,\t\tSEL_MSIOF2_3),\n+\tPINMUX_IPSR_MSEL(IP6_31_28,\tRX4_C,\t\t\tSEL_SCIF4_2),\n+\tPINMUX_IPSR_MSEL(IP6_31_28,\tVI4_DATA4_A,\t\tSEL_VIN4_0),\n+\tPINMUX_IPSR_GPSR(IP6_31_28,\tDU_DR4),\n+\n+\t/* IPSR7 */\n+\tPINMUX_IPSR_GPSR(IP7_3_0,\tD13),\n+\tPINMUX_IPSR_GPSR(IP7_3_0,\tLCDOUT5),\n+\tPINMUX_IPSR_MSEL(IP7_3_0,\tMSIOF2_SS2_D,\t\tSEL_MSIOF2_3),\n+\tPINMUX_IPSR_MSEL(IP7_3_0,\tTX4_C,\t\t\tSEL_SCIF4_2),\n+\tPINMUX_IPSR_MSEL(IP7_3_0,\tVI4_DATA5_A,\t\tSEL_VIN4_0),\n+\tPINMUX_IPSR_GPSR(IP7_3_0,\tDU_DR5),\n+\n+\tPINMUX_IPSR_GPSR(IP7_7_4,\tD14),\n+\tPINMUX_IPSR_GPSR(IP7_7_4,\tLCDOUT6),\n+\tPINMUX_IPSR_MSEL(IP7_7_4,\tMSIOF3_SS1_A,\t\tSEL_MSIOF3_0),\n+\tPINMUX_IPSR_MSEL(IP7_7_4,\tHRX3_C,\t\t\tSEL_HSCIF3_2),\n+\tPINMUX_IPSR_MSEL(IP7_7_4,\tVI4_DATA6_A,\t\tSEL_VIN4_0),\n+\tPINMUX_IPSR_GPSR(IP7_7_4,\tDU_DR6),\n+\tPINMUX_IPSR_MSEL(IP7_7_4,\tSCL6_C,\t\t\tSEL_I2C6_2),\n+\n+\tPINMUX_IPSR_GPSR(IP7_11_8,\tD15),\n+\tPINMUX_IPSR_GPSR(IP7_11_8,\tLCDOUT7),\n+\tPINMUX_IPSR_MSEL(IP7_11_8,\tMSIOF3_SS2_A,\t\tSEL_MSIOF3_0),\n+\tPINMUX_IPSR_MSEL(IP7_11_8,\tHTX3_C,\t\t\tSEL_HSCIF3_2),\n+\tPINMUX_IPSR_MSEL(IP7_11_8,\tVI4_DATA7_A,\t\tSEL_VIN4_0),\n+\tPINMUX_IPSR_GPSR(IP7_11_8,\tDU_DR7),\n+\tPINMUX_IPSR_MSEL(IP7_11_8,\tSDA6_C,\t\t\tSEL_I2C6_2),\n+\n+\tPINMUX_IPSR_GPSR(IP7_19_16,\tSD0_CLK),\n+\tPINMUX_IPSR_MSEL(IP7_19_16,\tMSIOF1_SCK_E,\t\tSEL_MSIOF1_4),\n+\tPINMUX_IPSR_MSEL(IP7_19_16,\tSTP_OPWM_0_B,\t\tSEL_SSP1_0_1),\n+\n+\tPINMUX_IPSR_GPSR(IP7_23_20,\tSD0_CMD),\n+\tPINMUX_IPSR_MSEL(IP7_23_20,\tMSIOF1_SYNC_E,\t\tSEL_MSIOF1_4),\n+\tPINMUX_IPSR_MSEL(IP7_23_20,\tSTP_IVCXO27_0_B,\tSEL_SSP1_0_1),\n+\n+\tPINMUX_IPSR_GPSR(IP7_27_24,\tSD0_DAT0),\n+\tPINMUX_IPSR_MSEL(IP7_27_24,\tMSIOF1_RXD_E,\t\tSEL_MSIOF1_4),\n+\tPINMUX_IPSR_MSEL(IP7_27_24,\tTS_SCK0_B,\t\tSEL_TSIF0_1),\n+\tPINMUX_IPSR_MSEL(IP7_27_24,\tSTP_ISCLK_0_B,\t\tSEL_SSP1_0_1),\n+\n+\tPINMUX_IPSR_GPSR(IP7_31_28,\tSD0_DAT1),\n+\tPINMUX_IPSR_MSEL(IP7_31_28,\tMSIOF1_TXD_E,\t\tSEL_MSIOF1_4),\n+\tPINMUX_IPSR_MSEL(IP7_31_28,\tTS_SPSYNC0_B,\t\tSEL_TSIF0_1),\n+\tPINMUX_IPSR_MSEL(IP7_31_28,\tSTP_ISSYNC_0_B,\t\tSEL_SSP1_0_1),\n+\n+\t/* IPSR8 */\n+\tPINMUX_IPSR_GPSR(IP8_3_0,\tSD0_DAT2),\n+\tPINMUX_IPSR_MSEL(IP8_3_0,\tMSIOF1_SS1_E,\t\tSEL_MSIOF1_4),\n+\tPINMUX_IPSR_MSEL(IP8_3_0,\tTS_SDAT0_B,\t\tSEL_TSIF0_1),\n+\tPINMUX_IPSR_MSEL(IP8_3_0,\tSTP_ISD_0_B,\t\tSEL_SSP1_0_1),\n+\n+\tPINMUX_IPSR_GPSR(IP8_7_4,\tSD0_DAT3),\n+\tPINMUX_IPSR_MSEL(IP8_7_4,\tMSIOF1_SS2_E,\t\tSEL_MSIOF1_4),\n+\tPINMUX_IPSR_MSEL(IP8_7_4,\tTS_SDEN0_B,\t\tSEL_TSIF0_1),\n+\tPINMUX_IPSR_MSEL(IP8_7_4,\tSTP_ISEN_0_B,\t\tSEL_SSP1_0_1),\n+\n+\tPINMUX_IPSR_GPSR(IP8_11_8,\tSD1_CLK),\n+\tPINMUX_IPSR_MSEL(IP8_11_8,\tMSIOF1_SCK_G,\t\tSEL_MSIOF1_6),\n+\tPINMUX_IPSR_MSEL(IP8_11_8,\tSIM0_CLK_A,\t\tSEL_SIMCARD_0),\n+\n+\tPINMUX_IPSR_GPSR(IP8_15_12,\tSD1_CMD),\n+\tPINMUX_IPSR_MSEL(IP8_15_12,\tMSIOF1_SYNC_G,\t\tSEL_MSIOF1_6),\n+\tPINMUX_IPSR_MSEL(IP8_15_12,\tNFCE_N_B,\t\tSEL_NDF_1),\n+\tPINMUX_IPSR_MSEL(IP8_15_12,\tSIM0_D_A,\t\tSEL_SIMCARD_0),\n+\tPINMUX_IPSR_MSEL(IP8_15_12,\tSTP_IVCXO27_1_B,\tSEL_SSP1_1_1),\n+\n+\tPINMUX_IPSR_GPSR(IP8_19_16,\tSD1_DAT0),\n+\tPINMUX_IPSR_GPSR(IP8_19_16,\tSD2_DAT4),\n+\tPINMUX_IPSR_MSEL(IP8_19_16,\tMSIOF1_RXD_G,\t\tSEL_MSIOF1_6),\n+\tPINMUX_IPSR_MSEL(IP8_19_16,\tNFWP_N_B,\t\tSEL_NDF_1),\n+\tPINMUX_IPSR_MSEL(IP8_19_16,\tTS_SCK1_B,\t\tSEL_TSIF1_1),\n+\tPINMUX_IPSR_MSEL(IP8_19_16,\tSTP_ISCLK_1_B,\t\tSEL_SSP1_1_1),\n+\n+\tPINMUX_IPSR_GPSR(IP8_23_20,\tSD1_DAT1),\n+\tPINMUX_IPSR_GPSR(IP8_23_20,\tSD2_DAT5),\n+\tPINMUX_IPSR_MSEL(IP8_23_20,\tMSIOF1_TXD_G,\t\tSEL_MSIOF1_6),\n+\tPINMUX_IPSR_MSEL(IP8_23_20,\tNFDATA14_B,\t\tSEL_NDF_1),\n+\tPINMUX_IPSR_MSEL(IP8_23_20,\tTS_SPSYNC1_B,\t\tSEL_TSIF1_1),\n+\tPINMUX_IPSR_MSEL(IP8_23_20,\tSTP_ISSYNC_1_B,\t\tSEL_SSP1_1_1),\n+\n+\tPINMUX_IPSR_GPSR(IP8_27_24,\tSD1_DAT2),\n+\tPINMUX_IPSR_GPSR(IP8_27_24,\tSD2_DAT6),\n+\tPINMUX_IPSR_MSEL(IP8_27_24,\tMSIOF1_SS1_G,\t\tSEL_MSIOF1_6),\n+\tPINMUX_IPSR_MSEL(IP8_27_24,\tNFDATA15_B,\t\tSEL_NDF_1),\n+\tPINMUX_IPSR_MSEL(IP8_27_24,\tTS_SDAT1_B,\t\tSEL_TSIF1_1),\n+\tPINMUX_IPSR_MSEL(IP8_27_24,\tSTP_ISD_1_B,\t\tSEL_SSP1_1_1),\n+\n+\tPINMUX_IPSR_GPSR(IP8_31_28,\tSD1_DAT3),\n+\tPINMUX_IPSR_GPSR(IP8_31_28,\tSD2_DAT7),\n+\tPINMUX_IPSR_MSEL(IP8_31_28,\tMSIOF1_SS2_G,\t\tSEL_MSIOF1_6),\n+\tPINMUX_IPSR_MSEL(IP8_31_28,\tNFRB_N_B,\t\tSEL_NDF_1),\n+\tPINMUX_IPSR_MSEL(IP8_31_28,\tTS_SDEN1_B,\t\tSEL_TSIF1_1),\n+\tPINMUX_IPSR_MSEL(IP8_31_28,\tSTP_ISEN_1_B,\t\tSEL_SSP1_1_1),\n+\n+\t/* IPSR9 */\n+\tPINMUX_IPSR_GPSR(IP9_3_0,\tSD2_CLK),\n+\tPINMUX_IPSR_GPSR(IP9_3_0,\tNFDATA8),\n+\n+\tPINMUX_IPSR_GPSR(IP9_7_4,\tSD2_CMD),\n+\tPINMUX_IPSR_GPSR(IP9_7_4,\tNFDATA9),\n+\n+\tPINMUX_IPSR_GPSR(IP9_11_8,\tSD2_DAT0),\n+\tPINMUX_IPSR_GPSR(IP9_11_8,\tNFDATA10),\n+\n+\tPINMUX_IPSR_GPSR(IP9_15_12,\tSD2_DAT1),\n+\tPINMUX_IPSR_GPSR(IP9_15_12,\tNFDATA11),\n+\n+\tPINMUX_IPSR_GPSR(IP9_19_16,\tSD2_DAT2),\n+\tPINMUX_IPSR_GPSR(IP9_19_16,\tNFDATA12),\n+\n+\tPINMUX_IPSR_GPSR(IP9_23_20,\tSD2_DAT3),\n+\tPINMUX_IPSR_GPSR(IP9_23_20,\tNFDATA13),\n+\n+\tPINMUX_IPSR_GPSR(IP9_27_24,\tSD2_DS),\n+\tPINMUX_IPSR_GPSR(IP9_27_24,\tNFALE),\n+\n+\tPINMUX_IPSR_GPSR(IP9_31_28,\tSD3_CLK),\n+\tPINMUX_IPSR_GPSR(IP9_31_28,\tNFWE_N),\n+\n+\t/* IPSR10 */\n+\tPINMUX_IPSR_GPSR(IP10_3_0,\tSD3_CMD),\n+\tPINMUX_IPSR_GPSR(IP10_3_0,\tNFRE_N),\n+\n+\tPINMUX_IPSR_GPSR(IP10_7_4,\tSD3_DAT0),\n+\tPINMUX_IPSR_GPSR(IP10_7_4,\tNFDATA0),\n+\n+\tPINMUX_IPSR_GPSR(IP10_11_8,\tSD3_DAT1),\n+\tPINMUX_IPSR_GPSR(IP10_11_8,\tNFDATA1),\n+\n+\tPINMUX_IPSR_GPSR(IP10_15_12,\tSD3_DAT2),\n+\tPINMUX_IPSR_GPSR(IP10_15_12,\tNFDATA2),\n+\n+\tPINMUX_IPSR_GPSR(IP10_19_16,\tSD3_DAT3),\n+\tPINMUX_IPSR_GPSR(IP10_19_16,\tNFDATA3),\n+\n+\tPINMUX_IPSR_GPSR(IP10_23_20,\tSD3_DAT4),\n+\tPINMUX_IPSR_MSEL(IP10_23_20,\tSD2_CD_A,\t\tSEL_SDHI2_0),\n+\tPINMUX_IPSR_GPSR(IP10_23_20,\tNFDATA4),\n+\n+\tPINMUX_IPSR_GPSR(IP10_27_24,\tSD3_DAT5),\n+\tPINMUX_IPSR_MSEL(IP10_27_24,\tSD2_WP_A,\t\tSEL_SDHI2_0),\n+\tPINMUX_IPSR_GPSR(IP10_27_24,\tNFDATA5),\n+\n+\tPINMUX_IPSR_GPSR(IP10_31_28,\tSD3_DAT6),\n+\tPINMUX_IPSR_GPSR(IP10_31_28,\tSD3_CD),\n+\tPINMUX_IPSR_GPSR(IP10_31_28,\tNFDATA6),\n+\n+\t/* IPSR11 */\n+\tPINMUX_IPSR_GPSR(IP11_3_0,\tSD3_DAT7),\n+\tPINMUX_IPSR_GPSR(IP11_3_0,\tSD3_WP),\n+\tPINMUX_IPSR_GPSR(IP11_3_0,\tNFDATA7),\n+\n+\tPINMUX_IPSR_GPSR(IP11_7_4,\tSD3_DS),\n+\tPINMUX_IPSR_GPSR(IP11_7_4,\tNFCLE),\n+\n+\tPINMUX_IPSR_GPSR(IP11_11_8,\tSD0_CD),\n+\tPINMUX_IPSR_MSEL(IP11_11_8,\tSCL2_B,\t\t\tSEL_I2C2_1),\n+\tPINMUX_IPSR_MSEL(IP11_11_8,\tSIM0_RST_A,\t\tSEL_SIMCARD_0),\n+\n+\tPINMUX_IPSR_GPSR(IP11_15_12,\tSD0_WP),\n+\tPINMUX_IPSR_MSEL(IP11_15_12,\tSDA2_B,\t\t\tSEL_I2C2_1),\n+\n+\tPINMUX_IPSR_GPSR(IP11_19_16,\tSD1_CD),\n+\tPINMUX_IPSR_MSEL(IP11_19_16,\tSIM0_CLK_B,\t\tSEL_SIMCARD_1),\n+\n+\tPINMUX_IPSR_GPSR(IP11_23_20,\tSD1_WP),\n+\tPINMUX_IPSR_MSEL(IP11_23_20,\tSIM0_D_B,\t\tSEL_SIMCARD_1),\n+\n+\tPINMUX_IPSR_GPSR(IP11_27_24,\tSCK0),\n+\tPINMUX_IPSR_MSEL(IP11_27_24,\tHSCK1_B,\t\tSEL_HSCIF1_1),\n+\tPINMUX_IPSR_MSEL(IP11_27_24,\tMSIOF1_SS2_B,\t\tSEL_MSIOF1_1),\n+\tPINMUX_IPSR_MSEL(IP11_27_24,\tAUDIO_CLKC_B,\t\tSEL_ADG_C_1),\n+\tPINMUX_IPSR_MSEL(IP11_27_24,\tSDA2_A,\t\t\tSEL_I2C2_0),\n+\tPINMUX_IPSR_MSEL(IP11_27_24,\tSIM0_RST_B,\t\tSEL_SIMCARD_1),\n+\tPINMUX_IPSR_MSEL(IP11_27_24,\tSTP_OPWM_0_C,\t\tSEL_SSP1_0_2),\n+\tPINMUX_IPSR_MSEL(IP11_27_24,\tRIF0_CLK_B,\t\tSEL_DRIF0_1),\n+\tPINMUX_IPSR_GPSR(IP11_27_24,\tADICHS2),\n+\tPINMUX_IPSR_MSEL(IP11_27_24,\tSCK5_B,\t\t\tSEL_SCIF5_1),\n+\n+\tPINMUX_IPSR_GPSR(IP11_31_28,\tRX0),\n+\tPINMUX_IPSR_MSEL(IP11_31_28,\tHRX1_B,\t\t\tSEL_HSCIF1_1),\n+\tPINMUX_IPSR_MSEL(IP11_31_28,\tTS_SCK0_C,\t\tSEL_TSIF0_2),\n+\tPINMUX_IPSR_MSEL(IP11_31_28,\tSTP_ISCLK_0_C,\t\tSEL_SSP1_0_2),\n+\tPINMUX_IPSR_MSEL(IP11_31_28,\tRIF0_D0_B,\t\tSEL_DRIF0_1),\n+\n+\t/* IPSR12 */\n+\tPINMUX_IPSR_GPSR(IP12_3_0,\tTX0),\n+\tPINMUX_IPSR_MSEL(IP12_3_0,\tHTX1_B,\t\t\tSEL_HSCIF1_1),\n+\tPINMUX_IPSR_MSEL(IP12_3_0,\tTS_SPSYNC0_C,\t\tSEL_TSIF0_2),\n+\tPINMUX_IPSR_MSEL(IP12_3_0,\tSTP_ISSYNC_0_C,\t\tSEL_SSP1_0_2),\n+\tPINMUX_IPSR_MSEL(IP12_3_0,\tRIF0_D1_B,\t\tSEL_DRIF0_1),\n+\n+\tPINMUX_IPSR_GPSR(IP12_7_4,\tCTS0_N),\n+\tPINMUX_IPSR_MSEL(IP12_7_4,\tHCTS1_N_B,\t\tSEL_HSCIF1_1),\n+\tPINMUX_IPSR_MSEL(IP12_7_4,\tMSIOF1_SYNC_B,\t\tSEL_MSIOF1_1),\n+\tPINMUX_IPSR_MSEL(IP12_7_4,\tTS_SPSYNC1_C,\t\tSEL_TSIF1_2),\n+\tPINMUX_IPSR_MSEL(IP12_7_4,\tSTP_ISSYNC_1_C,\t\tSEL_SSP1_1_2),\n+\tPINMUX_IPSR_MSEL(IP12_7_4,\tRIF1_SYNC_B,\t\tSEL_DRIF1_1),\n+\tPINMUX_IPSR_GPSR(IP12_7_4,\tAUDIO_CLKOUT_C),\n+\tPINMUX_IPSR_GPSR(IP12_7_4,\tADICS_SAMP),\n+\n+\tPINMUX_IPSR_GPSR(IP12_11_8,\tRTS0_N_TANS),\n+\tPINMUX_IPSR_MSEL(IP12_11_8,\tHRTS1_N_B,\t\tSEL_HSCIF1_1),\n+\tPINMUX_IPSR_MSEL(IP12_11_8,\tMSIOF1_SS1_B,\t\tSEL_MSIOF1_1),\n+\tPINMUX_IPSR_MSEL(IP12_11_8,\tAUDIO_CLKA_B,\t\tSEL_ADG_A_1),\n+\tPINMUX_IPSR_MSEL(IP12_11_8,\tSCL2_A,\t\t\tSEL_I2C2_0),\n+\tPINMUX_IPSR_MSEL(IP12_11_8,\tSTP_IVCXO27_1_C,\tSEL_SSP1_1_2),\n+\tPINMUX_IPSR_MSEL(IP12_11_8,\tRIF0_SYNC_B,\t\tSEL_DRIF0_1),\n+\tPINMUX_IPSR_GPSR(IP12_11_8,\tADICHS1),\n+\n+\tPINMUX_IPSR_MSEL(IP12_15_12,\tRX1_A,\t\t\tSEL_SCIF1_0),\n+\tPINMUX_IPSR_MSEL(IP12_15_12,\tHRX1_A,\t\t\tSEL_HSCIF1_0),\n+\tPINMUX_IPSR_MSEL(IP12_15_12,\tTS_SDAT0_C,\t\tSEL_TSIF0_2),\n+\tPINMUX_IPSR_MSEL(IP12_15_12,\tSTP_ISD_0_C,\t\tSEL_SSP1_0_2),\n+\tPINMUX_IPSR_MSEL(IP12_15_12,\tRIF1_CLK_C,\t\tSEL_DRIF1_2),\n+\n+\tPINMUX_IPSR_MSEL(IP12_19_16,\tTX1_A,\t\t\tSEL_SCIF1_0),\n+\tPINMUX_IPSR_MSEL(IP12_19_16,\tHTX1_A,\t\t\tSEL_HSCIF1_0),\n+\tPINMUX_IPSR_MSEL(IP12_19_16,\tTS_SDEN0_C,\t\tSEL_TSIF0_2),\n+\tPINMUX_IPSR_MSEL(IP12_19_16,\tSTP_ISEN_0_C,\t\tSEL_SSP1_0_2),\n+\tPINMUX_IPSR_MSEL(IP12_19_16,\tRIF1_D0_C,\t\tSEL_DRIF1_2),\n+\n+\tPINMUX_IPSR_GPSR(IP12_23_20,\tCTS1_N),\n+\tPINMUX_IPSR_MSEL(IP12_23_20,\tHCTS1_N_A,\t\tSEL_HSCIF1_0),\n+\tPINMUX_IPSR_MSEL(IP12_23_20,\tMSIOF1_RXD_B,\t\tSEL_MSIOF1_1),\n+\tPINMUX_IPSR_MSEL(IP12_23_20,\tTS_SDEN1_C,\t\tSEL_TSIF1_2),\n+\tPINMUX_IPSR_MSEL(IP12_23_20,\tSTP_ISEN_1_C,\t\tSEL_SSP1_1_2),\n+\tPINMUX_IPSR_MSEL(IP12_23_20,\tRIF1_D0_B,\t\tSEL_DRIF1_1),\n+\tPINMUX_IPSR_GPSR(IP12_23_20,\tADIDATA),\n+\n+\tPINMUX_IPSR_GPSR(IP12_27_24,\tRTS1_N_TANS),\n+\tPINMUX_IPSR_MSEL(IP12_27_24,\tHRTS1_N_A,\t\tSEL_HSCIF1_0),\n+\tPINMUX_IPSR_MSEL(IP12_27_24,\tMSIOF1_TXD_B,\t\tSEL_MSIOF1_1),\n+\tPINMUX_IPSR_MSEL(IP12_27_24,\tTS_SDAT1_C,\t\tSEL_TSIF1_2),\n+\tPINMUX_IPSR_MSEL(IP12_27_24,\tSTP_ISD_1_C,\t\tSEL_SSP1_1_2),\n+\tPINMUX_IPSR_MSEL(IP12_27_24,\tRIF1_D1_B,\t\tSEL_DRIF1_1),\n+\tPINMUX_IPSR_GPSR(IP12_27_24,\tADICHS0),\n+\n+\tPINMUX_IPSR_GPSR(IP12_31_28,\tSCK2),\n+\tPINMUX_IPSR_MSEL(IP12_31_28,\tSCIF_CLK_B,\t\tSEL_SCIF_1),\n+\tPINMUX_IPSR_MSEL(IP12_31_28,\tMSIOF1_SCK_B,\t\tSEL_MSIOF1_1),\n+\tPINMUX_IPSR_MSEL(IP12_31_28,\tTS_SCK1_C,\t\tSEL_TSIF1_2),\n+\tPINMUX_IPSR_MSEL(IP12_31_28,\tSTP_ISCLK_1_C,\t\tSEL_SSP1_1_2),\n+\tPINMUX_IPSR_MSEL(IP12_31_28,\tRIF1_CLK_B,\t\tSEL_DRIF1_1),\n+\tPINMUX_IPSR_GPSR(IP12_31_28,\tADICLK),\n+\n+\t/* IPSR13 */\n+\tPINMUX_IPSR_MSEL(IP13_3_0,\tTX2_A,\t\t\tSEL_SCIF2_0),\n+\tPINMUX_IPSR_MSEL(IP13_3_0,\tSD2_CD_B,\t\tSEL_SDHI2_1),\n+\tPINMUX_IPSR_MSEL(IP13_3_0,\tSCL1_A,\t\t\tSEL_I2C1_0),\n+\tPINMUX_IPSR_MSEL(IP13_3_0,\tFMCLK_A,\t\tSEL_FM_0),\n+\tPINMUX_IPSR_MSEL(IP13_3_0,\tRIF1_D1_C,\t\tSEL_DRIF1_2),\n+\tPINMUX_IPSR_GPSR(IP13_3_0,\tFSO_CFE_0_N),\n+\n+\tPINMUX_IPSR_MSEL(IP13_7_4,\tRX2_A,\t\t\tSEL_SCIF2_0),\n+\tPINMUX_IPSR_MSEL(IP13_7_4,\tSD2_WP_B,\t\tSEL_SDHI2_1),\n+\tPINMUX_IPSR_MSEL(IP13_7_4,\tSDA1_A,\t\t\tSEL_I2C1_0),\n+\tPINMUX_IPSR_MSEL(IP13_7_4,\tFMIN_A,\t\t\tSEL_FM_0),\n+\tPINMUX_IPSR_MSEL(IP13_7_4,\tRIF1_SYNC_C,\t\tSEL_DRIF1_2),\n+\tPINMUX_IPSR_GPSR(IP13_7_4,\tFSO_CFE_1_N),\n+\n+\tPINMUX_IPSR_GPSR(IP13_11_8,\tHSCK0),\n+\tPINMUX_IPSR_MSEL(IP13_11_8,\tMSIOF1_SCK_D,\t\tSEL_MSIOF1_3),\n+\tPINMUX_IPSR_MSEL(IP13_11_8,\tAUDIO_CLKB_A,\t\tSEL_ADG_B_0),\n+\tPINMUX_IPSR_MSEL(IP13_11_8,\tSSI_SDATA1_B,\t\tSEL_SSI_1),\n+\tPINMUX_IPSR_MSEL(IP13_11_8,\tTS_SCK0_D,\t\tSEL_TSIF0_3),\n+\tPINMUX_IPSR_MSEL(IP13_11_8,\tSTP_ISCLK_0_D,\t\tSEL_SSP1_0_3),\n+\tPINMUX_IPSR_MSEL(IP13_11_8,\tRIF0_CLK_C,\t\tSEL_DRIF0_2),\n+\tPINMUX_IPSR_MSEL(IP13_11_8,\tRX5_B,\t\t\tSEL_SCIF5_1),\n+\n+\tPINMUX_IPSR_GPSR(IP13_15_12,\tHRX0),\n+\tPINMUX_IPSR_MSEL(IP13_15_12,\tMSIOF1_RXD_D,\t\tSEL_MSIOF1_3),\n+\tPINMUX_IPSR_MSEL(IP13_15_12,\tSSI_SDATA2_B,\t\tSEL_SSI_1),\n+\tPINMUX_IPSR_MSEL(IP13_15_12,\tTS_SDEN0_D,\t\tSEL_TSIF0_3),\n+\tPINMUX_IPSR_MSEL(IP13_15_12,\tSTP_ISEN_0_D,\t\tSEL_SSP1_0_3),\n+\tPINMUX_IPSR_MSEL(IP13_15_12,\tRIF0_D0_C,\t\tSEL_DRIF0_2),\n+\n+\tPINMUX_IPSR_GPSR(IP13_19_16,\tHTX0),\n+\tPINMUX_IPSR_MSEL(IP13_19_16,\tMSIOF1_TXD_D,\t\tSEL_MSIOF1_3),\n+\tPINMUX_IPSR_MSEL(IP13_19_16,\tSSI_SDATA9_B,\t\tSEL_SSI_1),\n+\tPINMUX_IPSR_MSEL(IP13_19_16,\tTS_SDAT0_D,\t\tSEL_TSIF0_3),\n+\tPINMUX_IPSR_MSEL(IP13_19_16,\tSTP_ISD_0_D,\t\tSEL_SSP1_0_3),\n+\tPINMUX_IPSR_MSEL(IP13_19_16,\tRIF0_D1_C,\t\tSEL_DRIF0_2),\n+\n+\tPINMUX_IPSR_GPSR(IP13_23_20,\tHCTS0_N),\n+\tPINMUX_IPSR_MSEL(IP13_23_20,\tRX2_B,\t\t\tSEL_SCIF2_1),\n+\tPINMUX_IPSR_MSEL(IP13_23_20,\tMSIOF1_SYNC_D,\t\tSEL_MSIOF1_3),\n+\tPINMUX_IPSR_MSEL(IP13_23_20,\tSSI_SCK9_A,\t\tSEL_SSI_0),\n+\tPINMUX_IPSR_MSEL(IP13_23_20,\tTS_SPSYNC0_D,\t\tSEL_TSIF0_3),\n+\tPINMUX_IPSR_MSEL(IP13_23_20,\tSTP_ISSYNC_0_D,\t\tSEL_SSP1_0_3),\n+\tPINMUX_IPSR_MSEL(IP13_23_20,\tRIF0_SYNC_C,\t\tSEL_DRIF0_2),\n+\tPINMUX_IPSR_GPSR(IP13_23_20,\tAUDIO_CLKOUT1_A),\n+\n+\tPINMUX_IPSR_GPSR(IP13_27_24,\tHRTS0_N),\n+\tPINMUX_IPSR_MSEL(IP13_27_24,\tTX2_B,\t\t\tSEL_SCIF2_1),\n+\tPINMUX_IPSR_MSEL(IP13_27_24,\tMSIOF1_SS1_D,\t\tSEL_MSIOF1_3),\n+\tPINMUX_IPSR_MSEL(IP13_27_24,\tSSI_WS9_A,\t\tSEL_SSI_0),\n+\tPINMUX_IPSR_MSEL(IP13_27_24,\tSTP_IVCXO27_0_D,\tSEL_SSP1_0_3),\n+\tPINMUX_IPSR_MSEL(IP13_27_24,\tBPFCLK_A,\t\tSEL_FM_0),\n+\tPINMUX_IPSR_GPSR(IP13_27_24,\tAUDIO_CLKOUT2_A),\n+\n+\tPINMUX_IPSR_GPSR(IP13_31_28,\tMSIOF0_SYNC),\n+\tPINMUX_IPSR_GPSR(IP13_31_28,\tAUDIO_CLKOUT_A),\n+\tPINMUX_IPSR_MSEL(IP13_31_28,\tTX5_B,\t\t\tSEL_SCIF5_1),\n+\tPINMUX_IPSR_MSEL(IP13_31_28,\tBPFCLK_D,\t\tSEL_FM_3),\n+\n+\t/* IPSR14 */\n+\tPINMUX_IPSR_GPSR(IP14_3_0,\tMSIOF0_SS1),\n+\tPINMUX_IPSR_MSEL(IP14_3_0,\tRX5_A,\t\t\tSEL_SCIF5_0),\n+\tPINMUX_IPSR_MSEL(IP14_3_0,\tNFWP_N_A,\t\tSEL_NDF_0),\n+\tPINMUX_IPSR_MSEL(IP14_3_0,\tAUDIO_CLKA_C,\t\tSEL_ADG_A_2),\n+\tPINMUX_IPSR_MSEL(IP14_3_0,\tSSI_SCK2_A,\t\tSEL_SSI_0),\n+\tPINMUX_IPSR_MSEL(IP14_3_0,\tSTP_IVCXO27_0_C,\tSEL_SSP1_0_2),\n+\tPINMUX_IPSR_GPSR(IP14_3_0,\tAUDIO_CLKOUT3_A),\n+\tPINMUX_IPSR_MSEL(IP14_3_0,\tTCLK1_B,\t\tSEL_TIMER_TMU_1),\n+\n+\tPINMUX_IPSR_GPSR(IP14_7_4,\tMSIOF0_SS2),\n+\tPINMUX_IPSR_MSEL(IP14_7_4,\tTX5_A,\t\t\tSEL_SCIF5_0),\n+\tPINMUX_IPSR_MSEL(IP14_7_4,\tMSIOF1_SS2_D,\t\tSEL_MSIOF1_3),\n+\tPINMUX_IPSR_MSEL(IP14_7_4,\tAUDIO_CLKC_A,\t\tSEL_ADG_C_0),\n+\tPINMUX_IPSR_MSEL(IP14_7_4,\tSSI_WS2_A,\t\tSEL_SSI_0),\n+\tPINMUX_IPSR_MSEL(IP14_7_4,\tSTP_OPWM_0_D,\t\tSEL_SSP1_0_3),\n+\tPINMUX_IPSR_GPSR(IP14_7_4,\tAUDIO_CLKOUT_D),\n+\tPINMUX_IPSR_MSEL(IP14_7_4,\tSPEEDIN_B,\t\tSEL_SPEED_PULSE_1),\n+\n+\tPINMUX_IPSR_GPSR(IP14_11_8,\tMLB_CLK),\n+\tPINMUX_IPSR_MSEL(IP14_11_8,\tMSIOF1_SCK_F,\t\tSEL_MSIOF1_5),\n+\tPINMUX_IPSR_MSEL(IP14_11_8,\tSCL1_B,\t\t\tSEL_I2C1_1),\n+\n+\tPINMUX_IPSR_GPSR(IP14_15_12,\tMLB_SIG),\n+\tPINMUX_IPSR_MSEL(IP14_15_12,\tRX1_B,\t\t\tSEL_SCIF1_1),\n+\tPINMUX_IPSR_MSEL(IP14_15_12,\tMSIOF1_SYNC_F,\t\tSEL_MSIOF1_5),\n+\tPINMUX_IPSR_MSEL(IP14_15_12,\tSDA1_B,\t\t\tSEL_I2C1_1),\n+\n+\tPINMUX_IPSR_GPSR(IP14_19_16,\tMLB_DAT),\n+\tPINMUX_IPSR_MSEL(IP14_19_16,\tTX1_B,\t\t\tSEL_SCIF1_1),\n+\tPINMUX_IPSR_MSEL(IP14_19_16,\tMSIOF1_RXD_F,\t\tSEL_MSIOF1_5),\n+\n+\tPINMUX_IPSR_GPSR(IP14_23_20,\tSSI_SCK01239),\n+\tPINMUX_IPSR_MSEL(IP14_23_20,\tMSIOF1_TXD_F,\t\tSEL_MSIOF1_5),\n+\n+\tPINMUX_IPSR_GPSR(IP14_27_24,\tSSI_WS01239),\n+\tPINMUX_IPSR_MSEL(IP14_27_24,\tMSIOF1_SS1_F,\t\tSEL_MSIOF1_5),\n+\n+\tPINMUX_IPSR_GPSR(IP14_31_28,\tSSI_SDATA0),\n+\tPINMUX_IPSR_MSEL(IP14_31_28,\tMSIOF1_SS2_F,\t\tSEL_MSIOF1_5),\n+\n+\t/* IPSR15 */\n+\tPINMUX_IPSR_MSEL(IP15_3_0,\tSSI_SDATA1_A,\t\tSEL_SSI_0),\n+\n+\tPINMUX_IPSR_MSEL(IP15_7_4,\tSSI_SDATA2_A,\t\tSEL_SSI_0),\n+\tPINMUX_IPSR_MSEL(IP15_7_4,\tSSI_SCK1_B,\t\tSEL_SSI_1),\n+\n+\tPINMUX_IPSR_GPSR(IP15_11_8,\tSSI_SCK349),\n+\tPINMUX_IPSR_MSEL(IP15_11_8,\tMSIOF1_SS1_A,\t\tSEL_MSIOF1_0),\n+\tPINMUX_IPSR_MSEL(IP15_11_8,\tSTP_OPWM_0_A,\t\tSEL_SSP1_0_0),\n+\n+\tPINMUX_IPSR_GPSR(IP15_15_12,\tSSI_WS349),\n+\tPINMUX_IPSR_MSEL(IP15_15_12,\tHCTS2_N_A,\t\tSEL_HSCIF2_0),\n+\tPINMUX_IPSR_MSEL(IP15_15_12,\tMSIOF1_SS2_A,\t\tSEL_MSIOF1_0),\n+\tPINMUX_IPSR_MSEL(IP15_15_12,\tSTP_IVCXO27_0_A,\tSEL_SSP1_0_0),\n+\n+\tPINMUX_IPSR_GPSR(IP15_19_16,\tSSI_SDATA3),\n+\tPINMUX_IPSR_MSEL(IP15_19_16,\tHRTS2_N_A,\t\tSEL_HSCIF2_0),\n+\tPINMUX_IPSR_MSEL(IP15_19_16,\tMSIOF1_TXD_A,\t\tSEL_MSIOF1_0),\n+\tPINMUX_IPSR_MSEL(IP15_19_16,\tTS_SCK0_A,\t\tSEL_TSIF0_0),\n+\tPINMUX_IPSR_MSEL(IP15_19_16,\tSTP_ISCLK_0_A,\t\tSEL_SSP1_0_0),\n+\tPINMUX_IPSR_MSEL(IP15_19_16,\tRIF0_D1_A,\t\tSEL_DRIF0_0),\n+\tPINMUX_IPSR_MSEL(IP15_19_16,\tRIF2_D0_A,\t\tSEL_DRIF2_0),\n+\n+\tPINMUX_IPSR_GPSR(IP15_23_20,\tSSI_SCK4),\n+\tPINMUX_IPSR_MSEL(IP15_23_20,\tHRX2_A,\t\t\tSEL_HSCIF2_0),\n+\tPINMUX_IPSR_MSEL(IP15_23_20,\tMSIOF1_SCK_A,\t\tSEL_MSIOF1_0),\n+\tPINMUX_IPSR_MSEL(IP15_23_20,\tTS_SDAT0_A,\t\tSEL_TSIF0_0),\n+\tPINMUX_IPSR_MSEL(IP15_23_20,\tSTP_ISD_0_A,\t\tSEL_SSP1_0_0),\n+\tPINMUX_IPSR_MSEL(IP15_23_20,\tRIF0_CLK_A,\t\tSEL_DRIF0_0),\n+\tPINMUX_IPSR_MSEL(IP15_23_20,\tRIF2_CLK_A,\t\tSEL_DRIF2_0),\n+\n+\tPINMUX_IPSR_GPSR(IP15_27_24,\tSSI_WS4),\n+\tPINMUX_IPSR_MSEL(IP15_27_24,\tHTX2_A,\t\t\tSEL_HSCIF2_0),\n+\tPINMUX_IPSR_MSEL(IP15_27_24,\tMSIOF1_SYNC_A,\t\tSEL_MSIOF1_0),\n+\tPINMUX_IPSR_MSEL(IP15_27_24,\tTS_SDEN0_A,\t\tSEL_TSIF0_0),\n+\tPINMUX_IPSR_MSEL(IP15_27_24,\tSTP_ISEN_0_A,\t\tSEL_SSP1_0_0),\n+\tPINMUX_IPSR_MSEL(IP15_27_24,\tRIF0_SYNC_A,\t\tSEL_DRIF0_0),\n+\tPINMUX_IPSR_MSEL(IP15_27_24,\tRIF2_SYNC_A,\t\tSEL_DRIF2_0),\n+\n+\tPINMUX_IPSR_GPSR(IP15_31_28,\tSSI_SDATA4),\n+\tPINMUX_IPSR_MSEL(IP15_31_28,\tHSCK2_A,\t\tSEL_HSCIF2_0),\n+\tPINMUX_IPSR_MSEL(IP15_31_28,\tMSIOF1_RXD_A,\t\tSEL_MSIOF1_0),\n+\tPINMUX_IPSR_MSEL(IP15_31_28,\tTS_SPSYNC0_A,\t\tSEL_TSIF0_0),\n+\tPINMUX_IPSR_MSEL(IP15_31_28,\tSTP_ISSYNC_0_A,\t\tSEL_SSP1_0_0),\n+\tPINMUX_IPSR_MSEL(IP15_31_28,\tRIF0_D0_A,\t\tSEL_DRIF0_0),\n+\tPINMUX_IPSR_MSEL(IP15_31_28,\tRIF2_D1_A,\t\tSEL_DRIF2_0),\n+\n+\t/* IPSR16 */\n+\tPINMUX_IPSR_GPSR(IP16_3_0,\tSSI_SCK6),\n+\tPINMUX_IPSR_MSEL(IP16_3_0,\tSIM0_RST_D,\t\tSEL_SIMCARD_3),\n+\n+\tPINMUX_IPSR_GPSR(IP16_7_4,\tSSI_WS6),\n+\tPINMUX_IPSR_MSEL(IP16_7_4,\tSIM0_D_D,\t\tSEL_SIMCARD_3),\n+\n+\tPINMUX_IPSR_GPSR(IP16_11_8,\tSSI_SDATA6),\n+\tPINMUX_IPSR_MSEL(IP16_11_8,\tSIM0_CLK_D,\t\tSEL_SIMCARD_3),\n+\n+\tPINMUX_IPSR_GPSR(IP16_15_12,\tSSI_SCK78),\n+\tPINMUX_IPSR_MSEL(IP16_15_12,\tHRX2_B,\t\t\tSEL_HSCIF2_1),\n+\tPINMUX_IPSR_MSEL(IP16_15_12,\tMSIOF1_SCK_C,\t\tSEL_MSIOF1_2),\n+\tPINMUX_IPSR_MSEL(IP16_15_12,\tTS_SCK1_A,\t\tSEL_TSIF1_0),\n+\tPINMUX_IPSR_MSEL(IP16_15_12,\tSTP_ISCLK_1_A,\t\tSEL_SSP1_1_0),\n+\tPINMUX_IPSR_MSEL(IP16_15_12,\tRIF1_CLK_A,\t\tSEL_DRIF1_0),\n+\tPINMUX_IPSR_MSEL(IP16_15_12,\tRIF3_CLK_A,\t\tSEL_DRIF3_0),\n+\n+\tPINMUX_IPSR_GPSR(IP16_19_16,\tSSI_WS78),\n+\tPINMUX_IPSR_MSEL(IP16_19_16,\tHTX2_B,\t\t\tSEL_HSCIF2_1),\n+\tPINMUX_IPSR_MSEL(IP16_19_16,\tMSIOF1_SYNC_C,\t\tSEL_MSIOF1_2),\n+\tPINMUX_IPSR_MSEL(IP16_19_16,\tTS_SDAT1_A,\t\tSEL_TSIF1_0),\n+\tPINMUX_IPSR_MSEL(IP16_19_16,\tSTP_ISD_1_A,\t\tSEL_SSP1_1_0),\n+\tPINMUX_IPSR_MSEL(IP16_19_16,\tRIF1_SYNC_A,\t\tSEL_DRIF1_0),\n+\tPINMUX_IPSR_MSEL(IP16_19_16,\tRIF3_SYNC_A,\t\tSEL_DRIF3_0),\n+\n+\tPINMUX_IPSR_GPSR(IP16_23_20,\tSSI_SDATA7),\n+\tPINMUX_IPSR_MSEL(IP16_23_20,\tHCTS2_N_B,\t\tSEL_HSCIF2_1),\n+\tPINMUX_IPSR_MSEL(IP16_23_20,\tMSIOF1_RXD_C,\t\tSEL_MSIOF1_2),\n+\tPINMUX_IPSR_MSEL(IP16_23_20,\tTS_SDEN1_A,\t\tSEL_TSIF1_0),\n+\tPINMUX_IPSR_MSEL(IP16_23_20,\tSTP_ISEN_1_A,\t\tSEL_SSP1_1_0),\n+\tPINMUX_IPSR_MSEL(IP16_23_20,\tRIF1_D0_A,\t\tSEL_DRIF1_0),\n+\tPINMUX_IPSR_MSEL(IP16_23_20,\tRIF3_D0_A,\t\tSEL_DRIF3_0),\n+\tPINMUX_IPSR_MSEL(IP16_23_20,\tTCLK2_A,\t\tSEL_TIMER_TMU2_0),\n+\n+\tPINMUX_IPSR_GPSR(IP16_27_24,\tSSI_SDATA8),\n+\tPINMUX_IPSR_MSEL(IP16_27_24,\tHRTS2_N_B,\t\tSEL_HSCIF2_1),\n+\tPINMUX_IPSR_MSEL(IP16_27_24,\tMSIOF1_TXD_C,\t\tSEL_MSIOF1_2),\n+\tPINMUX_IPSR_MSEL(IP16_27_24,\tTS_SPSYNC1_A,\t\tSEL_TSIF1_0),\n+\tPINMUX_IPSR_MSEL(IP16_27_24,\tSTP_ISSYNC_1_A,\t\tSEL_SSP1_1_0),\n+\tPINMUX_IPSR_MSEL(IP16_27_24,\tRIF1_D1_A,\t\tSEL_DRIF1_0),\n+\tPINMUX_IPSR_MSEL(IP16_27_24,\tRIF3_D1_A,\t\tSEL_DRIF3_0),\n+\n+\tPINMUX_IPSR_MSEL(IP16_31_28,\tSSI_SDATA9_A,\t\tSEL_SSI_0),\n+\tPINMUX_IPSR_MSEL(IP16_31_28,\tHSCK2_B,\t\tSEL_HSCIF2_1),\n+\tPINMUX_IPSR_MSEL(IP16_31_28,\tMSIOF1_SS1_C,\t\tSEL_MSIOF1_2),\n+\tPINMUX_IPSR_MSEL(IP16_31_28,\tHSCK1_A,\t\tSEL_HSCIF1_0),\n+\tPINMUX_IPSR_MSEL(IP16_31_28,\tSSI_WS1_B,\t\tSEL_SSI_1),\n+\tPINMUX_IPSR_GPSR(IP16_31_28,\tSCK1),\n+\tPINMUX_IPSR_MSEL(IP16_31_28,\tSTP_IVCXO27_1_A,\tSEL_SSP1_1_0),\n+\tPINMUX_IPSR_MSEL(IP16_31_28,\tSCK5_A,\t\t\tSEL_SCIF5_0),\n+\n+\t/* IPSR17 */\n+\tPINMUX_IPSR_MSEL(IP17_3_0,\tAUDIO_CLKA_A,\t\tSEL_ADG_A_0),\n+\tPINMUX_IPSR_GPSR(IP17_3_0,\tCC5_OSCOUT),\n+\n+\tPINMUX_IPSR_MSEL(IP17_7_4,\tAUDIO_CLKB_B,\t\tSEL_ADG_B_1),\n+\tPINMUX_IPSR_MSEL(IP17_7_4,\tSCIF_CLK_A,\t\tSEL_SCIF_0),\n+\tPINMUX_IPSR_MSEL(IP17_7_4,\tSTP_IVCXO27_1_D,\tSEL_SSP1_1_3),\n+\tPINMUX_IPSR_MSEL(IP17_7_4,\tREMOCON_A,\t\tSEL_REMOCON_0),\n+\tPINMUX_IPSR_MSEL(IP17_7_4,\tTCLK1_A,\t\tSEL_TIMER_TMU_0),\n+\n+\tPINMUX_IPSR_GPSR(IP17_11_8,\tUSB0_PWEN),\n+\tPINMUX_IPSR_MSEL(IP17_11_8,\tSIM0_RST_C,\t\tSEL_SIMCARD_2),\n+\tPINMUX_IPSR_MSEL(IP17_11_8,\tTS_SCK1_D,\t\tSEL_TSIF1_3),\n+\tPINMUX_IPSR_MSEL(IP17_11_8,\tSTP_ISCLK_1_D,\t\tSEL_SSP1_1_3),\n+\tPINMUX_IPSR_MSEL(IP17_11_8,\tBPFCLK_B,\t\tSEL_FM_1),\n+\tPINMUX_IPSR_MSEL(IP17_11_8,\tRIF3_CLK_B,\t\tSEL_DRIF3_1),\n+\tPINMUX_IPSR_MSEL(IP17_11_8,\tHSCK2_C,\t\tSEL_HSCIF2_2),\n+\n+\tPINMUX_IPSR_GPSR(IP17_15_12,\tUSB0_OVC),\n+\tPINMUX_IPSR_MSEL(IP17_15_12,\tSIM0_D_C,\t\tSEL_SIMCARD_2),\n+\tPINMUX_IPSR_MSEL(IP17_15_12,\tTS_SDAT1_D,\t\tSEL_TSIF1_3),\n+\tPINMUX_IPSR_MSEL(IP17_15_12,\tSTP_ISD_1_D,\t\tSEL_SSP1_1_3),\n+\tPINMUX_IPSR_MSEL(IP17_15_12,\tRIF3_SYNC_B,\t\tSEL_DRIF3_1),\n+\tPINMUX_IPSR_MSEL(IP17_15_12,\tHRX2_C,\t\t\tSEL_HSCIF2_2),\n+\n+\tPINMUX_IPSR_GPSR(IP17_19_16,\tUSB1_PWEN),\n+\tPINMUX_IPSR_MSEL(IP17_19_16,\tSIM0_CLK_C,\t\tSEL_SIMCARD_2),\n+\tPINMUX_IPSR_MSEL(IP17_19_16,\tSSI_SCK1_A,\t\tSEL_SSI_0),\n+\tPINMUX_IPSR_MSEL(IP17_19_16,\tTS_SCK0_E,\t\tSEL_TSIF0_4),\n+\tPINMUX_IPSR_MSEL(IP17_19_16,\tSTP_ISCLK_0_E,\t\tSEL_SSP1_0_4),\n+\tPINMUX_IPSR_MSEL(IP17_19_16,\tFMCLK_B,\t\tSEL_FM_1),\n+\tPINMUX_IPSR_MSEL(IP17_19_16,\tRIF2_CLK_B,\t\tSEL_DRIF2_1),\n+\tPINMUX_IPSR_MSEL(IP17_19_16,\tSPEEDIN_A,\t\tSEL_SPEED_PULSE_0),\n+\tPINMUX_IPSR_MSEL(IP17_19_16,\tHTX2_C,\t\t\tSEL_HSCIF2_2),\n+\n+\tPINMUX_IPSR_GPSR(IP17_23_20,\tUSB1_OVC),\n+\tPINMUX_IPSR_MSEL(IP17_23_20,\tMSIOF1_SS2_C,\t\tSEL_MSIOF1_2),\n+\tPINMUX_IPSR_MSEL(IP17_23_20,\tSSI_WS1_A,\t\tSEL_SSI_0),\n+\tPINMUX_IPSR_MSEL(IP17_23_20,\tTS_SDAT0_E,\t\tSEL_TSIF0_4),\n+\tPINMUX_IPSR_MSEL(IP17_23_20,\tSTP_ISD_0_E,\t\tSEL_SSP1_0_4),\n+\tPINMUX_IPSR_MSEL(IP17_23_20,\tFMIN_B,\t\t\tSEL_FM_1),\n+\tPINMUX_IPSR_MSEL(IP17_23_20,\tRIF2_SYNC_B,\t\tSEL_DRIF2_1),\n+\tPINMUX_IPSR_MSEL(IP17_23_20,\tREMOCON_B,\t\tSEL_REMOCON_1),\n+\tPINMUX_IPSR_MSEL(IP17_23_20,\tHCTS2_N_C,\t\tSEL_HSCIF2_2),\n+\n+\tPINMUX_IPSR_GPSR(IP17_27_24,\tUSB30_PWEN),\n+\tPINMUX_IPSR_GPSR(IP17_27_24,\tAUDIO_CLKOUT_B),\n+\tPINMUX_IPSR_MSEL(IP17_27_24,\tSSI_SCK2_B,\t\tSEL_SSI_1),\n+\tPINMUX_IPSR_MSEL(IP17_27_24,\tTS_SDEN1_D,\t\tSEL_TSIF1_3),\n+\tPINMUX_IPSR_MSEL(IP17_27_24,\tSTP_ISEN_1_D,\t\tSEL_SSP1_1_3),\n+\tPINMUX_IPSR_MSEL(IP17_27_24,\tSTP_OPWM_0_E,\t\tSEL_SSP1_0_4),\n+\tPINMUX_IPSR_MSEL(IP17_27_24,\tRIF3_D0_B,\t\tSEL_DRIF3_1),\n+\tPINMUX_IPSR_MSEL(IP17_27_24,\tTCLK2_B,\t\tSEL_TIMER_TMU2_1),\n+\tPINMUX_IPSR_GPSR(IP17_27_24,\tTPU0TO0),\n+\tPINMUX_IPSR_MSEL(IP17_27_24,\tBPFCLK_C,\t\tSEL_FM_2),\n+\tPINMUX_IPSR_MSEL(IP17_27_24,\tHRTS2_N_C,\t\tSEL_HSCIF2_2),\n+\n+\tPINMUX_IPSR_GPSR(IP17_31_28,\tUSB30_OVC),\n+\tPINMUX_IPSR_GPSR(IP17_31_28,\tAUDIO_CLKOUT1_B),\n+\tPINMUX_IPSR_MSEL(IP17_31_28,\tSSI_WS2_B,\t\tSEL_SSI_1),\n+\tPINMUX_IPSR_MSEL(IP17_31_28,\tTS_SPSYNC1_D,\t\tSEL_TSIF1_3),\n+\tPINMUX_IPSR_MSEL(IP17_31_28,\tSTP_ISSYNC_1_D,\t\tSEL_SSP1_1_3),\n+\tPINMUX_IPSR_MSEL(IP17_31_28,\tSTP_IVCXO27_0_E,\tSEL_SSP1_0_4),\n+\tPINMUX_IPSR_MSEL(IP17_31_28,\tRIF3_D1_B,\t\tSEL_DRIF3_1),\n+\tPINMUX_IPSR_GPSR(IP17_31_28,\tFSO_TOE_N),\n+\tPINMUX_IPSR_GPSR(IP17_31_28,\tTPU0TO1),\n+\n+\t/* IPSR18 */\n+\tPINMUX_IPSR_GPSR(IP18_3_0,\tGP6_30),\n+\tPINMUX_IPSR_GPSR(IP18_3_0,\tAUDIO_CLKOUT2_B),\n+\tPINMUX_IPSR_MSEL(IP18_3_0,\tSSI_SCK9_B,\t\tSEL_SSI_1),\n+\tPINMUX_IPSR_MSEL(IP18_3_0,\tTS_SDEN0_E,\t\tSEL_TSIF0_4),\n+\tPINMUX_IPSR_MSEL(IP18_3_0,\tSTP_ISEN_0_E,\t\tSEL_SSP1_0_4),\n+\tPINMUX_IPSR_MSEL(IP18_3_0,\tRIF2_D0_B,\t\tSEL_DRIF2_1),\n+\tPINMUX_IPSR_GPSR(IP18_3_0,\tTPU0TO2),\n+\tPINMUX_IPSR_MSEL(IP18_3_0,\tFMCLK_C,\t\tSEL_FM_2),\n+\tPINMUX_IPSR_MSEL(IP18_3_0,\tFMCLK_D,\t\tSEL_FM_3),\n+\n+\tPINMUX_IPSR_GPSR(IP18_7_4,\tGP6_31),\n+\tPINMUX_IPSR_GPSR(IP18_7_4,\tAUDIO_CLKOUT3_B),\n+\tPINMUX_IPSR_MSEL(IP18_7_4,\tSSI_WS9_B,\t\tSEL_SSI_1),\n+\tPINMUX_IPSR_MSEL(IP18_7_4,\tTS_SPSYNC0_E,\t\tSEL_TSIF0_4),\n+\tPINMUX_IPSR_MSEL(IP18_7_4,\tSTP_ISSYNC_0_E,\t\tSEL_SSP1_0_4),\n+\tPINMUX_IPSR_MSEL(IP18_7_4,\tRIF2_D1_B,\t\tSEL_DRIF2_1),\n+\tPINMUX_IPSR_GPSR(IP18_7_4,\tTPU0TO3),\n+\tPINMUX_IPSR_MSEL(IP18_7_4,\tFMIN_C,\t\t\tSEL_FM_2),\n+\tPINMUX_IPSR_MSEL(IP18_7_4,\tFMIN_D,\t\t\tSEL_FM_3),\n+\n+\t/* I2C */\n+\tPINMUX_IPSR_NOGP(0,\t\tI2C_SEL_0_1),\n+\tPINMUX_IPSR_NOGP(0,\t\tI2C_SEL_3_1),\n+\tPINMUX_IPSR_NOGP(0,\t\tI2C_SEL_5_1),\n+\n+/*\n+ * Static pins can not be muxed between different functions but\n+ * still needs a mark entry in the pinmux list. Add each static\n+ * pin to the list without an associated function. The sh-pfc\n+ * core will do the right thing and skip trying to mux then pin\n+ * while still applying configuration to it\n+ */\n+#define FM(x)   PINMUX_DATA(x##_MARK, 0),\n+\tPINMUX_STATIC\n+#undef FM\n+};\n+\n+/*\n+ * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.\n+ * Physical layout rows: A - AW, cols: 1 - 39.\n+ */\n+#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))\n+#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)\n+#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)\n+\n+static const struct sh_pfc_pin pinmux_pins[] = {\n+\tPINMUX_GPIO_GP_ALL(),\n+\n+\t/*\n+\t * Pins not associated with a GPIO port.\n+\t *\n+\t * The pin positions are different between different r8a7796\n+\t * packages, all that is needed for the pfc driver is a unique\n+\t * number for each pin. To this end use the pin layout from\n+\t * R-Car M3SiP to calculate a unique number for each pin.\n+\t */\n+\tSH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN2, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),\n+\tSH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),\n+};\n+\n+/* - AUDIO CLOCK ------------------------------------------------------------ */\n+static const unsigned int audio_clk_a_a_pins[] = {\n+\t/* CLK A */\n+\tRCAR_GP_PIN(6, 22),\n+};\n+static const unsigned int audio_clk_a_a_mux[] = {\n+\tAUDIO_CLKA_A_MARK,\n+};\n+static const unsigned int audio_clk_a_b_pins[] = {\n+\t/* CLK A */\n+\tRCAR_GP_PIN(5, 4),\n+};\n+static const unsigned int audio_clk_a_b_mux[] = {\n+\tAUDIO_CLKA_B_MARK,\n+};\n+static const unsigned int audio_clk_a_c_pins[] = {\n+\t/* CLK A */\n+\tRCAR_GP_PIN(5, 19),\n+};\n+static const unsigned int audio_clk_a_c_mux[] = {\n+\tAUDIO_CLKA_C_MARK,\n+};\n+static const unsigned int audio_clk_b_a_pins[] = {\n+\t/* CLK B */\n+\tRCAR_GP_PIN(5, 12),\n+};\n+static const unsigned int audio_clk_b_a_mux[] = {\n+\tAUDIO_CLKB_A_MARK,\n+};\n+static const unsigned int audio_clk_b_b_pins[] = {\n+\t/* CLK B */\n+\tRCAR_GP_PIN(6, 23),\n+};\n+static const unsigned int audio_clk_b_b_mux[] = {\n+\tAUDIO_CLKB_B_MARK,\n+};\n+static const unsigned int audio_clk_c_a_pins[] = {\n+\t/* CLK C */\n+\tRCAR_GP_PIN(5, 21),\n+};\n+static const unsigned int audio_clk_c_a_mux[] = {\n+\tAUDIO_CLKC_A_MARK,\n+};\n+static const unsigned int audio_clk_c_b_pins[] = {\n+\t/* CLK C */\n+\tRCAR_GP_PIN(5, 0),\n+};\n+static const unsigned int audio_clk_c_b_mux[] = {\n+\tAUDIO_CLKC_B_MARK,\n+};\n+static const unsigned int audio_clkout_a_pins[] = {\n+\t/* CLKOUT */\n+\tRCAR_GP_PIN(5, 18),\n+};\n+static const unsigned int audio_clkout_a_mux[] = {\n+\tAUDIO_CLKOUT_A_MARK,\n+};\n+static const unsigned int audio_clkout_b_pins[] = {\n+\t/* CLKOUT */\n+\tRCAR_GP_PIN(6, 28),\n+};\n+static const unsigned int audio_clkout_b_mux[] = {\n+\tAUDIO_CLKOUT_B_MARK,\n+};\n+static const unsigned int audio_clkout_c_pins[] = {\n+\t/* CLKOUT */\n+\tRCAR_GP_PIN(5, 3),\n+};\n+static const unsigned int audio_clkout_c_mux[] = {\n+\tAUDIO_CLKOUT_C_MARK,\n+};\n+static const unsigned int audio_clkout_d_pins[] = {\n+\t/* CLKOUT */\n+\tRCAR_GP_PIN(5, 21),\n+};\n+static const unsigned int audio_clkout_d_mux[] = {\n+\tAUDIO_CLKOUT_D_MARK,\n+};\n+static const unsigned int audio_clkout1_a_pins[] = {\n+\t/* CLKOUT1 */\n+\tRCAR_GP_PIN(5, 15),\n+};\n+static const unsigned int audio_clkout1_a_mux[] = {\n+\tAUDIO_CLKOUT1_A_MARK,\n+};\n+static const unsigned int audio_clkout1_b_pins[] = {\n+\t/* CLKOUT1 */\n+\tRCAR_GP_PIN(6, 29),\n+};\n+static const unsigned int audio_clkout1_b_mux[] = {\n+\tAUDIO_CLKOUT1_B_MARK,\n+};\n+static const unsigned int audio_clkout2_a_pins[] = {\n+\t/* CLKOUT2 */\n+\tRCAR_GP_PIN(5, 16),\n+};\n+static const unsigned int audio_clkout2_a_mux[] = {\n+\tAUDIO_CLKOUT2_A_MARK,\n+};\n+static const unsigned int audio_clkout2_b_pins[] = {\n+\t/* CLKOUT2 */\n+\tRCAR_GP_PIN(6, 30),\n+};\n+static const unsigned int audio_clkout2_b_mux[] = {\n+\tAUDIO_CLKOUT2_B_MARK,\n+};\n+\n+static const unsigned int audio_clkout3_a_pins[] = {\n+\t/* CLKOUT3 */\n+\tRCAR_GP_PIN(5, 19),\n+};\n+static const unsigned int audio_clkout3_a_mux[] = {\n+\tAUDIO_CLKOUT3_A_MARK,\n+};\n+static const unsigned int audio_clkout3_b_pins[] = {\n+\t/* CLKOUT3 */\n+\tRCAR_GP_PIN(6, 31),\n+};\n+static const unsigned int audio_clkout3_b_mux[] = {\n+\tAUDIO_CLKOUT3_B_MARK,\n+};\n+\n+/* - EtherAVB --------------------------------------------------------------- */\n+static const unsigned int avb_link_pins[] = {\n+\t/* AVB_LINK */\n+\tRCAR_GP_PIN(2, 12),\n+};\n+static const unsigned int avb_link_mux[] = {\n+\tAVB_LINK_MARK,\n+};\n+static const unsigned int avb_magic_pins[] = {\n+\t/* AVB_MAGIC_ */\n+\tRCAR_GP_PIN(2, 10),\n+};\n+static const unsigned int avb_magic_mux[] = {\n+\tAVB_MAGIC_MARK,\n+};\n+static const unsigned int avb_phy_int_pins[] = {\n+\t/* AVB_PHY_INT */\n+\tRCAR_GP_PIN(2, 11),\n+};\n+static const unsigned int avb_phy_int_mux[] = {\n+\tAVB_PHY_INT_MARK,\n+};\n+static const unsigned int avb_mdc_pins[] = {\n+\t/* AVB_MDC, AVB_MDIO */\n+\tRCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),\n+};\n+static const unsigned int avb_mdc_mux[] = {\n+\tAVB_MDC_MARK, AVB_MDIO_MARK,\n+};\n+static const unsigned int avb_mii_pins[] = {\n+\t/*\n+\t * AVB_TX_CTL, AVB_TXC, AVB_TD0,\n+\t * AVB_TD1, AVB_TD2, AVB_TD3,\n+\t * AVB_RX_CTL, AVB_RXC, AVB_RD0,\n+\t * AVB_RD1, AVB_RD2, AVB_RD3,\n+\t * AVB_TXCREFCLK\n+\t */\n+\tPIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),\n+\tPIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),\n+\tPIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),\n+\tPIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),\n+\tPIN_NUMBER('A', 12),\n+\n+};\n+static const unsigned int avb_mii_mux[] = {\n+\tAVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,\n+\tAVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,\n+\tAVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,\n+\tAVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,\n+\tAVB_TXCREFCLK_MARK,\n+};\n+static const unsigned int avb_avtp_pps_pins[] = {\n+\t/* AVB_AVTP_PPS */\n+\tRCAR_GP_PIN(2, 6),\n+};\n+static const unsigned int avb_avtp_pps_mux[] = {\n+\tAVB_AVTP_PPS_MARK,\n+};\n+static const unsigned int avb_avtp_match_a_pins[] = {\n+\t/* AVB_AVTP_MATCH_A */\n+\tRCAR_GP_PIN(2, 13),\n+};\n+static const unsigned int avb_avtp_match_a_mux[] = {\n+\tAVB_AVTP_MATCH_A_MARK,\n+};\n+static const unsigned int avb_avtp_capture_a_pins[] = {\n+\t/* AVB_AVTP_CAPTURE_A */\n+\tRCAR_GP_PIN(2, 14),\n+};\n+static const unsigned int avb_avtp_capture_a_mux[] = {\n+\tAVB_AVTP_CAPTURE_A_MARK,\n+};\n+static const unsigned int avb_avtp_match_b_pins[] = {\n+\t/*  AVB_AVTP_MATCH_B */\n+\tRCAR_GP_PIN(1, 8),\n+};\n+static const unsigned int avb_avtp_match_b_mux[] = {\n+\tAVB_AVTP_MATCH_B_MARK,\n+};\n+static const unsigned int avb_avtp_capture_b_pins[] = {\n+\t/* AVB_AVTP_CAPTURE_B */\n+\tRCAR_GP_PIN(1, 11),\n+};\n+static const unsigned int avb_avtp_capture_b_mux[] = {\n+\tAVB_AVTP_CAPTURE_B_MARK,\n+};\n+\n+/* - CAN ------------------------------------------------------------------ */\n+static const unsigned int can0_data_a_pins[] = {\n+\t/* TX, RX */\n+\tRCAR_GP_PIN(1, 23),\tRCAR_GP_PIN(1, 24),\n+};\n+static const unsigned int can0_data_a_mux[] = {\n+\tCAN0_TX_A_MARK,\t\tCAN0_RX_A_MARK,\n+};\n+static const unsigned int can0_data_b_pins[] = {\n+\t/* TX, RX */\n+\tRCAR_GP_PIN(2, 0),\tRCAR_GP_PIN(2, 1),\n+};\n+static const unsigned int can0_data_b_mux[] = {\n+\tCAN0_TX_B_MARK,\t\tCAN0_RX_B_MARK,\n+};\n+static const unsigned int can1_data_pins[] = {\n+\t/* TX, RX */\n+\tRCAR_GP_PIN(1, 22),\tRCAR_GP_PIN(1, 26),\n+};\n+static const unsigned int can1_data_mux[] = {\n+\tCAN1_TX_MARK,\t\tCAN1_RX_MARK,\n+};\n+\n+/* - CAN Clock -------------------------------------------------------------- */\n+static const unsigned int can_clk_pins[] = {\n+\t/* CLK */\n+\tRCAR_GP_PIN(1, 25),\n+};\n+static const unsigned int can_clk_mux[] = {\n+\tCAN_CLK_MARK,\n+};\n+\n+/* - CAN FD --------------------------------------------------------------- */\n+static const unsigned int canfd0_data_a_pins[] = {\n+\t/* TX, RX */\n+\tRCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),\n+};\n+static const unsigned int canfd0_data_a_mux[] = {\n+\tCANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,\n+};\n+static const unsigned int canfd0_data_b_pins[] = {\n+\t/* TX, RX */\n+\tRCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),\n+};\n+static const unsigned int canfd0_data_b_mux[] = {\n+\tCANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,\n+};\n+static const unsigned int canfd1_data_pins[] = {\n+\t/* TX, RX */\n+\tRCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),\n+};\n+static const unsigned int canfd1_data_mux[] = {\n+\tCANFD1_TX_MARK,         CANFD1_RX_MARK,\n+};\n+\n+/* - DRIF0 --------------------------------------------------------------- */\n+static const unsigned int drif0_ctrl_a_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),\n+};\n+static const unsigned int drif0_ctrl_a_mux[] = {\n+\tRIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,\n+};\n+static const unsigned int drif0_data0_a_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(6, 10),\n+};\n+static const unsigned int drif0_data0_a_mux[] = {\n+\tRIF0_D0_A_MARK,\n+};\n+static const unsigned int drif0_data1_a_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(6, 7),\n+};\n+static const unsigned int drif0_data1_a_mux[] = {\n+\tRIF0_D1_A_MARK,\n+};\n+static const unsigned int drif0_ctrl_b_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),\n+};\n+static const unsigned int drif0_ctrl_b_mux[] = {\n+\tRIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,\n+};\n+static const unsigned int drif0_data0_b_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(5, 1),\n+};\n+static const unsigned int drif0_data0_b_mux[] = {\n+\tRIF0_D0_B_MARK,\n+};\n+static const unsigned int drif0_data1_b_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(5, 2),\n+};\n+static const unsigned int drif0_data1_b_mux[] = {\n+\tRIF0_D1_B_MARK,\n+};\n+static const unsigned int drif0_ctrl_c_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),\n+};\n+static const unsigned int drif0_ctrl_c_mux[] = {\n+\tRIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,\n+};\n+static const unsigned int drif0_data0_c_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(5, 13),\n+};\n+static const unsigned int drif0_data0_c_mux[] = {\n+\tRIF0_D0_C_MARK,\n+};\n+static const unsigned int drif0_data1_c_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(5, 14),\n+};\n+static const unsigned int drif0_data1_c_mux[] = {\n+\tRIF0_D1_C_MARK,\n+};\n+/* - DRIF1 --------------------------------------------------------------- */\n+static const unsigned int drif1_ctrl_a_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),\n+};\n+static const unsigned int drif1_ctrl_a_mux[] = {\n+\tRIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,\n+};\n+static const unsigned int drif1_data0_a_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(6, 19),\n+};\n+static const unsigned int drif1_data0_a_mux[] = {\n+\tRIF1_D0_A_MARK,\n+};\n+static const unsigned int drif1_data1_a_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(6, 20),\n+};\n+static const unsigned int drif1_data1_a_mux[] = {\n+\tRIF1_D1_A_MARK,\n+};\n+static const unsigned int drif1_ctrl_b_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),\n+};\n+static const unsigned int drif1_ctrl_b_mux[] = {\n+\tRIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,\n+};\n+static const unsigned int drif1_data0_b_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(5, 7),\n+};\n+static const unsigned int drif1_data0_b_mux[] = {\n+\tRIF1_D0_B_MARK,\n+};\n+static const unsigned int drif1_data1_b_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(5, 8),\n+};\n+static const unsigned int drif1_data1_b_mux[] = {\n+\tRIF1_D1_B_MARK,\n+};\n+static const unsigned int drif1_ctrl_c_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),\n+};\n+static const unsigned int drif1_ctrl_c_mux[] = {\n+\tRIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,\n+};\n+static const unsigned int drif1_data0_c_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(5, 6),\n+};\n+static const unsigned int drif1_data0_c_mux[] = {\n+\tRIF1_D0_C_MARK,\n+};\n+static const unsigned int drif1_data1_c_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(5, 10),\n+};\n+static const unsigned int drif1_data1_c_mux[] = {\n+\tRIF1_D1_C_MARK,\n+};\n+/* - DRIF2 --------------------------------------------------------------- */\n+static const unsigned int drif2_ctrl_a_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),\n+};\n+static const unsigned int drif2_ctrl_a_mux[] = {\n+\tRIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,\n+};\n+static const unsigned int drif2_data0_a_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(6, 7),\n+};\n+static const unsigned int drif2_data0_a_mux[] = {\n+\tRIF2_D0_A_MARK,\n+};\n+static const unsigned int drif2_data1_a_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(6, 10),\n+};\n+static const unsigned int drif2_data1_a_mux[] = {\n+\tRIF2_D1_A_MARK,\n+};\n+static const unsigned int drif2_ctrl_b_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),\n+};\n+static const unsigned int drif2_ctrl_b_mux[] = {\n+\tRIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,\n+};\n+static const unsigned int drif2_data0_b_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(6, 30),\n+};\n+static const unsigned int drif2_data0_b_mux[] = {\n+\tRIF2_D0_B_MARK,\n+};\n+static const unsigned int drif2_data1_b_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(6, 31),\n+};\n+static const unsigned int drif2_data1_b_mux[] = {\n+\tRIF2_D1_B_MARK,\n+};\n+/* - DRIF3 --------------------------------------------------------------- */\n+static const unsigned int drif3_ctrl_a_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),\n+};\n+static const unsigned int drif3_ctrl_a_mux[] = {\n+\tRIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,\n+};\n+static const unsigned int drif3_data0_a_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(6, 19),\n+};\n+static const unsigned int drif3_data0_a_mux[] = {\n+\tRIF3_D0_A_MARK,\n+};\n+static const unsigned int drif3_data1_a_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(6, 20),\n+};\n+static const unsigned int drif3_data1_a_mux[] = {\n+\tRIF3_D1_A_MARK,\n+};\n+static const unsigned int drif3_ctrl_b_pins[] = {\n+\t/* CLK, SYNC */\n+\tRCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),\n+};\n+static const unsigned int drif3_ctrl_b_mux[] = {\n+\tRIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,\n+};\n+static const unsigned int drif3_data0_b_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(6, 28),\n+};\n+static const unsigned int drif3_data0_b_mux[] = {\n+\tRIF3_D0_B_MARK,\n+};\n+static const unsigned int drif3_data1_b_pins[] = {\n+\t/* D1 */\n+\tRCAR_GP_PIN(6, 29),\n+};\n+static const unsigned int drif3_data1_b_mux[] = {\n+\tRIF3_D1_B_MARK,\n+};\n+\n+/* - DU --------------------------------------------------------------------- */\n+static const unsigned int du_rgb666_pins[] = {\n+\t/* R[7:2], G[7:2], B[7:2] */\n+\tRCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),\n+\tRCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),\n+\tRCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),\n+\tRCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),\n+\tRCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),\n+\tRCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),\n+};\n+static const unsigned int du_rgb666_mux[] = {\n+\tDU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,\n+\tDU_DR3_MARK, DU_DR2_MARK,\n+\tDU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,\n+\tDU_DG3_MARK, DU_DG2_MARK,\n+\tDU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,\n+\tDU_DB3_MARK, DU_DB2_MARK,\n+};\n+static const unsigned int du_rgb888_pins[] = {\n+\t/* R[7:0], G[7:0], B[7:0] */\n+\tRCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),\n+\tRCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),\n+\tRCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),\n+\tRCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),\n+\tRCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),\n+\tRCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),\n+\tRCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),\n+\tRCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),\n+\tRCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),\n+};\n+static const unsigned int du_rgb888_mux[] = {\n+\tDU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,\n+\tDU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,\n+\tDU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,\n+\tDU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,\n+\tDU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,\n+\tDU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,\n+};\n+static const unsigned int du_clk_out_0_pins[] = {\n+\t/* CLKOUT */\n+\tRCAR_GP_PIN(1, 27),\n+};\n+static const unsigned int du_clk_out_0_mux[] = {\n+\tDU_DOTCLKOUT0_MARK\n+};\n+static const unsigned int du_clk_out_1_pins[] = {\n+\t/* CLKOUT */\n+\tRCAR_GP_PIN(2, 3),\n+};\n+static const unsigned int du_clk_out_1_mux[] = {\n+\tDU_DOTCLKOUT1_MARK\n+};\n+static const unsigned int du_sync_pins[] = {\n+\t/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */\n+\tRCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),\n+};\n+static const unsigned int du_sync_mux[] = {\n+\tDU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK\n+};\n+static const unsigned int du_oddf_pins[] = {\n+\t/* EXDISP/EXODDF/EXCDE */\n+\tRCAR_GP_PIN(2, 2),\n+};\n+static const unsigned int du_oddf_mux[] = {\n+\tDU_EXODDF_DU_ODDF_DISP_CDE_MARK,\n+};\n+static const unsigned int du_cde_pins[] = {\n+\t/* CDE */\n+\tRCAR_GP_PIN(2, 0),\n+};\n+static const unsigned int du_cde_mux[] = {\n+\tDU_CDE_MARK,\n+};\n+static const unsigned int du_disp_pins[] = {\n+\t/* DISP */\n+\tRCAR_GP_PIN(2, 1),\n+};\n+static const unsigned int du_disp_mux[] = {\n+\tDU_DISP_MARK,\n+};\n+\n+/* - HSCIF0 ----------------------------------------------------------------- */\n+static const unsigned int hscif0_data_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),\n+};\n+static const unsigned int hscif0_data_mux[] = {\n+\tHRX0_MARK, HTX0_MARK,\n+};\n+static const unsigned int hscif0_clk_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(5, 12),\n+};\n+static const unsigned int hscif0_clk_mux[] = {\n+\tHSCK0_MARK,\n+};\n+static const unsigned int hscif0_ctrl_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),\n+};\n+static const unsigned int hscif0_ctrl_mux[] = {\n+\tHRTS0_N_MARK, HCTS0_N_MARK,\n+};\n+/* - HSCIF1 ----------------------------------------------------------------- */\n+static const unsigned int hscif1_data_a_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),\n+};\n+static const unsigned int hscif1_data_a_mux[] = {\n+\tHRX1_A_MARK, HTX1_A_MARK,\n+};\n+static const unsigned int hscif1_clk_a_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(6, 21),\n+};\n+static const unsigned int hscif1_clk_a_mux[] = {\n+\tHSCK1_A_MARK,\n+};\n+static const unsigned int hscif1_ctrl_a_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),\n+};\n+static const unsigned int hscif1_ctrl_a_mux[] = {\n+\tHRTS1_N_A_MARK, HCTS1_N_A_MARK,\n+};\n+\n+static const unsigned int hscif1_data_b_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),\n+};\n+static const unsigned int hscif1_data_b_mux[] = {\n+\tHRX1_B_MARK, HTX1_B_MARK,\n+};\n+static const unsigned int hscif1_clk_b_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(5, 0),\n+};\n+static const unsigned int hscif1_clk_b_mux[] = {\n+\tHSCK1_B_MARK,\n+};\n+static const unsigned int hscif1_ctrl_b_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),\n+};\n+static const unsigned int hscif1_ctrl_b_mux[] = {\n+\tHRTS1_N_B_MARK, HCTS1_N_B_MARK,\n+};\n+/* - HSCIF2 ----------------------------------------------------------------- */\n+static const unsigned int hscif2_data_a_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),\n+};\n+static const unsigned int hscif2_data_a_mux[] = {\n+\tHRX2_A_MARK, HTX2_A_MARK,\n+};\n+static const unsigned int hscif2_clk_a_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(6, 10),\n+};\n+static const unsigned int hscif2_clk_a_mux[] = {\n+\tHSCK2_A_MARK,\n+};\n+static const unsigned int hscif2_ctrl_a_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),\n+};\n+static const unsigned int hscif2_ctrl_a_mux[] = {\n+\tHRTS2_N_A_MARK, HCTS2_N_A_MARK,\n+};\n+\n+static const unsigned int hscif2_data_b_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),\n+};\n+static const unsigned int hscif2_data_b_mux[] = {\n+\tHRX2_B_MARK, HTX2_B_MARK,\n+};\n+static const unsigned int hscif2_clk_b_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(6, 21),\n+};\n+static const unsigned int hscif2_clk_b_mux[] = {\n+\tHSCK2_B_MARK,\n+};\n+static const unsigned int hscif2_ctrl_b_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),\n+};\n+static const unsigned int hscif2_ctrl_b_mux[] = {\n+\tHRTS2_N_B_MARK, HCTS2_N_B_MARK,\n+};\n+\n+static const unsigned int hscif2_data_c_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),\n+};\n+static const unsigned int hscif2_data_c_mux[] = {\n+\tHRX2_C_MARK, HTX2_C_MARK,\n+};\n+static const unsigned int hscif2_clk_c_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(6, 24),\n+};\n+static const unsigned int hscif2_clk_c_mux[] = {\n+\tHSCK2_C_MARK,\n+};\n+static const unsigned int hscif2_ctrl_c_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),\n+};\n+static const unsigned int hscif2_ctrl_c_mux[] = {\n+\tHRTS2_N_C_MARK, HCTS2_N_C_MARK,\n+};\n+/* - HSCIF3 ----------------------------------------------------------------- */\n+static const unsigned int hscif3_data_a_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),\n+};\n+static const unsigned int hscif3_data_a_mux[] = {\n+\tHRX3_A_MARK, HTX3_A_MARK,\n+};\n+static const unsigned int hscif3_clk_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(1, 22),\n+};\n+static const unsigned int hscif3_clk_mux[] = {\n+\tHSCK3_MARK,\n+};\n+static const unsigned int hscif3_ctrl_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),\n+};\n+static const unsigned int hscif3_ctrl_mux[] = {\n+\tHRTS3_N_MARK, HCTS3_N_MARK,\n+};\n+\n+static const unsigned int hscif3_data_b_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),\n+};\n+static const unsigned int hscif3_data_b_mux[] = {\n+\tHRX3_B_MARK, HTX3_B_MARK,\n+};\n+static const unsigned int hscif3_data_c_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),\n+};\n+static const unsigned int hscif3_data_c_mux[] = {\n+\tHRX3_C_MARK, HTX3_C_MARK,\n+};\n+static const unsigned int hscif3_data_d_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),\n+};\n+static const unsigned int hscif3_data_d_mux[] = {\n+\tHRX3_D_MARK, HTX3_D_MARK,\n+};\n+/* - HSCIF4 ----------------------------------------------------------------- */\n+static const unsigned int hscif4_data_a_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),\n+};\n+static const unsigned int hscif4_data_a_mux[] = {\n+\tHRX4_A_MARK, HTX4_A_MARK,\n+};\n+static const unsigned int hscif4_clk_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(1, 11),\n+};\n+static const unsigned int hscif4_clk_mux[] = {\n+\tHSCK4_MARK,\n+};\n+static const unsigned int hscif4_ctrl_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),\n+};\n+static const unsigned int hscif4_ctrl_mux[] = {\n+\tHRTS4_N_MARK, HCTS4_N_MARK,\n+};\n+\n+static const unsigned int hscif4_data_b_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),\n+};\n+static const unsigned int hscif4_data_b_mux[] = {\n+\tHRX4_B_MARK, HTX4_B_MARK,\n+};\n+\n+/* - I2C -------------------------------------------------------------------- */\n+static const unsigned int i2c1_a_pins[] = {\n+\t/* SDA, SCL */\n+\tRCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),\n+};\n+static const unsigned int i2c1_a_mux[] = {\n+\tSDA1_A_MARK, SCL1_A_MARK,\n+};\n+static const unsigned int i2c1_b_pins[] = {\n+\t/* SDA, SCL */\n+\tRCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),\n+};\n+static const unsigned int i2c1_b_mux[] = {\n+\tSDA1_B_MARK, SCL1_B_MARK,\n+};\n+static const unsigned int i2c2_a_pins[] = {\n+\t/* SDA, SCL */\n+\tRCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),\n+};\n+static const unsigned int i2c2_a_mux[] = {\n+\tSDA2_A_MARK, SCL2_A_MARK,\n+};\n+static const unsigned int i2c2_b_pins[] = {\n+\t/* SDA, SCL */\n+\tRCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),\n+};\n+static const unsigned int i2c2_b_mux[] = {\n+\tSDA2_B_MARK, SCL2_B_MARK,\n+};\n+static const unsigned int i2c6_a_pins[] = {\n+\t/* SDA, SCL */\n+\tRCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),\n+};\n+static const unsigned int i2c6_a_mux[] = {\n+\tSDA6_A_MARK, SCL6_A_MARK,\n+};\n+static const unsigned int i2c6_b_pins[] = {\n+\t/* SDA, SCL */\n+\tRCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),\n+};\n+static const unsigned int i2c6_b_mux[] = {\n+\tSDA6_B_MARK, SCL6_B_MARK,\n+};\n+static const unsigned int i2c6_c_pins[] = {\n+\t/* SDA, SCL */\n+\tRCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),\n+};\n+static const unsigned int i2c6_c_mux[] = {\n+\tSDA6_C_MARK, SCL6_C_MARK,\n+};\n+\n+/* - MSIOF0 ----------------------------------------------------------------- */\n+static const unsigned int msiof0_clk_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(5, 17),\n+};\n+static const unsigned int msiof0_clk_mux[] = {\n+\tMSIOF0_SCK_MARK,\n+};\n+static const unsigned int msiof0_sync_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(5, 18),\n+};\n+static const unsigned int msiof0_sync_mux[] = {\n+\tMSIOF0_SYNC_MARK,\n+};\n+static const unsigned int msiof0_ss1_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(5, 19),\n+};\n+static const unsigned int msiof0_ss1_mux[] = {\n+\tMSIOF0_SS1_MARK,\n+};\n+static const unsigned int msiof0_ss2_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(5, 21),\n+};\n+static const unsigned int msiof0_ss2_mux[] = {\n+\tMSIOF0_SS2_MARK,\n+};\n+static const unsigned int msiof0_txd_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(5, 20),\n+};\n+static const unsigned int msiof0_txd_mux[] = {\n+\tMSIOF0_TXD_MARK,\n+};\n+static const unsigned int msiof0_rxd_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(5, 22),\n+};\n+static const unsigned int msiof0_rxd_mux[] = {\n+\tMSIOF0_RXD_MARK,\n+};\n+/* - MSIOF1 ----------------------------------------------------------------- */\n+static const unsigned int msiof1_clk_a_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(6, 8),\n+};\n+static const unsigned int msiof1_clk_a_mux[] = {\n+\tMSIOF1_SCK_A_MARK,\n+};\n+static const unsigned int msiof1_sync_a_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(6, 9),\n+};\n+static const unsigned int msiof1_sync_a_mux[] = {\n+\tMSIOF1_SYNC_A_MARK,\n+};\n+static const unsigned int msiof1_ss1_a_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(6, 5),\n+};\n+static const unsigned int msiof1_ss1_a_mux[] = {\n+\tMSIOF1_SS1_A_MARK,\n+};\n+static const unsigned int msiof1_ss2_a_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(6, 6),\n+};\n+static const unsigned int msiof1_ss2_a_mux[] = {\n+\tMSIOF1_SS2_A_MARK,\n+};\n+static const unsigned int msiof1_txd_a_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(6, 7),\n+};\n+static const unsigned int msiof1_txd_a_mux[] = {\n+\tMSIOF1_TXD_A_MARK,\n+};\n+static const unsigned int msiof1_rxd_a_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(6, 10),\n+};\n+static const unsigned int msiof1_rxd_a_mux[] = {\n+\tMSIOF1_RXD_A_MARK,\n+};\n+static const unsigned int msiof1_clk_b_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(5, 9),\n+};\n+static const unsigned int msiof1_clk_b_mux[] = {\n+\tMSIOF1_SCK_B_MARK,\n+};\n+static const unsigned int msiof1_sync_b_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(5, 3),\n+};\n+static const unsigned int msiof1_sync_b_mux[] = {\n+\tMSIOF1_SYNC_B_MARK,\n+};\n+static const unsigned int msiof1_ss1_b_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(5, 4),\n+};\n+static const unsigned int msiof1_ss1_b_mux[] = {\n+\tMSIOF1_SS1_B_MARK,\n+};\n+static const unsigned int msiof1_ss2_b_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(5, 0),\n+};\n+static const unsigned int msiof1_ss2_b_mux[] = {\n+\tMSIOF1_SS2_B_MARK,\n+};\n+static const unsigned int msiof1_txd_b_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(5, 8),\n+};\n+static const unsigned int msiof1_txd_b_mux[] = {\n+\tMSIOF1_TXD_B_MARK,\n+};\n+static const unsigned int msiof1_rxd_b_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(5, 7),\n+};\n+static const unsigned int msiof1_rxd_b_mux[] = {\n+\tMSIOF1_RXD_B_MARK,\n+};\n+static const unsigned int msiof1_clk_c_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(6, 17),\n+};\n+static const unsigned int msiof1_clk_c_mux[] = {\n+\tMSIOF1_SCK_C_MARK,\n+};\n+static const unsigned int msiof1_sync_c_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(6, 18),\n+};\n+static const unsigned int msiof1_sync_c_mux[] = {\n+\tMSIOF1_SYNC_C_MARK,\n+};\n+static const unsigned int msiof1_ss1_c_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(6, 21),\n+};\n+static const unsigned int msiof1_ss1_c_mux[] = {\n+\tMSIOF1_SS1_C_MARK,\n+};\n+static const unsigned int msiof1_ss2_c_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(6, 27),\n+};\n+static const unsigned int msiof1_ss2_c_mux[] = {\n+\tMSIOF1_SS2_C_MARK,\n+};\n+static const unsigned int msiof1_txd_c_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(6, 20),\n+};\n+static const unsigned int msiof1_txd_c_mux[] = {\n+\tMSIOF1_TXD_C_MARK,\n+};\n+static const unsigned int msiof1_rxd_c_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(6, 19),\n+};\n+static const unsigned int msiof1_rxd_c_mux[] = {\n+\tMSIOF1_RXD_C_MARK,\n+};\n+static const unsigned int msiof1_clk_d_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(5, 12),\n+};\n+static const unsigned int msiof1_clk_d_mux[] = {\n+\tMSIOF1_SCK_D_MARK,\n+};\n+static const unsigned int msiof1_sync_d_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(5, 15),\n+};\n+static const unsigned int msiof1_sync_d_mux[] = {\n+\tMSIOF1_SYNC_D_MARK,\n+};\n+static const unsigned int msiof1_ss1_d_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(5, 16),\n+};\n+static const unsigned int msiof1_ss1_d_mux[] = {\n+\tMSIOF1_SS1_D_MARK,\n+};\n+static const unsigned int msiof1_ss2_d_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(5, 21),\n+};\n+static const unsigned int msiof1_ss2_d_mux[] = {\n+\tMSIOF1_SS2_D_MARK,\n+};\n+static const unsigned int msiof1_txd_d_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(5, 14),\n+};\n+static const unsigned int msiof1_txd_d_mux[] = {\n+\tMSIOF1_TXD_D_MARK,\n+};\n+static const unsigned int msiof1_rxd_d_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(5, 13),\n+};\n+static const unsigned int msiof1_rxd_d_mux[] = {\n+\tMSIOF1_RXD_D_MARK,\n+};\n+static const unsigned int msiof1_clk_e_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(3, 0),\n+};\n+static const unsigned int msiof1_clk_e_mux[] = {\n+\tMSIOF1_SCK_E_MARK,\n+};\n+static const unsigned int msiof1_sync_e_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(3, 1),\n+};\n+static const unsigned int msiof1_sync_e_mux[] = {\n+\tMSIOF1_SYNC_E_MARK,\n+};\n+static const unsigned int msiof1_ss1_e_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(3, 4),\n+};\n+static const unsigned int msiof1_ss1_e_mux[] = {\n+\tMSIOF1_SS1_E_MARK,\n+};\n+static const unsigned int msiof1_ss2_e_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(3, 5),\n+};\n+static const unsigned int msiof1_ss2_e_mux[] = {\n+\tMSIOF1_SS2_E_MARK,\n+};\n+static const unsigned int msiof1_txd_e_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(3, 3),\n+};\n+static const unsigned int msiof1_txd_e_mux[] = {\n+\tMSIOF1_TXD_E_MARK,\n+};\n+static const unsigned int msiof1_rxd_e_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(3, 2),\n+};\n+static const unsigned int msiof1_rxd_e_mux[] = {\n+\tMSIOF1_RXD_E_MARK,\n+};\n+static const unsigned int msiof1_clk_f_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(5, 23),\n+};\n+static const unsigned int msiof1_clk_f_mux[] = {\n+\tMSIOF1_SCK_F_MARK,\n+};\n+static const unsigned int msiof1_sync_f_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(5, 24),\n+};\n+static const unsigned int msiof1_sync_f_mux[] = {\n+\tMSIOF1_SYNC_F_MARK,\n+};\n+static const unsigned int msiof1_ss1_f_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(6, 1),\n+};\n+static const unsigned int msiof1_ss1_f_mux[] = {\n+\tMSIOF1_SS1_F_MARK,\n+};\n+static const unsigned int msiof1_ss2_f_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(6, 2),\n+};\n+static const unsigned int msiof1_ss2_f_mux[] = {\n+\tMSIOF1_SS2_F_MARK,\n+};\n+static const unsigned int msiof1_txd_f_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(6, 0),\n+};\n+static const unsigned int msiof1_txd_f_mux[] = {\n+\tMSIOF1_TXD_F_MARK,\n+};\n+static const unsigned int msiof1_rxd_f_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(5, 25),\n+};\n+static const unsigned int msiof1_rxd_f_mux[] = {\n+\tMSIOF1_RXD_F_MARK,\n+};\n+static const unsigned int msiof1_clk_g_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(3, 6),\n+};\n+static const unsigned int msiof1_clk_g_mux[] = {\n+\tMSIOF1_SCK_G_MARK,\n+};\n+static const unsigned int msiof1_sync_g_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(3, 7),\n+};\n+static const unsigned int msiof1_sync_g_mux[] = {\n+\tMSIOF1_SYNC_G_MARK,\n+};\n+static const unsigned int msiof1_ss1_g_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(3, 10),\n+};\n+static const unsigned int msiof1_ss1_g_mux[] = {\n+\tMSIOF1_SS1_G_MARK,\n+};\n+static const unsigned int msiof1_ss2_g_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(3, 11),\n+};\n+static const unsigned int msiof1_ss2_g_mux[] = {\n+\tMSIOF1_SS2_G_MARK,\n+};\n+static const unsigned int msiof1_txd_g_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(3, 9),\n+};\n+static const unsigned int msiof1_txd_g_mux[] = {\n+\tMSIOF1_TXD_G_MARK,\n+};\n+static const unsigned int msiof1_rxd_g_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(3, 8),\n+};\n+static const unsigned int msiof1_rxd_g_mux[] = {\n+\tMSIOF1_RXD_G_MARK,\n+};\n+/* - MSIOF2 ----------------------------------------------------------------- */\n+static const unsigned int msiof2_clk_a_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(1, 9),\n+};\n+static const unsigned int msiof2_clk_a_mux[] = {\n+\tMSIOF2_SCK_A_MARK,\n+};\n+static const unsigned int msiof2_sync_a_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(1, 8),\n+};\n+static const unsigned int msiof2_sync_a_mux[] = {\n+\tMSIOF2_SYNC_A_MARK,\n+};\n+static const unsigned int msiof2_ss1_a_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(1, 6),\n+};\n+static const unsigned int msiof2_ss1_a_mux[] = {\n+\tMSIOF2_SS1_A_MARK,\n+};\n+static const unsigned int msiof2_ss2_a_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(1, 7),\n+};\n+static const unsigned int msiof2_ss2_a_mux[] = {\n+\tMSIOF2_SS2_A_MARK,\n+};\n+static const unsigned int msiof2_txd_a_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(1, 11),\n+};\n+static const unsigned int msiof2_txd_a_mux[] = {\n+\tMSIOF2_TXD_A_MARK,\n+};\n+static const unsigned int msiof2_rxd_a_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(1, 10),\n+};\n+static const unsigned int msiof2_rxd_a_mux[] = {\n+\tMSIOF2_RXD_A_MARK,\n+};\n+static const unsigned int msiof2_clk_b_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(0, 4),\n+};\n+static const unsigned int msiof2_clk_b_mux[] = {\n+\tMSIOF2_SCK_B_MARK,\n+};\n+static const unsigned int msiof2_sync_b_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(0, 5),\n+};\n+static const unsigned int msiof2_sync_b_mux[] = {\n+\tMSIOF2_SYNC_B_MARK,\n+};\n+static const unsigned int msiof2_ss1_b_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(0, 0),\n+};\n+static const unsigned int msiof2_ss1_b_mux[] = {\n+\tMSIOF2_SS1_B_MARK,\n+};\n+static const unsigned int msiof2_ss2_b_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(0, 1),\n+};\n+static const unsigned int msiof2_ss2_b_mux[] = {\n+\tMSIOF2_SS2_B_MARK,\n+};\n+static const unsigned int msiof2_txd_b_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(0, 7),\n+};\n+static const unsigned int msiof2_txd_b_mux[] = {\n+\tMSIOF2_TXD_B_MARK,\n+};\n+static const unsigned int msiof2_rxd_b_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(0, 6),\n+};\n+static const unsigned int msiof2_rxd_b_mux[] = {\n+\tMSIOF2_RXD_B_MARK,\n+};\n+static const unsigned int msiof2_clk_c_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(2, 12),\n+};\n+static const unsigned int msiof2_clk_c_mux[] = {\n+\tMSIOF2_SCK_C_MARK,\n+};\n+static const unsigned int msiof2_sync_c_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(2, 11),\n+};\n+static const unsigned int msiof2_sync_c_mux[] = {\n+\tMSIOF2_SYNC_C_MARK,\n+};\n+static const unsigned int msiof2_ss1_c_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(2, 10),\n+};\n+static const unsigned int msiof2_ss1_c_mux[] = {\n+\tMSIOF2_SS1_C_MARK,\n+};\n+static const unsigned int msiof2_ss2_c_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(2, 9),\n+};\n+static const unsigned int msiof2_ss2_c_mux[] = {\n+\tMSIOF2_SS2_C_MARK,\n+};\n+static const unsigned int msiof2_txd_c_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(2, 14),\n+};\n+static const unsigned int msiof2_txd_c_mux[] = {\n+\tMSIOF2_TXD_C_MARK,\n+};\n+static const unsigned int msiof2_rxd_c_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(2, 13),\n+};\n+static const unsigned int msiof2_rxd_c_mux[] = {\n+\tMSIOF2_RXD_C_MARK,\n+};\n+static const unsigned int msiof2_clk_d_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(0, 8),\n+};\n+static const unsigned int msiof2_clk_d_mux[] = {\n+\tMSIOF2_SCK_D_MARK,\n+};\n+static const unsigned int msiof2_sync_d_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(0, 9),\n+};\n+static const unsigned int msiof2_sync_d_mux[] = {\n+\tMSIOF2_SYNC_D_MARK,\n+};\n+static const unsigned int msiof2_ss1_d_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(0, 12),\n+};\n+static const unsigned int msiof2_ss1_d_mux[] = {\n+\tMSIOF2_SS1_D_MARK,\n+};\n+static const unsigned int msiof2_ss2_d_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(0, 13),\n+};\n+static const unsigned int msiof2_ss2_d_mux[] = {\n+\tMSIOF2_SS2_D_MARK,\n+};\n+static const unsigned int msiof2_txd_d_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(0, 11),\n+};\n+static const unsigned int msiof2_txd_d_mux[] = {\n+\tMSIOF2_TXD_D_MARK,\n+};\n+static const unsigned int msiof2_rxd_d_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(0, 10),\n+};\n+static const unsigned int msiof2_rxd_d_mux[] = {\n+\tMSIOF2_RXD_D_MARK,\n+};\n+/* - MSIOF3 ----------------------------------------------------------------- */\n+static const unsigned int msiof3_clk_a_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(0, 0),\n+};\n+static const unsigned int msiof3_clk_a_mux[] = {\n+\tMSIOF3_SCK_A_MARK,\n+};\n+static const unsigned int msiof3_sync_a_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(0, 1),\n+};\n+static const unsigned int msiof3_sync_a_mux[] = {\n+\tMSIOF3_SYNC_A_MARK,\n+};\n+static const unsigned int msiof3_ss1_a_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(0, 14),\n+};\n+static const unsigned int msiof3_ss1_a_mux[] = {\n+\tMSIOF3_SS1_A_MARK,\n+};\n+static const unsigned int msiof3_ss2_a_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(0, 15),\n+};\n+static const unsigned int msiof3_ss2_a_mux[] = {\n+\tMSIOF3_SS2_A_MARK,\n+};\n+static const unsigned int msiof3_txd_a_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(0, 3),\n+};\n+static const unsigned int msiof3_txd_a_mux[] = {\n+\tMSIOF3_TXD_A_MARK,\n+};\n+static const unsigned int msiof3_rxd_a_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(0, 2),\n+};\n+static const unsigned int msiof3_rxd_a_mux[] = {\n+\tMSIOF3_RXD_A_MARK,\n+};\n+static const unsigned int msiof3_clk_b_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(1, 2),\n+};\n+static const unsigned int msiof3_clk_b_mux[] = {\n+\tMSIOF3_SCK_B_MARK,\n+};\n+static const unsigned int msiof3_sync_b_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(1, 0),\n+};\n+static const unsigned int msiof3_sync_b_mux[] = {\n+\tMSIOF3_SYNC_B_MARK,\n+};\n+static const unsigned int msiof3_ss1_b_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(1, 4),\n+};\n+static const unsigned int msiof3_ss1_b_mux[] = {\n+\tMSIOF3_SS1_B_MARK,\n+};\n+static const unsigned int msiof3_ss2_b_pins[] = {\n+\t/* SS2 */\n+\tRCAR_GP_PIN(1, 5),\n+};\n+static const unsigned int msiof3_ss2_b_mux[] = {\n+\tMSIOF3_SS2_B_MARK,\n+};\n+static const unsigned int msiof3_txd_b_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(1, 1),\n+};\n+static const unsigned int msiof3_txd_b_mux[] = {\n+\tMSIOF3_TXD_B_MARK,\n+};\n+static const unsigned int msiof3_rxd_b_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(1, 3),\n+};\n+static const unsigned int msiof3_rxd_b_mux[] = {\n+\tMSIOF3_RXD_B_MARK,\n+};\n+static const unsigned int msiof3_clk_c_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(1, 12),\n+};\n+static const unsigned int msiof3_clk_c_mux[] = {\n+\tMSIOF3_SCK_C_MARK,\n+};\n+static const unsigned int msiof3_sync_c_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(1, 13),\n+};\n+static const unsigned int msiof3_sync_c_mux[] = {\n+\tMSIOF3_SYNC_C_MARK,\n+};\n+static const unsigned int msiof3_txd_c_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(1, 15),\n+};\n+static const unsigned int msiof3_txd_c_mux[] = {\n+\tMSIOF3_TXD_C_MARK,\n+};\n+static const unsigned int msiof3_rxd_c_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(1, 14),\n+};\n+static const unsigned int msiof3_rxd_c_mux[] = {\n+\tMSIOF3_RXD_C_MARK,\n+};\n+static const unsigned int msiof3_clk_d_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(1, 22),\n+};\n+static const unsigned int msiof3_clk_d_mux[] = {\n+\tMSIOF3_SCK_D_MARK,\n+};\n+static const unsigned int msiof3_sync_d_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(1, 23),\n+};\n+static const unsigned int msiof3_sync_d_mux[] = {\n+\tMSIOF3_SYNC_D_MARK,\n+};\n+static const unsigned int msiof3_ss1_d_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(1, 26),\n+};\n+static const unsigned int msiof3_ss1_d_mux[] = {\n+\tMSIOF3_SS1_D_MARK,\n+};\n+static const unsigned int msiof3_txd_d_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(1, 25),\n+};\n+static const unsigned int msiof3_txd_d_mux[] = {\n+\tMSIOF3_TXD_D_MARK,\n+};\n+static const unsigned int msiof3_rxd_d_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(1, 24),\n+};\n+static const unsigned int msiof3_rxd_d_mux[] = {\n+\tMSIOF3_RXD_D_MARK,\n+};\n+\n+static const unsigned int msiof3_clk_e_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(2, 3),\n+};\n+static const unsigned int msiof3_clk_e_mux[] = {\n+\tMSIOF3_SCK_E_MARK,\n+};\n+static const unsigned int msiof3_sync_e_pins[] = {\n+\t/* SYNC */\n+\tRCAR_GP_PIN(2, 2),\n+};\n+static const unsigned int msiof3_sync_e_mux[] = {\n+\tMSIOF3_SYNC_E_MARK,\n+};\n+static const unsigned int msiof3_ss1_e_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(2, 1),\n+};\n+static const unsigned int msiof3_ss1_e_mux[] = {\n+\tMSIOF3_SS1_E_MARK,\n+};\n+static const unsigned int msiof3_ss2_e_pins[] = {\n+\t/* SS1 */\n+\tRCAR_GP_PIN(2, 0),\n+};\n+static const unsigned int msiof3_ss2_e_mux[] = {\n+\tMSIOF3_SS2_E_MARK,\n+};\n+static const unsigned int msiof3_txd_e_pins[] = {\n+\t/* TXD */\n+\tRCAR_GP_PIN(2, 5),\n+};\n+static const unsigned int msiof3_txd_e_mux[] = {\n+\tMSIOF3_TXD_E_MARK,\n+};\n+static const unsigned int msiof3_rxd_e_pins[] = {\n+\t/* RXD */\n+\tRCAR_GP_PIN(2, 4),\n+};\n+static const unsigned int msiof3_rxd_e_mux[] = {\n+\tMSIOF3_RXD_E_MARK,\n+};\n+\n+/* - PWM0 --------------------------------------------------------------------*/\n+static const unsigned int pwm0_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(2, 6),\n+};\n+static const unsigned int pwm0_mux[] = {\n+\tPWM0_MARK,\n+};\n+/* - PWM1 --------------------------------------------------------------------*/\n+static const unsigned int pwm1_a_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(2, 7),\n+};\n+static const unsigned int pwm1_a_mux[] = {\n+\tPWM1_A_MARK,\n+};\n+static const unsigned int pwm1_b_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(1, 8),\n+};\n+static const unsigned int pwm1_b_mux[] = {\n+\tPWM1_B_MARK,\n+};\n+/* - PWM2 --------------------------------------------------------------------*/\n+static const unsigned int pwm2_a_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(2, 8),\n+};\n+static const unsigned int pwm2_a_mux[] = {\n+\tPWM2_A_MARK,\n+};\n+static const unsigned int pwm2_b_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(1, 11),\n+};\n+static const unsigned int pwm2_b_mux[] = {\n+\tPWM2_B_MARK,\n+};\n+/* - PWM3 --------------------------------------------------------------------*/\n+static const unsigned int pwm3_a_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(1, 0),\n+};\n+static const unsigned int pwm3_a_mux[] = {\n+\tPWM3_A_MARK,\n+};\n+static const unsigned int pwm3_b_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(2, 2),\n+};\n+static const unsigned int pwm3_b_mux[] = {\n+\tPWM3_B_MARK,\n+};\n+/* - PWM4 --------------------------------------------------------------------*/\n+static const unsigned int pwm4_a_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(1, 1),\n+};\n+static const unsigned int pwm4_a_mux[] = {\n+\tPWM4_A_MARK,\n+};\n+static const unsigned int pwm4_b_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(2, 3),\n+};\n+static const unsigned int pwm4_b_mux[] = {\n+\tPWM4_B_MARK,\n+};\n+/* - PWM5 --------------------------------------------------------------------*/\n+static const unsigned int pwm5_a_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(1, 2),\n+};\n+static const unsigned int pwm5_a_mux[] = {\n+\tPWM5_A_MARK,\n+};\n+static const unsigned int pwm5_b_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(2, 4),\n+};\n+static const unsigned int pwm5_b_mux[] = {\n+\tPWM5_B_MARK,\n+};\n+/* - PWM6 --------------------------------------------------------------------*/\n+static const unsigned int pwm6_a_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(1, 3),\n+};\n+static const unsigned int pwm6_a_mux[] = {\n+\tPWM6_A_MARK,\n+};\n+static const unsigned int pwm6_b_pins[] = {\n+\t/* PWM */\n+\tRCAR_GP_PIN(2, 5),\n+};\n+static const unsigned int pwm6_b_mux[] = {\n+\tPWM6_B_MARK,\n+};\n+\n+/* - SCIF0 ------------------------------------------------------------------ */\n+static const unsigned int scif0_data_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),\n+};\n+static const unsigned int scif0_data_mux[] = {\n+\tRX0_MARK, TX0_MARK,\n+};\n+static const unsigned int scif0_clk_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(5, 0),\n+};\n+static const unsigned int scif0_clk_mux[] = {\n+\tSCK0_MARK,\n+};\n+static const unsigned int scif0_ctrl_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),\n+};\n+static const unsigned int scif0_ctrl_mux[] = {\n+\tRTS0_N_TANS_MARK, CTS0_N_MARK,\n+};\n+/* - SCIF1 ------------------------------------------------------------------ */\n+static const unsigned int scif1_data_a_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),\n+};\n+static const unsigned int scif1_data_a_mux[] = {\n+\tRX1_A_MARK, TX1_A_MARK,\n+};\n+static const unsigned int scif1_clk_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(6, 21),\n+};\n+static const unsigned int scif1_clk_mux[] = {\n+\tSCK1_MARK,\n+};\n+static const unsigned int scif1_ctrl_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),\n+};\n+static const unsigned int scif1_ctrl_mux[] = {\n+\tRTS1_N_TANS_MARK, CTS1_N_MARK,\n+};\n+\n+static const unsigned int scif1_data_b_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),\n+};\n+static const unsigned int scif1_data_b_mux[] = {\n+\tRX1_B_MARK, TX1_B_MARK,\n+};\n+/* - SCIF2 ------------------------------------------------------------------ */\n+static const unsigned int scif2_data_a_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),\n+};\n+static const unsigned int scif2_data_a_mux[] = {\n+\tRX2_A_MARK, TX2_A_MARK,\n+};\n+static const unsigned int scif2_clk_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(5, 9),\n+};\n+static const unsigned int scif2_clk_mux[] = {\n+\tSCK2_MARK,\n+};\n+static const unsigned int scif2_data_b_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),\n+};\n+static const unsigned int scif2_data_b_mux[] = {\n+\tRX2_B_MARK, TX2_B_MARK,\n+};\n+/* - SCIF3 ------------------------------------------------------------------ */\n+static const unsigned int scif3_data_a_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),\n+};\n+static const unsigned int scif3_data_a_mux[] = {\n+\tRX3_A_MARK, TX3_A_MARK,\n+};\n+static const unsigned int scif3_clk_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(1, 22),\n+};\n+static const unsigned int scif3_clk_mux[] = {\n+\tSCK3_MARK,\n+};\n+static const unsigned int scif3_ctrl_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),\n+};\n+static const unsigned int scif3_ctrl_mux[] = {\n+\tRTS3_N_TANS_MARK, CTS3_N_MARK,\n+};\n+static const unsigned int scif3_data_b_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),\n+};\n+static const unsigned int scif3_data_b_mux[] = {\n+\tRX3_B_MARK, TX3_B_MARK,\n+};\n+/* - SCIF4 ------------------------------------------------------------------ */\n+static const unsigned int scif4_data_a_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),\n+};\n+static const unsigned int scif4_data_a_mux[] = {\n+\tRX4_A_MARK, TX4_A_MARK,\n+};\n+static const unsigned int scif4_clk_a_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(2, 10),\n+};\n+static const unsigned int scif4_clk_a_mux[] = {\n+\tSCK4_A_MARK,\n+};\n+static const unsigned int scif4_ctrl_a_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),\n+};\n+static const unsigned int scif4_ctrl_a_mux[] = {\n+\tRTS4_N_TANS_A_MARK, CTS4_N_A_MARK,\n+};\n+static const unsigned int scif4_data_b_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),\n+};\n+static const unsigned int scif4_data_b_mux[] = {\n+\tRX4_B_MARK, TX4_B_MARK,\n+};\n+static const unsigned int scif4_clk_b_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(1, 5),\n+};\n+static const unsigned int scif4_clk_b_mux[] = {\n+\tSCK4_B_MARK,\n+};\n+static const unsigned int scif4_ctrl_b_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),\n+};\n+static const unsigned int scif4_ctrl_b_mux[] = {\n+\tRTS4_N_TANS_B_MARK, CTS4_N_B_MARK,\n+};\n+static const unsigned int scif4_data_c_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),\n+};\n+static const unsigned int scif4_data_c_mux[] = {\n+\tRX4_C_MARK, TX4_C_MARK,\n+};\n+static const unsigned int scif4_clk_c_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(0, 8),\n+};\n+static const unsigned int scif4_clk_c_mux[] = {\n+\tSCK4_C_MARK,\n+};\n+static const unsigned int scif4_ctrl_c_pins[] = {\n+\t/* RTS, CTS */\n+\tRCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),\n+};\n+static const unsigned int scif4_ctrl_c_mux[] = {\n+\tRTS4_N_TANS_C_MARK, CTS4_N_C_MARK,\n+};\n+/* - SCIF5 ------------------------------------------------------------------ */\n+static const unsigned int scif5_data_a_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),\n+};\n+static const unsigned int scif5_data_a_mux[] = {\n+\tRX5_A_MARK, TX5_A_MARK,\n+};\n+static const unsigned int scif5_clk_a_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(6, 21),\n+};\n+static const unsigned int scif5_clk_a_mux[] = {\n+\tSCK5_A_MARK,\n+};\n+\n+static const unsigned int scif5_data_b_pins[] = {\n+\t/* RX, TX */\n+\tRCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),\n+};\n+static const unsigned int scif5_data_b_mux[] = {\n+\tRX5_B_MARK, TX5_B_MARK,\n+};\n+static const unsigned int scif5_clk_b_pins[] = {\n+\t/* SCK */\n+\tRCAR_GP_PIN(5, 0),\n+};\n+static const unsigned int scif5_clk_b_mux[] = {\n+\tSCK5_B_MARK,\n+};\n+\n+/* - SCIF Clock ------------------------------------------------------------- */\n+static const unsigned int scif_clk_a_pins[] = {\n+\t/* SCIF_CLK */\n+\tRCAR_GP_PIN(6, 23),\n+};\n+static const unsigned int scif_clk_a_mux[] = {\n+\tSCIF_CLK_A_MARK,\n+};\n+static const unsigned int scif_clk_b_pins[] = {\n+\t/* SCIF_CLK */\n+\tRCAR_GP_PIN(5, 9),\n+};\n+static const unsigned int scif_clk_b_mux[] = {\n+\tSCIF_CLK_B_MARK,\n+};\n+\n+/* - SDHI0 ------------------------------------------------------------------ */\n+static const unsigned int sdhi0_data1_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(3, 2),\n+};\n+static const unsigned int sdhi0_data1_mux[] = {\n+\tSD0_DAT0_MARK,\n+};\n+static const unsigned int sdhi0_data4_pins[] = {\n+\t/* D[0:3] */\n+\tRCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),\n+\tRCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),\n+};\n+static const unsigned int sdhi0_data4_mux[] = {\n+\tSD0_DAT0_MARK, SD0_DAT1_MARK,\n+\tSD0_DAT2_MARK, SD0_DAT3_MARK,\n+};\n+static const unsigned int sdhi0_ctrl_pins[] = {\n+\t/* CLK, CMD */\n+\tRCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),\n+};\n+static const unsigned int sdhi0_ctrl_mux[] = {\n+\tSD0_CLK_MARK, SD0_CMD_MARK,\n+};\n+static const unsigned int sdhi0_cd_pins[] = {\n+\t/* CD */\n+\tRCAR_GP_PIN(3, 12),\n+};\n+static const unsigned int sdhi0_cd_mux[] = {\n+\tSD0_CD_MARK,\n+};\n+static const unsigned int sdhi0_wp_pins[] = {\n+\t/* WP */\n+\tRCAR_GP_PIN(3, 13),\n+};\n+static const unsigned int sdhi0_wp_mux[] = {\n+\tSD0_WP_MARK,\n+};\n+/* - SDHI1 ------------------------------------------------------------------ */\n+static const unsigned int sdhi1_data1_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(3, 8),\n+};\n+static const unsigned int sdhi1_data1_mux[] = {\n+\tSD1_DAT0_MARK,\n+};\n+static const unsigned int sdhi1_data4_pins[] = {\n+\t/* D[0:3] */\n+\tRCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),\n+\tRCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),\n+};\n+static const unsigned int sdhi1_data4_mux[] = {\n+\tSD1_DAT0_MARK, SD1_DAT1_MARK,\n+\tSD1_DAT2_MARK, SD1_DAT3_MARK,\n+};\n+static const unsigned int sdhi1_ctrl_pins[] = {\n+\t/* CLK, CMD */\n+\tRCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),\n+};\n+static const unsigned int sdhi1_ctrl_mux[] = {\n+\tSD1_CLK_MARK, SD1_CMD_MARK,\n+};\n+static const unsigned int sdhi1_cd_pins[] = {\n+\t/* CD */\n+\tRCAR_GP_PIN(3, 14),\n+};\n+static const unsigned int sdhi1_cd_mux[] = {\n+\tSD1_CD_MARK,\n+};\n+static const unsigned int sdhi1_wp_pins[] = {\n+\t/* WP */\n+\tRCAR_GP_PIN(3, 15),\n+};\n+static const unsigned int sdhi1_wp_mux[] = {\n+\tSD1_WP_MARK,\n+};\n+/* - SDHI2 ------------------------------------------------------------------ */\n+static const unsigned int sdhi2_data1_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(4, 2),\n+};\n+static const unsigned int sdhi2_data1_mux[] = {\n+\tSD2_DAT0_MARK,\n+};\n+static const unsigned int sdhi2_data4_pins[] = {\n+\t/* D[0:3] */\n+\tRCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),\n+\tRCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),\n+};\n+static const unsigned int sdhi2_data4_mux[] = {\n+\tSD2_DAT0_MARK, SD2_DAT1_MARK,\n+\tSD2_DAT2_MARK, SD2_DAT3_MARK,\n+};\n+static const unsigned int sdhi2_data8_pins[] = {\n+\t/* D[0:7] */\n+\tRCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),\n+\tRCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),\n+\tRCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),\n+\tRCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),\n+};\n+static const unsigned int sdhi2_data8_mux[] = {\n+\tSD2_DAT0_MARK, SD2_DAT1_MARK,\n+\tSD2_DAT2_MARK, SD2_DAT3_MARK,\n+\tSD2_DAT4_MARK, SD2_DAT5_MARK,\n+\tSD2_DAT6_MARK, SD2_DAT7_MARK,\n+};\n+static const unsigned int sdhi2_ctrl_pins[] = {\n+\t/* CLK, CMD */\n+\tRCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),\n+};\n+static const unsigned int sdhi2_ctrl_mux[] = {\n+\tSD2_CLK_MARK, SD2_CMD_MARK,\n+};\n+static const unsigned int sdhi2_cd_a_pins[] = {\n+\t/* CD */\n+\tRCAR_GP_PIN(4, 13),\n+};\n+static const unsigned int sdhi2_cd_a_mux[] = {\n+\tSD2_CD_A_MARK,\n+};\n+static const unsigned int sdhi2_cd_b_pins[] = {\n+\t/* CD */\n+\tRCAR_GP_PIN(5, 10),\n+};\n+static const unsigned int sdhi2_cd_b_mux[] = {\n+\tSD2_CD_B_MARK,\n+};\n+static const unsigned int sdhi2_wp_a_pins[] = {\n+\t/* WP */\n+\tRCAR_GP_PIN(4, 14),\n+};\n+static const unsigned int sdhi2_wp_a_mux[] = {\n+\tSD2_WP_A_MARK,\n+};\n+static const unsigned int sdhi2_wp_b_pins[] = {\n+\t/* WP */\n+\tRCAR_GP_PIN(5, 11),\n+};\n+static const unsigned int sdhi2_wp_b_mux[] = {\n+\tSD2_WP_B_MARK,\n+};\n+static const unsigned int sdhi2_ds_pins[] = {\n+\t/* DS */\n+\tRCAR_GP_PIN(4, 6),\n+};\n+static const unsigned int sdhi2_ds_mux[] = {\n+\tSD2_DS_MARK,\n+};\n+/* - SDHI3 ------------------------------------------------------------------ */\n+static const unsigned int sdhi3_data1_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(4, 9),\n+};\n+static const unsigned int sdhi3_data1_mux[] = {\n+\tSD3_DAT0_MARK,\n+};\n+static const unsigned int sdhi3_data4_pins[] = {\n+\t/* D[0:3] */\n+\tRCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),\n+\tRCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),\n+};\n+static const unsigned int sdhi3_data4_mux[] = {\n+\tSD3_DAT0_MARK, SD3_DAT1_MARK,\n+\tSD3_DAT2_MARK, SD3_DAT3_MARK,\n+};\n+static const unsigned int sdhi3_data8_pins[] = {\n+\t/* D[0:7] */\n+\tRCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),\n+\tRCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),\n+\tRCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),\n+\tRCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),\n+};\n+static const unsigned int sdhi3_data8_mux[] = {\n+\tSD3_DAT0_MARK, SD3_DAT1_MARK,\n+\tSD3_DAT2_MARK, SD3_DAT3_MARK,\n+\tSD3_DAT4_MARK, SD3_DAT5_MARK,\n+\tSD3_DAT6_MARK, SD3_DAT7_MARK,\n+};\n+static const unsigned int sdhi3_ctrl_pins[] = {\n+\t/* CLK, CMD */\n+\tRCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),\n+};\n+static const unsigned int sdhi3_ctrl_mux[] = {\n+\tSD3_CLK_MARK, SD3_CMD_MARK,\n+};\n+static const unsigned int sdhi3_cd_pins[] = {\n+\t/* CD */\n+\tRCAR_GP_PIN(4, 15),\n+};\n+static const unsigned int sdhi3_cd_mux[] = {\n+\tSD3_CD_MARK,\n+};\n+static const unsigned int sdhi3_wp_pins[] = {\n+\t/* WP */\n+\tRCAR_GP_PIN(4, 16),\n+};\n+static const unsigned int sdhi3_wp_mux[] = {\n+\tSD3_WP_MARK,\n+};\n+static const unsigned int sdhi3_ds_pins[] = {\n+\t/* DS */\n+\tRCAR_GP_PIN(4, 17),\n+};\n+static const unsigned int sdhi3_ds_mux[] = {\n+\tSD3_DS_MARK,\n+};\n+\n+/* - SSI -------------------------------------------------------------------- */\n+static const unsigned int ssi0_data_pins[] = {\n+\t/* SDATA */\n+\tRCAR_GP_PIN(6, 2),\n+};\n+static const unsigned int ssi0_data_mux[] = {\n+\tSSI_SDATA0_MARK,\n+};\n+static const unsigned int ssi01239_ctrl_pins[] = {\n+\t/* SCK, WS */\n+\tRCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),\n+};\n+static const unsigned int ssi01239_ctrl_mux[] = {\n+\tSSI_SCK01239_MARK, SSI_WS01239_MARK,\n+};\n+static const unsigned int ssi1_data_a_pins[] = {\n+\t/* SDATA */\n+\tRCAR_GP_PIN(6, 3),\n+};\n+static const unsigned int ssi1_data_a_mux[] = {\n+\tSSI_SDATA1_A_MARK,\n+};\n+static const unsigned int ssi1_data_b_pins[] = {\n+\t/* SDATA */\n+\tRCAR_GP_PIN(5, 12),\n+};\n+static const unsigned int ssi1_data_b_mux[] = {\n+\tSSI_SDATA1_B_MARK,\n+};\n+static const unsigned int ssi1_ctrl_a_pins[] = {\n+\t/* SCK, WS */\n+\tRCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),\n+};\n+static const unsigned int ssi1_ctrl_a_mux[] = {\n+\tSSI_SCK1_A_MARK, SSI_WS1_A_MARK,\n+};\n+static const unsigned int ssi1_ctrl_b_pins[] = {\n+\t/* SCK, WS */\n+\tRCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),\n+};\n+static const unsigned int ssi1_ctrl_b_mux[] = {\n+\tSSI_SCK1_B_MARK, SSI_WS1_B_MARK,\n+};\n+static const unsigned int ssi2_data_a_pins[] = {\n+\t/* SDATA */\n+\tRCAR_GP_PIN(6, 4),\n+};\n+static const unsigned int ssi2_data_a_mux[] = {\n+\tSSI_SDATA2_A_MARK,\n+};\n+static const unsigned int ssi2_data_b_pins[] = {\n+\t/* SDATA */\n+\tRCAR_GP_PIN(5, 13),\n+};\n+static const unsigned int ssi2_data_b_mux[] = {\n+\tSSI_SDATA2_B_MARK,\n+};\n+static const unsigned int ssi2_ctrl_a_pins[] = {\n+\t/* SCK, WS */\n+\tRCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),\n+};\n+static const unsigned int ssi2_ctrl_a_mux[] = {\n+\tSSI_SCK2_A_MARK, SSI_WS2_A_MARK,\n+};\n+static const unsigned int ssi2_ctrl_b_pins[] = {\n+\t/* SCK, WS */\n+\tRCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),\n+};\n+static const unsigned int ssi2_ctrl_b_mux[] = {\n+\tSSI_SCK2_B_MARK, SSI_WS2_B_MARK,\n+};\n+static const unsigned int ssi3_data_pins[] = {\n+\t/* SDATA */\n+\tRCAR_GP_PIN(6, 7),\n+};\n+static const unsigned int ssi3_data_mux[] = {\n+\tSSI_SDATA3_MARK,\n+};\n+static const unsigned int ssi349_ctrl_pins[] = {\n+\t/* SCK, WS */\n+\tRCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),\n+};\n+static const unsigned int ssi349_ctrl_mux[] = {\n+\tSSI_SCK349_MARK, SSI_WS349_MARK,\n+};\n+static const unsigned int ssi4_data_pins[] = {\n+\t/* SDATA */\n+\tRCAR_GP_PIN(6, 10),\n+};\n+static const unsigned int ssi4_data_mux[] = {\n+\tSSI_SDATA4_MARK,\n+};\n+static const unsigned int ssi4_ctrl_pins[] = {\n+\t/* SCK, WS */\n+\tRCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),\n+};\n+static const unsigned int ssi4_ctrl_mux[] = {\n+\tSSI_SCK4_MARK, SSI_WS4_MARK,\n+};\n+static const unsigned int ssi5_data_pins[] = {\n+\t/* SDATA */\n+\tRCAR_GP_PIN(6, 13),\n+};\n+static const unsigned int ssi5_data_mux[] = {\n+\tSSI_SDATA5_MARK,\n+};\n+static const unsigned int ssi5_ctrl_pins[] = {\n+\t/* SCK, WS */\n+\tRCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),\n+};\n+static const unsigned int ssi5_ctrl_mux[] = {\n+\tSSI_SCK5_MARK, SSI_WS5_MARK,\n+};\n+static const unsigned int ssi6_data_pins[] = {\n+\t/* SDATA */\n+\tRCAR_GP_PIN(6, 16),\n+};\n+static const unsigned int ssi6_data_mux[] = {\n+\tSSI_SDATA6_MARK,\n+};\n+static const unsigned int ssi6_ctrl_pins[] = {\n+\t/* SCK, WS */\n+\tRCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),\n+};\n+static const unsigned int ssi6_ctrl_mux[] = {\n+\tSSI_SCK6_MARK, SSI_WS6_MARK,\n+};\n+static const unsigned int ssi7_data_pins[] = {\n+\t/* SDATA */\n+\tRCAR_GP_PIN(6, 19),\n+};\n+static const unsigned int ssi7_data_mux[] = {\n+\tSSI_SDATA7_MARK,\n+};\n+static const unsigned int ssi78_ctrl_pins[] = {\n+\t/* SCK, WS */\n+\tRCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),\n+};\n+static const unsigned int ssi78_ctrl_mux[] = {\n+\tSSI_SCK78_MARK, SSI_WS78_MARK,\n+};\n+static const unsigned int ssi8_data_pins[] = {\n+\t/* SDATA */\n+\tRCAR_GP_PIN(6, 20),\n+};\n+static const unsigned int ssi8_data_mux[] = {\n+\tSSI_SDATA8_MARK,\n+};\n+static const unsigned int ssi9_data_a_pins[] = {\n+\t/* SDATA */\n+\tRCAR_GP_PIN(6, 21),\n+};\n+static const unsigned int ssi9_data_a_mux[] = {\n+\tSSI_SDATA9_A_MARK,\n+};\n+static const unsigned int ssi9_data_b_pins[] = {\n+\t/* SDATA */\n+\tRCAR_GP_PIN(5, 14),\n+};\n+static const unsigned int ssi9_data_b_mux[] = {\n+\tSSI_SDATA9_B_MARK,\n+};\n+static const unsigned int ssi9_ctrl_a_pins[] = {\n+\t/* SCK, WS */\n+\tRCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),\n+};\n+static const unsigned int ssi9_ctrl_a_mux[] = {\n+\tSSI_SCK9_A_MARK, SSI_WS9_A_MARK,\n+};\n+static const unsigned int ssi9_ctrl_b_pins[] = {\n+\t/* SCK, WS */\n+\tRCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),\n+};\n+static const unsigned int ssi9_ctrl_b_mux[] = {\n+\tSSI_SCK9_B_MARK, SSI_WS9_B_MARK,\n+};\n+\n+/* - USB0 ------------------------------------------------------------------- */\n+static const unsigned int usb0_pins[] = {\n+\t/* PWEN, OVC */\n+\tRCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),\n+};\n+static const unsigned int usb0_mux[] = {\n+\tUSB0_PWEN_MARK, USB0_OVC_MARK,\n+};\n+/* - USB1 ------------------------------------------------------------------- */\n+static const unsigned int usb1_pins[] = {\n+\t/* PWEN, OVC */\n+\tRCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),\n+};\n+static const unsigned int usb1_mux[] = {\n+\tUSB1_PWEN_MARK, USB1_OVC_MARK,\n+};\n+\n+/* - USB30 ------------------------------------------------------------------ */\n+static const unsigned int usb30_pins[] = {\n+\t/* PWEN, OVC */\n+\tRCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),\n+};\n+static const unsigned int usb30_mux[] = {\n+\tUSB30_PWEN_MARK, USB30_OVC_MARK,\n+};\n+\n+static const struct sh_pfc_pin_group pinmux_groups[] = {\n+\tSH_PFC_PIN_GROUP(audio_clk_a_a),\n+\tSH_PFC_PIN_GROUP(audio_clk_a_b),\n+\tSH_PFC_PIN_GROUP(audio_clk_a_c),\n+\tSH_PFC_PIN_GROUP(audio_clk_b_a),\n+\tSH_PFC_PIN_GROUP(audio_clk_b_b),\n+\tSH_PFC_PIN_GROUP(audio_clk_c_a),\n+\tSH_PFC_PIN_GROUP(audio_clk_c_b),\n+\tSH_PFC_PIN_GROUP(audio_clkout_a),\n+\tSH_PFC_PIN_GROUP(audio_clkout_b),\n+\tSH_PFC_PIN_GROUP(audio_clkout_c),\n+\tSH_PFC_PIN_GROUP(audio_clkout_d),\n+\tSH_PFC_PIN_GROUP(audio_clkout1_a),\n+\tSH_PFC_PIN_GROUP(audio_clkout1_b),\n+\tSH_PFC_PIN_GROUP(audio_clkout2_a),\n+\tSH_PFC_PIN_GROUP(audio_clkout2_b),\n+\tSH_PFC_PIN_GROUP(audio_clkout3_a),\n+\tSH_PFC_PIN_GROUP(audio_clkout3_b),\n+\tSH_PFC_PIN_GROUP(avb_link),\n+\tSH_PFC_PIN_GROUP(avb_magic),\n+\tSH_PFC_PIN_GROUP(avb_phy_int),\n+\tSH_PFC_PIN_GROUP(avb_mdc),\n+\tSH_PFC_PIN_GROUP(avb_mii),\n+\tSH_PFC_PIN_GROUP(avb_avtp_pps),\n+\tSH_PFC_PIN_GROUP(avb_avtp_match_a),\n+\tSH_PFC_PIN_GROUP(avb_avtp_capture_a),\n+\tSH_PFC_PIN_GROUP(avb_avtp_match_b),\n+\tSH_PFC_PIN_GROUP(avb_avtp_capture_b),\n+\tSH_PFC_PIN_GROUP(can0_data_a),\n+\tSH_PFC_PIN_GROUP(can0_data_b),\n+\tSH_PFC_PIN_GROUP(can1_data),\n+\tSH_PFC_PIN_GROUP(can_clk),\n+\tSH_PFC_PIN_GROUP(canfd0_data_a),\n+\tSH_PFC_PIN_GROUP(canfd0_data_b),\n+\tSH_PFC_PIN_GROUP(canfd1_data),\n+\tSH_PFC_PIN_GROUP(drif0_ctrl_a),\n+\tSH_PFC_PIN_GROUP(drif0_data0_a),\n+\tSH_PFC_PIN_GROUP(drif0_data1_a),\n+\tSH_PFC_PIN_GROUP(drif0_ctrl_b),\n+\tSH_PFC_PIN_GROUP(drif0_data0_b),\n+\tSH_PFC_PIN_GROUP(drif0_data1_b),\n+\tSH_PFC_PIN_GROUP(drif0_ctrl_c),\n+\tSH_PFC_PIN_GROUP(drif0_data0_c),\n+\tSH_PFC_PIN_GROUP(drif0_data1_c),\n+\tSH_PFC_PIN_GROUP(drif1_ctrl_a),\n+\tSH_PFC_PIN_GROUP(drif1_data0_a),\n+\tSH_PFC_PIN_GROUP(drif1_data1_a),\n+\tSH_PFC_PIN_GROUP(drif1_ctrl_b),\n+\tSH_PFC_PIN_GROUP(drif1_data0_b),\n+\tSH_PFC_PIN_GROUP(drif1_data1_b),\n+\tSH_PFC_PIN_GROUP(drif1_ctrl_c),\n+\tSH_PFC_PIN_GROUP(drif1_data0_c),\n+\tSH_PFC_PIN_GROUP(drif1_data1_c),\n+\tSH_PFC_PIN_GROUP(drif2_ctrl_a),\n+\tSH_PFC_PIN_GROUP(drif2_data0_a),\n+\tSH_PFC_PIN_GROUP(drif2_data1_a),\n+\tSH_PFC_PIN_GROUP(drif2_ctrl_b),\n+\tSH_PFC_PIN_GROUP(drif2_data0_b),\n+\tSH_PFC_PIN_GROUP(drif2_data1_b),\n+\tSH_PFC_PIN_GROUP(drif3_ctrl_a),\n+\tSH_PFC_PIN_GROUP(drif3_data0_a),\n+\tSH_PFC_PIN_GROUP(drif3_data1_a),\n+\tSH_PFC_PIN_GROUP(drif3_ctrl_b),\n+\tSH_PFC_PIN_GROUP(drif3_data0_b),\n+\tSH_PFC_PIN_GROUP(drif3_data1_b),\n+\tSH_PFC_PIN_GROUP(du_rgb666),\n+\tSH_PFC_PIN_GROUP(du_rgb888),\n+\tSH_PFC_PIN_GROUP(du_clk_out_0),\n+\tSH_PFC_PIN_GROUP(du_clk_out_1),\n+\tSH_PFC_PIN_GROUP(du_sync),\n+\tSH_PFC_PIN_GROUP(du_oddf),\n+\tSH_PFC_PIN_GROUP(du_cde),\n+\tSH_PFC_PIN_GROUP(du_disp),\n+\tSH_PFC_PIN_GROUP(hscif0_data),\n+\tSH_PFC_PIN_GROUP(hscif0_clk),\n+\tSH_PFC_PIN_GROUP(hscif0_ctrl),\n+\tSH_PFC_PIN_GROUP(hscif1_data_a),\n+\tSH_PFC_PIN_GROUP(hscif1_clk_a),\n+\tSH_PFC_PIN_GROUP(hscif1_ctrl_a),\n+\tSH_PFC_PIN_GROUP(hscif1_data_b),\n+\tSH_PFC_PIN_GROUP(hscif1_clk_b),\n+\tSH_PFC_PIN_GROUP(hscif1_ctrl_b),\n+\tSH_PFC_PIN_GROUP(hscif2_data_a),\n+\tSH_PFC_PIN_GROUP(hscif2_clk_a),\n+\tSH_PFC_PIN_GROUP(hscif2_ctrl_a),\n+\tSH_PFC_PIN_GROUP(hscif2_data_b),\n+\tSH_PFC_PIN_GROUP(hscif2_clk_b),\n+\tSH_PFC_PIN_GROUP(hscif2_ctrl_b),\n+\tSH_PFC_PIN_GROUP(hscif2_data_c),\n+\tSH_PFC_PIN_GROUP(hscif2_clk_c),\n+\tSH_PFC_PIN_GROUP(hscif2_ctrl_c),\n+\tSH_PFC_PIN_GROUP(hscif3_data_a),\n+\tSH_PFC_PIN_GROUP(hscif3_clk),\n+\tSH_PFC_PIN_GROUP(hscif3_ctrl),\n+\tSH_PFC_PIN_GROUP(hscif3_data_b),\n+\tSH_PFC_PIN_GROUP(hscif3_data_c),\n+\tSH_PFC_PIN_GROUP(hscif3_data_d),\n+\tSH_PFC_PIN_GROUP(hscif4_data_a),\n+\tSH_PFC_PIN_GROUP(hscif4_clk),\n+\tSH_PFC_PIN_GROUP(hscif4_ctrl),\n+\tSH_PFC_PIN_GROUP(hscif4_data_b),\n+\tSH_PFC_PIN_GROUP(i2c1_a),\n+\tSH_PFC_PIN_GROUP(i2c1_b),\n+\tSH_PFC_PIN_GROUP(i2c2_a),\n+\tSH_PFC_PIN_GROUP(i2c2_b),\n+\tSH_PFC_PIN_GROUP(i2c6_a),\n+\tSH_PFC_PIN_GROUP(i2c6_b),\n+\tSH_PFC_PIN_GROUP(i2c6_c),\n+\tSH_PFC_PIN_GROUP(msiof0_clk),\n+\tSH_PFC_PIN_GROUP(msiof0_sync),\n+\tSH_PFC_PIN_GROUP(msiof0_ss1),\n+\tSH_PFC_PIN_GROUP(msiof0_ss2),\n+\tSH_PFC_PIN_GROUP(msiof0_txd),\n+\tSH_PFC_PIN_GROUP(msiof0_rxd),\n+\tSH_PFC_PIN_GROUP(msiof1_clk_a),\n+\tSH_PFC_PIN_GROUP(msiof1_sync_a),\n+\tSH_PFC_PIN_GROUP(msiof1_ss1_a),\n+\tSH_PFC_PIN_GROUP(msiof1_ss2_a),\n+\tSH_PFC_PIN_GROUP(msiof1_txd_a),\n+\tSH_PFC_PIN_GROUP(msiof1_rxd_a),\n+\tSH_PFC_PIN_GROUP(msiof1_clk_b),\n+\tSH_PFC_PIN_GROUP(msiof1_sync_b),\n+\tSH_PFC_PIN_GROUP(msiof1_ss1_b),\n+\tSH_PFC_PIN_GROUP(msiof1_ss2_b),\n+\tSH_PFC_PIN_GROUP(msiof1_txd_b),\n+\tSH_PFC_PIN_GROUP(msiof1_rxd_b),\n+\tSH_PFC_PIN_GROUP(msiof1_clk_c),\n+\tSH_PFC_PIN_GROUP(msiof1_sync_c),\n+\tSH_PFC_PIN_GROUP(msiof1_ss1_c),\n+\tSH_PFC_PIN_GROUP(msiof1_ss2_c),\n+\tSH_PFC_PIN_GROUP(msiof1_txd_c),\n+\tSH_PFC_PIN_GROUP(msiof1_rxd_c),\n+\tSH_PFC_PIN_GROUP(msiof1_clk_d),\n+\tSH_PFC_PIN_GROUP(msiof1_sync_d),\n+\tSH_PFC_PIN_GROUP(msiof1_ss1_d),\n+\tSH_PFC_PIN_GROUP(msiof1_ss2_d),\n+\tSH_PFC_PIN_GROUP(msiof1_txd_d),\n+\tSH_PFC_PIN_GROUP(msiof1_rxd_d),\n+\tSH_PFC_PIN_GROUP(msiof1_clk_e),\n+\tSH_PFC_PIN_GROUP(msiof1_sync_e),\n+\tSH_PFC_PIN_GROUP(msiof1_ss1_e),\n+\tSH_PFC_PIN_GROUP(msiof1_ss2_e),\n+\tSH_PFC_PIN_GROUP(msiof1_txd_e),\n+\tSH_PFC_PIN_GROUP(msiof1_rxd_e),\n+\tSH_PFC_PIN_GROUP(msiof1_clk_f),\n+\tSH_PFC_PIN_GROUP(msiof1_sync_f),\n+\tSH_PFC_PIN_GROUP(msiof1_ss1_f),\n+\tSH_PFC_PIN_GROUP(msiof1_ss2_f),\n+\tSH_PFC_PIN_GROUP(msiof1_txd_f),\n+\tSH_PFC_PIN_GROUP(msiof1_rxd_f),\n+\tSH_PFC_PIN_GROUP(msiof1_clk_g),\n+\tSH_PFC_PIN_GROUP(msiof1_sync_g),\n+\tSH_PFC_PIN_GROUP(msiof1_ss1_g),\n+\tSH_PFC_PIN_GROUP(msiof1_ss2_g),\n+\tSH_PFC_PIN_GROUP(msiof1_txd_g),\n+\tSH_PFC_PIN_GROUP(msiof1_rxd_g),\n+\tSH_PFC_PIN_GROUP(msiof2_clk_a),\n+\tSH_PFC_PIN_GROUP(msiof2_sync_a),\n+\tSH_PFC_PIN_GROUP(msiof2_ss1_a),\n+\tSH_PFC_PIN_GROUP(msiof2_ss2_a),\n+\tSH_PFC_PIN_GROUP(msiof2_txd_a),\n+\tSH_PFC_PIN_GROUP(msiof2_rxd_a),\n+\tSH_PFC_PIN_GROUP(msiof2_clk_b),\n+\tSH_PFC_PIN_GROUP(msiof2_sync_b),\n+\tSH_PFC_PIN_GROUP(msiof2_ss1_b),\n+\tSH_PFC_PIN_GROUP(msiof2_ss2_b),\n+\tSH_PFC_PIN_GROUP(msiof2_txd_b),\n+\tSH_PFC_PIN_GROUP(msiof2_rxd_b),\n+\tSH_PFC_PIN_GROUP(msiof2_clk_c),\n+\tSH_PFC_PIN_GROUP(msiof2_sync_c),\n+\tSH_PFC_PIN_GROUP(msiof2_ss1_c),\n+\tSH_PFC_PIN_GROUP(msiof2_ss2_c),\n+\tSH_PFC_PIN_GROUP(msiof2_txd_c),\n+\tSH_PFC_PIN_GROUP(msiof2_rxd_c),\n+\tSH_PFC_PIN_GROUP(msiof2_clk_d),\n+\tSH_PFC_PIN_GROUP(msiof2_sync_d),\n+\tSH_PFC_PIN_GROUP(msiof2_ss1_d),\n+\tSH_PFC_PIN_GROUP(msiof2_ss2_d),\n+\tSH_PFC_PIN_GROUP(msiof2_txd_d),\n+\tSH_PFC_PIN_GROUP(msiof2_rxd_d),\n+\tSH_PFC_PIN_GROUP(msiof3_clk_a),\n+\tSH_PFC_PIN_GROUP(msiof3_sync_a),\n+\tSH_PFC_PIN_GROUP(msiof3_ss1_a),\n+\tSH_PFC_PIN_GROUP(msiof3_ss2_a),\n+\tSH_PFC_PIN_GROUP(msiof3_txd_a),\n+\tSH_PFC_PIN_GROUP(msiof3_rxd_a),\n+\tSH_PFC_PIN_GROUP(msiof3_clk_b),\n+\tSH_PFC_PIN_GROUP(msiof3_sync_b),\n+\tSH_PFC_PIN_GROUP(msiof3_ss1_b),\n+\tSH_PFC_PIN_GROUP(msiof3_ss2_b),\n+\tSH_PFC_PIN_GROUP(msiof3_txd_b),\n+\tSH_PFC_PIN_GROUP(msiof3_rxd_b),\n+\tSH_PFC_PIN_GROUP(msiof3_clk_c),\n+\tSH_PFC_PIN_GROUP(msiof3_sync_c),\n+\tSH_PFC_PIN_GROUP(msiof3_txd_c),\n+\tSH_PFC_PIN_GROUP(msiof3_rxd_c),\n+\tSH_PFC_PIN_GROUP(msiof3_clk_d),\n+\tSH_PFC_PIN_GROUP(msiof3_sync_d),\n+\tSH_PFC_PIN_GROUP(msiof3_ss1_d),\n+\tSH_PFC_PIN_GROUP(msiof3_txd_d),\n+\tSH_PFC_PIN_GROUP(msiof3_rxd_d),\n+\tSH_PFC_PIN_GROUP(msiof3_clk_e),\n+\tSH_PFC_PIN_GROUP(msiof3_sync_e),\n+\tSH_PFC_PIN_GROUP(msiof3_ss1_e),\n+\tSH_PFC_PIN_GROUP(msiof3_ss2_e),\n+\tSH_PFC_PIN_GROUP(msiof3_txd_e),\n+\tSH_PFC_PIN_GROUP(msiof3_rxd_e),\n+\tSH_PFC_PIN_GROUP(pwm0),\n+\tSH_PFC_PIN_GROUP(pwm1_a),\n+\tSH_PFC_PIN_GROUP(pwm1_b),\n+\tSH_PFC_PIN_GROUP(pwm2_a),\n+\tSH_PFC_PIN_GROUP(pwm2_b),\n+\tSH_PFC_PIN_GROUP(pwm3_a),\n+\tSH_PFC_PIN_GROUP(pwm3_b),\n+\tSH_PFC_PIN_GROUP(pwm4_a),\n+\tSH_PFC_PIN_GROUP(pwm4_b),\n+\tSH_PFC_PIN_GROUP(pwm5_a),\n+\tSH_PFC_PIN_GROUP(pwm5_b),\n+\tSH_PFC_PIN_GROUP(pwm6_a),\n+\tSH_PFC_PIN_GROUP(pwm6_b),\n+\tSH_PFC_PIN_GROUP(scif0_data),\n+\tSH_PFC_PIN_GROUP(scif0_clk),\n+\tSH_PFC_PIN_GROUP(scif0_ctrl),\n+\tSH_PFC_PIN_GROUP(scif1_data_a),\n+\tSH_PFC_PIN_GROUP(scif1_clk),\n+\tSH_PFC_PIN_GROUP(scif1_ctrl),\n+\tSH_PFC_PIN_GROUP(scif1_data_b),\n+\tSH_PFC_PIN_GROUP(scif2_data_a),\n+\tSH_PFC_PIN_GROUP(scif2_clk),\n+\tSH_PFC_PIN_GROUP(scif2_data_b),\n+\tSH_PFC_PIN_GROUP(scif3_data_a),\n+\tSH_PFC_PIN_GROUP(scif3_clk),\n+\tSH_PFC_PIN_GROUP(scif3_ctrl),\n+\tSH_PFC_PIN_GROUP(scif3_data_b),\n+\tSH_PFC_PIN_GROUP(scif4_data_a),\n+\tSH_PFC_PIN_GROUP(scif4_clk_a),\n+\tSH_PFC_PIN_GROUP(scif4_ctrl_a),\n+\tSH_PFC_PIN_GROUP(scif4_data_b),\n+\tSH_PFC_PIN_GROUP(scif4_clk_b),\n+\tSH_PFC_PIN_GROUP(scif4_ctrl_b),\n+\tSH_PFC_PIN_GROUP(scif4_data_c),\n+\tSH_PFC_PIN_GROUP(scif4_clk_c),\n+\tSH_PFC_PIN_GROUP(scif4_ctrl_c),\n+\tSH_PFC_PIN_GROUP(scif5_data_a),\n+\tSH_PFC_PIN_GROUP(scif5_clk_a),\n+\tSH_PFC_PIN_GROUP(scif5_data_b),\n+\tSH_PFC_PIN_GROUP(scif5_clk_b),\n+\tSH_PFC_PIN_GROUP(scif_clk_a),\n+\tSH_PFC_PIN_GROUP(scif_clk_b),\n+\tSH_PFC_PIN_GROUP(sdhi0_data1),\n+\tSH_PFC_PIN_GROUP(sdhi0_data4),\n+\tSH_PFC_PIN_GROUP(sdhi0_ctrl),\n+\tSH_PFC_PIN_GROUP(sdhi0_cd),\n+\tSH_PFC_PIN_GROUP(sdhi0_wp),\n+\tSH_PFC_PIN_GROUP(sdhi1_data1),\n+\tSH_PFC_PIN_GROUP(sdhi1_data4),\n+\tSH_PFC_PIN_GROUP(sdhi1_ctrl),\n+\tSH_PFC_PIN_GROUP(sdhi1_cd),\n+\tSH_PFC_PIN_GROUP(sdhi1_wp),\n+\tSH_PFC_PIN_GROUP(sdhi2_data1),\n+\tSH_PFC_PIN_GROUP(sdhi2_data4),\n+\tSH_PFC_PIN_GROUP(sdhi2_data8),\n+\tSH_PFC_PIN_GROUP(sdhi2_ctrl),\n+\tSH_PFC_PIN_GROUP(sdhi2_cd_a),\n+\tSH_PFC_PIN_GROUP(sdhi2_wp_a),\n+\tSH_PFC_PIN_GROUP(sdhi2_cd_b),\n+\tSH_PFC_PIN_GROUP(sdhi2_wp_b),\n+\tSH_PFC_PIN_GROUP(sdhi2_ds),\n+\tSH_PFC_PIN_GROUP(sdhi3_data1),\n+\tSH_PFC_PIN_GROUP(sdhi3_data4),\n+\tSH_PFC_PIN_GROUP(sdhi3_data8),\n+\tSH_PFC_PIN_GROUP(sdhi3_ctrl),\n+\tSH_PFC_PIN_GROUP(sdhi3_cd),\n+\tSH_PFC_PIN_GROUP(sdhi3_wp),\n+\tSH_PFC_PIN_GROUP(sdhi3_ds),\n+\tSH_PFC_PIN_GROUP(ssi0_data),\n+\tSH_PFC_PIN_GROUP(ssi01239_ctrl),\n+\tSH_PFC_PIN_GROUP(ssi1_data_a),\n+\tSH_PFC_PIN_GROUP(ssi1_data_b),\n+\tSH_PFC_PIN_GROUP(ssi1_ctrl_a),\n+\tSH_PFC_PIN_GROUP(ssi1_ctrl_b),\n+\tSH_PFC_PIN_GROUP(ssi2_data_a),\n+\tSH_PFC_PIN_GROUP(ssi2_data_b),\n+\tSH_PFC_PIN_GROUP(ssi2_ctrl_a),\n+\tSH_PFC_PIN_GROUP(ssi2_ctrl_b),\n+\tSH_PFC_PIN_GROUP(ssi3_data),\n+\tSH_PFC_PIN_GROUP(ssi349_ctrl),\n+\tSH_PFC_PIN_GROUP(ssi4_data),\n+\tSH_PFC_PIN_GROUP(ssi4_ctrl),\n+\tSH_PFC_PIN_GROUP(ssi5_data),\n+\tSH_PFC_PIN_GROUP(ssi5_ctrl),\n+\tSH_PFC_PIN_GROUP(ssi6_data),\n+\tSH_PFC_PIN_GROUP(ssi6_ctrl),\n+\tSH_PFC_PIN_GROUP(ssi7_data),\n+\tSH_PFC_PIN_GROUP(ssi78_ctrl),\n+\tSH_PFC_PIN_GROUP(ssi8_data),\n+\tSH_PFC_PIN_GROUP(ssi9_data_a),\n+\tSH_PFC_PIN_GROUP(ssi9_data_b),\n+\tSH_PFC_PIN_GROUP(ssi9_ctrl_a),\n+\tSH_PFC_PIN_GROUP(ssi9_ctrl_b),\n+\tSH_PFC_PIN_GROUP(usb0),\n+\tSH_PFC_PIN_GROUP(usb1),\n+\tSH_PFC_PIN_GROUP(usb30),\n+};\n+\n+static const char * const audio_clk_groups[] = {\n+\t\"audio_clk_a_a\",\n+\t\"audio_clk_a_b\",\n+\t\"audio_clk_a_c\",\n+\t\"audio_clk_b_a\",\n+\t\"audio_clk_b_b\",\n+\t\"audio_clk_c_a\",\n+\t\"audio_clk_c_b\",\n+\t\"audio_clkout_a\",\n+\t\"audio_clkout_b\",\n+\t\"audio_clkout_c\",\n+\t\"audio_clkout_d\",\n+\t\"audio_clkout1_a\",\n+\t\"audio_clkout1_b\",\n+\t\"audio_clkout2_a\",\n+\t\"audio_clkout2_b\",\n+\t\"audio_clkout3_a\",\n+\t\"audio_clkout3_b\",\n+};\n+\n+static const char * const avb_groups[] = {\n+\t\"avb_link\",\n+\t\"avb_magic\",\n+\t\"avb_phy_int\",\n+\t\"avb_mdc\",\n+\t\"avb_mii\",\n+\t\"avb_avtp_pps\",\n+\t\"avb_avtp_match_a\",\n+\t\"avb_avtp_capture_a\",\n+\t\"avb_avtp_match_b\",\n+\t\"avb_avtp_capture_b\",\n+};\n+\n+static const char * const can0_groups[] = {\n+\t\"can0_data_a\",\n+\t\"can0_data_b\",\n+};\n+\n+static const char * const can1_groups[] = {\n+\t\"can1_data\",\n+};\n+\n+static const char * const can_clk_groups[] = {\n+\t\"can_clk\",\n+};\n+\n+static const char * const canfd0_groups[] = {\n+\t\"canfd0_data_a\",\n+\t\"canfd0_data_b\",\n+};\n+\n+static const char * const canfd1_groups[] = {\n+\t\"canfd1_data\",\n+};\n+\n+static const char * const drif0_groups[] = {\n+\t\"drif0_ctrl_a\",\n+\t\"drif0_data0_a\",\n+\t\"drif0_data1_a\",\n+\t\"drif0_ctrl_b\",\n+\t\"drif0_data0_b\",\n+\t\"drif0_data1_b\",\n+\t\"drif0_ctrl_c\",\n+\t\"drif0_data0_c\",\n+\t\"drif0_data1_c\",\n+};\n+\n+static const char * const drif1_groups[] = {\n+\t\"drif1_ctrl_a\",\n+\t\"drif1_data0_a\",\n+\t\"drif1_data1_a\",\n+\t\"drif1_ctrl_b\",\n+\t\"drif1_data0_b\",\n+\t\"drif1_data1_b\",\n+\t\"drif1_ctrl_c\",\n+\t\"drif1_data0_c\",\n+\t\"drif1_data1_c\",\n+};\n+\n+static const char * const drif2_groups[] = {\n+\t\"drif2_ctrl_a\",\n+\t\"drif2_data0_a\",\n+\t\"drif2_data1_a\",\n+\t\"drif2_ctrl_b\",\n+\t\"drif2_data0_b\",\n+\t\"drif2_data1_b\",\n+};\n+\n+static const char * const drif3_groups[] = {\n+\t\"drif3_ctrl_a\",\n+\t\"drif3_data0_a\",\n+\t\"drif3_data1_a\",\n+\t\"drif3_ctrl_b\",\n+\t\"drif3_data0_b\",\n+\t\"drif3_data1_b\",\n+};\n+\n+static const char * const du_groups[] = {\n+\t\"du_rgb666\",\n+\t\"du_rgb888\",\n+\t\"du_clk_out_0\",\n+\t\"du_clk_out_1\",\n+\t\"du_sync\",\n+\t\"du_oddf\",\n+\t\"du_cde\",\n+\t\"du_disp\",\n+};\n+\n+static const char * const hscif0_groups[] = {\n+\t\"hscif0_data\",\n+\t\"hscif0_clk\",\n+\t\"hscif0_ctrl\",\n+};\n+\n+static const char * const hscif1_groups[] = {\n+\t\"hscif1_data_a\",\n+\t\"hscif1_clk_a\",\n+\t\"hscif1_ctrl_a\",\n+\t\"hscif1_data_b\",\n+\t\"hscif1_clk_b\",\n+\t\"hscif1_ctrl_b\",\n+};\n+\n+static const char * const hscif2_groups[] = {\n+\t\"hscif2_data_a\",\n+\t\"hscif2_clk_a\",\n+\t\"hscif2_ctrl_a\",\n+\t\"hscif2_data_b\",\n+\t\"hscif2_clk_b\",\n+\t\"hscif2_ctrl_b\",\n+\t\"hscif2_data_c\",\n+\t\"hscif2_clk_c\",\n+\t\"hscif2_ctrl_c\",\n+};\n+\n+static const char * const hscif3_groups[] = {\n+\t\"hscif3_data_a\",\n+\t\"hscif3_clk\",\n+\t\"hscif3_ctrl\",\n+\t\"hscif3_data_b\",\n+\t\"hscif3_data_c\",\n+\t\"hscif3_data_d\",\n+};\n+\n+static const char * const hscif4_groups[] = {\n+\t\"hscif4_data_a\",\n+\t\"hscif4_clk\",\n+\t\"hscif4_ctrl\",\n+\t\"hscif4_data_b\",\n+};\n+\n+static const char * const i2c1_groups[] = {\n+\t\"i2c1_a\",\n+\t\"i2c1_b\",\n+};\n+\n+static const char * const i2c2_groups[] = {\n+\t\"i2c2_a\",\n+\t\"i2c2_b\",\n+};\n+\n+static const char * const i2c6_groups[] = {\n+\t\"i2c6_a\",\n+\t\"i2c6_b\",\n+\t\"i2c6_c\",\n+};\n+\n+static const char * const msiof0_groups[] = {\n+\t\"msiof0_clk\",\n+\t\"msiof0_sync\",\n+\t\"msiof0_ss1\",\n+\t\"msiof0_ss2\",\n+\t\"msiof0_txd\",\n+\t\"msiof0_rxd\",\n+};\n+\n+static const char * const msiof1_groups[] = {\n+\t\"msiof1_clk_a\",\n+\t\"msiof1_sync_a\",\n+\t\"msiof1_ss1_a\",\n+\t\"msiof1_ss2_a\",\n+\t\"msiof1_txd_a\",\n+\t\"msiof1_rxd_a\",\n+\t\"msiof1_clk_b\",\n+\t\"msiof1_sync_b\",\n+\t\"msiof1_ss1_b\",\n+\t\"msiof1_ss2_b\",\n+\t\"msiof1_txd_b\",\n+\t\"msiof1_rxd_b\",\n+\t\"msiof1_clk_c\",\n+\t\"msiof1_sync_c\",\n+\t\"msiof1_ss1_c\",\n+\t\"msiof1_ss2_c\",\n+\t\"msiof1_txd_c\",\n+\t\"msiof1_rxd_c\",\n+\t\"msiof1_clk_d\",\n+\t\"msiof1_sync_d\",\n+\t\"msiof1_ss1_d\",\n+\t\"msiof1_ss2_d\",\n+\t\"msiof1_txd_d\",\n+\t\"msiof1_rxd_d\",\n+\t\"msiof1_clk_e\",\n+\t\"msiof1_sync_e\",\n+\t\"msiof1_ss1_e\",\n+\t\"msiof1_ss2_e\",\n+\t\"msiof1_txd_e\",\n+\t\"msiof1_rxd_e\",\n+\t\"msiof1_clk_f\",\n+\t\"msiof1_sync_f\",\n+\t\"msiof1_ss1_f\",\n+\t\"msiof1_ss2_f\",\n+\t\"msiof1_txd_f\",\n+\t\"msiof1_rxd_f\",\n+\t\"msiof1_clk_g\",\n+\t\"msiof1_sync_g\",\n+\t\"msiof1_ss1_g\",\n+\t\"msiof1_ss2_g\",\n+\t\"msiof1_txd_g\",\n+\t\"msiof1_rxd_g\",\n+};\n+\n+static const char * const msiof2_groups[] = {\n+\t\"msiof2_clk_a\",\n+\t\"msiof2_sync_a\",\n+\t\"msiof2_ss1_a\",\n+\t\"msiof2_ss2_a\",\n+\t\"msiof2_txd_a\",\n+\t\"msiof2_rxd_a\",\n+\t\"msiof2_clk_b\",\n+\t\"msiof2_sync_b\",\n+\t\"msiof2_ss1_b\",\n+\t\"msiof2_ss2_b\",\n+\t\"msiof2_txd_b\",\n+\t\"msiof2_rxd_b\",\n+\t\"msiof2_clk_c\",\n+\t\"msiof2_sync_c\",\n+\t\"msiof2_ss1_c\",\n+\t\"msiof2_ss2_c\",\n+\t\"msiof2_txd_c\",\n+\t\"msiof2_rxd_c\",\n+\t\"msiof2_clk_d\",\n+\t\"msiof2_sync_d\",\n+\t\"msiof2_ss1_d\",\n+\t\"msiof2_ss2_d\",\n+\t\"msiof2_txd_d\",\n+\t\"msiof2_rxd_d\",\n+};\n+\n+static const char * const msiof3_groups[] = {\n+\t\"msiof3_clk_a\",\n+\t\"msiof3_sync_a\",\n+\t\"msiof3_ss1_a\",\n+\t\"msiof3_ss2_a\",\n+\t\"msiof3_txd_a\",\n+\t\"msiof3_rxd_a\",\n+\t\"msiof3_clk_b\",\n+\t\"msiof3_sync_b\",\n+\t\"msiof3_ss1_b\",\n+\t\"msiof3_ss2_b\",\n+\t\"msiof3_txd_b\",\n+\t\"msiof3_rxd_b\",\n+\t\"msiof3_clk_c\",\n+\t\"msiof3_sync_c\",\n+\t\"msiof3_txd_c\",\n+\t\"msiof3_rxd_c\",\n+\t\"msiof3_clk_d\",\n+\t\"msiof3_sync_d\",\n+\t\"msiof3_ss1_d\",\n+\t\"msiof3_txd_d\",\n+\t\"msiof3_rxd_d\",\n+\t\"msiof3_clk_e\",\n+\t\"msiof3_sync_e\",\n+\t\"msiof3_ss1_e\",\n+\t\"msiof3_ss2_e\",\n+\t\"msiof3_txd_e\",\n+\t\"msiof3_rxd_e\",\n+};\n+\n+static const char * const pwm0_groups[] = {\n+\t\"pwm0\",\n+};\n+\n+static const char * const pwm1_groups[] = {\n+\t\"pwm1_a\",\n+\t\"pwm1_b\",\n+};\n+\n+static const char * const pwm2_groups[] = {\n+\t\"pwm2_a\",\n+\t\"pwm2_b\",\n+};\n+\n+static const char * const pwm3_groups[] = {\n+\t\"pwm3_a\",\n+\t\"pwm3_b\",\n+};\n+\n+static const char * const pwm4_groups[] = {\n+\t\"pwm4_a\",\n+\t\"pwm4_b\",\n+};\n+\n+static const char * const pwm5_groups[] = {\n+\t\"pwm5_a\",\n+\t\"pwm5_b\",\n+};\n+\n+static const char * const pwm6_groups[] = {\n+\t\"pwm6_a\",\n+\t\"pwm6_b\",\n+};\n+\n+static const char * const scif0_groups[] = {\n+\t\"scif0_data\",\n+\t\"scif0_clk\",\n+\t\"scif0_ctrl\",\n+};\n+\n+static const char * const scif1_groups[] = {\n+\t\"scif1_data_a\",\n+\t\"scif1_clk\",\n+\t\"scif1_ctrl\",\n+\t\"scif1_data_b\",\n+};\n+\n+static const char * const scif2_groups[] = {\n+\t\"scif2_data_a\",\n+\t\"scif2_clk\",\n+\t\"scif2_data_b\",\n+};\n+\n+static const char * const scif3_groups[] = {\n+\t\"scif3_data_a\",\n+\t\"scif3_clk\",\n+\t\"scif3_ctrl\",\n+\t\"scif3_data_b\",\n+};\n+\n+static const char * const scif4_groups[] = {\n+\t\"scif4_data_a\",\n+\t\"scif4_clk_a\",\n+\t\"scif4_ctrl_a\",\n+\t\"scif4_data_b\",\n+\t\"scif4_clk_b\",\n+\t\"scif4_ctrl_b\",\n+\t\"scif4_data_c\",\n+\t\"scif4_clk_c\",\n+\t\"scif4_ctrl_c\",\n+};\n+\n+static const char * const scif5_groups[] = {\n+\t\"scif5_data_a\",\n+\t\"scif5_clk_a\",\n+\t\"scif5_data_b\",\n+\t\"scif5_clk_b\",\n+};\n+\n+static const char * const scif_clk_groups[] = {\n+\t\"scif_clk_a\",\n+\t\"scif_clk_b\",\n+};\n+\n+static const char * const sdhi0_groups[] = {\n+\t\"sdhi0_data1\",\n+\t\"sdhi0_data4\",\n+\t\"sdhi0_ctrl\",\n+\t\"sdhi0_cd\",\n+\t\"sdhi0_wp\",\n+};\n+\n+static const char * const sdhi1_groups[] = {\n+\t\"sdhi1_data1\",\n+\t\"sdhi1_data4\",\n+\t\"sdhi1_ctrl\",\n+\t\"sdhi1_cd\",\n+\t\"sdhi1_wp\",\n+};\n+\n+static const char * const sdhi2_groups[] = {\n+\t\"sdhi2_data1\",\n+\t\"sdhi2_data4\",\n+\t\"sdhi2_data8\",\n+\t\"sdhi2_ctrl\",\n+\t\"sdhi2_cd_a\",\n+\t\"sdhi2_wp_a\",\n+\t\"sdhi2_cd_b\",\n+\t\"sdhi2_wp_b\",\n+\t\"sdhi2_ds\",\n+};\n+\n+static const char * const sdhi3_groups[] = {\n+\t\"sdhi3_data1\",\n+\t\"sdhi3_data4\",\n+\t\"sdhi3_data8\",\n+\t\"sdhi3_ctrl\",\n+\t\"sdhi3_cd\",\n+\t\"sdhi3_wp\",\n+\t\"sdhi3_ds\",\n+};\n+\n+static const char * const ssi_groups[] = {\n+\t\"ssi0_data\",\n+\t\"ssi01239_ctrl\",\n+\t\"ssi1_data_a\",\n+\t\"ssi1_data_b\",\n+\t\"ssi1_ctrl_a\",\n+\t\"ssi1_ctrl_b\",\n+\t\"ssi2_data_a\",\n+\t\"ssi2_data_b\",\n+\t\"ssi2_ctrl_a\",\n+\t\"ssi2_ctrl_b\",\n+\t\"ssi3_data\",\n+\t\"ssi349_ctrl\",\n+\t\"ssi4_data\",\n+\t\"ssi4_ctrl\",\n+\t\"ssi5_data\",\n+\t\"ssi5_ctrl\",\n+\t\"ssi6_data\",\n+\t\"ssi6_ctrl\",\n+\t\"ssi7_data\",\n+\t\"ssi78_ctrl\",\n+\t\"ssi8_data\",\n+\t\"ssi9_data_a\",\n+\t\"ssi9_data_b\",\n+\t\"ssi9_ctrl_a\",\n+\t\"ssi9_ctrl_b\",\n+};\n+\n+static const char * const usb0_groups[] = {\n+\t\"usb0\",\n+};\n+\n+static const char * const usb1_groups[] = {\n+\t\"usb1\",\n+};\n+\n+static const char * const usb30_groups[] = {\n+\t\"usb30\",\n+};\n+\n+static const struct sh_pfc_function pinmux_functions[] = {\n+\tSH_PFC_FUNCTION(audio_clk),\n+\tSH_PFC_FUNCTION(avb),\n+\tSH_PFC_FUNCTION(can0),\n+\tSH_PFC_FUNCTION(can1),\n+\tSH_PFC_FUNCTION(can_clk),\n+\tSH_PFC_FUNCTION(canfd0),\n+\tSH_PFC_FUNCTION(canfd1),\n+\tSH_PFC_FUNCTION(drif0),\n+\tSH_PFC_FUNCTION(drif1),\n+\tSH_PFC_FUNCTION(drif2),\n+\tSH_PFC_FUNCTION(drif3),\n+\tSH_PFC_FUNCTION(du),\n+\tSH_PFC_FUNCTION(hscif0),\n+\tSH_PFC_FUNCTION(hscif1),\n+\tSH_PFC_FUNCTION(hscif2),\n+\tSH_PFC_FUNCTION(hscif3),\n+\tSH_PFC_FUNCTION(hscif4),\n+\tSH_PFC_FUNCTION(i2c1),\n+\tSH_PFC_FUNCTION(i2c2),\n+\tSH_PFC_FUNCTION(i2c6),\n+\tSH_PFC_FUNCTION(msiof0),\n+\tSH_PFC_FUNCTION(msiof1),\n+\tSH_PFC_FUNCTION(msiof2),\n+\tSH_PFC_FUNCTION(msiof3),\n+\tSH_PFC_FUNCTION(pwm0),\n+\tSH_PFC_FUNCTION(pwm1),\n+\tSH_PFC_FUNCTION(pwm2),\n+\tSH_PFC_FUNCTION(pwm3),\n+\tSH_PFC_FUNCTION(pwm4),\n+\tSH_PFC_FUNCTION(pwm5),\n+\tSH_PFC_FUNCTION(pwm6),\n+\tSH_PFC_FUNCTION(scif0),\n+\tSH_PFC_FUNCTION(scif1),\n+\tSH_PFC_FUNCTION(scif2),\n+\tSH_PFC_FUNCTION(scif3),\n+\tSH_PFC_FUNCTION(scif4),\n+\tSH_PFC_FUNCTION(scif5),\n+\tSH_PFC_FUNCTION(scif_clk),\n+\tSH_PFC_FUNCTION(sdhi0),\n+\tSH_PFC_FUNCTION(sdhi1),\n+\tSH_PFC_FUNCTION(sdhi2),\n+\tSH_PFC_FUNCTION(sdhi3),\n+\tSH_PFC_FUNCTION(ssi),\n+\tSH_PFC_FUNCTION(usb0),\n+\tSH_PFC_FUNCTION(usb1),\n+\tSH_PFC_FUNCTION(usb30),\n+};\n+\n+static const struct pinmux_cfg_reg pinmux_config_regs[] = {\n+#define F_(x, y)\tFN_##y\n+#define FM(x)\t\tFN_##x\n+\t{ PINMUX_CFG_REG(\"GPSR0\", 0xe6060100, 32, 1) {\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\tGP_0_15_FN,\tGPSR0_15,\n+\t\tGP_0_14_FN,\tGPSR0_14,\n+\t\tGP_0_13_FN,\tGPSR0_13,\n+\t\tGP_0_12_FN,\tGPSR0_12,\n+\t\tGP_0_11_FN,\tGPSR0_11,\n+\t\tGP_0_10_FN,\tGPSR0_10,\n+\t\tGP_0_9_FN,\tGPSR0_9,\n+\t\tGP_0_8_FN,\tGPSR0_8,\n+\t\tGP_0_7_FN,\tGPSR0_7,\n+\t\tGP_0_6_FN,\tGPSR0_6,\n+\t\tGP_0_5_FN,\tGPSR0_5,\n+\t\tGP_0_4_FN,\tGPSR0_4,\n+\t\tGP_0_3_FN,\tGPSR0_3,\n+\t\tGP_0_2_FN,\tGPSR0_2,\n+\t\tGP_0_1_FN,\tGPSR0_1,\n+\t\tGP_0_0_FN,\tGPSR0_0, }\n+\t},\n+\t{ PINMUX_CFG_REG(\"GPSR1\", 0xe6060104, 32, 1) {\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\tGP_1_28_FN,\tGPSR1_28,\n+\t\tGP_1_27_FN,\tGPSR1_27,\n+\t\tGP_1_26_FN,\tGPSR1_26,\n+\t\tGP_1_25_FN,\tGPSR1_25,\n+\t\tGP_1_24_FN,\tGPSR1_24,\n+\t\tGP_1_23_FN,\tGPSR1_23,\n+\t\tGP_1_22_FN,\tGPSR1_22,\n+\t\tGP_1_21_FN,\tGPSR1_21,\n+\t\tGP_1_20_FN,\tGPSR1_20,\n+\t\tGP_1_19_FN,\tGPSR1_19,\n+\t\tGP_1_18_FN,\tGPSR1_18,\n+\t\tGP_1_17_FN,\tGPSR1_17,\n+\t\tGP_1_16_FN,\tGPSR1_16,\n+\t\tGP_1_15_FN,\tGPSR1_15,\n+\t\tGP_1_14_FN,\tGPSR1_14,\n+\t\tGP_1_13_FN,\tGPSR1_13,\n+\t\tGP_1_12_FN,\tGPSR1_12,\n+\t\tGP_1_11_FN,\tGPSR1_11,\n+\t\tGP_1_10_FN,\tGPSR1_10,\n+\t\tGP_1_9_FN,\tGPSR1_9,\n+\t\tGP_1_8_FN,\tGPSR1_8,\n+\t\tGP_1_7_FN,\tGPSR1_7,\n+\t\tGP_1_6_FN,\tGPSR1_6,\n+\t\tGP_1_5_FN,\tGPSR1_5,\n+\t\tGP_1_4_FN,\tGPSR1_4,\n+\t\tGP_1_3_FN,\tGPSR1_3,\n+\t\tGP_1_2_FN,\tGPSR1_2,\n+\t\tGP_1_1_FN,\tGPSR1_1,\n+\t\tGP_1_0_FN,\tGPSR1_0, }\n+\t},\n+\t{ PINMUX_CFG_REG(\"GPSR2\", 0xe6060108, 32, 1) {\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\tGP_2_14_FN,\tGPSR2_14,\n+\t\tGP_2_13_FN,\tGPSR2_13,\n+\t\tGP_2_12_FN,\tGPSR2_12,\n+\t\tGP_2_11_FN,\tGPSR2_11,\n+\t\tGP_2_10_FN,\tGPSR2_10,\n+\t\tGP_2_9_FN,\tGPSR2_9,\n+\t\tGP_2_8_FN,\tGPSR2_8,\n+\t\tGP_2_7_FN,\tGPSR2_7,\n+\t\tGP_2_6_FN,\tGPSR2_6,\n+\t\tGP_2_5_FN,\tGPSR2_5,\n+\t\tGP_2_4_FN,\tGPSR2_4,\n+\t\tGP_2_3_FN,\tGPSR2_3,\n+\t\tGP_2_2_FN,\tGPSR2_2,\n+\t\tGP_2_1_FN,\tGPSR2_1,\n+\t\tGP_2_0_FN,\tGPSR2_0, }\n+\t},\n+\t{ PINMUX_CFG_REG(\"GPSR3\", 0xe606010c, 32, 1) {\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\tGP_3_15_FN,\tGPSR3_15,\n+\t\tGP_3_14_FN,\tGPSR3_14,\n+\t\tGP_3_13_FN,\tGPSR3_13,\n+\t\tGP_3_12_FN,\tGPSR3_12,\n+\t\tGP_3_11_FN,\tGPSR3_11,\n+\t\tGP_3_10_FN,\tGPSR3_10,\n+\t\tGP_3_9_FN,\tGPSR3_9,\n+\t\tGP_3_8_FN,\tGPSR3_8,\n+\t\tGP_3_7_FN,\tGPSR3_7,\n+\t\tGP_3_6_FN,\tGPSR3_6,\n+\t\tGP_3_5_FN,\tGPSR3_5,\n+\t\tGP_3_4_FN,\tGPSR3_4,\n+\t\tGP_3_3_FN,\tGPSR3_3,\n+\t\tGP_3_2_FN,\tGPSR3_2,\n+\t\tGP_3_1_FN,\tGPSR3_1,\n+\t\tGP_3_0_FN,\tGPSR3_0, }\n+\t},\n+\t{ PINMUX_CFG_REG(\"GPSR4\", 0xe6060110, 32, 1) {\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\tGP_4_17_FN,\tGPSR4_17,\n+\t\tGP_4_16_FN,\tGPSR4_16,\n+\t\tGP_4_15_FN,\tGPSR4_15,\n+\t\tGP_4_14_FN,\tGPSR4_14,\n+\t\tGP_4_13_FN,\tGPSR4_13,\n+\t\tGP_4_12_FN,\tGPSR4_12,\n+\t\tGP_4_11_FN,\tGPSR4_11,\n+\t\tGP_4_10_FN,\tGPSR4_10,\n+\t\tGP_4_9_FN,\tGPSR4_9,\n+\t\tGP_4_8_FN,\tGPSR4_8,\n+\t\tGP_4_7_FN,\tGPSR4_7,\n+\t\tGP_4_6_FN,\tGPSR4_6,\n+\t\tGP_4_5_FN,\tGPSR4_5,\n+\t\tGP_4_4_FN,\tGPSR4_4,\n+\t\tGP_4_3_FN,\tGPSR4_3,\n+\t\tGP_4_2_FN,\tGPSR4_2,\n+\t\tGP_4_1_FN,\tGPSR4_1,\n+\t\tGP_4_0_FN,\tGPSR4_0, }\n+\t},\n+\t{ PINMUX_CFG_REG(\"GPSR5\", 0xe6060114, 32, 1) {\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\tGP_5_25_FN,\tGPSR5_25,\n+\t\tGP_5_24_FN,\tGPSR5_24,\n+\t\tGP_5_23_FN,\tGPSR5_23,\n+\t\tGP_5_22_FN,\tGPSR5_22,\n+\t\tGP_5_21_FN,\tGPSR5_21,\n+\t\tGP_5_20_FN,\tGPSR5_20,\n+\t\tGP_5_19_FN,\tGPSR5_19,\n+\t\tGP_5_18_FN,\tGPSR5_18,\n+\t\tGP_5_17_FN,\tGPSR5_17,\n+\t\tGP_5_16_FN,\tGPSR5_16,\n+\t\tGP_5_15_FN,\tGPSR5_15,\n+\t\tGP_5_14_FN,\tGPSR5_14,\n+\t\tGP_5_13_FN,\tGPSR5_13,\n+\t\tGP_5_12_FN,\tGPSR5_12,\n+\t\tGP_5_11_FN,\tGPSR5_11,\n+\t\tGP_5_10_FN,\tGPSR5_10,\n+\t\tGP_5_9_FN,\tGPSR5_9,\n+\t\tGP_5_8_FN,\tGPSR5_8,\n+\t\tGP_5_7_FN,\tGPSR5_7,\n+\t\tGP_5_6_FN,\tGPSR5_6,\n+\t\tGP_5_5_FN,\tGPSR5_5,\n+\t\tGP_5_4_FN,\tGPSR5_4,\n+\t\tGP_5_3_FN,\tGPSR5_3,\n+\t\tGP_5_2_FN,\tGPSR5_2,\n+\t\tGP_5_1_FN,\tGPSR5_1,\n+\t\tGP_5_0_FN,\tGPSR5_0, }\n+\t},\n+\t{ PINMUX_CFG_REG(\"GPSR6\", 0xe6060118, 32, 1) {\n+\t\tGP_6_31_FN,\tGPSR6_31,\n+\t\tGP_6_30_FN,\tGPSR6_30,\n+\t\tGP_6_29_FN,\tGPSR6_29,\n+\t\tGP_6_28_FN,\tGPSR6_28,\n+\t\tGP_6_27_FN,\tGPSR6_27,\n+\t\tGP_6_26_FN,\tGPSR6_26,\n+\t\tGP_6_25_FN,\tGPSR6_25,\n+\t\tGP_6_24_FN,\tGPSR6_24,\n+\t\tGP_6_23_FN,\tGPSR6_23,\n+\t\tGP_6_22_FN,\tGPSR6_22,\n+\t\tGP_6_21_FN,\tGPSR6_21,\n+\t\tGP_6_20_FN,\tGPSR6_20,\n+\t\tGP_6_19_FN,\tGPSR6_19,\n+\t\tGP_6_18_FN,\tGPSR6_18,\n+\t\tGP_6_17_FN,\tGPSR6_17,\n+\t\tGP_6_16_FN,\tGPSR6_16,\n+\t\tGP_6_15_FN,\tGPSR6_15,\n+\t\tGP_6_14_FN,\tGPSR6_14,\n+\t\tGP_6_13_FN,\tGPSR6_13,\n+\t\tGP_6_12_FN,\tGPSR6_12,\n+\t\tGP_6_11_FN,\tGPSR6_11,\n+\t\tGP_6_10_FN,\tGPSR6_10,\n+\t\tGP_6_9_FN,\tGPSR6_9,\n+\t\tGP_6_8_FN,\tGPSR6_8,\n+\t\tGP_6_7_FN,\tGPSR6_7,\n+\t\tGP_6_6_FN,\tGPSR6_6,\n+\t\tGP_6_5_FN,\tGPSR6_5,\n+\t\tGP_6_4_FN,\tGPSR6_4,\n+\t\tGP_6_3_FN,\tGPSR6_3,\n+\t\tGP_6_2_FN,\tGPSR6_2,\n+\t\tGP_6_1_FN,\tGPSR6_1,\n+\t\tGP_6_0_FN,\tGPSR6_0, }\n+\t},\n+\t{ PINMUX_CFG_REG(\"GPSR7\", 0xe606011c, 32, 1) {\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\t0, 0,\n+\t\tGP_7_3_FN, GPSR7_3,\n+\t\tGP_7_2_FN, GPSR7_2,\n+\t\tGP_7_1_FN, GPSR7_1,\n+\t\tGP_7_0_FN, GPSR7_0, }\n+\t},\n+#undef F_\n+#undef FM\n+\n+#define F_(x, y)\tx,\n+#define FM(x)\t\tFN_##x,\n+\t{ PINMUX_CFG_REG(\"IPSR0\", 0xe6060200, 32, 4) {\n+\t\tIP0_31_28\n+\t\tIP0_27_24\n+\t\tIP0_23_20\n+\t\tIP0_19_16\n+\t\tIP0_15_12\n+\t\tIP0_11_8\n+\t\tIP0_7_4\n+\t\tIP0_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR1\", 0xe6060204, 32, 4) {\n+\t\tIP1_31_28\n+\t\tIP1_27_24\n+\t\tIP1_23_20\n+\t\tIP1_19_16\n+\t\tIP1_15_12\n+\t\tIP1_11_8\n+\t\tIP1_7_4\n+\t\tIP1_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR2\", 0xe6060208, 32, 4) {\n+\t\tIP2_31_28\n+\t\tIP2_27_24\n+\t\tIP2_23_20\n+\t\tIP2_19_16\n+\t\tIP2_15_12\n+\t\tIP2_11_8\n+\t\tIP2_7_4\n+\t\tIP2_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR3\", 0xe606020c, 32, 4) {\n+\t\tIP3_31_28\n+\t\tIP3_27_24\n+\t\tIP3_23_20\n+\t\tIP3_19_16\n+\t\tIP3_15_12\n+\t\tIP3_11_8\n+\t\tIP3_7_4\n+\t\tIP3_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR4\", 0xe6060210, 32, 4) {\n+\t\tIP4_31_28\n+\t\tIP4_27_24\n+\t\tIP4_23_20\n+\t\tIP4_19_16\n+\t\tIP4_15_12\n+\t\tIP4_11_8\n+\t\tIP4_7_4\n+\t\tIP4_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR5\", 0xe6060214, 32, 4) {\n+\t\tIP5_31_28\n+\t\tIP5_27_24\n+\t\tIP5_23_20\n+\t\tIP5_19_16\n+\t\tIP5_15_12\n+\t\tIP5_11_8\n+\t\tIP5_7_4\n+\t\tIP5_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR6\", 0xe6060218, 32, 4) {\n+\t\tIP6_31_28\n+\t\tIP6_27_24\n+\t\tIP6_23_20\n+\t\tIP6_19_16\n+\t\tIP6_15_12\n+\t\tIP6_11_8\n+\t\tIP6_7_4\n+\t\tIP6_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR7\", 0xe606021c, 32, 4) {\n+\t\tIP7_31_28\n+\t\tIP7_27_24\n+\t\tIP7_23_20\n+\t\tIP7_19_16\n+\t\t/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+\t\tIP7_11_8\n+\t\tIP7_7_4\n+\t\tIP7_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR8\", 0xe6060220, 32, 4) {\n+\t\tIP8_31_28\n+\t\tIP8_27_24\n+\t\tIP8_23_20\n+\t\tIP8_19_16\n+\t\tIP8_15_12\n+\t\tIP8_11_8\n+\t\tIP8_7_4\n+\t\tIP8_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR9\", 0xe6060224, 32, 4) {\n+\t\tIP9_31_28\n+\t\tIP9_27_24\n+\t\tIP9_23_20\n+\t\tIP9_19_16\n+\t\tIP9_15_12\n+\t\tIP9_11_8\n+\t\tIP9_7_4\n+\t\tIP9_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR10\", 0xe6060228, 32, 4) {\n+\t\tIP10_31_28\n+\t\tIP10_27_24\n+\t\tIP10_23_20\n+\t\tIP10_19_16\n+\t\tIP10_15_12\n+\t\tIP10_11_8\n+\t\tIP10_7_4\n+\t\tIP10_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR11\", 0xe606022c, 32, 4) {\n+\t\tIP11_31_28\n+\t\tIP11_27_24\n+\t\tIP11_23_20\n+\t\tIP11_19_16\n+\t\tIP11_15_12\n+\t\tIP11_11_8\n+\t\tIP11_7_4\n+\t\tIP11_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR12\", 0xe6060230, 32, 4) {\n+\t\tIP12_31_28\n+\t\tIP12_27_24\n+\t\tIP12_23_20\n+\t\tIP12_19_16\n+\t\tIP12_15_12\n+\t\tIP12_11_8\n+\t\tIP12_7_4\n+\t\tIP12_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR13\", 0xe6060234, 32, 4) {\n+\t\tIP13_31_28\n+\t\tIP13_27_24\n+\t\tIP13_23_20\n+\t\tIP13_19_16\n+\t\tIP13_15_12\n+\t\tIP13_11_8\n+\t\tIP13_7_4\n+\t\tIP13_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR14\", 0xe6060238, 32, 4) {\n+\t\tIP14_31_28\n+\t\tIP14_27_24\n+\t\tIP14_23_20\n+\t\tIP14_19_16\n+\t\tIP14_15_12\n+\t\tIP14_11_8\n+\t\tIP14_7_4\n+\t\tIP14_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR15\", 0xe606023c, 32, 4) {\n+\t\tIP15_31_28\n+\t\tIP15_27_24\n+\t\tIP15_23_20\n+\t\tIP15_19_16\n+\t\tIP15_15_12\n+\t\tIP15_11_8\n+\t\tIP15_7_4\n+\t\tIP15_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR16\", 0xe6060240, 32, 4) {\n+\t\tIP16_31_28\n+\t\tIP16_27_24\n+\t\tIP16_23_20\n+\t\tIP16_19_16\n+\t\tIP16_15_12\n+\t\tIP16_11_8\n+\t\tIP16_7_4\n+\t\tIP16_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR17\", 0xe6060244, 32, 4) {\n+\t\tIP17_31_28\n+\t\tIP17_27_24\n+\t\tIP17_23_20\n+\t\tIP17_19_16\n+\t\tIP17_15_12\n+\t\tIP17_11_8\n+\t\tIP17_7_4\n+\t\tIP17_3_0 }\n+\t},\n+\t{ PINMUX_CFG_REG(\"IPSR18\", 0xe6060248, 32, 4) {\n+\t\t/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t/* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t/* IP18_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+\t\tIP18_7_4\n+\t\tIP18_3_0 }\n+\t},\n+#undef F_\n+#undef FM\n+\n+#define F_(x, y)\tx,\n+#define FM(x)\t\tFN_##x,\n+\t{ PINMUX_CFG_REG_VAR(\"MOD_SEL0\", 0xe6060500, 32,\n+\t\t\t     3, 2, 3, 1, 1, 1, 1, 1, 2, 1,\n+\t\t\t     1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {\n+\t\tMOD_SEL0_31_30_29\n+\t\tMOD_SEL0_28_27\n+\t\tMOD_SEL0_26_25_24\n+\t\tMOD_SEL0_23\n+\t\tMOD_SEL0_22\n+\t\tMOD_SEL0_21\n+\t\tMOD_SEL0_20\n+\t\tMOD_SEL0_19\n+\t\tMOD_SEL0_18_17\n+\t\tMOD_SEL0_16\n+\t\t0, 0, /* RESERVED 15 */\n+\t\tMOD_SEL0_14_13\n+\t\tMOD_SEL0_12\n+\t\tMOD_SEL0_11\n+\t\tMOD_SEL0_10\n+\t\tMOD_SEL0_9_8\n+\t\tMOD_SEL0_7_6\n+\t\tMOD_SEL0_5\n+\t\tMOD_SEL0_4_3\n+\t\t/* RESERVED 2, 1, 0 */\n+\t\t0, 0, 0, 0, 0, 0, 0, 0 }\n+\t},\n+\t{ PINMUX_CFG_REG_VAR(\"MOD_SEL1\", 0xe6060504, 32,\n+\t\t\t     2, 3, 1, 2, 3, 1, 1, 2, 1,\n+\t\t\t     2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {\n+\t\tMOD_SEL1_31_30\n+\t\tMOD_SEL1_29_28_27\n+\t\tMOD_SEL1_26\n+\t\tMOD_SEL1_25_24\n+\t\tMOD_SEL1_23_22_21\n+\t\tMOD_SEL1_20\n+\t\tMOD_SEL1_19\n+\t\tMOD_SEL1_18_17\n+\t\tMOD_SEL1_16\n+\t\tMOD_SEL1_15_14\n+\t\tMOD_SEL1_13\n+\t\tMOD_SEL1_12\n+\t\tMOD_SEL1_11\n+\t\tMOD_SEL1_10\n+\t\tMOD_SEL1_9\n+\t\t0, 0, 0, 0, /* RESERVED 8, 7 */\n+\t\tMOD_SEL1_6\n+\t\tMOD_SEL1_5\n+\t\tMOD_SEL1_4\n+\t\tMOD_SEL1_3\n+\t\tMOD_SEL1_2\n+\t\tMOD_SEL1_1\n+\t\tMOD_SEL1_0 }\n+\t},\n+\t{ PINMUX_CFG_REG_VAR(\"MOD_SEL2\", 0xe6060508, 32,\n+\t\t\t     1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,\n+\t\t\t     4, 4, 4, 3, 1) {\n+\t\tMOD_SEL2_31\n+\t\tMOD_SEL2_30\n+\t\tMOD_SEL2_29\n+\t\tMOD_SEL2_28_27\n+\t\tMOD_SEL2_26\n+\t\tMOD_SEL2_25_24_23\n+\t\tMOD_SEL2_22\n+\t\tMOD_SEL2_21\n+\t\tMOD_SEL2_20\n+\t\tMOD_SEL2_19\n+\t\tMOD_SEL2_18\n+\t\tMOD_SEL2_17\n+\t\t/* RESERVED 16 */\n+\t\t0, 0,\n+\t\t/* RESERVED 15, 14, 13, 12 */\n+\t\t0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t/* RESERVED 11, 10, 9, 8 */\n+\t\t0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t/* RESERVED 7, 6, 5, 4 */\n+\t\t0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t/* RESERVED 3, 2, 1 */\n+\t\t0, 0, 0, 0, 0, 0, 0, 0,\n+\t\tMOD_SEL2_0 }\n+\t},\n+\t{ },\n+};\n+\n+static const struct pinmux_drive_reg pinmux_drive_regs[] = {\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL0\", 0xe6060300) {\n+\t\t{ PIN_NUMBER('W', 3),   28, 2 },\t/* QSPI0_SPCLK */\n+\t\t{ PIN_A_NUMBER('C', 5), 24, 2 },\t/* QSPI0_MOSI_IO0 */\n+\t\t{ PIN_A_NUMBER('B', 4), 20, 2 },\t/* QSPI0_MISO_IO1 */\n+\t\t{ PIN_NUMBER('Y', 6),   16, 2 },\t/* QSPI0_IO2 */\n+\t\t{ PIN_A_NUMBER('B', 6), 12, 2 },\t/* QSPI0_IO3 */\n+\t\t{ PIN_NUMBER('Y', 3),    8, 2 },\t/* QSPI0_SSL */\n+\t\t{ PIN_NUMBER('V', 3),    4, 2 },\t/* QSPI1_SPCLK */\n+\t\t{ PIN_A_NUMBER('C', 7),  0, 2 },\t/* QSPI1_MOSI_IO0 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL1\", 0xe6060304) {\n+\t\t{ PIN_A_NUMBER('E', 5), 28, 2 },\t/* QSPI1_MISO_IO1 */\n+\t\t{ PIN_A_NUMBER('E', 4), 24, 2 },\t/* QSPI1_IO2 */\n+\t\t{ PIN_A_NUMBER('C', 3), 20, 2 },\t/* QSPI1_IO3 */\n+\t\t{ PIN_NUMBER('V', 5),   16, 2 },\t/* QSPI1_SSL */\n+\t\t{ PIN_NUMBER('Y', 7),   12, 2 },\t/* RPC_INT# */\n+\t\t{ PIN_NUMBER('V', 6),    8, 2 },\t/* RPC_WP# */\n+\t\t{ PIN_NUMBER('V', 7),    4, 2 },\t/* RPC_RESET# */\n+\t\t{ PIN_NUMBER('A', 16),   0, 3 },\t/* AVB_RX_CTL */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL2\", 0xe6060308) {\n+\t\t{ PIN_NUMBER('B', 19),  28, 3 },\t/* AVB_RXC */\n+\t\t{ PIN_NUMBER('A', 13),  24, 3 },\t/* AVB_RD0 */\n+\t\t{ PIN_NUMBER('B', 13),  20, 3 },\t/* AVB_RD1 */\n+\t\t{ PIN_NUMBER('A', 14),  16, 3 },\t/* AVB_RD2 */\n+\t\t{ PIN_NUMBER('B', 14),  12, 3 },\t/* AVB_RD3 */\n+\t\t{ PIN_NUMBER('A', 8),    8, 3 },\t/* AVB_TX_CTL */\n+\t\t{ PIN_NUMBER('A', 19),   4, 3 },\t/* AVB_TXC */\n+\t\t{ PIN_NUMBER('A', 18),   0, 3 },\t/* AVB_TD0 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL3\", 0xe606030c) {\n+\t\t{ PIN_NUMBER('B', 18),  28, 3 },\t/* AVB_TD1 */\n+\t\t{ PIN_NUMBER('A', 17),  24, 3 },\t/* AVB_TD2 */\n+\t\t{ PIN_NUMBER('B', 17),  20, 3 },\t/* AVB_TD3 */\n+\t\t{ PIN_NUMBER('A', 12),  16, 3 },\t/* AVB_TXCREFCLK */\n+\t\t{ PIN_NUMBER('A', 9),   12, 3 },\t/* AVB_MDIO */\n+\t\t{ RCAR_GP_PIN(2,  9),    8, 3 },\t/* AVB_MDC */\n+\t\t{ RCAR_GP_PIN(2, 10),    4, 3 },\t/* AVB_MAGIC */\n+\t\t{ RCAR_GP_PIN(2, 11),    0, 3 },\t/* AVB_PHY_INT */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL4\", 0xe6060310) {\n+\t\t{ RCAR_GP_PIN(2, 12), 28, 3 },\t/* AVB_LINK */\n+\t\t{ RCAR_GP_PIN(2, 13), 24, 3 },\t/* AVB_AVTP_MATCH */\n+\t\t{ RCAR_GP_PIN(2, 14), 20, 3 },\t/* AVB_AVTP_CAPTURE */\n+\t\t{ RCAR_GP_PIN(2,  0), 16, 3 },\t/* IRQ0 */\n+\t\t{ RCAR_GP_PIN(2,  1), 12, 3 },\t/* IRQ1 */\n+\t\t{ RCAR_GP_PIN(2,  2),  8, 3 },\t/* IRQ2 */\n+\t\t{ RCAR_GP_PIN(2,  3),  4, 3 },\t/* IRQ3 */\n+\t\t{ RCAR_GP_PIN(2,  4),  0, 3 },\t/* IRQ4 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL5\", 0xe6060314) {\n+\t\t{ RCAR_GP_PIN(2,  5), 28, 3 },\t/* IRQ5 */\n+\t\t{ RCAR_GP_PIN(2,  6), 24, 3 },\t/* PWM0 */\n+\t\t{ RCAR_GP_PIN(2,  7), 20, 3 },\t/* PWM1 */\n+\t\t{ RCAR_GP_PIN(2,  8), 16, 3 },\t/* PWM2 */\n+\t\t{ RCAR_GP_PIN(1,  0), 12, 3 },\t/* A0 */\n+\t\t{ RCAR_GP_PIN(1,  1),  8, 3 },\t/* A1 */\n+\t\t{ RCAR_GP_PIN(1,  2),  4, 3 },\t/* A2 */\n+\t\t{ RCAR_GP_PIN(1,  3),  0, 3 },\t/* A3 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL6\", 0xe6060318) {\n+\t\t{ RCAR_GP_PIN(1,  4), 28, 3 },\t/* A4 */\n+\t\t{ RCAR_GP_PIN(1,  5), 24, 3 },\t/* A5 */\n+\t\t{ RCAR_GP_PIN(1,  6), 20, 3 },\t/* A6 */\n+\t\t{ RCAR_GP_PIN(1,  7), 16, 3 },\t/* A7 */\n+\t\t{ RCAR_GP_PIN(1,  8), 12, 3 },\t/* A8 */\n+\t\t{ RCAR_GP_PIN(1,  9),  8, 3 },\t/* A9 */\n+\t\t{ RCAR_GP_PIN(1, 10),  4, 3 },\t/* A10 */\n+\t\t{ RCAR_GP_PIN(1, 11),  0, 3 },\t/* A11 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL7\", 0xe606031c) {\n+\t\t{ RCAR_GP_PIN(1, 12), 28, 3 },\t/* A12 */\n+\t\t{ RCAR_GP_PIN(1, 13), 24, 3 },\t/* A13 */\n+\t\t{ RCAR_GP_PIN(1, 14), 20, 3 },\t/* A14 */\n+\t\t{ RCAR_GP_PIN(1, 15), 16, 3 },\t/* A15 */\n+\t\t{ RCAR_GP_PIN(1, 16), 12, 3 },\t/* A16 */\n+\t\t{ RCAR_GP_PIN(1, 17),  8, 3 },\t/* A17 */\n+\t\t{ RCAR_GP_PIN(1, 18),  4, 3 },\t/* A18 */\n+\t\t{ RCAR_GP_PIN(1, 19),  0, 3 },\t/* A19 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL8\", 0xe6060320) {\n+\t\t{ RCAR_GP_PIN(1, 28), 28, 3 },\t/* CLKOUT */\n+\t\t{ RCAR_GP_PIN(1, 20), 24, 3 },\t/* CS0 */\n+\t\t{ RCAR_GP_PIN(1, 21), 20, 3 },\t/* CS1_A26 */\n+\t\t{ RCAR_GP_PIN(1, 22), 16, 3 },\t/* BS */\n+\t\t{ RCAR_GP_PIN(1, 23), 12, 3 },\t/* RD */\n+\t\t{ RCAR_GP_PIN(1, 24),  8, 3 },\t/* RD_WR */\n+\t\t{ RCAR_GP_PIN(1, 25),  4, 3 },\t/* WE0 */\n+\t\t{ RCAR_GP_PIN(1, 26),  0, 3 },\t/* WE1 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL9\", 0xe6060324) {\n+\t\t{ RCAR_GP_PIN(1, 27), 28, 3 },\t/* EX_WAIT0 */\n+\t\t{ PIN_NUMBER('C', 1), 24, 3 },\t/* PRESETOUT# */\n+\t\t{ RCAR_GP_PIN(0,  0), 20, 3 },\t/* D0 */\n+\t\t{ RCAR_GP_PIN(0,  1), 16, 3 },\t/* D1 */\n+\t\t{ RCAR_GP_PIN(0,  2), 12, 3 },\t/* D2 */\n+\t\t{ RCAR_GP_PIN(0,  3),  8, 3 },\t/* D3 */\n+\t\t{ RCAR_GP_PIN(0,  4),  4, 3 },\t/* D4 */\n+\t\t{ RCAR_GP_PIN(0,  5),  0, 3 },\t/* D5 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL10\", 0xe6060328) {\n+\t\t{ RCAR_GP_PIN(0,  6), 28, 3 },\t/* D6 */\n+\t\t{ RCAR_GP_PIN(0,  7), 24, 3 },\t/* D7 */\n+\t\t{ RCAR_GP_PIN(0,  8), 20, 3 },\t/* D8 */\n+\t\t{ RCAR_GP_PIN(0,  9), 16, 3 },\t/* D9 */\n+\t\t{ RCAR_GP_PIN(0, 10), 12, 3 },\t/* D10 */\n+\t\t{ RCAR_GP_PIN(0, 11),  8, 3 },\t/* D11 */\n+\t\t{ RCAR_GP_PIN(0, 12),  4, 3 },\t/* D12 */\n+\t\t{ RCAR_GP_PIN(0, 13),  0, 3 },\t/* D13 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL11\", 0xe606032c) {\n+\t\t{ RCAR_GP_PIN(0, 14),   28, 3 },\t/* D14 */\n+\t\t{ RCAR_GP_PIN(0, 15),   24, 3 },\t/* D15 */\n+\t\t{ RCAR_GP_PIN(7,  0),   20, 3 },\t/* AVS1 */\n+\t\t{ RCAR_GP_PIN(7,  1),   16, 3 },\t/* AVS2 */\n+\t\t{ RCAR_GP_PIN(7,  2),   12, 3 },\t/* HDMI0_CEC */\n+\t\t{ RCAR_GP_PIN(7,  3),    8, 3 },\t/* GP7_03 */\n+\t\t{ PIN_A_NUMBER('P', 7),  4, 2 },\t/* DU_DOTCLKIN0 */\n+\t\t{ PIN_A_NUMBER('P', 8),  0, 2 },\t/* DU_DOTCLKIN1 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL12\", 0xe6060330) {\n+\t\t{ PIN_A_NUMBER('R', 8),  28, 2 },\t/* DU_DOTCLKIN2 */\n+\t\t{ PIN_A_NUMBER('D', 38), 20, 2 },\t/* FSCLKST */\n+\t\t{ PIN_A_NUMBER('R', 30),  4, 2 },\t/* TMS */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL13\", 0xe6060334) {\n+\t\t{ PIN_A_NUMBER('T', 28), 28, 2 },\t/* TDO */\n+\t\t{ PIN_A_NUMBER('T', 30), 24, 2 },\t/* ASEBRK */\n+\t\t{ RCAR_GP_PIN(3,  0),    20, 3 },\t/* SD0_CLK */\n+\t\t{ RCAR_GP_PIN(3,  1),    16, 3 },\t/* SD0_CMD */\n+\t\t{ RCAR_GP_PIN(3,  2),    12, 3 },\t/* SD0_DAT0 */\n+\t\t{ RCAR_GP_PIN(3,  3),     8, 3 },\t/* SD0_DAT1 */\n+\t\t{ RCAR_GP_PIN(3,  4),     4, 3 },\t/* SD0_DAT2 */\n+\t\t{ RCAR_GP_PIN(3,  5),     0, 3 },\t/* SD0_DAT3 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL14\", 0xe6060338) {\n+\t\t{ RCAR_GP_PIN(3,  6), 28, 3 },\t/* SD1_CLK */\n+\t\t{ RCAR_GP_PIN(3,  7), 24, 3 },\t/* SD1_CMD */\n+\t\t{ RCAR_GP_PIN(3,  8), 20, 3 },\t/* SD1_DAT0 */\n+\t\t{ RCAR_GP_PIN(3,  9), 16, 3 },\t/* SD1_DAT1 */\n+\t\t{ RCAR_GP_PIN(3, 10), 12, 3 },\t/* SD1_DAT2 */\n+\t\t{ RCAR_GP_PIN(3, 11),  8, 3 },\t/* SD1_DAT3 */\n+\t\t{ RCAR_GP_PIN(4,  0),  4, 3 },\t/* SD2_CLK */\n+\t\t{ RCAR_GP_PIN(4,  1),  0, 3 },\t/* SD2_CMD */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL15\", 0xe606033c) {\n+\t\t{ RCAR_GP_PIN(4,  2), 28, 3 },\t/* SD2_DAT0 */\n+\t\t{ RCAR_GP_PIN(4,  3), 24, 3 },\t/* SD2_DAT1 */\n+\t\t{ RCAR_GP_PIN(4,  4), 20, 3 },\t/* SD2_DAT2 */\n+\t\t{ RCAR_GP_PIN(4,  5), 16, 3 },\t/* SD2_DAT3 */\n+\t\t{ RCAR_GP_PIN(4,  6), 12, 3 },\t/* SD2_DS */\n+\t\t{ RCAR_GP_PIN(4,  7),  8, 3 },\t/* SD3_CLK */\n+\t\t{ RCAR_GP_PIN(4,  8),  4, 3 },\t/* SD3_CMD */\n+\t\t{ RCAR_GP_PIN(4,  9),  0, 3 },\t/* SD3_DAT0 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL16\", 0xe6060340) {\n+\t\t{ RCAR_GP_PIN(4, 10), 28, 3 },\t/* SD3_DAT1 */\n+\t\t{ RCAR_GP_PIN(4, 11), 24, 3 },\t/* SD3_DAT2 */\n+\t\t{ RCAR_GP_PIN(4, 12), 20, 3 },\t/* SD3_DAT3 */\n+\t\t{ RCAR_GP_PIN(4, 13), 16, 3 },\t/* SD3_DAT4 */\n+\t\t{ RCAR_GP_PIN(4, 14), 12, 3 },\t/* SD3_DAT5 */\n+\t\t{ RCAR_GP_PIN(4, 15),  8, 3 },\t/* SD3_DAT6 */\n+\t\t{ RCAR_GP_PIN(4, 16),  4, 3 },\t/* SD3_DAT7 */\n+\t\t{ RCAR_GP_PIN(4, 17),  0, 3 },\t/* SD3_DS */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL17\", 0xe6060344) {\n+\t\t{ RCAR_GP_PIN(3, 12), 28, 3 },\t/* SD0_CD */\n+\t\t{ RCAR_GP_PIN(3, 13), 24, 3 },\t/* SD0_WP */\n+\t\t{ RCAR_GP_PIN(3, 14), 20, 3 },\t/* SD1_CD */\n+\t\t{ RCAR_GP_PIN(3, 15), 16, 3 },\t/* SD1_WP */\n+\t\t{ RCAR_GP_PIN(5,  0), 12, 3 },\t/* SCK0 */\n+\t\t{ RCAR_GP_PIN(5,  1),  8, 3 },\t/* RX0 */\n+\t\t{ RCAR_GP_PIN(5,  2),  4, 3 },\t/* TX0 */\n+\t\t{ RCAR_GP_PIN(5,  3),  0, 3 },\t/* CTS0 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL18\", 0xe6060348) {\n+\t\t{ RCAR_GP_PIN(5,  4), 28, 3 },\t/* RTS0_TANS */\n+\t\t{ RCAR_GP_PIN(5,  5), 24, 3 },\t/* RX1 */\n+\t\t{ RCAR_GP_PIN(5,  6), 20, 3 },\t/* TX1 */\n+\t\t{ RCAR_GP_PIN(5,  7), 16, 3 },\t/* CTS1 */\n+\t\t{ RCAR_GP_PIN(5,  8), 12, 3 },\t/* RTS1_TANS */\n+\t\t{ RCAR_GP_PIN(5,  9),  8, 3 },\t/* SCK2 */\n+\t\t{ RCAR_GP_PIN(5, 10),  4, 3 },\t/* TX2 */\n+\t\t{ RCAR_GP_PIN(5, 11),  0, 3 },\t/* RX2 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL19\", 0xe606034c) {\n+\t\t{ RCAR_GP_PIN(5, 12), 28, 3 },\t/* HSCK0 */\n+\t\t{ RCAR_GP_PIN(5, 13), 24, 3 },\t/* HRX0 */\n+\t\t{ RCAR_GP_PIN(5, 14), 20, 3 },\t/* HTX0 */\n+\t\t{ RCAR_GP_PIN(5, 15), 16, 3 },\t/* HCTS0 */\n+\t\t{ RCAR_GP_PIN(5, 16), 12, 3 },\t/* HRTS0 */\n+\t\t{ RCAR_GP_PIN(5, 17),  8, 3 },\t/* MSIOF0_SCK */\n+\t\t{ RCAR_GP_PIN(5, 18),  4, 3 },\t/* MSIOF0_SYNC */\n+\t\t{ RCAR_GP_PIN(5, 19),  0, 3 },\t/* MSIOF0_SS1 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL20\", 0xe6060350) {\n+\t\t{ RCAR_GP_PIN(5, 20), 28, 3 },\t/* MSIOF0_TXD */\n+\t\t{ RCAR_GP_PIN(5, 21), 24, 3 },\t/* MSIOF0_SS2 */\n+\t\t{ RCAR_GP_PIN(5, 22), 20, 3 },\t/* MSIOF0_RXD */\n+\t\t{ RCAR_GP_PIN(5, 23), 16, 3 },\t/* MLB_CLK */\n+\t\t{ RCAR_GP_PIN(5, 24), 12, 3 },\t/* MLB_SIG */\n+\t\t{ RCAR_GP_PIN(5, 25),  8, 3 },\t/* MLB_DAT */\n+\t\t{ PIN_NUMBER('H', 37),  4, 3 },\t/* MLB_REF */\n+\t\t{ RCAR_GP_PIN(6,  0),  0, 3 },\t/* SSI_SCK01239 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL21\", 0xe6060354) {\n+\t\t{ RCAR_GP_PIN(6,  1), 28, 3 },\t/* SSI_WS01239 */\n+\t\t{ RCAR_GP_PIN(6,  2), 24, 3 },\t/* SSI_SDATA0 */\n+\t\t{ RCAR_GP_PIN(6,  3), 20, 3 },\t/* SSI_SDATA1 */\n+\t\t{ RCAR_GP_PIN(6,  4), 16, 3 },\t/* SSI_SDATA2 */\n+\t\t{ RCAR_GP_PIN(6,  5), 12, 3 },\t/* SSI_SCK349 */\n+\t\t{ RCAR_GP_PIN(6,  6),  8, 3 },\t/* SSI_WS349 */\n+\t\t{ RCAR_GP_PIN(6,  7),  4, 3 },\t/* SSI_SDATA3 */\n+\t\t{ RCAR_GP_PIN(6,  8),  0, 3 },\t/* SSI_SCK4 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL22\", 0xe6060358) {\n+\t\t{ RCAR_GP_PIN(6,  9), 28, 3 },\t/* SSI_WS4 */\n+\t\t{ RCAR_GP_PIN(6, 10), 24, 3 },\t/* SSI_SDATA4 */\n+\t\t{ RCAR_GP_PIN(6, 11), 20, 3 },\t/* SSI_SCK5 */\n+\t\t{ RCAR_GP_PIN(6, 12), 16, 3 },\t/* SSI_WS5 */\n+\t\t{ RCAR_GP_PIN(6, 13), 12, 3 },\t/* SSI_SDATA5 */\n+\t\t{ RCAR_GP_PIN(6, 14),  8, 3 },\t/* SSI_SCK6 */\n+\t\t{ RCAR_GP_PIN(6, 15),  4, 3 },\t/* SSI_WS6 */\n+\t\t{ RCAR_GP_PIN(6, 16),  0, 3 },\t/* SSI_SDATA6 */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL23\", 0xe606035c) {\n+\t\t{ RCAR_GP_PIN(6, 17), 28, 3 },\t/* SSI_SCK78 */\n+\t\t{ RCAR_GP_PIN(6, 18), 24, 3 },\t/* SSI_WS78 */\n+\t\t{ RCAR_GP_PIN(6, 19), 20, 3 },\t/* SSI_SDATA7 */\n+\t\t{ RCAR_GP_PIN(6, 20), 16, 3 },\t/* SSI_SDATA8 */\n+\t\t{ RCAR_GP_PIN(6, 21), 12, 3 },\t/* SSI_SDATA9 */\n+\t\t{ RCAR_GP_PIN(6, 22),  8, 3 },\t/* AUDIO_CLKA */\n+\t\t{ RCAR_GP_PIN(6, 23),  4, 3 },\t/* AUDIO_CLKB */\n+\t\t{ RCAR_GP_PIN(6, 24),  0, 3 },\t/* USB0_PWEN */\n+\t} },\n+\t{ PINMUX_DRIVE_REG(\"DRVCTRL24\", 0xe6060360) {\n+\t\t{ RCAR_GP_PIN(6, 25), 28, 3 },\t/* USB0_OVC */\n+\t\t{ RCAR_GP_PIN(6, 26), 24, 3 },\t/* USB1_PWEN */\n+\t\t{ RCAR_GP_PIN(6, 27), 20, 3 },\t/* USB1_OVC */\n+\t\t{ RCAR_GP_PIN(6, 28), 16, 3 },\t/* USB30_PWEN */\n+\t\t{ RCAR_GP_PIN(6, 29), 12, 3 },\t/* USB30_OVC */\n+\t\t{ RCAR_GP_PIN(6, 30),  8, 3 },\t/* GP6_30 */\n+\t\t{ RCAR_GP_PIN(6, 31),  4, 3 },\t/* GP6_31 */\n+\t} },\n+\t{ },\n+};\n+\n+static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)\n+{\n+\tint bit = -EINVAL;\n+\n+\t*pocctrl = 0xe6060380;\n+\n+\tif (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))\n+\t\tbit = pin & 0x1f;\n+\n+\tif (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))\n+\t\tbit = (pin & 0x1f) + 12;\n+\n+\treturn bit;\n+}\n+\n+#define PUEN\t0xe6060400\n+#define PUD\t0xe6060440\n+\n+#define PU0\t0x00\n+#define PU1\t0x04\n+#define PU2\t0x08\n+#define PU3\t0x0c\n+#define PU4\t0x10\n+#define PU5\t0x14\n+#define PU6\t0x18\n+\n+static const struct sh_pfc_bias_info bias_info[] = {\n+\t{ RCAR_GP_PIN(2, 11),    PU0, 31 },\t/* AVB_PHY_INT */\n+\t{ RCAR_GP_PIN(2, 10),    PU0, 30 },\t/* AVB_MAGIC */\n+\t{ RCAR_GP_PIN(2,  9),    PU0, 29 },\t/* AVB_MDC */\n+\t{ PIN_NUMBER('A', 9),    PU0, 28 },\t/* AVB_MDIO */\n+\t{ PIN_NUMBER('A', 12),   PU0, 27 },\t/* AVB_TXCREFCLK */\n+\t{ PIN_NUMBER('B', 17),   PU0, 26 },\t/* AVB_TD3 */\n+\t{ PIN_NUMBER('A', 17),   PU0, 25 },\t/* AVB_TD2 */\n+\t{ PIN_NUMBER('B', 18),   PU0, 24 },\t/* AVB_TD1 */\n+\t{ PIN_NUMBER('A', 18),   PU0, 23 },\t/* AVB_TD0 */\n+\t{ PIN_NUMBER('A', 19),   PU0, 22 },\t/* AVB_TXC */\n+\t{ PIN_NUMBER('A', 8),    PU0, 21 },\t/* AVB_TX_CTL */\n+\t{ PIN_NUMBER('B', 14),   PU0, 20 },\t/* AVB_RD3 */\n+\t{ PIN_NUMBER('A', 14),   PU0, 19 },\t/* AVB_RD2 */\n+\t{ PIN_NUMBER('B', 13),   PU0, 18 },\t/* AVB_RD1 */\n+\t{ PIN_NUMBER('A', 13),   PU0, 17 },\t/* AVB_RD0 */\n+\t{ PIN_NUMBER('B', 19),   PU0, 16 },\t/* AVB_RXC */\n+\t{ PIN_NUMBER('A', 16),   PU0, 15 },\t/* AVB_RX_CTL */\n+\t{ PIN_NUMBER('V', 7),    PU0, 14 },\t/* RPC_RESET# */\n+\t{ PIN_NUMBER('V', 6),    PU0, 13 },\t/* RPC_WP# */\n+\t{ PIN_NUMBER('Y', 7),    PU0, 12 },\t/* RPC_INT# */\n+\t{ PIN_NUMBER('V', 5),    PU0, 11 },\t/* QSPI1_SSL */\n+\t{ PIN_A_NUMBER('C', 3),  PU0, 10 },\t/* QSPI1_IO3 */\n+\t{ PIN_A_NUMBER('E', 4),  PU0,  9 },\t/* QSPI1_IO2 */\n+\t{ PIN_A_NUMBER('E', 5),  PU0,  8 },\t/* QSPI1_MISO_IO1 */\n+\t{ PIN_A_NUMBER('C', 7),  PU0,  7 },\t/* QSPI1_MOSI_IO0 */\n+\t{ PIN_NUMBER('V', 3),    PU0,  6 },\t/* QSPI1_SPCLK */\n+\t{ PIN_NUMBER('Y', 3),    PU0,  5 },\t/* QSPI0_SSL */\n+\t{ PIN_A_NUMBER('B', 6),  PU0,  4 },\t/* QSPI0_IO3 */\n+\t{ PIN_NUMBER('Y', 6),    PU0,  3 },\t/* QSPI0_IO2 */\n+\t{ PIN_A_NUMBER('B', 4),  PU0,  2 },\t/* QSPI0_MISO_IO1 */\n+\t{ PIN_A_NUMBER('C', 5),  PU0,  1 },\t/* QSPI0_MOSI_IO0 */\n+\t{ PIN_NUMBER('W', 3),    PU0,  0 },\t/* QSPI0_SPCLK */\n+\n+\t{ RCAR_GP_PIN(1, 19),    PU1, 31 },\t/* A19 */\n+\t{ RCAR_GP_PIN(1, 18),    PU1, 30 },\t/* A18 */\n+\t{ RCAR_GP_PIN(1, 17),    PU1, 29 },\t/* A17 */\n+\t{ RCAR_GP_PIN(1, 16),    PU1, 28 },\t/* A16 */\n+\t{ RCAR_GP_PIN(1, 15),    PU1, 27 },\t/* A15 */\n+\t{ RCAR_GP_PIN(1, 14),    PU1, 26 },\t/* A14 */\n+\t{ RCAR_GP_PIN(1, 13),    PU1, 25 },\t/* A13 */\n+\t{ RCAR_GP_PIN(1, 12),    PU1, 24 },\t/* A12 */\n+\t{ RCAR_GP_PIN(1, 11),    PU1, 23 },\t/* A11 */\n+\t{ RCAR_GP_PIN(1, 10),    PU1, 22 },\t/* A10 */\n+\t{ RCAR_GP_PIN(1,  9),    PU1, 21 },\t/* A9 */\n+\t{ RCAR_GP_PIN(1,  8),    PU1, 20 },\t/* A8 */\n+\t{ RCAR_GP_PIN(1,  7),    PU1, 19 },\t/* A7 */\n+\t{ RCAR_GP_PIN(1,  6),    PU1, 18 },\t/* A6 */\n+\t{ RCAR_GP_PIN(1,  5),    PU1, 17 },\t/* A5 */\n+\t{ RCAR_GP_PIN(1,  4),    PU1, 16 },\t/* A4 */\n+\t{ RCAR_GP_PIN(1,  3),    PU1, 15 },\t/* A3 */\n+\t{ RCAR_GP_PIN(1,  2),    PU1, 14 },\t/* A2 */\n+\t{ RCAR_GP_PIN(1,  1),    PU1, 13 },\t/* A1 */\n+\t{ RCAR_GP_PIN(1,  0),    PU1, 12 },\t/* A0 */\n+\t{ RCAR_GP_PIN(2,  8),    PU1, 11 },\t/* PWM2_A */\n+\t{ RCAR_GP_PIN(2,  7),    PU1, 10 },\t/* PWM1_A */\n+\t{ RCAR_GP_PIN(2,  6),    PU1,  9 },\t/* PWM0 */\n+\t{ RCAR_GP_PIN(2,  5),    PU1,  8 },\t/* IRQ5 */\n+\t{ RCAR_GP_PIN(2,  4),    PU1,  7 },\t/* IRQ4 */\n+\t{ RCAR_GP_PIN(2,  3),    PU1,  6 },\t/* IRQ3 */\n+\t{ RCAR_GP_PIN(2,  2),    PU1,  5 },\t/* IRQ2 */\n+\t{ RCAR_GP_PIN(2,  1),    PU1,  4 },\t/* IRQ1 */\n+\t{ RCAR_GP_PIN(2,  0),    PU1,  3 },\t/* IRQ0 */\n+\t{ RCAR_GP_PIN(2, 14),    PU1,  2 },\t/* AVB_AVTP_CAPTURE_A */\n+\t{ RCAR_GP_PIN(2, 13),    PU1,  1 },\t/* AVB_AVTP_MATCH_A */\n+\t{ RCAR_GP_PIN(2, 12),    PU1,  0 },\t/* AVB_LINK */\n+\n+\t{ PIN_A_NUMBER('P', 8),  PU2, 31 },\t/* DU_DOTCLKIN1 */\n+\t{ PIN_A_NUMBER('P', 7),  PU2, 30 },\t/* DU_DOTCLKIN0 */\n+\t{ RCAR_GP_PIN(7,  3),    PU2, 29 },\t/* GP7_03 */\n+\t{ RCAR_GP_PIN(7,  2),    PU2, 28 },\t/* HDMI0_CEC */\n+\t{ RCAR_GP_PIN(7,  1),    PU2, 27 },\t/* AVS2 */\n+\t{ RCAR_GP_PIN(7,  0),    PU2, 26 },\t/* AVS1 */\n+\t{ RCAR_GP_PIN(0, 15),    PU2, 25 },\t/* D15 */\n+\t{ RCAR_GP_PIN(0, 14),    PU2, 24 },\t/* D14 */\n+\t{ RCAR_GP_PIN(0, 13),    PU2, 23 },\t/* D13 */\n+\t{ RCAR_GP_PIN(0, 12),    PU2, 22 },\t/* D12 */\n+\t{ RCAR_GP_PIN(0, 11),    PU2, 21 },\t/* D11 */\n+\t{ RCAR_GP_PIN(0, 10),    PU2, 20 },\t/* D10 */\n+\t{ RCAR_GP_PIN(0,  9),    PU2, 19 },\t/* D9 */\n+\t{ RCAR_GP_PIN(0,  8),    PU2, 18 },\t/* D8 */\n+\t{ RCAR_GP_PIN(0,  7),    PU2, 17 },\t/* D7 */\n+\t{ RCAR_GP_PIN(0,  6),    PU2, 16 },\t/* D6 */\n+\t{ RCAR_GP_PIN(0,  5),    PU2, 15 },\t/* D5 */\n+\t{ RCAR_GP_PIN(0,  4),    PU2, 14 },\t/* D4 */\n+\t{ RCAR_GP_PIN(0,  3),    PU2, 13 },\t/* D3 */\n+\t{ RCAR_GP_PIN(0,  2),    PU2, 12 },\t/* D2 */\n+\t{ RCAR_GP_PIN(0,  1),    PU2, 11 },\t/* D1 */\n+\t{ RCAR_GP_PIN(0,  0),    PU2, 10 },\t/* D0 */\n+\t{ PIN_NUMBER('C', 1),    PU2,  9 },\t/* PRESETOUT# */\n+\t{ RCAR_GP_PIN(1, 27),    PU2,  8 },\t/* EX_WAIT0_A */\n+\t{ RCAR_GP_PIN(1, 26),    PU2,  7 },\t/* WE1_N */\n+\t{ RCAR_GP_PIN(1, 25),    PU2,  6 },\t/* WE0_N */\n+\t{ RCAR_GP_PIN(1, 24),    PU2,  5 },\t/* RD_WR_N */\n+\t{ RCAR_GP_PIN(1, 23),    PU2,  4 },\t/* RD_N */\n+\t{ RCAR_GP_PIN(1, 22),    PU2,  3 },\t/* BS_N */\n+\t{ RCAR_GP_PIN(1, 21),    PU2,  2 },\t/* CS1_N */\n+\t{ RCAR_GP_PIN(1, 20),    PU2,  1 },\t/* CS0_N */\n+\t{ RCAR_GP_PIN(1, 28),    PU2,  0 },\t/* CLKOUT */\n+\n+\t{ RCAR_GP_PIN(4,  9),    PU3, 31 },\t/* SD3_DAT0 */\n+\t{ RCAR_GP_PIN(4,  8),    PU3, 30 },\t/* SD3_CMD */\n+\t{ RCAR_GP_PIN(4,  7),    PU3, 29 },\t/* SD3_CLK */\n+\t{ RCAR_GP_PIN(4,  6),    PU3, 28 },\t/* SD2_DS */\n+\t{ RCAR_GP_PIN(4,  5),    PU3, 27 },\t/* SD2_DAT3 */\n+\t{ RCAR_GP_PIN(4,  4),    PU3, 26 },\t/* SD2_DAT2 */\n+\t{ RCAR_GP_PIN(4,  3),    PU3, 25 },\t/* SD2_DAT1 */\n+\t{ RCAR_GP_PIN(4,  2),    PU3, 24 },\t/* SD2_DAT0 */\n+\t{ RCAR_GP_PIN(4,  1),    PU3, 23 },\t/* SD2_CMD */\n+\t{ RCAR_GP_PIN(4,  0),    PU3, 22 },\t/* SD2_CLK */\n+\t{ RCAR_GP_PIN(3, 11),    PU3, 21 },\t/* SD1_DAT3 */\n+\t{ RCAR_GP_PIN(3, 10),    PU3, 20 },\t/* SD1_DAT2 */\n+\t{ RCAR_GP_PIN(3,  9),    PU3, 19 },\t/* SD1_DAT1 */\n+\t{ RCAR_GP_PIN(3,  8),    PU3, 18 },\t/* SD1_DAT0 */\n+\t{ RCAR_GP_PIN(3,  7),    PU3, 17 },\t/* SD1_CMD */\n+\t{ RCAR_GP_PIN(3,  6),    PU3, 16 },\t/* SD1_CLK */\n+\t{ RCAR_GP_PIN(3,  5),    PU3, 15 },\t/* SD0_DAT3 */\n+\t{ RCAR_GP_PIN(3,  4),    PU3, 14 },\t/* SD0_DAT2 */\n+\t{ RCAR_GP_PIN(3,  3),    PU3, 13 },\t/* SD0_DAT1 */\n+\t{ RCAR_GP_PIN(3,  2),    PU3, 12 },\t/* SD0_DAT0 */\n+\t{ RCAR_GP_PIN(3,  1),    PU3, 11 },\t/* SD0_CMD */\n+\t{ RCAR_GP_PIN(3,  0),    PU3, 10 },\t/* SD0_CLK */\n+\t{ PIN_A_NUMBER('T', 30), PU3,  9 },\t/* ASEBRK */\n+\t/* bit 8 n/a */\n+\t{ PIN_A_NUMBER('R', 29), PU3,  7 },\t/* TDI */\n+\t{ PIN_A_NUMBER('R', 30), PU3,  6 },\t/* TMS */\n+\t{ PIN_A_NUMBER('T', 27), PU3,  5 },\t/* TCK */\n+\t{ PIN_A_NUMBER('R', 26), PU3,  4 },\t/* TRST# */\n+\t{ PIN_A_NUMBER('D', 39), PU3,  3 },\t/* EXTALR*/\n+\t{ PIN_A_NUMBER('D', 38), PU3,  2 },\t/* FSCLKST */\n+\t/* bit 1 n/a on M3*/\n+\t{ PIN_A_NUMBER('R', 8),  PU3,  0 },\t/* DU_DOTCLKIN2 */\n+\n+\t{ RCAR_GP_PIN(5, 19),    PU4, 31 },\t/* MSIOF0_SS1 */\n+\t{ RCAR_GP_PIN(5, 18),    PU4, 30 },\t/* MSIOF0_SYNC */\n+\t{ RCAR_GP_PIN(5, 17),    PU4, 29 },\t/* MSIOF0_SCK */\n+\t{ RCAR_GP_PIN(5, 16),    PU4, 28 },\t/* HRTS0_N */\n+\t{ RCAR_GP_PIN(5, 15),    PU4, 27 },\t/* HCTS0_N */\n+\t{ RCAR_GP_PIN(5, 14),    PU4, 26 },\t/* HTX0 */\n+\t{ RCAR_GP_PIN(5, 13),    PU4, 25 },\t/* HRX0 */\n+\t{ RCAR_GP_PIN(5, 12),    PU4, 24 },\t/* HSCK0 */\n+\t{ RCAR_GP_PIN(5, 11),    PU4, 23 },\t/* RX2_A */\n+\t{ RCAR_GP_PIN(5, 10),    PU4, 22 },\t/* TX2_A */\n+\t{ RCAR_GP_PIN(5,  9),    PU4, 21 },\t/* SCK2 */\n+\t{ RCAR_GP_PIN(5,  8),    PU4, 20 },\t/* RTS1_N_TANS */\n+\t{ RCAR_GP_PIN(5,  7),    PU4, 19 },\t/* CTS1_N */\n+\t{ RCAR_GP_PIN(5,  6),    PU4, 18 },\t/* TX1_A */\n+\t{ RCAR_GP_PIN(5,  5),    PU4, 17 },\t/* RX1_A */\n+\t{ RCAR_GP_PIN(5,  4),    PU4, 16 },\t/* RTS0_N_TANS */\n+\t{ RCAR_GP_PIN(5,  3),    PU4, 15 },\t/* CTS0_N */\n+\t{ RCAR_GP_PIN(5,  2),    PU4, 14 },\t/* TX0 */\n+\t{ RCAR_GP_PIN(5,  1),    PU4, 13 },\t/* RX0 */\n+\t{ RCAR_GP_PIN(5,  0),    PU4, 12 },\t/* SCK0 */\n+\t{ RCAR_GP_PIN(3, 15),    PU4, 11 },\t/* SD1_WP */\n+\t{ RCAR_GP_PIN(3, 14),    PU4, 10 },\t/* SD1_CD */\n+\t{ RCAR_GP_PIN(3, 13),    PU4,  9 },\t/* SD0_WP */\n+\t{ RCAR_GP_PIN(3, 12),    PU4,  8 },\t/* SD0_CD */\n+\t{ RCAR_GP_PIN(4, 17),    PU4,  7 },\t/* SD3_DS */\n+\t{ RCAR_GP_PIN(4, 16),    PU4,  6 },\t/* SD3_DAT7 */\n+\t{ RCAR_GP_PIN(4, 15),    PU4,  5 },\t/* SD3_DAT6 */\n+\t{ RCAR_GP_PIN(4, 14),    PU4,  4 },\t/* SD3_DAT5 */\n+\t{ RCAR_GP_PIN(4, 13),    PU4,  3 },\t/* SD3_DAT4 */\n+\t{ RCAR_GP_PIN(4, 12),    PU4,  2 },\t/* SD3_DAT3 */\n+\t{ RCAR_GP_PIN(4, 11),    PU4,  1 },\t/* SD3_DAT2 */\n+\t{ RCAR_GP_PIN(4, 10),    PU4,  0 },\t/* SD3_DAT1 */\n+\n+\t{ RCAR_GP_PIN(6, 24),    PU5, 31 },\t/* USB0_PWEN */\n+\t{ RCAR_GP_PIN(6, 23),    PU5, 30 },\t/* AUDIO_CLKB_B */\n+\t{ RCAR_GP_PIN(6, 22),    PU5, 29 },\t/* AUDIO_CLKA_A */\n+\t{ RCAR_GP_PIN(6, 21),    PU5, 28 },\t/* SSI_SDATA9_A */\n+\t{ RCAR_GP_PIN(6, 20),    PU5, 27 },\t/* SSI_SDATA8 */\n+\t{ RCAR_GP_PIN(6, 19),    PU5, 26 },\t/* SSI_SDATA7 */\n+\t{ RCAR_GP_PIN(6, 18),    PU5, 25 },\t/* SSI_WS78 */\n+\t{ RCAR_GP_PIN(6, 17),    PU5, 24 },\t/* SSI_SCK78 */\n+\t{ RCAR_GP_PIN(6, 16),    PU5, 23 },\t/* SSI_SDATA6 */\n+\t{ RCAR_GP_PIN(6, 15),    PU5, 22 },\t/* SSI_WS6 */\n+\t{ RCAR_GP_PIN(6, 14),    PU5, 21 },\t/* SSI_SCK6 */\n+\t{ RCAR_GP_PIN(6, 13),    PU5, 20 },\t/* SSI_SDATA5 */\n+\t{ RCAR_GP_PIN(6, 12),    PU5, 19 },\t/* SSI_WS5 */\n+\t{ RCAR_GP_PIN(6, 11),    PU5, 18 },\t/* SSI_SCK5 */\n+\t{ RCAR_GP_PIN(6, 10),    PU5, 17 },\t/* SSI_SDATA4 */\n+\t{ RCAR_GP_PIN(6,  9),    PU5, 16 },\t/* SSI_WS4 */\n+\t{ RCAR_GP_PIN(6,  8),    PU5, 15 },\t/* SSI_SCK4 */\n+\t{ RCAR_GP_PIN(6,  7),    PU5, 14 },\t/* SSI_SDATA3 */\n+\t{ RCAR_GP_PIN(6,  6),    PU5, 13 },\t/* SSI_WS349 */\n+\t{ RCAR_GP_PIN(6,  5),    PU5, 12 },\t/* SSI_SCK349 */\n+\t{ RCAR_GP_PIN(6,  4),    PU5, 11 },\t/* SSI_SDATA2_A */\n+\t{ RCAR_GP_PIN(6,  3),    PU5, 10 },\t/* SSI_SDATA1_A */\n+\t{ RCAR_GP_PIN(6,  2),    PU5,  9 },\t/* SSI_SDATA0 */\n+\t{ RCAR_GP_PIN(6,  1),    PU5,  8 },\t/* SSI_WS01239 */\n+\t{ RCAR_GP_PIN(6,  0),    PU5,  7 },\t/* SSI_SCK01239 */\n+\t{ PIN_NUMBER('H', 37),   PU5,  6 },\t/* MLB_REF */\n+\t{ RCAR_GP_PIN(5, 25),    PU5,  5 },\t/* MLB_DAT */\n+\t{ RCAR_GP_PIN(5, 24),    PU5,  4 },\t/* MLB_SIG */\n+\t{ RCAR_GP_PIN(5, 23),    PU5,  3 },\t/* MLB_CLK */\n+\t{ RCAR_GP_PIN(5, 22),    PU5,  2 },\t/* MSIOF0_RXD */\n+\t{ RCAR_GP_PIN(5, 21),    PU5,  1 },\t/* MSIOF0_SS2 */\n+\t{ RCAR_GP_PIN(5, 20),    PU5,  0 },\t/* MSIOF0_TXD */\n+\n+\t{ RCAR_GP_PIN(6, 31),    PU6,  6 },\t/* GP6_31 */\n+\t{ RCAR_GP_PIN(6, 30),    PU6,  5 },\t/* GP6_30 */\n+\t{ RCAR_GP_PIN(6, 29),    PU6,  4 },\t/* USB30_OVC */\n+\t{ RCAR_GP_PIN(6, 28),    PU6,  3 },\t/* USB30_PWEN */\n+\t{ RCAR_GP_PIN(6, 27),    PU6,  2 },\t/* USB1_OVC */\n+\t{ RCAR_GP_PIN(6, 26),    PU6,  1 },\t/* USB1_PWEN */\n+\t{ RCAR_GP_PIN(6, 25),    PU6,  0 },\t/* USB0_OVC */\n+};\n+\n+static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,\n+\t\t\t\t\t    unsigned int pin)\n+{\n+\tconst struct sh_pfc_bias_info *info;\n+\tu32 reg;\n+\tu32 bit;\n+\n+\tinfo = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);\n+\tif (!info)\n+\t\treturn PIN_CONFIG_BIAS_DISABLE;\n+\n+\treg = info->reg;\n+\tbit = BIT(info->bit);\n+\n+\tif (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))\n+\t\treturn PIN_CONFIG_BIAS_DISABLE;\n+\telse if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)\n+\t\treturn PIN_CONFIG_BIAS_PULL_UP;\n+\telse\n+\t\treturn PIN_CONFIG_BIAS_PULL_DOWN;\n+}\n+\n+static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,\n+\t\t\t\t   unsigned int bias)\n+{\n+\tconst struct sh_pfc_bias_info *info;\n+\tu32 enable, updown;\n+\tu32 reg;\n+\tu32 bit;\n+\n+\tinfo = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);\n+\tif (!info)\n+\t\treturn;\n+\n+\treg = info->reg;\n+\tbit = BIT(info->bit);\n+\n+\tenable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;\n+\tif (bias != PIN_CONFIG_BIAS_DISABLE)\n+\t\tenable |= bit;\n+\n+\tupdown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;\n+\tif (bias == PIN_CONFIG_BIAS_PULL_UP)\n+\t\tupdown |= bit;\n+\n+\tsh_pfc_write_reg(pfc, PUD + reg, 32, updown);\n+\tsh_pfc_write_reg(pfc, PUEN + reg, 32, enable);\n+}\n+\n+static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {\n+\t.pin_to_pocctrl = r8a7796_pin_to_pocctrl,\n+\t.get_bias = r8a7796_pinmux_get_bias,\n+\t.set_bias = r8a7796_pinmux_set_bias,\n+};\n+\n+const struct sh_pfc_soc_info r8a7796_pinmux_info = {\n+\t.name = \"r8a77960_pfc\",\n+\t.ops = &r8a7796_pinmux_ops,\n+\t.unlock_reg = 0xe6060000, /* PMMR */\n+\n+\t.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },\n+\n+\t.pins = pinmux_pins,\n+\t.nr_pins = ARRAY_SIZE(pinmux_pins),\n+\t.groups = pinmux_groups,\n+\t.nr_groups = ARRAY_SIZE(pinmux_groups),\n+\t.functions = pinmux_functions,\n+\t.nr_functions = ARRAY_SIZE(pinmux_functions),\n+\n+\t.cfg_regs = pinmux_config_regs,\n+\t.drive_regs = pinmux_drive_regs,\n+\n+\t.pinmux_data = pinmux_data,\n+\t.pinmux_data_size = ARRAY_SIZE(pinmux_data),\n+};\ndiff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c\nnew file mode 100644\nindex 0000000000..63e2eeb449\n--- /dev/null\n+++ b/drivers/pinctrl/renesas/pfc.c\n@@ -0,0 +1,565 @@\n+/*\n+ * Pin Control driver for SuperH Pin Function Controller.\n+ *\n+ * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart\n+ *\n+ * Copyright (C) 2008 Magnus Damm\n+ * Copyright (C) 2009 - 2012 Paul Mundt\n+ * Copyright (C) 2017 Marek Vasut\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#define DRV_NAME \"sh-pfc\"\n+\n+#include <common.h>\n+#include <dm.h>\n+#include <errno.h>\n+#include <dm/pinctrl.h>\n+#include <linux/io.h>\n+#include <linux/sizes.h>\n+\n+#include \"sh_pfc.h\"\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+enum sh_pfc_model {\n+\tSH_PFC_R8A7795 = 0,\n+\tSH_PFC_R8A7796,\n+};\n+\n+struct sh_pfc_pin_config {\n+\tu32 type;\n+};\n+\n+struct sh_pfc_pinctrl {\n+\tstruct sh_pfc *pfc;\n+\n+\tstruct sh_pfc_pin_config *configs;\n+\n+\tconst char *func_prop_name;\n+\tconst char *groups_prop_name;\n+\tconst char *pins_prop_name;\n+};\n+\n+struct sh_pfc_pin_range {\n+\tu16 start;\n+\tu16 end;\n+};\n+\n+struct sh_pfc_pinctrl_priv {\n+\tstruct sh_pfc\t\t\tpfc;\n+\tstruct sh_pfc_pinctrl\t\tpmx;\n+};\n+\n+int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)\n+{\n+\tunsigned int offset;\n+\tunsigned int i;\n+\n+\tfor (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {\n+\t\tconst struct sh_pfc_pin_range *range = &pfc->ranges[i];\n+\n+\t\tif (pin <= range->end)\n+\t\t\treturn pin >= range->start\n+\t\t\t     ? offset + pin - range->start : -1;\n+\n+\t\toffset += range->end - range->start + 1;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n+static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)\n+{\n+\tif (enum_id < r->begin)\n+\t\treturn 0;\n+\n+\tif (enum_id > r->end)\n+\t\treturn 0;\n+\n+\treturn 1;\n+}\n+\n+u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)\n+{\n+\tswitch (reg_width) {\n+\tcase 8:\n+\t\treturn readb(mapped_reg);\n+\tcase 16:\n+\t\treturn readw(mapped_reg);\n+\tcase 32:\n+\t\treturn readl(mapped_reg);\n+\t}\n+\n+\tBUG();\n+\treturn 0;\n+}\n+\n+void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,\n+\t\t\t  u32 data)\n+{\n+\tswitch (reg_width) {\n+\tcase 8:\n+\t\twriteb(data, mapped_reg);\n+\t\treturn;\n+\tcase 16:\n+\t\twritew(data, mapped_reg);\n+\t\treturn;\n+\tcase 32:\n+\t\twritel(data, mapped_reg);\n+\t\treturn;\n+\t}\n+\n+\tBUG();\n+}\n+\n+u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width)\n+{\n+\treturn sh_pfc_read_raw_reg(pfc->regs + reg, width);\n+}\n+\n+void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)\n+{\n+\tvoid __iomem *unlock_reg =\n+\t\t(void __iomem *)(uintptr_t)pfc->info->unlock_reg;\n+\n+\tif (pfc->info->unlock_reg)\n+\t\tsh_pfc_write_raw_reg(unlock_reg, 32, ~data);\n+\n+\tsh_pfc_write_raw_reg(pfc->regs + reg, width, data);\n+}\n+\n+static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,\n+\t\t\t\t     const struct pinmux_cfg_reg *crp,\n+\t\t\t\t     unsigned int in_pos,\n+\t\t\t\t     void __iomem **mapped_regp, u32 *maskp,\n+\t\t\t\t     unsigned int *posp)\n+{\n+\tunsigned int k;\n+\n+\t*mapped_regp = (void __iomem *)(uintptr_t)crp->reg;\n+\n+\tif (crp->field_width) {\n+\t\t*maskp = (1 << crp->field_width) - 1;\n+\t\t*posp = crp->reg_width - ((in_pos + 1) * crp->field_width);\n+\t} else {\n+\t\t*maskp = (1 << crp->var_field_width[in_pos]) - 1;\n+\t\t*posp = crp->reg_width;\n+\t\tfor (k = 0; k <= in_pos; k++)\n+\t\t\t*posp -= crp->var_field_width[k];\n+\t}\n+}\n+\n+static void sh_pfc_write_config_reg(struct sh_pfc *pfc,\n+\t\t\t\t    const struct pinmux_cfg_reg *crp,\n+\t\t\t\t    unsigned int field, u32 value)\n+{\n+\tvoid __iomem *mapped_reg;\n+\tvoid __iomem *unlock_reg =\n+\t\t(void __iomem *)(uintptr_t)pfc->info->unlock_reg;\n+\tunsigned int pos;\n+\tu32 mask, data;\n+\n+\tsh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);\n+\n+\tdev_dbg(pfc->dev, \"write_reg addr = %x, value = 0x%x, field = %u, \"\n+\t\t\"r_width = %u, f_width = %u\\n\",\n+\t\tcrp->reg, value, field, crp->reg_width, crp->field_width);\n+\n+\tmask = ~(mask << pos);\n+\tvalue = value << pos;\n+\n+\tdata = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);\n+\tdata &= mask;\n+\tdata |= value;\n+\n+\tif (pfc->info->unlock_reg)\n+\t\tsh_pfc_write_raw_reg(unlock_reg, 32, ~data);\n+\n+\tsh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);\n+}\n+\n+static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,\n+\t\t\t\t const struct pinmux_cfg_reg **crp,\n+\t\t\t\t unsigned int *fieldp, u32 *valuep)\n+{\n+\tunsigned int k = 0;\n+\n+\twhile (1) {\n+\t\tconst struct pinmux_cfg_reg *config_reg =\n+\t\t\tpfc->info->cfg_regs + k;\n+\t\tunsigned int r_width = config_reg->reg_width;\n+\t\tunsigned int f_width = config_reg->field_width;\n+\t\tunsigned int curr_width;\n+\t\tunsigned int bit_pos;\n+\t\tunsigned int pos = 0;\n+\t\tunsigned int m = 0;\n+\n+\t\tif (!r_width)\n+\t\t\tbreak;\n+\n+\t\tfor (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {\n+\t\t\tu32 ncomb;\n+\t\t\tu32 n;\n+\n+\t\t\tif (f_width)\n+\t\t\t\tcurr_width = f_width;\n+\t\t\telse\n+\t\t\t\tcurr_width = config_reg->var_field_width[m];\n+\n+\t\t\tncomb = 1 << curr_width;\n+\t\t\tfor (n = 0; n < ncomb; n++) {\n+\t\t\t\tif (config_reg->enum_ids[pos + n] == enum_id) {\n+\t\t\t\t\t*crp = config_reg;\n+\t\t\t\t\t*fieldp = m;\n+\t\t\t\t\t*valuep = n;\n+\t\t\t\t\treturn 0;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tpos += ncomb;\n+\t\t\tm++;\n+\t\t}\n+\t\tk++;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n+static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,\n+\t\t\t      u16 *enum_idp)\n+{\n+\tconst u16 *data = pfc->info->pinmux_data;\n+\tunsigned int k;\n+\n+\tif (pos) {\n+\t\t*enum_idp = data[pos + 1];\n+\t\treturn pos + 1;\n+\t}\n+\n+\tfor (k = 0; k < pfc->info->pinmux_data_size; k++) {\n+\t\tif (data[k] == mark) {\n+\t\t\t*enum_idp = data[k + 1];\n+\t\t\treturn k + 1;\n+\t\t}\n+\t}\n+\n+\tdev_err(pfc->dev, \"cannot locate data/mark enum_id for mark %d\\n\",\n+\t\tmark);\n+\treturn -EINVAL;\n+}\n+\n+int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)\n+{\n+\tconst struct pinmux_range *range;\n+\tint pos = 0;\n+\n+\tswitch (pinmux_type) {\n+\tcase PINMUX_TYPE_GPIO:\n+\tcase PINMUX_TYPE_FUNCTION:\n+\t\trange = NULL;\n+\t\tbreak;\n+\n+\tcase PINMUX_TYPE_OUTPUT:\n+\t\trange = &pfc->info->output;\n+\t\tbreak;\n+\n+\tcase PINMUX_TYPE_INPUT:\n+\t\trange = &pfc->info->input;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Iterate over all the configuration fields we need to update. */\n+\twhile (1) {\n+\t\tconst struct pinmux_cfg_reg *cr;\n+\t\tunsigned int field;\n+\t\tu16 enum_id;\n+\t\tu32 value;\n+\t\tint in_range;\n+\t\tint ret;\n+\n+\t\tpos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);\n+\t\tif (pos < 0)\n+\t\t\treturn pos;\n+\n+\t\tif (!enum_id)\n+\t\t\tbreak;\n+\n+\t\t/* Check if the configuration field selects a function. If it\n+\t\t * doesn't, skip the field if it's not applicable to the\n+\t\t * requested pinmux type.\n+\t\t */\n+\t\tin_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);\n+\t\tif (!in_range) {\n+\t\t\tif (pinmux_type == PINMUX_TYPE_FUNCTION) {\n+\t\t\t\t/* Functions are allowed to modify all\n+\t\t\t\t * fields.\n+\t\t\t\t */\n+\t\t\t\tin_range = 1;\n+\t\t\t} else if (pinmux_type != PINMUX_TYPE_GPIO) {\n+\t\t\t\t/* Input/output types can only modify fields\n+\t\t\t\t * that correspond to their respective ranges.\n+\t\t\t\t */\n+\t\t\t\tin_range = sh_pfc_enum_in_range(enum_id, range);\n+\n+\t\t\t\t/*\n+\t\t\t\t * special case pass through for fixed\n+\t\t\t\t * input-only or output-only pins without\n+\t\t\t\t * function enum register association.\n+\t\t\t\t */\n+\t\t\t\tif (in_range && enum_id == range->force)\n+\t\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t\t/* GPIOs are only allowed to modify function fields. */\n+\t\t}\n+\n+\t\tif (!in_range)\n+\t\t\tcontinue;\n+\n+\t\tret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\tsh_pfc_write_config_reg(pfc, cr, field, value);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+const struct sh_pfc_bias_info *\n+sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,\n+\t\t\tunsigned int num, unsigned int pin)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < num; i++)\n+\t\tif (info[i].pin == pin)\n+\t\t\treturn &info[i];\n+\n+\tprintf(\"Pin %u is not in bias info list\\n\", pin);\n+\n+\treturn NULL;\n+}\n+\n+static int sh_pfc_init_ranges(struct sh_pfc *pfc)\n+{\n+\tstruct sh_pfc_pin_range *range;\n+\tunsigned int nr_ranges;\n+\tunsigned int i;\n+\n+\tif (pfc->info->pins[0].pin == (u16)-1) {\n+\t\t/* Pin number -1 denotes that the SoC doesn't report pin numbers\n+\t\t * in its pin arrays yet. Consider the pin numbers range as\n+\t\t * continuous and allocate a single range.\n+\t\t */\n+\t\tpfc->nr_ranges = 1;\n+\t\tpfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);\n+\t\tif (pfc->ranges == NULL)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tpfc->ranges->start = 0;\n+\t\tpfc->ranges->end = pfc->info->nr_pins - 1;\n+\t\tpfc->nr_gpio_pins = pfc->info->nr_pins;\n+\n+\t\treturn 0;\n+\t}\n+\n+\t/* Count, allocate and fill the ranges. The PFC SoC data pins array must\n+\t * be sorted by pin numbers, and pins without a GPIO port must come\n+\t * last.\n+\t */\n+\tfor (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {\n+\t\tif (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)\n+\t\t\tnr_ranges++;\n+\t}\n+\n+\tpfc->nr_ranges = nr_ranges;\n+\tpfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);\n+\tif (pfc->ranges == NULL)\n+\t\treturn -ENOMEM;\n+\n+\trange = pfc->ranges;\n+\trange->start = pfc->info->pins[0].pin;\n+\n+\tfor (i = 1; i < pfc->info->nr_pins; ++i) {\n+\t\tif (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)\n+\t\t\tcontinue;\n+\n+\t\trange->end = pfc->info->pins[i-1].pin;\n+\t\tif (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))\n+\t\t\tpfc->nr_gpio_pins = range->end + 1;\n+\n+\t\trange++;\n+\t\trange->start = pfc->info->pins[i].pin;\n+\t}\n+\n+\trange->end = pfc->info->pins[i-1].pin;\n+\tif (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))\n+\t\tpfc->nr_gpio_pins = range->end + 1;\n+\n+\treturn 0;\n+}\n+\n+static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)\n+{\n+\tstruct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);\n+\n+\treturn priv->pfc.info->nr_pins;\n+}\n+\n+static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,\n+\t\t\t\t\t\t  unsigned selector)\n+{\n+\tstruct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);\n+\n+\treturn priv->pfc.info->pins[selector].name;\n+}\n+\n+static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)\n+{\n+\tstruct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);\n+\n+\treturn priv->pfc.info->nr_groups;\n+}\n+\n+static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,\n+\t\t\t\t\t\t  unsigned selector)\n+{\n+\tstruct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);\n+\n+\treturn priv->pfc.info->groups[selector].name;\n+}\n+\n+static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)\n+{\n+\tstruct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);\n+\n+\treturn priv->pfc.info->nr_functions;\n+}\n+\n+static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,\n+\t\t\t\t\t\t  unsigned selector)\n+{\n+\tstruct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);\n+\n+\treturn priv->pfc.info->functions[selector].name;\n+}\n+\n+static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,\n+\t\t\t\t     unsigned func_selector)\n+{\n+\tstruct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);\n+\tstruct sh_pfc_pinctrl *pmx = &priv->pmx;\n+\tstruct sh_pfc *pfc = &priv->pfc;\n+\tconst struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];\n+\tunsigned int i;\n+\tint ret = 0;\n+\n+\tfor (i = 0; i < grp->nr_pins; ++i) {\n+\t\tint idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);\n+\t\tstruct sh_pfc_pin_config *cfg = &pmx->configs[idx];\n+\n+\t\tif (cfg->type != PINMUX_TYPE_NONE) {\n+\t\t\tret = -EBUSY;\n+\t\t\tgoto done;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < grp->nr_pins; ++i) {\n+\t\tret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);\n+\t\tif (ret < 0)\n+\t\t\tbreak;\n+\t}\n+\n+done:\n+\treturn ret;\n+}\n+\n+static struct pinctrl_ops sh_pfc_pinctrl_ops = {\n+\t.get_pins_count\t\t= sh_pfc_pinctrl_get_pins_count,\n+\t.get_pin_name\t\t= sh_pfc_pinctrl_get_pin_name,\n+\t.get_groups_count\t= sh_pfc_pinctrl_get_groups_count,\n+\t.get_group_name\t\t= sh_pfc_pinctrl_get_group_name,\n+\t.get_functions_count\t= sh_pfc_pinctrl_get_functions_count,\n+\t.get_function_name\t= sh_pfc_pinctrl_get_function_name,\n+\n+\t.pinmux_group_set\t= sh_pfc_pinctrl_group_set,\n+\t.set_state\t\t= pinctrl_generic_set_state,\n+};\n+\n+static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)\n+{\n+\tunsigned int i;\n+\n+\t/* Allocate and initialize the pins and configs arrays. */\n+\tpmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,\n+\t\t\t\t    GFP_KERNEL);\n+\tif (unlikely(!pmx->configs))\n+\t\treturn -ENOMEM;\n+\n+\tfor (i = 0; i < pfc->info->nr_pins; ++i) {\n+\t\tstruct sh_pfc_pin_config *cfg = &pmx->configs[i];\n+\t\tcfg->type = PINMUX_TYPE_NONE;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+\n+static int sh_pfc_pinctrl_probe(struct udevice *dev)\n+{\n+\tstruct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);\n+\tenum sh_pfc_model model = dev_get_driver_data(dev);\n+\tfdt_addr_t base;\n+\n+\tbase = devfdt_get_addr(dev);\n+\tif (base == FDT_ADDR_T_NONE)\n+\t\treturn -EINVAL;\n+\n+\tpriv->pfc.regs = devm_ioremap(dev, base, SZ_2K);\n+\tif (!priv->pfc.regs)\n+\t\treturn -ENOMEM;\n+\n+#ifdef CONFIG_PINCTRL_PFC_R8A7795\n+\tif (model == SH_PFC_R8A7795)\n+\t\tpriv->pfc.info = &r8a7795_pinmux_info;\n+#endif\n+#ifdef CONFIG_PINCTRL_PFC_R8A7796\n+\tif (model == SH_PFC_R8A7796)\n+\t\tpriv->pfc.info = &r8a7796_pinmux_info;\n+#endif\n+\n+\tpriv->pmx.pfc = &priv->pfc;\n+\tsh_pfc_init_ranges(&priv->pfc);\n+\tsh_pfc_map_pins(&priv->pfc, &priv->pmx);\n+\n+\treturn 0;\n+}\n+\n+static const struct udevice_id sh_pfc_pinctrl_ids[] = {\n+#ifdef CONFIG_PINCTRL_PFC_R8A7795\n+\t{\n+\t\t.compatible = \"renesas,pfc-r8a7795\",\n+\t\t.data = SH_PFC_R8A7795,\n+\t},\n+#endif\n+#ifdef CONFIG_PINCTRL_PFC_R8A7796\n+\t{\n+\t\t.compatible = \"renesas,pfc-r8a7796\",\n+\t\t.data = SH_PFC_R8A7796,\n+\t},\n+#endif\n+\t{ },\n+};\n+\n+U_BOOT_DRIVER(pinctrl_sh_pfc) = {\n+\t.name\t\t= \"sh_pfc_pinctrl\",\n+\t.id\t\t= UCLASS_PINCTRL,\n+\t.of_match\t= sh_pfc_pinctrl_ids,\n+\t.priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),\n+\t.ops\t\t= &sh_pfc_pinctrl_ops,\n+\t.probe\t\t= sh_pfc_pinctrl_probe,\n+};\ndiff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h\nnew file mode 100644\nindex 0000000000..7aef2d360b\n--- /dev/null\n+++ b/drivers/pinctrl/renesas/sh_pfc.h\n@@ -0,0 +1,575 @@\n+/*\n+ * SuperH Pin Function Controller Support\n+ *\n+ * Copyright (c) 2008 Magnus Damm\n+ *\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ */\n+\n+#ifndef __SH_PFC_H\n+#define __SH_PFC_H\n+\n+#include <linux/stringify.h>\n+\n+enum {\n+\tPINMUX_TYPE_NONE,\n+\tPINMUX_TYPE_FUNCTION,\n+\tPINMUX_TYPE_GPIO,\n+\tPINMUX_TYPE_OUTPUT,\n+\tPINMUX_TYPE_INPUT,\n+};\n+\n+#define SH_PFC_PIN_CFG_INPUT\t\t(1 << 0)\n+#define SH_PFC_PIN_CFG_OUTPUT\t\t(1 << 1)\n+#define SH_PFC_PIN_CFG_PULL_UP\t\t(1 << 2)\n+#define SH_PFC_PIN_CFG_PULL_DOWN\t(1 << 3)\n+#define SH_PFC_PIN_CFG_IO_VOLTAGE\t(1 << 4)\n+#define SH_PFC_PIN_CFG_DRIVE_STRENGTH\t(1 << 5)\n+#define SH_PFC_PIN_CFG_NO_GPIO\t\t(1 << 31)\n+\n+struct sh_pfc_pin {\n+\tu16 pin;\n+\tu16 enum_id;\n+\tconst char *name;\n+\tunsigned int configs;\n+};\n+\n+#define SH_PFC_PIN_GROUP(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.pins = n##_pins,\t\t\t\\\n+\t\t.mux = n##_mux,\t\t\t\t\\\n+\t\t.nr_pins = ARRAY_SIZE(n##_pins),\t\\\n+\t}\n+\n+struct sh_pfc_pin_group {\n+\tconst char *name;\n+\tconst unsigned int *pins;\n+\tconst unsigned int *mux;\n+\tunsigned int nr_pins;\n+};\n+\n+/*\n+ * Using union vin_data saves memory occupied by the VIN data pins.\n+ * VIN_DATA_PIN_GROUP() is  a macro  used  to describe the VIN pin groups\n+ * in this case.\n+ */\n+#define VIN_DATA_PIN_GROUP(n, s)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\\\n+\t\t.name = #n#s,\t\t\t\t\t\\\n+\t\t.pins = n##_pins.data##s,\t\t\t\\\n+\t\t.mux = n##_mux.data##s,\t\t\t\t\\\n+\t\t.nr_pins = ARRAY_SIZE(n##_pins.data##s),\t\\\n+\t}\n+\n+union vin_data {\n+\tunsigned int data24[24];\n+\tunsigned int data20[20];\n+\tunsigned int data16[16];\n+\tunsigned int data12[12];\n+\tunsigned int data10[10];\n+\tunsigned int data8[8];\n+\tunsigned int data4[4];\n+};\n+\n+#define SH_PFC_FUNCTION(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.nr_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t}\n+\n+struct sh_pfc_function {\n+\tconst char *name;\n+\tconst char * const *groups;\n+\tunsigned int nr_groups;\n+};\n+\n+struct pinmux_func {\n+\tu16 enum_id;\n+\tconst char *name;\n+};\n+\n+struct pinmux_cfg_reg {\n+\tu32 reg;\n+\tu8 reg_width, field_width;\n+\tconst u16 *enum_ids;\n+\tconst u8 *var_field_width;\n+};\n+\n+/*\n+ * Describe a config register consisting of several fields of the same width\n+ *   - name: Register name (unused, for documentation purposes only)\n+ *   - r: Physical register address\n+ *   - r_width: Width of the register (in bits)\n+ *   - f_width: Width of the fixed-width register fields (in bits)\n+ * This macro must be followed by initialization data: For each register field\n+ * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,\n+ * one for each possible combination of the register field bit values.\n+ */\n+#define PINMUX_CFG_REG(name, r, r_width, f_width) \\\n+\t.reg = r, .reg_width = r_width, .field_width = f_width,\t\t\\\n+\t.enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])\n+\n+/*\n+ * Describe a config register consisting of several fields of different widths\n+ *   - name: Register name (unused, for documentation purposes only)\n+ *   - r: Physical register address\n+ *   - r_width: Width of the register (in bits)\n+ *   - var_fw0, var_fwn...: List of widths of the register fields (in bits),\n+ *                          From left to right (i.e. MSB to LSB)\n+ * This macro must be followed by initialization data: For each register field\n+ * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,\n+ * one for each possible combination of the register field bit values.\n+ */\n+#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \\\n+\t.reg = r, .reg_width = r_width,\t\\\n+\t.var_field_width = (const u8 [r_width]) \\\n+\t\t{ var_fw0, var_fwn, 0 }, \\\n+\t.enum_ids = (const u16 [])\n+\n+struct pinmux_drive_reg_field {\n+\tu16 pin;\n+\tu8 offset;\n+\tu8 size;\n+};\n+\n+struct pinmux_drive_reg {\n+\tu32 reg;\n+\tconst struct pinmux_drive_reg_field fields[8];\n+};\n+\n+#define PINMUX_DRIVE_REG(name, r) \\\n+\t.reg = r, \\\n+\t.fields =\n+\n+struct pinmux_data_reg {\n+\tu32 reg;\n+\tu8 reg_width;\n+\tconst u16 *enum_ids;\n+};\n+\n+/*\n+ * Describe a data register\n+ *   - name: Register name (unused, for documentation purposes only)\n+ *   - r: Physical register address\n+ *   - r_width: Width of the register (in bits)\n+ * This macro must be followed by initialization data: For each register bit\n+ * (from left to right, i.e. MSB to LSB), one enum ID must be specified.\n+ */\n+#define PINMUX_DATA_REG(name, r, r_width) \\\n+\t.reg = r, .reg_width = r_width,\t\\\n+\t.enum_ids = (const u16 [r_width]) \\\n+\n+struct pinmux_irq {\n+\tconst short *gpios;\n+};\n+\n+/*\n+ * Describe the mapping from GPIOs to a single IRQ\n+ *   - ids...: List of GPIOs that are mapped to the same IRQ\n+ */\n+#define PINMUX_IRQ(ids...)\t\t\t   \\\n+\t{ .gpios = (const short []) { ids, -1 } }\n+\n+struct pinmux_range {\n+\tu16 begin;\n+\tu16 end;\n+\tu16 force;\n+};\n+\n+struct sh_pfc_bias_info {\n+\tu16 pin;\n+\tu16 reg : 11;\n+\tu16 bit : 5;\n+};\n+\n+struct sh_pfc_pin_range;\n+\n+struct sh_pfc {\n+\tstruct device *dev;\n+\tconst struct sh_pfc_soc_info *info;\n+\n+\tvoid *regs;\n+\n+\tstruct sh_pfc_pin_range *ranges;\n+\tunsigned int nr_ranges;\n+\n+\tunsigned int nr_gpio_pins;\n+\n+\tstruct sh_pfc_chip *gpio;\n+};\n+\n+struct sh_pfc_soc_operations {\n+\tint (*init)(struct sh_pfc *pfc);\n+\tunsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);\n+\tvoid (*set_bias)(struct sh_pfc *pfc, unsigned int pin,\n+\t\t\t unsigned int bias);\n+\tint (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);\n+};\n+\n+struct sh_pfc_soc_info {\n+\tconst char *name;\n+\tconst struct sh_pfc_soc_operations *ops;\n+\n+\tstruct pinmux_range input;\n+\tstruct pinmux_range output;\n+\tstruct pinmux_range function;\n+\n+\tconst struct sh_pfc_pin *pins;\n+\tunsigned int nr_pins;\n+\tconst struct sh_pfc_pin_group *groups;\n+\tunsigned int nr_groups;\n+\tconst struct sh_pfc_function *functions;\n+\tunsigned int nr_functions;\n+\n+\tconst struct pinmux_cfg_reg *cfg_regs;\n+\tconst struct pinmux_drive_reg *drive_regs;\n+\tconst struct pinmux_data_reg *data_regs;\n+\n+\tconst u16 *pinmux_data;\n+\tunsigned int pinmux_data_size;\n+\n+\tconst struct pinmux_irq *gpio_irq;\n+\tunsigned int gpio_irq_size;\n+\n+\tu32 unlock_reg;\n+};\n+\n+u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width);\n+void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data);\n+const struct sh_pfc_bias_info *\n+sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,\n+\t\t\tunsigned int num, unsigned int pin);\n+\n+extern const struct sh_pfc_soc_info r8a7795_pinmux_info;\n+extern const struct sh_pfc_soc_info r8a7796_pinmux_info;\n+/* -----------------------------------------------------------------------------\n+ * Helper macros to create pin and port lists\n+ */\n+\n+/*\n+ * sh_pfc_soc_info pinmux_data array macros\n+ */\n+\n+/*\n+ * Describe generic pinmux data\n+ *   - data_or_mark: *_DATA or *_MARK enum ID\n+ *   - ids...: List of enum IDs to associate with data_or_mark\n+ */\n+#define PINMUX_DATA(data_or_mark, ids...)\tdata_or_mark, ids, 0\n+\n+/*\n+ * Describe a pinmux configuration without GPIO function that needs\n+ * configuration in a Peripheral Function Select Register (IPSR)\n+ *   - ipsr: IPSR field (unused, for documentation purposes only)\n+ *   - fn: Function name, referring to a field in the IPSR\n+ */\n+#define PINMUX_IPSR_NOGP(ipsr, fn)\t\t\t\t\t\\\n+\tPINMUX_DATA(fn##_MARK, FN_##fn)\n+\n+/*\n+ * Describe a pinmux configuration with GPIO function that needs configuration\n+ * in both a Peripheral Function Select Register (IPSR) and in a\n+ * GPIO/Peripheral Function Select Register (GPSR)\n+ *   - ipsr: IPSR field\n+ *   - fn: Function name, also referring to the IPSR field\n+ */\n+#define PINMUX_IPSR_GPSR(ipsr, fn)\t\t\t\t\t\\\n+\tPINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)\n+\n+/*\n+ * Describe a pinmux configuration without GPIO function that needs\n+ * configuration in a Peripheral Function Select Register (IPSR), and where the\n+ * pinmux function has a representation in a Module Select Register (MOD_SEL).\n+ *   - ipsr: IPSR field (unused, for documentation purposes only)\n+ *   - fn: Function name, also referring to the IPSR field\n+ *   - msel: Module selector\n+ */\n+#define PINMUX_IPSR_NOGM(ipsr, fn, msel)\t\t\t\t\\\n+\tPINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)\n+\n+/*\n+ * Describe a pinmux configuration with GPIO function where the pinmux function\n+ * has no representation in a Peripheral Function Select Register (IPSR), but\n+ * instead solely depends on a group selection.\n+ *   - gpsr: GPSR field\n+ *   - fn: Function name, also referring to the GPSR field\n+ *   - gsel: Group selector\n+ */\n+#define PINMUX_IPSR_NOFN(gpsr, fn, gsel)\t\t\t\t\\\n+\tPINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)\n+\n+/*\n+ * Describe a pinmux configuration with GPIO function that needs configuration\n+ * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral\n+ * Function Select Register (GPSR), and where the pinmux function has a\n+ * representation in a Module Select Register (MOD_SEL).\n+ *   - ipsr: IPSR field\n+ *   - fn: Function name, also referring to the IPSR field\n+ *   - msel: Module selector\n+ */\n+#define PINMUX_IPSR_MSEL(ipsr, fn, msel)\t\t\t\t\\\n+\tPINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)\n+\n+/*\n+ * Describe a pinmux configuration for a single-function pin with GPIO\n+ * capability.\n+ *   - fn: Function name\n+ */\n+#define PINMUX_SINGLE(fn)\t\t\t\t\t\t\\\n+\tPINMUX_DATA(fn##_MARK, FN_##fn)\n+\n+/*\n+ * GP port style (32 ports banks)\n+ */\n+\n+#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg)\t\t\t\t\\\n+\tfn(bank, pin, GP_##bank##_##pin, sfx, cfg)\n+#define PORT_GP_1(bank, pin, fn, sfx)\tPORT_GP_CFG_1(bank, pin, fn, sfx, 0)\n+\n+#define PORT_GP_CFG_4(bank, fn, sfx, cfg)\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 0,  fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 1,  fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 2,  fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 3,  fn, sfx, cfg)\n+#define PORT_GP_4(bank, fn, sfx)\tPORT_GP_CFG_4(bank, fn, sfx, 0)\n+\n+#define PORT_GP_CFG_8(bank, fn, sfx, cfg)\t\t\t\t\\\n+\tPORT_GP_CFG_4(bank, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 4,  fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 5,  fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 6,  fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 7,  fn, sfx, cfg)\n+#define PORT_GP_8(bank, fn, sfx)\tPORT_GP_CFG_8(bank, fn, sfx, 0)\n+\n+#define PORT_GP_CFG_9(bank, fn, sfx, cfg)\t\t\t\t\\\n+\tPORT_GP_CFG_8(bank, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 8,  fn, sfx, cfg)\n+#define PORT_GP_9(bank, fn, sfx)\tPORT_GP_CFG_9(bank, fn, sfx, 0)\n+\n+#define PORT_GP_CFG_10(bank, fn, sfx, cfg)\t\t\t\t\\\n+\tPORT_GP_CFG_9(bank, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 9,  fn, sfx, cfg)\n+#define PORT_GP_10(bank, fn, sfx)\tPORT_GP_CFG_10(bank, fn, sfx, 0)\n+\n+#define PORT_GP_CFG_12(bank, fn, sfx, cfg)\t\t\t\t\\\n+\tPORT_GP_CFG_10(bank, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 10, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 11, fn, sfx, cfg)\n+#define PORT_GP_12(bank, fn, sfx)\tPORT_GP_CFG_12(bank, fn, sfx, 0)\n+\n+#define PORT_GP_CFG_14(bank, fn, sfx, cfg)\t\t\t\t\\\n+\tPORT_GP_CFG_12(bank, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 12, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 13, fn, sfx, cfg)\n+#define PORT_GP_14(bank, fn, sfx)\tPORT_GP_CFG_14(bank, fn, sfx, 0)\n+\n+#define PORT_GP_CFG_15(bank, fn, sfx, cfg)\t\t\t\t\\\n+\tPORT_GP_CFG_14(bank, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 14, fn, sfx, cfg)\n+#define PORT_GP_15(bank, fn, sfx)\tPORT_GP_CFG_15(bank, fn, sfx, 0)\n+\n+#define PORT_GP_CFG_16(bank, fn, sfx, cfg)\t\t\t\t\\\n+\tPORT_GP_CFG_15(bank, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 15, fn, sfx, cfg)\n+#define PORT_GP_16(bank, fn, sfx)\tPORT_GP_CFG_16(bank, fn, sfx, 0)\n+\n+#define PORT_GP_CFG_17(bank, fn, sfx, cfg)\t\t\t\t\\\n+\tPORT_GP_CFG_16(bank, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 16, fn, sfx, cfg)\n+#define PORT_GP_17(bank, fn, sfx)\tPORT_GP_CFG_17(bank, fn, sfx, 0)\n+\n+#define PORT_GP_CFG_18(bank, fn, sfx, cfg)\t\t\t\t\\\n+\tPORT_GP_CFG_17(bank, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 17, fn, sfx, cfg)\n+#define PORT_GP_18(bank, fn, sfx)\tPORT_GP_CFG_18(bank, fn, sfx, 0)\n+\n+#define PORT_GP_CFG_20(bank, fn, sfx, cfg)\t\t\t\t\\\n+\tPORT_GP_CFG_18(bank, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 18, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 19, fn, sfx, cfg)\n+#define PORT_GP_20(bank, fn, sfx)\tPORT_GP_CFG_20(bank, fn, sfx, 0)\n+\n+#define PORT_GP_CFG_21(bank, fn, sfx, cfg)\t\t\t\t\\\n+\tPORT_GP_CFG_20(bank, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 20, fn, sfx, cfg)\n+#define PORT_GP_21(bank, fn, sfx)\tPORT_GP_CFG_21(bank, fn, sfx, 0)\n+\n+#define PORT_GP_CFG_23(bank, fn, sfx, cfg)\t\t\t\t\\\n+\tPORT_GP_CFG_21(bank, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 21, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 22, fn, sfx, cfg)\n+#define PORT_GP_23(bank, fn, sfx)\tPORT_GP_CFG_23(bank, fn, sfx, 0)\n+\n+#define PORT_GP_CFG_24(bank, fn, sfx, cfg)\t\t\t\t\\\n+\tPORT_GP_CFG_23(bank, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 23, fn, sfx, cfg)\n+#define PORT_GP_24(bank, fn, sfx)\tPORT_GP_CFG_24(bank, fn, sfx, 0)\n+\n+#define PORT_GP_CFG_26(bank, fn, sfx, cfg)\t\t\t\t\\\n+\tPORT_GP_CFG_24(bank, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 24, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 25, fn, sfx, cfg)\n+#define PORT_GP_26(bank, fn, sfx)\tPORT_GP_CFG_26(bank, fn, sfx, 0)\n+\n+#define PORT_GP_CFG_28(bank, fn, sfx, cfg)\t\t\t\t\\\n+\tPORT_GP_CFG_26(bank, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 26, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 27, fn, sfx, cfg)\n+#define PORT_GP_28(bank, fn, sfx)\tPORT_GP_CFG_28(bank, fn, sfx, 0)\n+\n+#define PORT_GP_CFG_29(bank, fn, sfx, cfg)\t\t\t\t\\\n+\tPORT_GP_CFG_28(bank, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 28, fn, sfx, cfg)\n+#define PORT_GP_29(bank, fn, sfx)\tPORT_GP_CFG_29(bank, fn, sfx, 0)\n+\n+#define PORT_GP_CFG_30(bank, fn, sfx, cfg)\t\t\t\t\\\n+\tPORT_GP_CFG_29(bank, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 29, fn, sfx, cfg)\n+#define PORT_GP_30(bank, fn, sfx)\tPORT_GP_CFG_30(bank, fn, sfx, 0)\n+\n+#define PORT_GP_CFG_32(bank, fn, sfx, cfg)\t\t\t\t\\\n+\tPORT_GP_CFG_30(bank, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 30, fn, sfx, cfg),\t\t\t\t\\\n+\tPORT_GP_CFG_1(bank, 31, fn, sfx, cfg)\n+#define PORT_GP_32(bank, fn, sfx)\tPORT_GP_CFG_32(bank, fn, sfx, 0)\n+\n+#define PORT_GP_32_REV(bank, fn, sfx)\t\t\t\t\t\\\n+\tPORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),\t\\\n+\tPORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),\t\\\n+\tPORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),\t\\\n+\tPORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),\t\\\n+\tPORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),\t\\\n+\tPORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),\t\\\n+\tPORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),\t\\\n+\tPORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),\t\\\n+\tPORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),\t\\\n+\tPORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),\t\\\n+\tPORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),\t\\\n+\tPORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),\t\\\n+\tPORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),\t\\\n+\tPORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),\t\\\n+\tPORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),\t\\\n+\tPORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)\n+\n+/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */\n+#define _GP_ALL(bank, pin, name, sfx, cfg)\tname##_##sfx\n+#define GP_ALL(str)\t\t\tCPU_ALL_PORT(_GP_ALL, str)\n+\n+/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */\n+#define _GP_GPIO(bank, _pin, _name, sfx, cfg)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.pin = (bank * 32) + _pin,\t\t\t\t\\\n+\t\t.name = __stringify(_name),\t\t\t\t\\\n+\t\t.enum_id = _name##_DATA,\t\t\t\t\\\n+\t\t.configs = cfg,\t\t\t\t\t\t\\\n+\t}\n+#define PINMUX_GPIO_GP_ALL()\t\tCPU_ALL_PORT(_GP_GPIO, unused)\n+\n+/* PINMUX_DATA_GP_ALL -  Expand to a list of name_DATA, name_FN marks */\n+#define _GP_DATA(bank, pin, name, sfx, cfg)\tPINMUX_DATA(name##_DATA, name##_FN)\n+#define PINMUX_DATA_GP_ALL()\t\tCPU_ALL_PORT(_GP_DATA, unused)\n+\n+/*\n+ * PORT style (linear pin space)\n+ */\n+\n+#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)\n+\n+#define PORT_10(pn, fn, pfx, sfx)\t\t\t\t\t  \\\n+\tPORT_1(pn,   fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx),\t  \\\n+\tPORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx),\t  \\\n+\tPORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx),\t  \\\n+\tPORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx),\t  \\\n+\tPORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)\n+\n+#define PORT_90(pn, fn, pfx, sfx)\t\t\t\t\t  \\\n+\tPORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \\\n+\tPORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \\\n+\tPORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \\\n+\tPORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \\\n+\tPORT_10(pn+90, fn, pfx##9, sfx)\n+\n+/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */\n+#define _PORT_ALL(pn, pfx, sfx)\t\tpfx##_##sfx\n+#define PORT_ALL(str)\t\t\tCPU_ALL_PORT(_PORT_ALL, PORT, str)\n+\n+/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */\n+#define PINMUX_GPIO(_pin)\t\t\t\t\t\t\\\n+\t[GPIO_##_pin] = {\t\t\t\t\t\t\\\n+\t\t.pin = (u16)-1,\t\t\t\t\t\t\\\n+\t\t.name = __stringify(GPIO_##_pin),\t\t\t\\\n+\t\t.enum_id = _pin##_DATA,\t\t\t\t\t\\\n+\t}\n+\n+/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */\n+#define SH_PFC_PIN_CFG(_pin, cfgs)\t\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.pin = _pin,\t\t\t\t\t\t\\\n+\t\t.name = __stringify(PORT##_pin),\t\t\t\\\n+\t\t.enum_id = PORT##_pin##_DATA,\t\t\t\t\\\n+\t\t.configs = cfgs,\t\t\t\t\t\\\n+\t}\n+\n+/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */\n+#define SH_PFC_PIN_NAMED(row, col, _name)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.pin = PIN_NUMBER(row, col),\t\t\t\t\\\n+\t\t.name = __stringify(PIN_##_name),\t\t\t\\\n+\t\t.configs = SH_PFC_PIN_CFG_NO_GPIO,\t\t\t\\\n+\t}\n+\n+/* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */\n+#define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs)\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.pin = PIN_NUMBER(row, col),\t\t\t\t\\\n+\t\t.name = __stringify(PIN_##_name),\t\t\t\\\n+\t\t.configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs,\t\t\\\n+\t}\n+\n+/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,\n+ *\t\t     PORT_name_OUT, PORT_name_IN marks\n+ */\n+#define _PORT_DATA(pn, pfx, sfx)\t\t\t\t\t\\\n+\tPINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0,\t\t\t\\\n+\t\t    PORT##pfx##_OUT, PORT##pfx##_IN)\n+#define PINMUX_DATA_ALL()\t\tCPU_ALL_PORT(_PORT_DATA, , unused)\n+\n+/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */\n+#define PINMUX_GPIO_FN(gpio, base, data_or_mark)\t\t\t\\\n+\t[gpio - (base)] = {\t\t\t\t\t\t\\\n+\t\t.name = __stringify(gpio),\t\t\t\t\\\n+\t\t.enum_id = data_or_mark,\t\t\t\t\\\n+\t}\n+#define GPIO_FN(str)\t\t\t\t\t\t\t\\\n+\tPINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)\n+\n+/*\n+ * PORTnCR helper macro for SH-Mobile/R-Mobile\n+ */\n+#define PORTCR(nr, reg)\t\t\t\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tPINMUX_CFG_REG_VAR(\"PORT\" nr \"CR\", reg, 8, 2, 2, 1, 3) {\\\n+\t\t\t/* PULMD[1:0], handled by .set_bias() */\t\\\n+\t\t\t0, 0, 0, 0,\t\t\t\t\t\\\n+\t\t\t/* IE and OE */\t\t\t\t\t\\\n+\t\t\t0, PORT##nr##_OUT, PORT##nr##_IN, 0,\t\t\\\n+\t\t\t/* SEC, not supported */\t\t\t\\\n+\t\t\t0, 0,\t\t\t\t\t\t\\\n+\t\t\t/* PTMD[2:0] */\t\t\t\t\t\\\n+\t\t\tPORT##nr##_FN0, PORT##nr##_FN1,\t\t\t\\\n+\t\t\tPORT##nr##_FN2, PORT##nr##_FN3,\t\t\t\\\n+\t\t\tPORT##nr##_FN4, PORT##nr##_FN5,\t\t\t\\\n+\t\t\tPORT##nr##_FN6, PORT##nr##_FN7\t\t\t\\\n+\t\t}\t\t\t\t\t\t\t\\\n+\t}\n+\n+/*\n+ * GPIO number helper macro for R-Car\n+ */\n+#define RCAR_GP_PIN(bank, pin)\t\t(((bank) * 32) + (pin))\n+\n+#endif /* __SH_PFC_H */\n",
    "prefixes": [
        "U-Boot",
        "1/5"
    ]
}