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GET /api/1.2/patches/814376/?format=api
{ "id": 814376, "url": "http://patchwork.ozlabs.org/api/1.2/patches/814376/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170915191359.28712-2-marek.vasut+renesas@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170915191359.28712-2-marek.vasut+renesas@gmail.com>", "list_archive_url": null, "date": "2017-09-15T19:13:56", "name": "[U-Boot,2/5] gpio: rmobile: Add Renesas RCar GPIO driver", "commit_ref": "f5f6959444d07bfc71221a6ba18a2b3eca195e05", "pull_url": null, "state": "accepted", "archived": false, "hash": "d1f723f3e2b3bd57d8dc712c8d2dd18c78306d11", "submitter": { "id": 1124, "url": "http://patchwork.ozlabs.org/api/1.2/people/1124/?format=api", "name": "Marek Vasut", "email": "marek.vasut@gmail.com" }, "delegate": { "id": 1750, "url": "http://patchwork.ozlabs.org/api/1.2/users/1750/?format=api", "username": "iwamatsu", "first_name": "Nobuhiro", "last_name": "Iwamatsu", "email": "iwamatsu@nigauri.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170915191359.28712-2-marek.vasut+renesas@gmail.com/mbox/", "series": [ { "id": 3365, "url": "http://patchwork.ozlabs.org/api/1.2/series/3365/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=3365", "date": "2017-09-15T19:13:58", "name": "[U-Boot,1/5] pinctrl: rmobile: Add Renesas RCar pincontrol driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/3365/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/814376/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/814376/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"FLvYP40a\"; dkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xv4ty4pbVz9sMN\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 16 Sep 2017 05:18:34 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 19EDCC21EFB; Fri, 15 Sep 2017 19:15:27 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id D3720C21EFB;\n\tFri, 15 Sep 2017 19:15:22 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 1510FC21E84; Fri, 15 Sep 2017 19:14:05 +0000 (UTC)", "from mail-wr0-f193.google.com (mail-wr0-f193.google.com\n\t[209.85.128.193])\n\tby lists.denx.de (Postfix) with ESMTPS id 481DAC21E84\n\tfor <u-boot@lists.denx.de>; Fri, 15 Sep 2017 19:14:05 +0000 (UTC)", "by mail-wr0-f193.google.com with SMTP id n64so1778298wrb.2\n\tfor <u-boot@lists.denx.de>; Fri, 15 Sep 2017 12:14:05 -0700 (PDT)", "from kurokawa.lan (ip-86-49-107-50.net.upcbroadband.cz.\n\t[86.49.107.50]) by smtp.gmail.com with ESMTPSA id\n\ta39sm1710995wrc.48.2017.09.15.12.14.03\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tFri, 15 Sep 2017 12:14:04 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=FREEMAIL_FROM,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,\n\tT_DKIM_INVALID autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=m1TaIqQ5stwkdAW7Q973atoUfj3+biCVfYjRKJgNjJM=;\n\tb=FLvYP40aLqkw1LDXIWHGJsPE73xh9xdHpCkvDba/us0i19b7LEAnOiPj6mMcYY8z2k\n\tezebKCN9ynAxTjIzbhX+SoUuwvqKeY8HByuj93oso6ziw7QzbwnZpVzyEoQjcNHDgbEP\n\tEzxwXTn/MJnDGI9tQHSt+nByKYN0UFAuoEEEwET3PX0QqKTlQRpdXqNa2r7IVTe3oPPO\n\tTHN0JWrn6WN7OePdTonW3rMvm7VyitQ+PDUiMOXB3QaynQUq0dTGfz10yLRk1wFzT6EJ\n\tAIbL9LaeWy8+4j8J7LHYOMkM4RwMdYhOfjoS4PGg3loP5ll8bzRTAzBvQ9Ji86S7F/G2\n\tOIwA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=m1TaIqQ5stwkdAW7Q973atoUfj3+biCVfYjRKJgNjJM=;\n\tb=IgSCVRuB5bkwBUc+1v/kr0ithZTiQGPMQYXuXM4DLwLEBRRgITpPERFCWc9m+bnWyN\n\tMBjw0GUROXOPMQh70WcCZVj9btz5q28OrS3N+LKlbp6QzFoovvwWBb5GhndJq7zHP5g/\n\txWIi0R0QxHQExEUqLc2ztF2eL/YKkQNxf3LTRHNRqiBj1jKep7uifb6IxO3cP0v1nmIg\n\t8FvBG/SfWehtXbX337AOf45g3RBCiS6rdV8PVa9FZUX8qJ4I95zKvvApIAf524ba3NOD\n\t+AdLFuYXUsyzxY4JuZ5qAsYf9udfyBtq+Fc54Sl7LUZZRZuOgH1EwqUYtablS1qK8LRu\n\twjDg==", "X-Gm-Message-State": "AHPjjUgvghrBjushmfgH9g9lZGkT+iBktD5ExpnnFWxBmXgt4HbOpKCo\n\tEuMfEjYPhxho91cgOeU=", "X-Google-Smtp-Source": "ADKCNb5LbqOQ1tQ4wX6nGAVHt3woR7AV6iVfjxsnJ6kJusXQf5+61Ky4f4gc1y+3MQL4LcHysvLwJg==", "X-Received": "by 10.223.176.46 with SMTP id f43mr22810562wra.206.1505502844701;\n\tFri, 15 Sep 2017 12:14:04 -0700 (PDT)", "From": "Marek Vasut <marek.vasut@gmail.com>", "X-Google-Original-From": "Marek Vasut <marek.vasut+renesas@gmail.com>", "To": "u-boot@lists.denx.de", "Date": "Fri, 15 Sep 2017 21:13:56 +0200", "Message-Id": "<20170915191359.28712-2-marek.vasut+renesas@gmail.com>", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": "<20170915191359.28712-1-marek.vasut+renesas@gmail.com>", "References": "<20170915191359.28712-1-marek.vasut+renesas@gmail.com>", "Cc": "Marek Vasut <marek.vasut+renesas@gmail.com>", "Subject": "[U-Boot] [PATCH 2/5] gpio: rmobile: Add Renesas RCar GPIO driver", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Add GPIO driver for the Renesas RCar SoCs . The driver currently supports\nonly the RCar Gen3 R8A7795 and R8A7796 SoCs, but is easily extensible for\nthe other RCar SoCs as well.\n\nThis driver is meant to replace the pinmux part of SH_GPIO_PFC driver.\n\nSigned-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>\nCc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>\n---\n drivers/gpio/Kconfig | 6 ++\n drivers/gpio/Makefile | 1 +\n drivers/gpio/gpio-rcar.c | 169 +++++++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 176 insertions(+)\n create mode 100644 drivers/gpio/gpio-rcar.c", "diff": "diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig\nindex ffeda9425a..6240c39539 100644\n--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -135,6 +135,12 @@ config PCF8575_GPIO\n \t Support for PCF8575 I2C 16-bit GPIO expander. Most of these\n \t chips are from NXP and TI.\n \n+config RCAR_GPIO\n+\tbool \"Renesas RCar GPIO driver\"\n+\tdepends on DM_GPIO && ARCH_RMOBILE\n+\thelp\n+\t This driver supports the GPIO banks on Renesas RCar SoCs.\n+\n config ROCKCHIP_GPIO\n \tbool \"Rockchip GPIO driver\"\n \tdepends on DM_GPIO\ndiff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile\nindex 1396467ab6..81f55a576b 100644\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -28,6 +28,7 @@ obj-$(CONFIG_MXS_GPIO)\t+= mxs_gpio.o\n obj-$(CONFIG_PCA953X)\t\t+= pca953x.o\n obj-$(CONFIG_PCA9698)\t\t+= pca9698.o\n obj-$(CONFIG_ROCKCHIP_GPIO)\t+= rk_gpio.o\n+obj-$(CONFIG_RCAR_GPIO)\t\t+= gpio-rcar.o\n obj-$(CONFIG_S5P)\t\t+= s5p_gpio.o\n obj-$(CONFIG_SANDBOX_GPIO)\t+= sandbox.o\n obj-$(CONFIG_SPEAR_GPIO)\t+= spear_gpio.o\ndiff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c\nnew file mode 100644\nindex 0000000000..8504dceb84\n--- /dev/null\n+++ b/drivers/gpio/gpio-rcar.c\n@@ -0,0 +1,169 @@\n+/*\n+ * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <clk.h>\n+#include <dm.h>\n+#include <errno.h>\n+#include <asm/gpio.h>\n+#include <asm/io.h>\n+\n+#define GPIO_IOINTSEL\t0x00\t/* General IO/Interrupt Switching Register */\n+#define GPIO_INOUTSEL\t0x04\t/* General Input/Output Switching Register */\n+#define GPIO_OUTDT\t0x08\t/* General Output Register */\n+#define GPIO_INDT\t0x0c\t/* General Input Register */\n+#define GPIO_INTDT\t0x10\t/* Interrupt Display Register */\n+#define GPIO_INTCLR\t0x14\t/* Interrupt Clear Register */\n+#define GPIO_INTMSK\t0x18\t/* Interrupt Mask Register */\n+#define GPIO_MSKCLR\t0x1c\t/* Interrupt Mask Clear Register */\n+#define GPIO_POSNEG\t0x20\t/* Positive/Negative Logic Select Register */\n+#define GPIO_EDGLEVEL\t0x24\t/* Edge/level Select Register */\n+#define GPIO_FILONOFF\t0x28\t/* Chattering Prevention On/Off Register */\n+#define GPIO_BOTHEDGE\t0x4c\t/* One Edge/Both Edge Select Register */\n+\n+#define RCAR_MAX_GPIO_PER_BANK\t\t32\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+struct rcar_gpio_priv {\n+\tvoid __iomem *regs;\n+};\n+\n+static int rcar_gpio_get_value(struct udevice *dev, unsigned offset)\n+{\n+\tstruct rcar_gpio_priv *priv = dev_get_priv(dev);\n+\tconst u32 bit = BIT(offset);\n+\n+\t/*\n+\t * Testing on r8a7790 shows that INDT does not show correct pin state\n+\t * when configured as output, so use OUTDT in case of output pins.\n+\t */\n+\tif (readl(priv->regs + GPIO_INOUTSEL) & bit)\n+\t\treturn !!(readl(priv->regs + GPIO_OUTDT) & bit);\n+\telse\n+\t\treturn !!(readl(priv->regs + GPIO_INDT) & bit);\n+}\n+\n+static int rcar_gpio_set_value(struct udevice *dev, unsigned offset,\n+\t\t\t int value)\n+{\n+\tstruct rcar_gpio_priv *priv = dev_get_priv(dev);\n+\n+\tif (value)\n+\t\tsetbits_le32(priv->regs + GPIO_OUTDT, BIT(offset));\n+\telse\n+\t\tclrbits_le32(priv->regs + GPIO_OUTDT, BIT(offset));\n+\n+\treturn 0;\n+}\n+\n+static void rcar_gpio_set_direction(void __iomem *regs, unsigned offset,\n+\t\t\t\t bool output)\n+{\n+\t/*\n+\t * follow steps in the GPIO documentation for\n+\t * \"Setting General Output Mode\" and\n+\t * \"Setting General Input Mode\"\n+\t */\n+\n+\t/* Configure postive logic in POSNEG */\n+\tclrbits_le32(regs + GPIO_POSNEG, BIT(offset));\n+\n+\t/* Select \"General Input/Output Mode\" in IOINTSEL */\n+\tclrbits_le32(regs + GPIO_IOINTSEL, BIT(offset));\n+\n+\t/* Select Input Mode or Output Mode in INOUTSEL */\n+\tif (output)\n+\t\tsetbits_le32(regs + GPIO_INOUTSEL, BIT(offset));\n+\telse\n+\t\tclrbits_le32(regs + GPIO_INOUTSEL, BIT(offset));\n+}\n+\n+static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset)\n+{\n+\tstruct rcar_gpio_priv *priv = dev_get_priv(dev);\n+\n+\trcar_gpio_set_direction(priv->regs, offset, false);\n+\n+\treturn 0;\n+}\n+\n+static int rcar_gpio_direction_output(struct udevice *dev, unsigned offset,\n+\t\t\t\t int value)\n+{\n+\tstruct rcar_gpio_priv *priv = dev_get_priv(dev);\n+\n+\t/* write GPIO value to output before selecting output mode of pin */\n+\trcar_gpio_set_value(dev, offset, value);\n+\trcar_gpio_set_direction(priv->regs, offset, true);\n+\n+\treturn 0;\n+}\n+\n+static int rcar_gpio_get_function(struct udevice *dev, unsigned offset)\n+{\n+\tstruct rcar_gpio_priv *priv = dev_get_priv(dev);\n+\n+\tif (readl(priv->regs + GPIO_INOUTSEL) & BIT(offset))\n+\t\treturn GPIOF_OUTPUT;\n+\telse\n+\t\treturn GPIOF_INPUT;\n+}\n+\n+static const struct dm_gpio_ops rcar_gpio_ops = {\n+\t.direction_input\t= rcar_gpio_direction_input,\n+\t.direction_output\t= rcar_gpio_direction_output,\n+\t.get_value\t\t= rcar_gpio_get_value,\n+\t.set_value\t\t= rcar_gpio_set_value,\n+\t.get_function\t\t= rcar_gpio_get_function,\n+};\n+\n+static int rcar_gpio_probe(struct udevice *dev)\n+{\n+\tstruct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);\n+\tstruct rcar_gpio_priv *priv = dev_get_priv(dev);\n+\tstruct fdtdec_phandle_args args;\n+\tstruct clk clk;\n+\tint node = dev_of_offset(dev);\n+\tint ret;\n+\n+\tpriv->regs = (void __iomem *)devfdt_get_addr(dev);\n+\tuc_priv->bank_name = dev->name;\n+\n+\tret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, \"gpio-ranges\",\n+\t\t\t\t\t NULL, 3, 0, &args);\n+\tuc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;\n+\n+\tret = clk_get_by_index(dev, 0, &clk);\n+\tif (ret < 0) {\n+\t\tdev_err(dev, \"Failed to get GPIO bank clock\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = clk_enable(&clk);\n+\tclk_free(&clk);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Failed to enable GPIO bank clock\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct udevice_id rcar_gpio_ids[] = {\n+\t{ .compatible = \"renesas,gpio-r8a7795\" },\n+\t{ .compatible = \"renesas,gpio-r8a7796\" },\n+\t{ /* sentinel */ }\n+};\n+\n+U_BOOT_DRIVER(rcar_gpio) = {\n+\t.name\t= \"rcar-gpio\",\n+\t.id\t= UCLASS_GPIO,\n+\t.of_match = rcar_gpio_ids,\n+\t.ops\t= &rcar_gpio_ops,\n+\t.priv_auto_alloc_size = sizeof(struct rcar_gpio_priv),\n+\t.probe\t= rcar_gpio_probe,\n+};\n", "prefixes": [ "U-Boot", "2/5" ] }