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GET /api/1.2/patches/811260/?format=api
{ "id": 811260, "url": "http://patchwork.ozlabs.org/api/1.2/patches/811260/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-22-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170907224051.21518-22-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-07T22:40:49", "name": "[PULL,21/23] tcg/ppc: Change TCG_REG_RA to TCG_REG_TB", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "cbf3a11fb71a2c172fb5f982d628e51d8b7a9747", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-22-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2073, "url": "http://patchwork.ozlabs.org/api/1.2/series/2073/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2073", "date": "2017-09-07T22:40:28", "name": "[PULL,01/23] tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2073/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811260/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811260/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"JUmCS+8I\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpG6M0fZgz9s81\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 08:56:43 +1000 (AEST)", "from localhost ([::1]:42578 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dq5iz-0007IL-5L\n\tfor incoming@patchwork.ozlabs.org; Thu, 07 Sep 2017 18:56:41 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:52403)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq5UK-0003Ib-0A\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:37 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq5UE-0008Pu-43\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:32 -0400", "from mail-pg0-x22b.google.com ([2607:f8b0:400e:c05::22b]:35578)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dq5UD-0008PQ-RX\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:26 -0400", "by mail-pg0-x22b.google.com with SMTP id 188so1820206pgb.2\n\tfor <qemu-devel@nongnu.org>; Thu, 07 Sep 2017 15:41:25 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\th19sm770678pfh.142.2017.09.07.15.41.22\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 07 Sep 2017 15:41:23 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=1KhGx0qtsp/MTCShkhoI1NsYI1NCaIblZvH8Oahm9TU=;\n\tb=JUmCS+8IFZ3Uc+R9GEjERjaA+gpfRz+lajt26SqqjlK+ggOqFGFVmHlqdnCNazc2YA\n\trBGo9guDx/h4e6e+QPYwS/JmXOKn76jIO+C4WDA4351PudXtl2wXzdXmDU0KwFG1Nt20\n\tENOOLb9vo9OeekDj3cqmYBZaXQ8e4U+C5ioxk=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=1KhGx0qtsp/MTCShkhoI1NsYI1NCaIblZvH8Oahm9TU=;\n\tb=X3g6qBywQv4X4FohLWKVmZ9L9pLk3PNoMCKAThYP+qhf9kBFdxvQAKa8vAuuhte+7h\n\tZ7+sZ0xAikvpq5ViM/PL9Kl2wkriMM3ZmRQeYbSuHfXKSUEDmUDbd9AxKT2tMFXewEZe\n\tUUl9lxpdYu0egtDJzKgPxZdU0yn76E9/Cy37tQ/snuc4HyM/3QWEpKi9yWTPuUdwjiwE\n\tP8Hg4eEueJE6EWPBI/DEDz+RF3jAo5IoG7UOUACdZHhVvwJmvrYd/TUPkqKeMv6wIbIY\n\tSDVpiA0ArjzCwREeCclnEIrKDqwGTCdx/Cbc2GSVbjlcMCZIXb3X2CdHhcCQZ/vwVVYG\n\tiIhA==", "X-Gm-Message-State": "AHPjjUhnoFXSge5/AZIlhSY0noskBfGfEmly1enCSDy5bcOvR+/rBRs5\n\tn+AV9FcBVfqhtSzPqkKy7A==", "X-Google-Smtp-Source": "ADKCNb4OXM8IHipUs6E4EpekV7tppLEXaQ+W8Dduq2fEzoEOM/PbMid8w2TLQNonHoD+Y5oSHxW4bg==", "X-Received": "by 10.99.126.84 with SMTP id o20mr947319pgn.141.1504824084272;\n\tThu, 07 Sep 2017 15:41:24 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Thu, 7 Sep 2017 15:40:49 -0700", "Message-Id": "<20170907224051.21518-22-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170907224051.21518-1-richard.henderson@linaro.org>", "References": "<20170907224051.21518-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::22b", "Subject": "[Qemu-devel] [PULL 21/23] tcg/ppc: Change TCG_REG_RA to TCG_REG_TB", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Richard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nAt this point the conversion is a wash. Loading of TB+ofs is\nsmaller, but the actual return address from exit_tb is larger.\nThere are a few more insns required to transition between TBs.\n\nBut the expectation is that accesses to the constant pool will\non the whole be smaller.\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n tcg/ppc/tcg-target.inc.c | 273 +++++++++++++++++++++--------------------------\n 1 file changed, 122 insertions(+), 151 deletions(-)", "diff": "diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c\nindex d772faf7be..bc14d2c9c6 100644\n--- a/tcg/ppc/tcg-target.inc.c\n+++ b/tcg/ppc/tcg-target.inc.c\n@@ -39,29 +39,8 @@\n # define TCG_REG_TMP1 TCG_REG_R12\n #endif\n \n-/* For the 64-bit target, we don't like the 5 insn sequence needed to build\n- full 64-bit addresses. Better to have a base register to which we can\n- apply a 32-bit displacement.\n-\n- There are generally three items of interest:\n- (1) helper functions in the main executable,\n- (2) TranslationBlock data structures,\n- (3) the return address in the epilogue.\n-\n- For user-only, we USE_STATIC_CODE_GEN_BUFFER, so the code_gen_buffer\n- will be inside the main executable, and thus near enough to make a\n- pointer to the epilogue be within 2GB of all helper functions.\n-\n- For softmmu, we'll let the kernel choose the address of code_gen_buffer,\n- and odds are it'll be somewhere close to the main malloc arena, and so\n- a pointer to the epilogue will be within 2GB of the TranslationBlocks.\n-\n- For --enable-pie, everything will be kinda near everything else,\n- somewhere in high memory.\n-\n- Thus we choose to keep the return address in a call-saved register. */\n-#define TCG_REG_RA TCG_REG_R31\n-#define USE_REG_RA (TCG_TARGET_REG_BITS == 64)\n+#define TCG_REG_TB TCG_REG_R31\n+#define USE_REG_TB (TCG_TARGET_REG_BITS == 64)\n \n /* Shorthand for size of a pointer. Avoid promotion to unsigned. */\n #define SZP ((int)sizeof(void *))\n@@ -614,50 +593,68 @@ static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)\n tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);\n }\n \n-static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg)\n+static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,\n+ tcg_target_long arg, bool in_prologue)\n {\n- if (arg == (int16_t) arg) {\n+ intptr_t tb_diff;\n+ int32_t high;\n+\n+ tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);\n+\n+ if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {\n+ arg = (int32_t)arg;\n+ }\n+\n+ /* Load 16-bit immediates with one insn. */\n+ if (arg == (int16_t)arg) {\n tcg_out32(s, ADDI | TAI(ret, 0, arg));\n- } else {\n+ return;\n+ }\n+\n+ /* Load addresses within the TB with one insn. */\n+ tb_diff = arg - (intptr_t)s->code_gen_ptr;\n+ if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) {\n+ tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff));\n+ return;\n+ }\n+\n+ /* Load 32-bit immediates with two insns. */\n+ if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {\n tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));\n if (arg & 0xffff) {\n tcg_out32(s, ORI | SAI(ret, ret, arg));\n }\n+ return;\n }\n-}\n-\n-static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,\n- tcg_target_long arg)\n-{\n- tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);\n- if (type == TCG_TYPE_I32 || arg == (int32_t)arg) {\n- tcg_out_movi32(s, ret, arg);\n- } else if (arg == (uint32_t)arg && !(arg & 0x8000)) {\n+ if (arg == (uint32_t)arg && !(arg & 0x8000)) {\n tcg_out32(s, ADDI | TAI(ret, 0, arg));\n tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));\n- } else {\n- int32_t high;\n+ return;\n+ }\n \n- if (USE_REG_RA) {\n- intptr_t diff = arg - (intptr_t)tb_ret_addr;\n- if (diff == (int32_t)diff) {\n- tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_RA, diff);\n- return;\n- }\n- }\n+ /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */\n+ if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) {\n+ tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff);\n+ return;\n+ }\n \n- high = arg >> 31 >> 1;\n- tcg_out_movi32(s, ret, high);\n- if (high) {\n- tcg_out_shli64(s, ret, ret, 32);\n- }\n- if (arg & 0xffff0000) {\n- tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));\n- }\n- if (arg & 0xffff) {\n- tcg_out32(s, ORI | SAI(ret, ret, arg));\n- }\n+ high = arg >> 31 >> 1;\n+ tcg_out_movi(s, TCG_TYPE_I32, ret, high);\n+ if (high) {\n+ tcg_out_shli64(s, ret, ret, 32);\n }\n+ if (arg & 0xffff0000) {\n+ tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));\n+ }\n+ if (arg & 0xffff) {\n+ tcg_out32(s, ORI | SAI(ret, ret, arg));\n+ }\n+}\n+\n+static inline void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,\n+ tcg_target_long arg)\n+{\n+ tcg_out_movi_int(s, type, ret, arg, false);\n }\n \n static bool mask_operand(uint32_t c, int *mb, int *me)\n@@ -1293,49 +1290,43 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)\n tcg_out32(s, insn);\n }\n \n-#ifdef __powerpc64__\n void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,\n uintptr_t addr)\n {\n- tcg_insn_unit i1, i2;\n- uint64_t pair;\n- intptr_t diff = addr - jmp_addr;\n-\n- if (in_range_b(diff)) {\n- i1 = B | (diff & 0x3fffffc);\n- i2 = NOP;\n- } else if (USE_REG_RA) {\n- intptr_t lo, hi;\n- diff = addr - (uintptr_t)tb_ret_addr;\n- lo = (int16_t)diff;\n- hi = (int32_t)(diff - lo);\n- tcg_debug_assert(diff == hi + lo);\n- i1 = ADDIS | TAI(TCG_REG_TMP1, TCG_REG_RA, hi >> 16);\n- i2 = ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, lo);\n- } else {\n- tcg_debug_assert(TCG_TARGET_REG_BITS == 32 || addr == (int32_t)addr);\n- i1 = ADDIS | TAI(TCG_REG_TMP1, 0, addr >> 16);\n- i2 = ORI | SAI(TCG_REG_TMP1, TCG_REG_TMP1, addr);\n- }\n+ if (TCG_TARGET_REG_BITS == 64) {\n+ tcg_insn_unit i1, i2;\n+ intptr_t tb_diff = addr - tc_ptr;\n+ intptr_t br_diff = addr - (jmp_addr + 4);\n+ uint64_t pair;\n+\n+ /* This does not exercise the range of the branch, but we do\n+ still need to be able to load the new value of TCG_REG_TB.\n+ But this does still happen quite often. */\n+ if (tb_diff == (int16_t)tb_diff) {\n+ i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);\n+ i2 = B | (br_diff & 0x3fffffc);\n+ } else {\n+ intptr_t lo = (int16_t)tb_diff;\n+ intptr_t hi = (int32_t)(tb_diff - lo);\n+ assert(tb_diff == hi + lo);\n+ i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);\n+ i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);\n+ }\n #ifdef HOST_WORDS_BIGENDIAN\n- pair = (uint64_t)i1 << 32 | i2;\n+ pair = (uint64_t)i1 << 32 | i2;\n #else\n- pair = (uint64_t)i2 << 32 | i1;\n+ pair = (uint64_t)i2 << 32 | i1;\n #endif\n \n- atomic_set((uint64_t *)jmp_addr, pair);\n- flush_icache_range(jmp_addr, jmp_addr + 8);\n-}\n-#else\n-void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,\n- uintptr_t addr)\n-{\n- intptr_t diff = addr - jmp_addr;\n- tcg_debug_assert(in_range_b(diff));\n- atomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc));\n- flush_icache_range(jmp_addr, jmp_addr + 4);\n+ atomic_set((uint64_t *)jmp_addr, pair);\n+ flush_icache_range(jmp_addr, jmp_addr + 8);\n+ } else {\n+ intptr_t diff = addr - jmp_addr;\n+ tcg_debug_assert(in_range_b(diff));\n+ atomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc));\n+ flush_icache_range(jmp_addr, jmp_addr + 4);\n+ }\n }\n-#endif\n \n static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)\n {\n@@ -1897,44 +1888,20 @@ static void tcg_target_qemu_prologue(TCGContext *s)\n \n #ifndef CONFIG_SOFTMMU\n if (guest_base) {\n- tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);\n+ tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);\n tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);\n }\n #endif\n \n tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);\n tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);\n-\n- if (USE_REG_RA) {\n-#ifdef _CALL_AIX\n- /* Make the caller load the value as the TOC into R2. */\n- tb_ret_addr = s->code_ptr + 2;\n- desc[1] = tb_ret_addr;\n- tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_RA, TCG_REG_R2);\n- tcg_out32(s, BCCTR | BO_ALWAYS);\n-#elif defined(_CALL_ELF) && _CALL_ELF == 2\n- /* Compute from the incoming R12 value. */\n- tb_ret_addr = s->code_ptr + 2;\n- tcg_out32(s, ADDI | TAI(TCG_REG_RA, TCG_REG_R12,\n- tcg_ptr_byte_diff(tb_ret_addr, s->code_buf)));\n- tcg_out32(s, BCCTR | BO_ALWAYS);\n-#else\n- /* Reserve max 5 insns for the constant load. */\n- tb_ret_addr = s->code_ptr + 6;\n- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)tb_ret_addr);\n- tcg_out32(s, BCCTR | BO_ALWAYS);\n- while (s->code_ptr < tb_ret_addr) {\n- tcg_out32(s, NOP);\n- }\n-#endif\n- } else {\n- tcg_out32(s, BCCTR | BO_ALWAYS);\n- tb_ret_addr = s->code_ptr;\n+ if (USE_REG_TB) {\n+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);\n }\n+ tcg_out32(s, BCCTR | BO_ALWAYS);\n \n /* Epilogue */\n- tcg_debug_assert(tb_ret_addr == s->code_ptr);\n- s->code_gen_epilogue = tb_ret_addr;\n+ s->code_gen_epilogue = tb_ret_addr = s->code_ptr;\n \n tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);\n for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {\n@@ -1954,44 +1921,48 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,\n \n switch (opc) {\n case INDEX_op_exit_tb:\n- if (USE_REG_RA) {\n- ptrdiff_t disp = tcg_pcrel_diff(s, tb_ret_addr);\n-\n- /* Use a direct branch if we can, otherwise use the value in RA.\n- Note that the direct branch is always backward, thus we need\n- to account for the possibility of 5 insns from the movi. */\n- if (!in_range_b(disp - 20)) {\n- tcg_out32(s, MTSPR | RS(TCG_REG_RA) | CTR);\n- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);\n- tcg_out32(s, BCCTR | BO_ALWAYS);\n- break;\n- }\n- }\n tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);\n tcg_out_b(s, 0, tb_ret_addr);\n break;\n case INDEX_op_goto_tb:\n- tcg_debug_assert(s->tb_jmp_insn_offset);\n- /* Direct jump. */\n-#ifdef __powerpc64__\n- /* Ensure the next insns are 8-byte aligned. */\n- if ((uintptr_t)s->code_ptr & 7) {\n- tcg_out32(s, NOP);\n- }\n- s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);\n- /* To be replaced by either a branch+nop or a load into TMP1. */\n- s->code_ptr += 2;\n- tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR);\n+ if (s->tb_jmp_insn_offset) {\n+ /* Direct jump. */\n+ if (TCG_TARGET_REG_BITS == 64) {\n+ /* Ensure the next insns are 8-byte aligned. */\n+ if ((uintptr_t)s->code_ptr & 7) {\n+ tcg_out32(s, NOP);\n+ }\n+ s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);\n+ tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0));\n+ tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0));\n+ } else {\n+ s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);\n+ tcg_out32(s, B);\n+ s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);\n+ break;\n+ }\n+ } else {\n+ /* Indirect jump. */\n+ tcg_debug_assert(s->tb_jmp_insn_offset == NULL);\n+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0,\n+ (intptr_t)(s->tb_jmp_insn_offset + args[0]));\n+ }\n+ tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR);\n tcg_out32(s, BCCTR | BO_ALWAYS);\n-#else\n- /* To be replaced by a branch. */\n- s->code_ptr++;\n-#endif\n- s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);\n+ s->tb_jmp_reset_offset[args[0]] = c = tcg_current_code_size(s);\n+ if (USE_REG_TB) {\n+ /* For the unlinked case, need to reset TCG_REG_TB. */\n+ c = -c;\n+ assert(c == (int16_t)c);\n+ tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, c));\n+ }\n break;\n case INDEX_op_goto_ptr:\n tcg_out32(s, MTSPR | RS(args[0]) | CTR);\n- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, 0);\n+ if (USE_REG_TB) {\n+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]);\n+ }\n+ tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0));\n tcg_out32(s, BCCTR | BO_ALWAYS);\n break;\n case INDEX_op_br:\n@@ -2761,8 +2732,8 @@ static void tcg_target_init(TCGContext *s)\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */\n #endif\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */\n- if (USE_REG_RA) {\n- tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return addr */\n+ if (USE_REG_TB) {\n+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */\n }\n }\n \n", "prefixes": [ "PULL", "21/23" ] }