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GET /api/1.2/patches/811258/?format=api
{ "id": 811258, "url": "http://patchwork.ozlabs.org/api/1.2/patches/811258/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-16-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170907224051.21518-16-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-07T22:40:43", "name": "[PULL,15/23] tcg/arm: Improve tlb load for armv7", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a9ad273e6fbe3bcb5df482139aaa8e7749a2734c", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-16-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2073, "url": "http://patchwork.ozlabs.org/api/1.2/series/2073/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2073", "date": "2017-09-07T22:40:28", "name": "[PULL,01/23] tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2073/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811258/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811258/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"avymF+iO\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpG4T6DCmz9rxl\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 08:55:05 +1000 (AEST)", "from localhost ([::1]:42568 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dq5hQ-0005zD-0l\n\tfor incoming@patchwork.ozlabs.org; Thu, 07 Sep 2017 18:55:04 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:52250)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq5UA-0003B0-DV\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:27 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq5U5-0008JB-Js\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:22 -0400", "from mail-pg0-x235.google.com ([2607:f8b0:400e:c05::235]:37080)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dq5U5-0008Ig-Af\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:17 -0400", "by mail-pg0-x235.google.com with SMTP id d8so1804111pgt.4\n\tfor <qemu-devel@nongnu.org>; Thu, 07 Sep 2017 15:41:17 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\th19sm770678pfh.142.2017.09.07.15.41.14\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 07 Sep 2017 15:41:15 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=5QX8KOLakpmoalYp7gpxxqobtH+OmlG68TqfOqz5jpo=;\n\tb=avymF+iOfoV8ayOmc8Mnwihij2BQDSjIC91GwHzdyHC85dBGmOAKFQVUNUKL6SoqHR\n\tHfsCyZPnb5oWDhqxFe5uMxIAm36ZL0815l1YPzK18v761+2voPbgt1wBv39eNtrBpyku\n\tLtzGCRbLx46rV185K81dEjxWwxjp6yl7diF9A=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=5QX8KOLakpmoalYp7gpxxqobtH+OmlG68TqfOqz5jpo=;\n\tb=JgkVAgAiKIDm6H/0nC15PrjYpkT2gRyy13enAxkF/ukQlJzgAKoPZb1gQxEEf6IYlW\n\trDGHxkh/B/9PzEKR1N0j8jWrKWWpb9MfAQbYIWuxF6vildGztQzyn9LtQuVw91nvbIH2\n\tVkibDzOllyA4q3Hn4si16uBmfXAcWrvEdZ07znvt5T3IOKH34k1YlrycImMKF0YzuFRQ\n\t1QUut3EXaAt2y0pIyHIFpnh8XQsRDpRI0xr9z8BTNhZaNwu8a+QgivZVpo8wegrShEI2\n\tf0DUrmJxjrdDf5hG5ELwyhIU903sGHa4ux3uz6MyVmnK1IEKNzp7JaUhiEZwPWDcNtLj\n\tSXog==", "X-Gm-Message-State": "AHPjjUh8PLoIduf1YyN8KbTp5450uIRQSpVEhlNxRPafejJrWut1cOzy\n\tErfA4PpVI40KWcW709Wvzg==", "X-Google-Smtp-Source": "ADKCNb63ADnTh4NOSJD7r9onJtaYBix66AUmwIAEck69NSjD9CCs//JMcSPn5sgDBOYDsft4+/w9pw==", "X-Received": "by 10.84.132.1 with SMTP id 1mr1003215ple.253.1504824076120;\n\tThu, 07 Sep 2017 15:41:16 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Thu, 7 Sep 2017 15:40:43 -0700", "Message-Id": "<20170907224051.21518-16-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170907224051.21518-1-richard.henderson@linaro.org>", "References": "<20170907224051.21518-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::235", "Subject": "[Qemu-devel] [PULL 15/23] tcg/arm: Improve tlb load for armv7", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Richard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nUse UBFX to avoid limitation on CPU_TLB_BITS. Since we're dropping\nthe initial shift, we need to replace the page masking. We can use\nMOVW+BIC to do this without shifting. The result is the same size\nas the armv6 path with one less conditional instruction.\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n tcg/arm/tcg-target.inc.c | 72 ++++++++++++++++++++++++++++++++++--------------\n 1 file changed, 52 insertions(+), 20 deletions(-)", "diff": "diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c\nindex 81ea900852..66c369c239 100644\n--- a/tcg/arm/tcg-target.inc.c\n+++ b/tcg/arm/tcg-target.inc.c\n@@ -1173,18 +1173,33 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,\n unsigned s_bits = opc & MO_SIZE;\n unsigned a_bits = get_alignment_bits(opc);\n \n- /* Should generate something like the following:\n- * shr tmp, addrlo, #TARGET_PAGE_BITS (1)\n+ /* V7 generates the following:\n+ * ubfx r0, addrlo, #TARGET_PAGE_BITS, #CPU_TLB_BITS\n * add r2, env, #high\n- * and r0, tmp, #(CPU_TLB_SIZE - 1) (2)\n- * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS (3)\n- * ldr r0, [r2, #cmp] (4)\n+ * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS\n+ * ldr r0, [r2, #cmp]\n+ * ldr r2, [r2, #add]\n+ * movw tmp, #page_align_mask\n+ * bic tmp, addrlo, tmp\n+ * cmp r0, tmp\n+ *\n+ * Otherwise we generate:\n+ * shr tmp, addrlo, #TARGET_PAGE_BITS\n+ * add r2, env, #high\n+ * and r0, tmp, #(CPU_TLB_SIZE - 1)\n+ * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS\n+ * ldr r0, [r2, #cmp]\n+ * ldr r2, [r2, #add]\n * tst addrlo, #s_mask\n- * ldr r2, [r2, #add] (5)\n * cmpeq r0, tmp, lsl #TARGET_PAGE_BITS\n */\n- tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP,\n- 0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS));\n+ if (use_armv7_instructions) {\n+ tcg_out_extract(s, COND_AL, TCG_REG_R0, addrlo,\n+ TARGET_PAGE_BITS, CPU_TLB_BITS);\n+ } else {\n+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP,\n+ 0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS));\n+ }\n \n /* We checked that the offset is contained within 16 bits above. */\n if (add_off > 0xfff || (use_armv6_instructions && cmp_off > 0xff)) {\n@@ -1194,9 +1209,10 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,\n add_off -= cmp_off & 0xff00;\n cmp_off &= 0xff;\n }\n-\n- tcg_out_dat_imm(s, COND_AL, ARITH_AND,\n- TCG_REG_R0, TCG_REG_TMP, CPU_TLB_SIZE - 1);\n+ if (!use_armv7_instructions) {\n+ tcg_out_dat_imm(s, COND_AL, ARITH_AND,\n+ TCG_REG_R0, TCG_REG_TMP, CPU_TLB_SIZE - 1);\n+ }\n tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R2, base,\n TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));\n \n@@ -1212,24 +1228,40 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,\n }\n }\n \n+ /* Load the tlb addend. */\n+ tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R2, add_off);\n+\n /* Check alignment. We don't support inline unaligned acceses,\n but we can easily support overalignment checks. */\n if (a_bits < s_bits) {\n a_bits = s_bits;\n }\n- if (a_bits) {\n- tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, (1 << a_bits) - 1);\n- }\n \n- /* Load the tlb addend. */\n- tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R2, add_off);\n+ if (use_armv7_instructions) {\n+ tcg_target_ulong mask = ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1));\n+ int rot = encode_imm(mask);\n \n- tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, 0,\n- TCG_REG_R0, TCG_REG_TMP, SHIFT_IMM_LSL(TARGET_PAGE_BITS));\n+ if (rot >= 0) { \n+ tcg_out_dat_imm(s, COND_AL, ARITH_BIC, TCG_REG_TMP, addrlo,\n+ rotl(mask, rot) | (rot << 7));\n+ } else {\n+ tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask);\n+ tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP,\n+ addrlo, TCG_REG_TMP, 0);\n+ }\n+ tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R0, TCG_REG_TMP, 0);\n+ } else {\n+ if (a_bits) {\n+ tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo,\n+ (1 << a_bits) - 1);\n+ }\n+ tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP,\n+ 0, TCG_REG_R0, TCG_REG_TMP,\n+ SHIFT_IMM_LSL(TARGET_PAGE_BITS));\n+ }\n \n if (TARGET_LONG_BITS == 64) {\n- tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,\n- TCG_REG_R1, addrhi, SHIFT_IMM_LSL(0));\n+ tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R1, addrhi, 0);\n }\n \n return TCG_REG_R2;\n", "prefixes": [ "PULL", "15/23" ] }