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GET /api/1.2/patches/811256/?format=api
{ "id": 811256, "url": "http://patchwork.ozlabs.org/api/1.2/patches/811256/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-10-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170907224051.21518-10-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-07T22:40:37", "name": "[PULL,09/23] tcg/s390: Use constant pool for ori", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1b064a5c85c877b4da94548eaba1f91589734f39", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-10-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2073, "url": "http://patchwork.ozlabs.org/api/1.2/series/2073/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2073", "date": "2017-09-07T22:40:28", "name": "[PULL,01/23] tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2073/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811256/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811256/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"X0C8TEZH\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpG2642DJz9sDB\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 08:53:02 +1000 (AEST)", "from localhost ([::1]:42560 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dq5fQ-0004Jd-J9\n\tfor incoming@patchwork.ozlabs.org; Thu, 07 Sep 2017 18:53:00 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:52125)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq5U2-00034f-10\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:20 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq5Tw-0008AU-UJ\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:14 -0400", "from mail-pg0-x236.google.com ([2607:f8b0:400e:c05::236]:36680)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dq5Tw-00089a-Mf\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:08 -0400", "by mail-pg0-x236.google.com with SMTP id m9so1818296pgd.3\n\tfor <qemu-devel@nongnu.org>; Thu, 07 Sep 2017 15:41:08 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\th19sm770678pfh.142.2017.09.07.15.41.05\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 07 Sep 2017 15:41:06 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=6BZlkqXrN46LW44YziE4XJkyjG2E07rBsSu0/OqDgZ4=;\n\tb=X0C8TEZHwGE0r3KhVzHXhj0eogm0P9cokFHCW8TqzmLZTf9NXsf2q2fujsOy0aK2Em\n\tv06iN67Et+Fl1YkwiHOHvcc6GZESsgj8rwUBAb/yGk+pnzroRAq3GiVyVKg/wX6JBJue\n\tgTwn4nKGZhL3UHuHTK1arPonfB1wbFm2MVQ+A=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=6BZlkqXrN46LW44YziE4XJkyjG2E07rBsSu0/OqDgZ4=;\n\tb=cBOCBeYTBh4kZTU1mbf9323lrfa1fpHDbZKO5nt5VfVrPBJGLA6gtkdo1sfQVFdc/1\n\tM0IN/J8q8Vzpq4P5F0p8CgU7LFOOvT5P7S9BfF3oczYjq/xAegmgxUeM467hHfLhCKnh\n\tvkmQFjggAgETSFmdUP6zKPBhp/yR0hwxb66xmRzfjRCbdRPGoMUb2vyr1fhZMjXqUq1y\n\tjkMyUrAblF2bhvSm7q1ZBDmCkfF0Ej36T8MnhbM3HvRHK/CJePMLuBlVKA1Y5rt123zC\n\twTE1L7gZMAT529b34nafJqH4Q8DBwh/9gHn1RPmQj0uWK4d9AGi9LOE63K1n1+U0QG4K\n\t3GEQ==", "X-Gm-Message-State": "AHPjjUiAj/W+fVAvaxDd2OgM591kDBj0aXSAv2SX/3eShFkPEV5WE2LA\n\t+gclL6wxRGTcm6L81+UCnQ==", "X-Google-Smtp-Source": "ADKCNb69USj5KoA5Uhw6McWLOPHNZowhGXze5T7tUwEnLZx9RftruzBpr6yYUoin0GBZB/xYAXPDsw==", "X-Received": "by 10.99.3.9 with SMTP id 9mr932146pgd.205.1504824067239;\n\tThu, 07 Sep 2017 15:41:07 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Thu, 7 Sep 2017 15:40:37 -0700", "Message-Id": "<20170907224051.21518-10-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170907224051.21518-1-richard.henderson@linaro.org>", "References": "<20170907224051.21518-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::236", "Subject": "[Qemu-devel] [PULL 09/23] tcg/s390: Use constant pool for ori", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Richard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n tcg/s390/tcg-target.inc.c | 74 ++++++++++++++++++++++-------------------------\n 1 file changed, 34 insertions(+), 40 deletions(-)", "diff": "diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c\nindex 4be57c5765..83fac71c31 100644\n--- a/tcg/s390/tcg-target.inc.c\n+++ b/tcg/s390/tcg-target.inc.c\n@@ -225,6 +225,7 @@ typedef enum S390Opcode {\n RXY_LRVH = 0xe31f,\n RXY_LY = 0xe358,\n RXY_NG = 0xe380,\n+ RXY_OG = 0xe381,\n RXY_STCY = 0xe372,\n RXY_STG = 0xe324,\n RXY_STHY = 0xe370,\n@@ -1004,55 +1005,60 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)\n }\n }\n \n-static void tgen64_ori(TCGContext *s, TCGReg dest, tcg_target_ulong val)\n+static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)\n {\n static const S390Opcode oi_insns[4] = {\n RI_OILL, RI_OILH, RI_OIHL, RI_OIHH\n };\n- static const S390Opcode nif_insns[2] = {\n+ static const S390Opcode oif_insns[2] = {\n RIL_OILF, RIL_OIHF\n };\n \n int i;\n \n /* Look for no-op. */\n- if (val == 0) {\n+ if (unlikely(val == 0)) {\n return;\n }\n \n- if (s390_facilities & FACILITY_EXT_IMM) {\n- /* Try all 32-bit insns that can perform it in one go. */\n- for (i = 0; i < 4; i++) {\n- tcg_target_ulong mask = (0xffffull << i*16);\n- if ((val & mask) != 0 && (val & ~mask) == 0) {\n- tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16);\n- return;\n- }\n+ /* Try all 32-bit insns that can perform it in one go. */\n+ for (i = 0; i < 4; i++) {\n+ tcg_target_ulong mask = (0xffffull << i*16);\n+ if ((val & mask) != 0 && (val & ~mask) == 0) {\n+ tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16);\n+ return;\n }\n+ }\n \n- /* Try all 48-bit insns that can perform it in one go. */\n+ /* Try all 48-bit insns that can perform it in one go. */\n+ if (s390_facilities & FACILITY_EXT_IMM) {\n for (i = 0; i < 2; i++) {\n tcg_target_ulong mask = (0xffffffffull << i*32);\n if ((val & mask) != 0 && (val & ~mask) == 0) {\n- tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32);\n+ tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i*32);\n return;\n }\n }\n+ }\n \n+ /* Use the constant pool if USE_REG_TB, but not for small constants. */\n+ if (maybe_out_small_movi(s, type, TCG_TMP0, val)) {\n+ if (type == TCG_TYPE_I32) {\n+ tcg_out_insn(s, RR, OR, dest, TCG_TMP0);\n+ } else {\n+ tcg_out_insn(s, RRE, OGR, dest, TCG_TMP0);\n+ }\n+ } else if (USE_REG_TB) {\n+ tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0);\n+ new_pool_label(s, val, R_390_20, s->code_ptr - 2,\n+ -(intptr_t)s->code_gen_ptr);\n+ } else {\n /* Perform the OR via sequential modifications to the high and\n low parts. Do this via recursion to handle 16-bit vs 32-bit\n masks in each half. */\n- tgen64_ori(s, dest, val & 0x00000000ffffffffull);\n- tgen64_ori(s, dest, val & 0xffffffff00000000ull);\n- } else {\n- /* With no extended-immediate facility, we don't need to be so\n- clever. Just iterate over the insns and mask in the constant. */\n- for (i = 0; i < 4; i++) {\n- tcg_target_ulong mask = (0xffffull << i*16);\n- if ((val & mask) != 0) {\n- tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16);\n- }\n- }\n+ tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM);\n+ tgen_ori(s, type, dest, val & 0x00000000ffffffffull);\n+ tgen_ori(s, type, dest, val & 0xffffffff00000000ull);\n }\n }\n \n@@ -1872,7 +1878,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,\n a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];\n if (const_args[2]) {\n tcg_out_mov(s, TCG_TYPE_I32, a0, a1);\n- tgen64_ori(s, a0, a2);\n+ tgen_ori(s, TCG_TYPE_I32, a0, a2);\n } else if (a0 == a1) {\n tcg_out_insn(s, RR, OR, a0, a2);\n } else {\n@@ -2104,7 +2110,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,\n a0 = args[0], a1 = args[1], a2 = args[2];\n if (const_args[2]) {\n tcg_out_mov(s, TCG_TYPE_I64, a0, a1);\n- tgen64_ori(s, a0, a2);\n+ tgen_ori(s, TCG_TYPE_I64, a0, a2);\n } else if (a0 == a1) {\n tcg_out_insn(s, RRE, OGR, a0, a2);\n } else {\n@@ -2312,7 +2318,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n static const TCGTargetOpDef r_0_ri = { .args_ct_str = { \"r\", \"0\", \"ri\" } };\n static const TCGTargetOpDef r_0_rI = { .args_ct_str = { \"r\", \"0\", \"rI\" } };\n static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { \"r\", \"0\", \"rJ\" } };\n- static const TCGTargetOpDef r_0_rN = { .args_ct_str = { \"r\", \"0\", \"rN\" } };\n static const TCGTargetOpDef r_0_rM = { .args_ct_str = { \"r\", \"0\", \"rM\" } };\n static const TCGTargetOpDef a2_r\n = { .args_ct_str = { \"r\", \"r\", \"0\", \"1\", \"r\", \"r\" } };\n@@ -2353,6 +2358,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n case INDEX_op_sub_i64:\n case INDEX_op_and_i32:\n case INDEX_op_and_i64:\n+ case INDEX_op_or_i32:\n+ case INDEX_op_or_i64:\n return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);\n \n case INDEX_op_mul_i32:\n@@ -2363,19 +2370,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n case INDEX_op_mul_i64:\n return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);\n \n- case INDEX_op_or_i32:\n- /* The use of [iNM] constraints are optimization only, since a full\n- 64-bit immediate OR can always be performed with 4 sequential\n- OI[LH][LH] instructions. By rejecting certain negative ranges,\n- the immediate load plus the reg-reg OR is smaller. */\n- return (s390_facilities & FACILITY_EXT_IMM\n- ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri)\n- : &r_0_rN);\n- case INDEX_op_or_i64:\n- return (s390_facilities & FACILITY_EXT_IMM\n- ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_0_rM)\n- : &r_0_rN);\n-\n case INDEX_op_xor_i32:\n /* Without EXT_IMM, no immediates are supported. Otherwise,\n rejecting certain negative ranges leads to smaller code. */\n", "prefixes": [ "PULL", "09/23" ] }