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GET /api/1.2/patches/811255/?format=api
{ "id": 811255, "url": "http://patchwork.ozlabs.org/api/1.2/patches/811255/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-18-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170907224051.21518-18-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-07T22:40:45", "name": "[PULL,17/23] tcg/arm: Code rearrangement", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "acf708fb60d752b944e6e33629e2a042e93db881", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-18-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2073, "url": "http://patchwork.ozlabs.org/api/1.2/series/2073/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2073", "date": "2017-09-07T22:40:28", "name": "[PULL,01/23] tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2073/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811255/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811255/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"c1o8Tht+\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpG1B67r6z9rxl\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 08:52:14 +1000 (AEST)", "from localhost ([::1]:42558 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dq5ee-0003Vw-Ta\n\tfor incoming@patchwork.ozlabs.org; Thu, 07 Sep 2017 18:52:12 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:52332)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq5UF-0003Ge-II\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:34 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq5U8-0008Li-TT\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:27 -0400", "from mail-pf0-x22a.google.com ([2607:f8b0:400e:c00::22a]:34083)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dq5U8-0008Kz-Kd\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:20 -0400", "by mail-pf0-x22a.google.com with SMTP id e1so1640981pfk.1\n\tfor <qemu-devel@nongnu.org>; Thu, 07 Sep 2017 15:41:20 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\th19sm770678pfh.142.2017.09.07.15.41.17\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 07 Sep 2017 15:41:17 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=my5u9zTRSGJTRSMPjvCTuuzuAPHbQ/HrYQ7To4qpkd4=;\n\tb=c1o8Tht+Y1OQ5l4EvBr7lPYOO8u99EiYJdKJnQtD/Tau++C3iq1BP97KCgOS+6ZwtO\n\tBoouIhijTnWMDTbEVicG+F89UVCu94EmYcAy7fq3ci34KkeTX/cC9I2MYb+5ymCxTt0N\n\twEYk2P2Ms67EaK+k1VN47IqDZAZlZkeVhaoAY=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=my5u9zTRSGJTRSMPjvCTuuzuAPHbQ/HrYQ7To4qpkd4=;\n\tb=hmkIMDsonARcbFWaFGY/Npx1t3L5YDJLnAlBk99EtYiG/2JMHLzVJWcbz0kH/OMLeL\n\tA+M1ybo3XvylIAduOtPlpD4pFZxKHwRARwmQbAqfFf+BAaeEc10i077bM7ulT/i+0ESu\n\t/EU6lOpS/5WTXi3+2H8jaFcytk9dUBdpLxbwyjdsgWsCqPkVU5LCKFFFJlEpeUXeWc8r\n\toxNkhOOKqr3zus0Y9uqsQmr1cQxvOF9UJDN5bZELNhqk4dqGh1gILOpi3w7L647yL3YA\n\t3ya0MAJbl8VGTbjA7eEzvcZ9RQLa5N7tfgIs2yotXVlIL03304eiUPJ1BJQ+GFvBYs4v\n\t5xBw==", "X-Gm-Message-State": "AHPjjUjQeJVCkOnn2LX6Vkm9To7NXSGf9O1Mzt7WtvPYSj1Yq/PKzDa8\n\tdz1DSlC+oYSYlpZ4q7XqMw==", "X-Google-Smtp-Source": "ADKCNb4X44g49RQ2XLMAe0r016eYXsXgEgEU/A90Kp4Pjx8UlOz1linE6hMQWb3tqmNlc/nFAzfAMg==", "X-Received": "by 10.98.75.152 with SMTP id d24mr993866pfj.38.1504824078838;\n\tThu, 07 Sep 2017 15:41:18 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Thu, 7 Sep 2017 15:40:45 -0700", "Message-Id": "<20170907224051.21518-18-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170907224051.21518-1-richard.henderson@linaro.org>", "References": "<20170907224051.21518-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c00::22a", "Subject": "[Qemu-devel] [PULL 17/23] tcg/arm: Code rearrangement", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Richard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nMove constants before all of the functions.\nMove tcg_out_<format> functions before all\nof the others. No functional change.\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n tcg/arm/tcg-target.inc.c | 599 +++++++++++++++++++++++------------------------\n 1 file changed, 299 insertions(+), 300 deletions(-)", "diff": "diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c\nindex 6c12b169ce..f40e87066f 100644\n--- a/tcg/arm/tcg-target.inc.c\n+++ b/tcg/arm/tcg-target.inc.c\n@@ -85,6 +85,97 @@ static const int tcg_target_call_oarg_regs[2] = {\n \n #define TCG_REG_TMP TCG_REG_R12\n \n+enum arm_cond_code_e {\n+ COND_EQ = 0x0,\n+ COND_NE = 0x1,\n+ COND_CS = 0x2,\t/* Unsigned greater or equal */\n+ COND_CC = 0x3,\t/* Unsigned less than */\n+ COND_MI = 0x4,\t/* Negative */\n+ COND_PL = 0x5,\t/* Zero or greater */\n+ COND_VS = 0x6,\t/* Overflow */\n+ COND_VC = 0x7,\t/* No overflow */\n+ COND_HI = 0x8,\t/* Unsigned greater than */\n+ COND_LS = 0x9,\t/* Unsigned less or equal */\n+ COND_GE = 0xa,\n+ COND_LT = 0xb,\n+ COND_GT = 0xc,\n+ COND_LE = 0xd,\n+ COND_AL = 0xe,\n+};\n+\n+#define TO_CPSR (1 << 20)\n+\n+#define SHIFT_IMM_LSL(im)\t(((im) << 7) | 0x00)\n+#define SHIFT_IMM_LSR(im)\t(((im) << 7) | 0x20)\n+#define SHIFT_IMM_ASR(im)\t(((im) << 7) | 0x40)\n+#define SHIFT_IMM_ROR(im)\t(((im) << 7) | 0x60)\n+#define SHIFT_REG_LSL(rs)\t(((rs) << 8) | 0x10)\n+#define SHIFT_REG_LSR(rs)\t(((rs) << 8) | 0x30)\n+#define SHIFT_REG_ASR(rs)\t(((rs) << 8) | 0x50)\n+#define SHIFT_REG_ROR(rs)\t(((rs) << 8) | 0x70)\n+\n+typedef enum {\n+ ARITH_AND = 0x0 << 21,\n+ ARITH_EOR = 0x1 << 21,\n+ ARITH_SUB = 0x2 << 21,\n+ ARITH_RSB = 0x3 << 21,\n+ ARITH_ADD = 0x4 << 21,\n+ ARITH_ADC = 0x5 << 21,\n+ ARITH_SBC = 0x6 << 21,\n+ ARITH_RSC = 0x7 << 21,\n+ ARITH_TST = 0x8 << 21 | TO_CPSR,\n+ ARITH_CMP = 0xa << 21 | TO_CPSR,\n+ ARITH_CMN = 0xb << 21 | TO_CPSR,\n+ ARITH_ORR = 0xc << 21,\n+ ARITH_MOV = 0xd << 21,\n+ ARITH_BIC = 0xe << 21,\n+ ARITH_MVN = 0xf << 21,\n+\n+ INSN_CLZ = 0x016f0f10,\n+ INSN_RBIT = 0x06ff0f30,\n+\n+ INSN_LDR_IMM = 0x04100000,\n+ INSN_LDR_REG = 0x06100000,\n+ INSN_STR_IMM = 0x04000000,\n+ INSN_STR_REG = 0x06000000,\n+\n+ INSN_LDRH_IMM = 0x005000b0,\n+ INSN_LDRH_REG = 0x001000b0,\n+ INSN_LDRSH_IMM = 0x005000f0,\n+ INSN_LDRSH_REG = 0x001000f0,\n+ INSN_STRH_IMM = 0x004000b0,\n+ INSN_STRH_REG = 0x000000b0,\n+\n+ INSN_LDRB_IMM = 0x04500000,\n+ INSN_LDRB_REG = 0x06500000,\n+ INSN_LDRSB_IMM = 0x005000d0,\n+ INSN_LDRSB_REG = 0x001000d0,\n+ INSN_STRB_IMM = 0x04400000,\n+ INSN_STRB_REG = 0x06400000,\n+\n+ INSN_LDRD_IMM = 0x004000d0,\n+ INSN_LDRD_REG = 0x000000d0,\n+ INSN_STRD_IMM = 0x004000f0,\n+ INSN_STRD_REG = 0x000000f0,\n+\n+ INSN_DMB_ISH = 0x5bf07ff5,\n+ INSN_DMB_MCR = 0xba0f07ee,\n+} ARMInsn;\n+\n+static const uint8_t tcg_cond_to_arm_cond[] = {\n+ [TCG_COND_EQ] = COND_EQ,\n+ [TCG_COND_NE] = COND_NE,\n+ [TCG_COND_LT] = COND_LT,\n+ [TCG_COND_GE] = COND_GE,\n+ [TCG_COND_LE] = COND_LE,\n+ [TCG_COND_GT] = COND_GT,\n+ /* unsigned */\n+ [TCG_COND_LTU] = COND_CC,\n+ [TCG_COND_GEU] = COND_CS,\n+ [TCG_COND_LEU] = COND_LS,\n+ [TCG_COND_GTU] = COND_HI,\n+};\n+\n static inline void reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *target)\n {\n ptrdiff_t offset = (tcg_ptr_byte_diff(target, code_ptr) - 8) >> 2;\n@@ -236,183 +327,257 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,\n }\n }\n \n-#define TO_CPSR (1 << 20)\n+static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)\n+{\n+ tcg_out32(s, (cond << 28) | 0x0a000000 |\n+ (((offset - 8) >> 2) & 0x00ffffff));\n+}\n \n-typedef enum {\n- ARITH_AND = 0x0 << 21,\n- ARITH_EOR = 0x1 << 21,\n- ARITH_SUB = 0x2 << 21,\n- ARITH_RSB = 0x3 << 21,\n- ARITH_ADD = 0x4 << 21,\n- ARITH_ADC = 0x5 << 21,\n- ARITH_SBC = 0x6 << 21,\n- ARITH_RSC = 0x7 << 21,\n- ARITH_TST = 0x8 << 21 | TO_CPSR,\n- ARITH_CMP = 0xa << 21 | TO_CPSR,\n- ARITH_CMN = 0xb << 21 | TO_CPSR,\n- ARITH_ORR = 0xc << 21,\n- ARITH_MOV = 0xd << 21,\n- ARITH_BIC = 0xe << 21,\n- ARITH_MVN = 0xf << 21,\n+static inline void tcg_out_b_noaddr(TCGContext *s, int cond)\n+{\n+ /* We pay attention here to not modify the branch target by masking\n+ the corresponding bytes. This ensure that caches and memory are\n+ kept coherent during retranslation. */\n+ tcg_out32(s, deposit32(*s->code_ptr, 24, 8, (cond << 4) | 0x0a));\n+}\n \n- INSN_CLZ = 0x016f0f10,\n- INSN_RBIT = 0x06ff0f30,\n+static inline void tcg_out_bl_noaddr(TCGContext *s, int cond)\n+{\n+ /* We pay attention here to not modify the branch target by masking\n+ the corresponding bytes. This ensure that caches and memory are\n+ kept coherent during retranslation. */\n+ tcg_out32(s, deposit32(*s->code_ptr, 24, 8, (cond << 4) | 0x0b));\n+}\n \n- INSN_LDR_IMM = 0x04100000,\n- INSN_LDR_REG = 0x06100000,\n- INSN_STR_IMM = 0x04000000,\n- INSN_STR_REG = 0x06000000,\n+static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)\n+{\n+ tcg_out32(s, (cond << 28) | 0x0b000000 |\n+ (((offset - 8) >> 2) & 0x00ffffff));\n+}\n \n- INSN_LDRH_IMM = 0x005000b0,\n- INSN_LDRH_REG = 0x001000b0,\n- INSN_LDRSH_IMM = 0x005000f0,\n- INSN_LDRSH_REG = 0x001000f0,\n- INSN_STRH_IMM = 0x004000b0,\n- INSN_STRH_REG = 0x000000b0,\n+static inline void tcg_out_blx(TCGContext *s, int cond, int rn)\n+{\n+ tcg_out32(s, (cond << 28) | 0x012fff30 | rn);\n+}\n \n- INSN_LDRB_IMM = 0x04500000,\n- INSN_LDRB_REG = 0x06500000,\n- INSN_LDRSB_IMM = 0x005000d0,\n- INSN_LDRSB_REG = 0x001000d0,\n- INSN_STRB_IMM = 0x04400000,\n- INSN_STRB_REG = 0x06400000,\n+static inline void tcg_out_blx_imm(TCGContext *s, int32_t offset)\n+{\n+ tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) |\n+ (((offset - 8) >> 2) & 0x00ffffff));\n+}\n \n- INSN_LDRD_IMM = 0x004000d0,\n- INSN_LDRD_REG = 0x000000d0,\n- INSN_STRD_IMM = 0x004000f0,\n- INSN_STRD_REG = 0x000000f0,\n+static inline void tcg_out_dat_reg(TCGContext *s,\n+ int cond, int opc, int rd, int rn, int rm, int shift)\n+{\n+ tcg_out32(s, (cond << 28) | (0 << 25) | opc |\n+ (rn << 16) | (rd << 12) | shift | rm);\n+}\n \n- INSN_DMB_ISH = 0x5bf07ff5,\n- INSN_DMB_MCR = 0xba0f07ee,\n+static inline void tcg_out_nop(TCGContext *s)\n+{\n+ if (use_armv7_instructions) {\n+ /* Architected nop introduced in v6k. */\n+ /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this\n+ also Just So Happened to do nothing on pre-v6k so that we\n+ don't need to conditionalize it? */\n+ tcg_out32(s, 0xe320f000);\n+ } else {\n+ /* Prior to that the assembler uses mov r0, r0. */\n+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, 0, 0, 0, SHIFT_IMM_LSL(0));\n+ }\n+}\n \n-} ARMInsn;\n+static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm)\n+{\n+ /* Simple reg-reg move, optimising out the 'do nothing' case */\n+ if (rd != rm) {\n+ tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0));\n+ }\n+}\n \n-#define SHIFT_IMM_LSL(im)\t(((im) << 7) | 0x00)\n-#define SHIFT_IMM_LSR(im)\t(((im) << 7) | 0x20)\n-#define SHIFT_IMM_ASR(im)\t(((im) << 7) | 0x40)\n-#define SHIFT_IMM_ROR(im)\t(((im) << 7) | 0x60)\n-#define SHIFT_REG_LSL(rs)\t(((rs) << 8) | 0x10)\n-#define SHIFT_REG_LSR(rs)\t(((rs) << 8) | 0x30)\n-#define SHIFT_REG_ASR(rs)\t(((rs) << 8) | 0x50)\n-#define SHIFT_REG_ROR(rs)\t(((rs) << 8) | 0x70)\n+static inline void tcg_out_bx(TCGContext *s, int cond, TCGReg rn)\n+{\n+ /* Unless the C portion of QEMU is compiled as thumb, we don't\n+ actually need true BX semantics; merely a branch to an address\n+ held in a register. */\n+ if (use_armv5t_instructions) {\n+ tcg_out32(s, (cond << 28) | 0x012fff10 | rn);\n+ } else {\n+ tcg_out_mov_reg(s, cond, TCG_REG_PC, rn);\n+ }\n+}\n \n-enum arm_cond_code_e {\n- COND_EQ = 0x0,\n- COND_NE = 0x1,\n- COND_CS = 0x2,\t/* Unsigned greater or equal */\n- COND_CC = 0x3,\t/* Unsigned less than */\n- COND_MI = 0x4,\t/* Negative */\n- COND_PL = 0x5,\t/* Zero or greater */\n- COND_VS = 0x6,\t/* Overflow */\n- COND_VC = 0x7,\t/* No overflow */\n- COND_HI = 0x8,\t/* Unsigned greater than */\n- COND_LS = 0x9,\t/* Unsigned less or equal */\n- COND_GE = 0xa,\n- COND_LT = 0xb,\n- COND_GT = 0xc,\n- COND_LE = 0xd,\n- COND_AL = 0xe,\n-};\n+static inline void tcg_out_dat_imm(TCGContext *s,\n+ int cond, int opc, int rd, int rn, int im)\n+{\n+ tcg_out32(s, (cond << 28) | (1 << 25) | opc |\n+ (rn << 16) | (rd << 12) | im);\n+}\n \n-static const uint8_t tcg_cond_to_arm_cond[] = {\n- [TCG_COND_EQ] = COND_EQ,\n- [TCG_COND_NE] = COND_NE,\n- [TCG_COND_LT] = COND_LT,\n- [TCG_COND_GE] = COND_GE,\n- [TCG_COND_LE] = COND_LE,\n- [TCG_COND_GT] = COND_GT,\n- /* unsigned */\n- [TCG_COND_LTU] = COND_CC,\n- [TCG_COND_GEU] = COND_CS,\n- [TCG_COND_LEU] = COND_LS,\n- [TCG_COND_GTU] = COND_HI,\n-};\n+/* Note that this routine is used for both LDR and LDRH formats, so we do\n+ not wish to include an immediate shift at this point. */\n+static void tcg_out_memop_r(TCGContext *s, int cond, ARMInsn opc, TCGReg rt,\n+ TCGReg rn, TCGReg rm, bool u, bool p, bool w)\n+{\n+ tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24)\n+ | (w << 21) | (rn << 16) | (rt << 12) | rm);\n+}\n+\n+static void tcg_out_memop_8(TCGContext *s, int cond, ARMInsn opc, TCGReg rt,\n+ TCGReg rn, int imm8, bool p, bool w)\n+{\n+ bool u = 1;\n+ if (imm8 < 0) {\n+ imm8 = -imm8;\n+ u = 0;\n+ }\n+ tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) |\n+ (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf));\n+}\n+\n+static void tcg_out_memop_12(TCGContext *s, int cond, ARMInsn opc, TCGReg rt,\n+ TCGReg rn, int imm12, bool p, bool w)\n+{\n+ bool u = 1;\n+ if (imm12 < 0) {\n+ imm12 = -imm12;\n+ u = 0;\n+ }\n+ tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) |\n+ (rn << 16) | (rt << 12) | imm12);\n+}\n+\n+static inline void tcg_out_ld32_12(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, int imm12)\n+{\n+ tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0);\n+}\n+\n+static inline void tcg_out_st32_12(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, int imm12)\n+{\n+ tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0);\n+}\n+\n+static inline void tcg_out_ld32_r(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, TCGReg rm)\n+{\n+ tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0);\n+}\n+\n+static inline void tcg_out_st32_r(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, TCGReg rm)\n+{\n+ tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0);\n+}\n+\n+static inline void tcg_out_ldrd_8(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, int imm8)\n+{\n+ tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0);\n+}\n+\n+static inline void tcg_out_ldrd_r(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, TCGReg rm)\n+{\n+ tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0);\n+}\n+\n+static inline void tcg_out_strd_8(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, int imm8)\n+{\n+ tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0);\n+}\n+\n+static inline void tcg_out_strd_r(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, TCGReg rm)\n+{\n+ tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0);\n+}\n+\n+/* Register pre-increment with base writeback. */\n+static inline void tcg_out_ld32_rwb(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, TCGReg rm)\n+{\n+ tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1);\n+}\n+\n+static inline void tcg_out_st32_rwb(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, TCGReg rm)\n+{\n+ tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1);\n+}\n+\n+static inline void tcg_out_ld16u_8(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, int imm8)\n+{\n+ tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0);\n+}\n \n-static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)\n+static inline void tcg_out_st16_8(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, int imm8)\n {\n- tcg_out32(s, (cond << 28) | 0x0a000000 |\n- (((offset - 8) >> 2) & 0x00ffffff));\n+ tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0);\n }\n \n-static inline void tcg_out_b_noaddr(TCGContext *s, int cond)\n+static inline void tcg_out_ld16u_r(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, TCGReg rm)\n {\n- /* We pay attention here to not modify the branch target by masking\n- the corresponding bytes. This ensure that caches and memory are\n- kept coherent during retranslation. */\n- tcg_out32(s, deposit32(*s->code_ptr, 24, 8, (cond << 4) | 0x0a));\n+ tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0);\n }\n \n-static inline void tcg_out_bl_noaddr(TCGContext *s, int cond)\n+static inline void tcg_out_st16_r(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, TCGReg rm)\n {\n- /* We pay attention here to not modify the branch target by masking\n- the corresponding bytes. This ensure that caches and memory are\n- kept coherent during retranslation. */\n- tcg_out32(s, deposit32(*s->code_ptr, 24, 8, (cond << 4) | 0x0b));\n+ tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0);\n }\n \n-static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)\n+static inline void tcg_out_ld16s_8(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, int imm8)\n {\n- tcg_out32(s, (cond << 28) | 0x0b000000 |\n- (((offset - 8) >> 2) & 0x00ffffff));\n+ tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0);\n }\n \n-static inline void tcg_out_blx(TCGContext *s, int cond, int rn)\n+static inline void tcg_out_ld16s_r(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, TCGReg rm)\n {\n- tcg_out32(s, (cond << 28) | 0x012fff30 | rn);\n+ tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0);\n }\n \n-static inline void tcg_out_blx_imm(TCGContext *s, int32_t offset)\n+static inline void tcg_out_ld8_12(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, int imm12)\n {\n- tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) |\n- (((offset - 8) >> 2) & 0x00ffffff));\n+ tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0);\n }\n \n-static inline void tcg_out_dat_reg(TCGContext *s,\n- int cond, int opc, int rd, int rn, int rm, int shift)\n+static inline void tcg_out_st8_12(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, int imm12)\n {\n- tcg_out32(s, (cond << 28) | (0 << 25) | opc |\n- (rn << 16) | (rd << 12) | shift | rm);\n+ tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0);\n }\n \n-static inline void tcg_out_nop(TCGContext *s)\n+static inline void tcg_out_ld8_r(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, TCGReg rm)\n {\n- if (use_armv7_instructions) {\n- /* Architected nop introduced in v6k. */\n- /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this\n- also Just So Happened to do nothing on pre-v6k so that we\n- don't need to conditionalize it? */\n- tcg_out32(s, 0xe320f000);\n- } else {\n- /* Prior to that the assembler uses mov r0, r0. */\n- tcg_out_dat_reg(s, COND_AL, ARITH_MOV, 0, 0, 0, SHIFT_IMM_LSL(0));\n- }\n+ tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0);\n }\n \n-static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm)\n+static inline void tcg_out_st8_r(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, TCGReg rm)\n {\n- /* Simple reg-reg move, optimising out the 'do nothing' case */\n- if (rd != rm) {\n- tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0));\n- }\n+ tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0);\n }\n \n-static inline void tcg_out_bx(TCGContext *s, int cond, TCGReg rn)\n+static inline void tcg_out_ld8s_8(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, int imm8)\n {\n- /* Unless the C portion of QEMU is compiled as thumb, we don't\n- actually need true BX semantics; merely a branch to an address\n- held in a register. */\n- if (use_armv5t_instructions) {\n- tcg_out32(s, (cond << 28) | 0x012fff10 | rn);\n- } else {\n- tcg_out_mov_reg(s, cond, TCG_REG_PC, rn);\n- }\n+ tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0);\n }\n \n-static inline void tcg_out_dat_imm(TCGContext *s,\n- int cond, int opc, int rd, int rn, int im)\n+static inline void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt,\n+ TCGReg rn, TCGReg rm)\n {\n- tcg_out32(s, (cond << 28) | (1 << 25) | opc |\n- (rn << 16) | (rd << 12) | im);\n+ tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0);\n }\n \n static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg)\n@@ -747,172 +912,6 @@ static inline void tcg_out_sextract(TCGContext *s, int cond, TCGReg rd,\n | (ofs << 7) | ((len - 1) << 16));\n }\n \n-/* Note that this routine is used for both LDR and LDRH formats, so we do\n- not wish to include an immediate shift at this point. */\n-static void tcg_out_memop_r(TCGContext *s, int cond, ARMInsn opc, TCGReg rt,\n- TCGReg rn, TCGReg rm, bool u, bool p, bool w)\n-{\n- tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24)\n- | (w << 21) | (rn << 16) | (rt << 12) | rm);\n-}\n-\n-static void tcg_out_memop_8(TCGContext *s, int cond, ARMInsn opc, TCGReg rt,\n- TCGReg rn, int imm8, bool p, bool w)\n-{\n- bool u = 1;\n- if (imm8 < 0) {\n- imm8 = -imm8;\n- u = 0;\n- }\n- tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) |\n- (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf));\n-}\n-\n-static void tcg_out_memop_12(TCGContext *s, int cond, ARMInsn opc, TCGReg rt,\n- TCGReg rn, int imm12, bool p, bool w)\n-{\n- bool u = 1;\n- if (imm12 < 0) {\n- imm12 = -imm12;\n- u = 0;\n- }\n- tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) |\n- (rn << 16) | (rt << 12) | imm12);\n-}\n-\n-static inline void tcg_out_ld32_12(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, int imm12)\n-{\n- tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0);\n-}\n-\n-static inline void tcg_out_st32_12(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, int imm12)\n-{\n- tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0);\n-}\n-\n-static inline void tcg_out_ld32_r(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, TCGReg rm)\n-{\n- tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0);\n-}\n-\n-static inline void tcg_out_st32_r(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, TCGReg rm)\n-{\n- tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0);\n-}\n-\n-static inline void tcg_out_ldrd_8(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, int imm8)\n-{\n- tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0);\n-}\n-\n-static inline void tcg_out_ldrd_r(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, TCGReg rm)\n-{\n- tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0);\n-}\n-\n-static inline void tcg_out_strd_8(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, int imm8)\n-{\n- tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0);\n-}\n-\n-static inline void tcg_out_strd_r(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, TCGReg rm)\n-{\n- tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0);\n-}\n-\n-/* Register pre-increment with base writeback. */\n-static inline void tcg_out_ld32_rwb(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, TCGReg rm)\n-{\n- tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1);\n-}\n-\n-static inline void tcg_out_st32_rwb(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, TCGReg rm)\n-{\n- tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1);\n-}\n-\n-static inline void tcg_out_ld16u_8(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, int imm8)\n-{\n- tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0);\n-}\n-\n-static inline void tcg_out_st16_8(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, int imm8)\n-{\n- tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0);\n-}\n-\n-static inline void tcg_out_ld16u_r(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, TCGReg rm)\n-{\n- tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0);\n-}\n-\n-static inline void tcg_out_st16_r(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, TCGReg rm)\n-{\n- tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0);\n-}\n-\n-static inline void tcg_out_ld16s_8(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, int imm8)\n-{\n- tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0);\n-}\n-\n-static inline void tcg_out_ld16s_r(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, TCGReg rm)\n-{\n- tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0);\n-}\n-\n-static inline void tcg_out_ld8_12(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, int imm12)\n-{\n- tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0);\n-}\n-\n-static inline void tcg_out_st8_12(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, int imm12)\n-{\n- tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0);\n-}\n-\n-static inline void tcg_out_ld8_r(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, TCGReg rm)\n-{\n- tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0);\n-}\n-\n-static inline void tcg_out_st8_r(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, TCGReg rm)\n-{\n- tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0);\n-}\n-\n-static inline void tcg_out_ld8s_8(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, int imm8)\n-{\n- tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0);\n-}\n-\n-static inline void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt,\n- TCGReg rn, TCGReg rm)\n-{\n- tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0);\n-}\n-\n static inline void tcg_out_ld32u(TCGContext *s, int cond,\n int rd, int rn, int32_t offset)\n {\n", "prefixes": [ "PULL", "17/23" ] }