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GET /api/1.2/patches/811209/?format=api
{ "id": 811209, "url": "http://patchwork.ozlabs.org/api/1.2/patches/811209/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-8-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170907224051.21518-8-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-07T22:40:35", "name": "[PULL,07/23] tcg/s390: Use constant pool for movi", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8d367912a30193c657228830b7286f146d4b7212", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-8-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2073, "url": "http://patchwork.ozlabs.org/api/1.2/series/2073/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2073", "date": "2017-09-07T22:40:28", "name": "[PULL,01/23] tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2073/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811209/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811209/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"jsbqvqt+\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpFrp1R57z9s81\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 08:44:58 +1000 (AEST)", "from localhost ([::1]:42525 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dq5Xc-0005hY-30\n\tfor incoming@patchwork.ozlabs.org; Thu, 07 Sep 2017 18:44:56 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:52063)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq5Ty-00031e-Tl\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:16 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq5Tt-00087W-PN\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:10 -0400", "from mail-pg0-x235.google.com ([2607:f8b0:400e:c05::235]:37894)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dq5Tt-00086u-H5\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:05 -0400", "by mail-pg0-x235.google.com with SMTP id v66so1788168pgb.5\n\tfor <qemu-devel@nongnu.org>; Thu, 07 Sep 2017 15:41:05 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\th19sm770678pfh.142.2017.09.07.15.41.02\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 07 Sep 2017 15:41:03 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=sJPZYRXenZB9l4KsHJUB2AueMWnCWt02iaTztenK5Zk=;\n\tb=jsbqvqt+35Uh5cmXuTfgbCcIUhAUCVzzD7h8Y/cmxB0/mdnn5XcEoxRV8bpUWiUAJw\n\tiqPqaVDjsP0CBk2nxxnrHSerwCDZSynW7e5wgYbX+9hmTMPDKUiQv162YN9jNfWmXsEi\n\tb2qBsyR4zAEmR/RpZRPrkUsaTYYpM1Z0ELGOQ=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=sJPZYRXenZB9l4KsHJUB2AueMWnCWt02iaTztenK5Zk=;\n\tb=VVKrLTuuKeOZy4gdo1cJ9g6FcgM2r54hmqwJgvY7PGIFovC/JeGoRgoYo3k8X0QOfd\n\tGvuMJTU8kgTlBD63iHZWaz0yGkBiMu/Ndc0ASktoa5cDiyTSPwQ9kkbNkgcRr7EYYW12\n\tB84axXK9qFaSSncCG52xFCq/78zFdYCch91XNx9TCdnMDy40zE4iLq4uwGNsnVP1zlRM\n\tziJHlpTlFniwbXoR6ZDzV6W3f5JsZECH1G0TfLrlygmI3Xuj9S9AsPotr5tE7I8VSh8m\n\tlIqVBluIQXyA7d3y39L91M/TwmNs37sv/h98jZ+wE76pr+ik0vQFZJnqyTSoUwoZkKza\n\t9/2g==", "X-Gm-Message-State": "AHPjjUjHdc6rQ49c4iYwM875BD1mDqynGKSgQSptmh3uf9BJvYHhL4Yh\n\tPMbkMqx5Q2byzqvGq3PLTg==", "X-Google-Smtp-Source": "ADKCNb576cECp2qzAj1Tw0h5mxFoBNCU1JQ3sy6m0YDIp3SY+zrNZ7HKTVbHMAWeyuBWegOhau8xyw==", "X-Received": "by 10.99.67.130 with SMTP id q124mr940512pga.97.1504824064097;\n\tThu, 07 Sep 2017 15:41:04 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Thu, 7 Sep 2017 15:40:35 -0700", "Message-Id": "<20170907224051.21518-8-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170907224051.21518-1-richard.henderson@linaro.org>", "References": "<20170907224051.21518-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::235", "Subject": "[Qemu-devel] [PULL 07/23] tcg/s390: Use constant pool for movi", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Richard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nSplit out maybe_out_small_movi for use with other operations\nthat want to add to the constant pool.\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n include/elf.h | 3 +-\n tcg/s390/tcg-target.h | 1 +\n tcg/s390/tcg-target.inc.c | 130 +++++++++++++++++++++++++++-------------------\n 3 files changed, 80 insertions(+), 54 deletions(-)", "diff": "diff --git a/include/elf.h b/include/elf.h\nindex cd51434877..e8a515ce3d 100644\n--- a/include/elf.h\n+++ b/include/elf.h\n@@ -942,8 +942,9 @@ typedef struct {\n #define R_390_TLS_DTPOFF\t55\t/* Offset in TLS block. */\n #define R_390_TLS_TPOFF\t\t56\t/* Negate offset in static TLS\n block. */\n+#define R_390_20 57\n /* Keep this the last entry. */\n-#define R_390_NUM\t57\n+#define R_390_NUM 58\n \n /* x86-64 relocation types */\n #define R_X86_64_NONE\t\t0\t/* No reloc */\ndiff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h\nindex 9c9c8cd464..6f2b06a7d1 100644\n--- a/tcg/s390/tcg-target.h\n+++ b/tcg/s390/tcg-target.h\n@@ -158,5 +158,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,\n #ifdef CONFIG_SOFTMMU\n #define TCG_TARGET_NEED_LDST_LABELS\n #endif\n+#define TCG_TARGET_NEED_POOL_LABELS\n \n #endif\ndiff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c\nindex 59c0da0922..29b77ff67f 100644\n--- a/tcg/s390/tcg-target.inc.c\n+++ b/tcg/s390/tcg-target.inc.c\n@@ -29,6 +29,7 @@\n #error \"unsupported code generation mode\"\n #endif\n \n+#include \"tcg-pool.inc.c\"\n #include \"elf.h\"\n \n /* ??? The translation blocks produced by TCG are generally small enough to\n@@ -361,6 +362,7 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type,\n intptr_t value, intptr_t addend)\n {\n intptr_t pcrel2;\n+ uint32_t old;\n \n value += addend;\n pcrel2 = (tcg_insn_unit *)value - code_ptr;\n@@ -374,6 +376,12 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type,\n assert(pcrel2 == (int32_t)pcrel2);\n tcg_patch32(code_ptr, pcrel2);\n break;\n+ case R_390_20:\n+ assert(value == sextract64(value, 0, 20));\n+ old = *(uint32_t *)code_ptr & 0xf00000ff;\n+ old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4);\n+ tcg_patch32(code_ptr, old);\n+ break;\n default:\n g_assert_not_reached();\n }\n@@ -562,14 +570,16 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)\n }\n }\n \n-/* load a register with an immediate value */\n-static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,\n- tcg_target_long sval, bool in_prologue)\n-{\n- static const S390Opcode lli_insns[4] = {\n- RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH\n- };\n+static const S390Opcode lli_insns[4] = {\n+ RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH\n+};\n+static const S390Opcode ii_insns[4] = {\n+ RI_IILL, RI_IILH, RI_IIHL, RI_IIHH\n+};\n \n+static bool maybe_out_small_movi(TCGContext *s, TCGType type,\n+ TCGReg ret, tcg_target_long sval)\n+{\n tcg_target_ulong uval = sval;\n int i;\n \n@@ -581,17 +591,37 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,\n /* Try all 32-bit insns that can load it in one go. */\n if (sval >= -0x8000 && sval < 0x8000) {\n tcg_out_insn(s, RI, LGHI, ret, sval);\n- return;\n+ return true;\n }\n \n for (i = 0; i < 4; i++) {\n tcg_target_long mask = 0xffffull << i*16;\n if ((uval & mask) == uval) {\n tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i*16);\n- return;\n+ return true;\n }\n }\n \n+ return false;\n+}\n+\n+/* load a register with an immediate value */\n+static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,\n+ tcg_target_long sval, bool in_prologue)\n+{\n+ tcg_target_ulong uval;\n+\n+ /* Try all 32-bit insns that can load it in one go. */\n+ if (maybe_out_small_movi(s, type, ret, sval)) {\n+ return;\n+ }\n+\n+ uval = sval;\n+ if (type == TCG_TYPE_I32) {\n+ uval = (uint32_t)sval;\n+ sval = (int32_t)sval;\n+ }\n+\n /* Try all 48-bit insns that can load it in one go. */\n if (s390_facilities & FACILITY_EXT_IMM) {\n if (sval == (int32_t)sval) {\n@@ -603,7 +633,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,\n return;\n }\n if ((uval & 0xffffffff) == 0) {\n- tcg_out_insn(s, RIL, LLIHF, ret, uval >> 31 >> 1);\n+ tcg_out_insn(s, RIL, LLIHF, ret, uval >> 32);\n return;\n }\n }\n@@ -626,55 +656,44 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,\n }\n }\n \n- /* If extended immediates are not present, then we may have to issue\n- several instructions to load the low 32 bits. */\n- if (!(s390_facilities & FACILITY_EXT_IMM)) {\n- /* A 32-bit unsigned value can be loaded in 2 insns. And given\n- that the lli_insns loop above did not succeed, we know that\n- both insns are required. */\n- if (uval <= 0xffffffff) {\n- tcg_out_insn(s, RI, LLILL, ret, uval);\n- tcg_out_insn(s, RI, IILH, ret, uval >> 16);\n- return;\n- }\n+ /* A 32-bit unsigned value can be loaded in 2 insns. And given\n+ that LLILL, LLIHL, LLILF above did not succeed, we know that\n+ both insns are required. */\n+ if (uval <= 0xffffffff) {\n+ tcg_out_insn(s, RI, LLILL, ret, uval);\n+ tcg_out_insn(s, RI, IILH, ret, uval >> 16);\n+ return;\n+ }\n \n- /* If all high bits are set, the value can be loaded in 2 or 3 insns.\n- We first want to make sure that all the high bits get set. With\n- luck the low 16-bits can be considered negative to perform that for\n- free, otherwise we load an explicit -1. */\n- if (sval >> 31 >> 1 == -1) {\n- if (uval & 0x8000) {\n- tcg_out_insn(s, RI, LGHI, ret, uval);\n- } else {\n- tcg_out_insn(s, RI, LGHI, ret, -1);\n- tcg_out_insn(s, RI, IILL, ret, uval);\n- }\n- tcg_out_insn(s, RI, IILH, ret, uval >> 16);\n- return;\n+ /* When allowed, stuff it in the constant pool. */\n+ if (!in_prologue) {\n+ if (USE_REG_TB) {\n+ tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0);\n+ new_pool_label(s, sval, R_390_20, s->code_ptr - 2,\n+ -(intptr_t)s->code_gen_ptr);\n+ } else {\n+ tcg_out_insn(s, RIL, LGRL, ret, 0);\n+ new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2);\n }\n+ return;\n }\n \n- /* If we get here, both the high and low parts have non-zero bits. */\n-\n- /* Recurse to load the lower 32-bits. */\n- tcg_out_movi(s, TCG_TYPE_I64, ret, uval & 0xffffffff);\n-\n- /* Insert data into the high 32-bits. */\n- uval = uval >> 31 >> 1;\n+ /* What's left is for the prologue, loading GUEST_BASE, and because\n+ it failed to match above, is known to be a full 64-bit quantity.\n+ We could try more than this, but it probably wouldn't pay off. */\n if (s390_facilities & FACILITY_EXT_IMM) {\n- if (uval < 0x10000) {\n- tcg_out_insn(s, RI, IIHL, ret, uval);\n- } else if ((uval & 0xffff) == 0) {\n- tcg_out_insn(s, RI, IIHH, ret, uval >> 16);\n- } else {\n- tcg_out_insn(s, RIL, IIHF, ret, uval);\n- }\n+ tcg_out_insn(s, RIL, LLILF, ret, uval);\n+ tcg_out_insn(s, RIL, IIHF, ret, uval >> 32);\n } else {\n- if (uval & 0xffff) {\n- tcg_out_insn(s, RI, IIHL, ret, uval);\n- }\n- if (uval & 0xffff0000) {\n- tcg_out_insn(s, RI, IIHH, ret, uval >> 16);\n+ const S390Opcode *insns = lli_insns;\n+ int i;\n+\n+ for (i = 0; i < 4; i++) {\n+ uint16_t part = uval >> (16 * i);\n+ if (part) {\n+ tcg_out_insn_RI(s, insns[i], ret, part);\n+ insns = ii_insns;\n+ }\n }\n }\n }\n@@ -2573,6 +2592,11 @@ static void tcg_target_qemu_prologue(TCGContext *s)\n tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14);\n }\n \n+static void tcg_out_nop_fill(tcg_insn_unit *p, int count)\n+{\n+ memset(p, 0x07, count * sizeof(tcg_insn_unit));\n+}\n+\n typedef struct {\n DebugFrameHeader h;\n uint8_t fde_def_cfa[4];\n", "prefixes": [ "PULL", "07/23" ] }