Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.2/patches/811193/?format=api
{ "id": 811193, "url": "http://patchwork.ozlabs.org/api/1.2/patches/811193/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-11-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170907224051.21518-11-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-07T22:40:38", "name": "[PULL,10/23] tcg/s390: Use constant pool for xori", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "506f8c75b4d371ef9dbf85a1f3507ba5d1cbca6d", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-11-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2073, "url": "http://patchwork.ozlabs.org/api/1.2/series/2073/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2073", "date": "2017-09-07T22:40:28", "name": "[PULL,01/23] tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2073/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811193/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811193/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"PIKpuhUK\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpFnj1mgSz9sCZ\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 08:42:17 +1000 (AEST)", "from localhost ([::1]:42518 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dq5V1-0003Bn-7w\n\tfor incoming@patchwork.ozlabs.org; Thu, 07 Sep 2017 18:42:15 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:52153)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq5U3-000369-GA\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:20 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq5Ty-0008DF-Jc\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:15 -0400", "from mail-pg0-x22c.google.com ([2607:f8b0:400e:c05::22c]:37895)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dq5Ty-0008C0-BN\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:10 -0400", "by mail-pg0-x22c.google.com with SMTP id v66so1788427pgb.5\n\tfor <qemu-devel@nongnu.org>; Thu, 07 Sep 2017 15:41:10 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\th19sm770678pfh.142.2017.09.07.15.41.07\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 07 Sep 2017 15:41:08 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=oyI5YSLX1e92RjCHfsEWw9AulBFo8RWIJPmlBultFFM=;\n\tb=PIKpuhUKOZHlwiaDmyMEaOKOpsvHB8dTCxeqBlty/hWy0tSU885F+wlpuulnFDmNvn\n\t/jV6zg1WsTpSQ3+070mcpttW6nkPMDs8Z2a8Hai3gs+W4Ie1UOMtFPKrxfad3lCSOgr7\n\txYDanSt5p2QhhSMlMhLLUJ7J9dMRkLwjSj3E8=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=oyI5YSLX1e92RjCHfsEWw9AulBFo8RWIJPmlBultFFM=;\n\tb=OdrnqWCcJLaQMstqRtVY/zE8z5hIRIMXYNa/W7ouID4oGGaXDW523HPp1ddgFbyjh2\n\t7CRTwKPrYfW5RgEF/zFHMmMgbMeb4O11sEnqVsMmSToRKb9CEztj/erBlzkrcixAHxXT\n\tmMar1pgNIw0zDSZPiz0uMnODl741I4RwKy0hAACvTJ/yHnvopX74VxqEGVoQzV49NVTI\n\tqB0oAgknqlIPFcxBJmtlNp7EC7UE0ee0lV8JqjTTFmIDzS5vyQ/bEr5oCcVh95Nftyl0\n\t7Q3ZcPIuNvDQY4O6QAqeNs6aSWHSLe4PO86r/o5Y0W3a5uRQKDKqLQ6nW3caNvOI5gwP\n\tNwgA==", "X-Gm-Message-State": "AHPjjUgh45D+sb9OhxiTLzMk6SyXvUDlPt2VskJ0JK75PzsCVNyNqYSM\n\t+4J+3Cq/al4yX8L7FvSffg==", "X-Google-Smtp-Source": "ADKCNb7+HSU0Xs3a9D0YfO+yKlMhCWAeRIK/U6R0fSNsABv0LeV6c3l0XURlFJApHd6Q874iGaDvNw==", "X-Received": "by 10.99.181.23 with SMTP id y23mr934634pge.191.1504824069009;\n\tThu, 07 Sep 2017 15:41:09 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Thu, 7 Sep 2017 15:40:38 -0700", "Message-Id": "<20170907224051.21518-11-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170907224051.21518-1-richard.henderson@linaro.org>", "References": "<20170907224051.21518-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::22c", "Subject": "[Qemu-devel] [PULL 10/23] tcg/s390: Use constant pool for xori", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Richard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n tcg/s390/tcg-target.inc.c | 77 ++++++++++++++++++++++++-----------------------\n 1 file changed, 40 insertions(+), 37 deletions(-)", "diff": "diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c\nindex 83fac71c31..b0b34fa5ab 100644\n--- a/tcg/s390/tcg-target.inc.c\n+++ b/tcg/s390/tcg-target.inc.c\n@@ -39,11 +39,9 @@\n \n #define TCG_CT_CONST_S16 0x100\n #define TCG_CT_CONST_S32 0x200\n-#define TCG_CT_CONST_NN16 0x400\n-#define TCG_CT_CONST_NN32 0x800\n-#define TCG_CT_CONST_U31 0x1000\n-#define TCG_CT_CONST_S33 0x2000\n-#define TCG_CT_CONST_ZERO 0x4000\n+#define TCG_CT_CONST_U31 0x400\n+#define TCG_CT_CONST_S33 0x800\n+#define TCG_CT_CONST_ZERO 0x1000\n \n /* Several places within the instruction set 0 means \"no register\"\n rather than TCG_REG_R0. */\n@@ -234,6 +232,7 @@ typedef enum S390Opcode {\n RXY_STRVG = 0xe32f,\n RXY_STRVH = 0xe33f,\n RXY_STY = 0xe350,\n+ RXY_XG = 0xe382,\n \n RX_A = 0x5a,\n RX_C = 0x59,\n@@ -424,12 +423,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n case 'J':\n ct->ct |= TCG_CT_CONST_S32;\n break;\n- case 'N':\n- ct->ct |= TCG_CT_CONST_NN16;\n- break;\n- case 'M':\n- ct->ct |= TCG_CT_CONST_NN32;\n- break;\n case 'C':\n /* ??? We have no insight here into whether the comparison is\n signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit\n@@ -474,10 +467,6 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,\n return val == (int32_t)val;\n } else if (ct & TCG_CT_CONST_S33) {\n return val >= -0xffffffffll && val <= 0xffffffffll;\n- } else if (ct & TCG_CT_CONST_NN16) {\n- return !(val < 0 && val == (int16_t)val);\n- } else if (ct & TCG_CT_CONST_NN32) {\n- return !(val < 0 && val == (int32_t)val);\n } else if (ct & TCG_CT_CONST_U31) {\n return val >= 0 && val <= 0x7fffffff;\n } else if (ct & TCG_CT_CONST_ZERO) {\n@@ -1062,14 +1051,40 @@ static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)\n }\n }\n \n-static void tgen64_xori(TCGContext *s, TCGReg dest, tcg_target_ulong val)\n+static void tgen_xori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)\n {\n- /* Perform the xor by parts. */\n- if (val & 0xffffffff) {\n- tcg_out_insn(s, RIL, XILF, dest, val);\n+ /* Try all 48-bit insns that can perform it in one go. */\n+ if (s390_facilities & FACILITY_EXT_IMM) {\n+ if ((val & 0xffffffff00000000ull) == 0) {\n+ tcg_out_insn(s, RIL, XILF, dest, val);\n+ return;\n+ }\n+ if ((val & 0x00000000ffffffffull) == 0) {\n+ tcg_out_insn(s, RIL, XIHF, dest, val >> 32);\n+ return;\n+ }\n }\n- if (val > 0xffffffff) {\n- tcg_out_insn(s, RIL, XIHF, dest, val >> 31 >> 1);\n+\n+ /* Use the constant pool if USE_REG_TB, but not for small constants. */\n+ if (maybe_out_small_movi(s, type, TCG_TMP0, val)) {\n+ if (type == TCG_TYPE_I32) {\n+ tcg_out_insn(s, RR, XR, dest, TCG_TMP0);\n+ } else {\n+ tcg_out_insn(s, RRE, XGR, dest, TCG_TMP0);\n+ }\n+ } else if (USE_REG_TB) {\n+ tcg_out_insn(s, RXY, XG, dest, TCG_REG_TB, TCG_REG_NONE, 0);\n+ new_pool_label(s, val, R_390_20, s->code_ptr - 2,\n+ -(intptr_t)s->code_gen_ptr);\n+ } else {\n+ /* Perform the xor by parts. */\n+ tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM);\n+ if (val & 0xffffffff) {\n+ tcg_out_insn(s, RIL, XILF, dest, val);\n+ }\n+ if (val > 0xffffffff) {\n+ tcg_out_insn(s, RIL, XIHF, dest, val >> 32);\n+ }\n }\n }\n \n@@ -1889,7 +1904,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,\n a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];\n if (const_args[2]) {\n tcg_out_mov(s, TCG_TYPE_I32, a0, a1);\n- tgen64_xori(s, a0, a2);\n+ tgen_xori(s, TCG_TYPE_I32, a0, a2);\n } else if (a0 == a1) {\n tcg_out_insn(s, RR, XR, args[0], args[2]);\n } else {\n@@ -2121,7 +2136,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,\n a0 = args[0], a1 = args[1], a2 = args[2];\n if (const_args[2]) {\n tcg_out_mov(s, TCG_TYPE_I64, a0, a1);\n- tgen64_xori(s, a0, a2);\n+ tgen_xori(s, TCG_TYPE_I64, a0, a2);\n } else if (a0 == a1) {\n tcg_out_insn(s, RRE, XGR, a0, a2);\n } else {\n@@ -2313,12 +2328,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n static const TCGTargetOpDef r_rC = { .args_ct_str = { \"r\", \"rC\" } };\n static const TCGTargetOpDef r_rZ = { .args_ct_str = { \"r\", \"rZ\" } };\n static const TCGTargetOpDef r_r_ri = { .args_ct_str = { \"r\", \"r\", \"ri\" } };\n- static const TCGTargetOpDef r_r_rM = { .args_ct_str = { \"r\", \"r\", \"rM\" } };\n- static const TCGTargetOpDef r_0_r = { .args_ct_str = { \"r\", \"0\", \"r\" } };\n static const TCGTargetOpDef r_0_ri = { .args_ct_str = { \"r\", \"0\", \"ri\" } };\n static const TCGTargetOpDef r_0_rI = { .args_ct_str = { \"r\", \"0\", \"rI\" } };\n static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { \"r\", \"0\", \"rJ\" } };\n- static const TCGTargetOpDef r_0_rM = { .args_ct_str = { \"r\", \"0\", \"rM\" } };\n static const TCGTargetOpDef a2_r\n = { .args_ct_str = { \"r\", \"r\", \"0\", \"1\", \"r\", \"r\" } };\n static const TCGTargetOpDef a2_ri\n@@ -2360,6 +2372,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n case INDEX_op_and_i64:\n case INDEX_op_or_i32:\n case INDEX_op_or_i64:\n+ case INDEX_op_xor_i32:\n+ case INDEX_op_xor_i64:\n return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);\n \n case INDEX_op_mul_i32:\n@@ -2370,17 +2384,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n case INDEX_op_mul_i64:\n return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);\n \n- case INDEX_op_xor_i32:\n- /* Without EXT_IMM, no immediates are supported. Otherwise,\n- rejecting certain negative ranges leads to smaller code. */\n- return (s390_facilities & FACILITY_EXT_IMM\n- ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri)\n- : &r_0_r);\n- case INDEX_op_xor_i64:\n- return (s390_facilities & FACILITY_EXT_IMM\n- ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_0_rM)\n- : &r_0_r);\n-\n case INDEX_op_shl_i32:\n case INDEX_op_shr_i32:\n case INDEX_op_sar_i32:\n", "prefixes": [ "PULL", "10/23" ] }