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GET /api/1.2/patches/811192/?format=api
{ "id": 811192, "url": "http://patchwork.ozlabs.org/api/1.2/patches/811192/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-6-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170907224051.21518-6-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-07T22:40:33", "name": "[PULL,05/23] tcg/s390: Introduce TCG_REG_TB", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8b6ff4d20ab6803d4cd8b3928a3b20f84731beb5", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-6-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2073, "url": "http://patchwork.ozlabs.org/api/1.2/series/2073/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2073", "date": "2017-09-07T22:40:28", "name": "[PULL,01/23] tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2073/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811192/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811192/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"MilTOnt5\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpFnV1hlTz9sDB\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 08:42:06 +1000 (AEST)", "from localhost ([::1]:42517 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dq5Uq-00035t-7y\n\tfor incoming@patchwork.ozlabs.org; Thu, 07 Sep 2017 18:42:04 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:52010)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq5Tv-0002yJ-PS\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:13 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq5Tq-000859-RW\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:07 -0400", "from mail-pg0-x22a.google.com ([2607:f8b0:400e:c05::22a]:33213)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dq5Tq-00084W-J7\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:02 -0400", "by mail-pg0-x22a.google.com with SMTP id t3so1832996pgt.0\n\tfor <qemu-devel@nongnu.org>; Thu, 07 Sep 2017 15:41:02 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\th19sm770678pfh.142.2017.09.07.15.41.00\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 07 Sep 2017 15:41:00 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=AsoJlWiUc2xIlOEw/Aqp10soH/fjgwUnxjIzF/rW2gY=;\n\tb=MilTOnt5bR0VOkATf0S31FOyrhcAg563hoBcomNSz7fPMeVCo632x9OfhF1sKsHtHK\n\thOLpjeS6Y83B9BUvVefe7eR3/hoKTIa1QR8GY3uRSMYQHoQFmP1exzeEwByagYLIvZ8E\n\txLvdKUbCzUR+tYyrDc/cZHf1EsZ/HgFjqsfvU=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=AsoJlWiUc2xIlOEw/Aqp10soH/fjgwUnxjIzF/rW2gY=;\n\tb=dmRuSurYUcXHYVDHzqrPuciStcnpeL+rr6kyveY7dQJhuy1uzaL6D3doTKTiUJkT4g\n\t6hMmKqZ1DxveqLNjuUpuGORGeudxc0vXDO6el2zYix+EiMcMgQoO4G/pl740BF83yaaK\n\t4uOp0MGIZh6HK051aFBetUwtJIV00FSkgEGBD+SUVniJ281PIMA32otvmkS6ullu6RSL\n\tXrstGZtfeOAO5hV4iFhYEmZNqb6n3hdOyN1Ok2QNa1Fmw542uTcd09/Gnylq04c1XBCe\n\t7uNYj4FhD5uYkbeu50J9Swzen88SP3FaGO2bEJ7EBUyNE7Q2lAgpaQo3FAQi1SrZ21+A\n\tAkWg==", "X-Gm-Message-State": "AHPjjUjiRJzIIov4ozjTUNJO2NVMLMi2mi0wQ0uNRfeP9JqeBex5EPH9\n\thiT9KvlUV+tFn5RCSx5o+A==", "X-Google-Smtp-Source": "ADKCNb5aCksKsO78EiindBGqssFd6nR9200pM+/zUiK0wZshWGqYnBqNQZchTfjYW4X7tdcdb8MapA==", "X-Received": "by 10.99.98.131 with SMTP id w125mr977385pgb.214.1504824061249; \n\tThu, 07 Sep 2017 15:41:01 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Thu, 7 Sep 2017 15:40:33 -0700", "Message-Id": "<20170907224051.21518-6-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170907224051.21518-1-richard.henderson@linaro.org>", "References": "<20170907224051.21518-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::22a", "Subject": "[Qemu-devel] [PULL 05/23] tcg/s390: Introduce TCG_REG_TB", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Richard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n tcg/s390/tcg-target.h | 2 +-\n tcg/s390/tcg-target.inc.c | 71 +++++++++++++++++++++++++++++++++++++++--------\n 2 files changed, 61 insertions(+), 12 deletions(-)", "diff": "diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h\nindex 52010c30cb..9c9c8cd464 100644\n--- a/tcg/s390/tcg-target.h\n+++ b/tcg/s390/tcg-target.h\n@@ -95,7 +95,7 @@ extern uint64_t s390_facilities;\n #define TCG_TARGET_HAS_extrl_i64_i32 0\n #define TCG_TARGET_HAS_extrh_i64_i32 0\n #define TCG_TARGET_HAS_goto_ptr 1\n-#define TCG_TARGET_HAS_direct_jump 1\n+#define TCG_TARGET_HAS_direct_jump (s390_facilities & FACILITY_GEN_INST_EXT)\n \n #define TCG_TARGET_HAS_div2_i64 1\n #define TCG_TARGET_HAS_rot_i64 1\ndiff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c\nindex ee0dff995a..e007586315 100644\n--- a/tcg/s390/tcg-target.inc.c\n+++ b/tcg/s390/tcg-target.inc.c\n@@ -51,6 +51,12 @@\n /* A scratch register that may be be used throughout the backend. */\n #define TCG_TMP0 TCG_REG_R1\n \n+/* A scratch register that holds a pointer to the beginning of the TB.\n+ We don't need this when we have pc-relative loads with the general\n+ instructions extension facility. */\n+#define TCG_REG_TB TCG_REG_R12\n+#define USE_REG_TB (!(s390_facilities & FACILITY_GEN_INST_EXT))\n+\n #ifndef CONFIG_SOFTMMU\n #define TCG_GUEST_BASE_REG TCG_REG_R13\n #endif\n@@ -556,8 +562,8 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)\n }\n \n /* load a register with an immediate value */\n-static void tcg_out_movi(TCGContext *s, TCGType type,\n- TCGReg ret, tcg_target_long sval)\n+static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,\n+ tcg_target_long sval, bool in_prologue)\n {\n static const S390Opcode lli_insns[4] = {\n RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH\n@@ -601,13 +607,22 @@ static void tcg_out_movi(TCGContext *s, TCGType type,\n }\n }\n \n- /* Try for PC-relative address load. */\n+ /* Try for PC-relative address load. For odd addresses,\n+ attempt to use an offset from the start of the TB. */\n if ((sval & 1) == 0) {\n ptrdiff_t off = tcg_pcrel_diff(s, (void *)sval) >> 1;\n if (off == (int32_t)off) {\n tcg_out_insn(s, RIL, LARL, ret, off);\n return;\n }\n+ } else if (USE_REG_TB && !in_prologue) {\n+ ptrdiff_t off = sval - (uintptr_t)s->code_gen_ptr;\n+ if (off == sextract64(off, 0, 20)) {\n+ /* This is certain to be an address within TB, and therefore\n+ OFF will be negative; don't try RX_LA. */\n+ tcg_out_insn(s, RXY, LAY, ret, TCG_REG_TB, TCG_REG_NONE, off);\n+ return;\n+ }\n }\n \n /* If extended immediates are not present, then we may have to issue\n@@ -663,6 +678,11 @@ static void tcg_out_movi(TCGContext *s, TCGType type,\n }\n }\n \n+static void tcg_out_movi(TCGContext *s, TCGType type,\n+ TCGReg ret, tcg_target_long sval)\n+{\n+ tcg_out_movi_int(s, type, ret, sval, false);\n+}\n \n /* Emit a load/store type instruction. Inputs are:\n DATA: The register to be loaded or stored.\n@@ -739,6 +759,13 @@ static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, void *abs)\n return;\n }\n }\n+ if (USE_REG_TB) {\n+ ptrdiff_t disp = abs - (void *)s->code_gen_ptr;\n+ if (disp == sextract64(disp, 0, 20)) {\n+ tcg_out_ld(s, type, dest, TCG_REG_TB, disp);\n+ return;\n+ }\n+ }\n \n tcg_out_movi(s, TCG_TYPE_PTR, dest, addr & ~0xffff);\n tcg_out_ld(s, type, dest, dest, addr & 0xffff);\n@@ -1690,6 +1717,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,\n break;\n \n case INDEX_op_goto_tb:\n+ a0 = args[0];\n if (s->tb_jmp_insn_offset) {\n /* branch displacement must be aligned for atomic patching;\n * see if we need to add extra nop before branch\n@@ -1697,21 +1725,34 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,\n if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) {\n tcg_out16(s, NOP);\n }\n+ tcg_debug_assert(!USE_REG_TB);\n tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4));\n- s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);\n+ s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);\n s->code_ptr += 2;\n } else {\n- /* load address stored at s->tb_jmp_target_addr + args[0] */\n- tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_TMP0,\n- s->tb_jmp_target_addr + args[0]);\n+ /* load address stored at s->tb_jmp_target_addr + a0 */\n+ tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB,\n+ s->tb_jmp_target_addr + a0);\n /* and go there */\n- tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_TMP0);\n+ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB);\n+ }\n+ s->tb_jmp_reset_offset[a0] = tcg_current_code_size(s);\n+\n+ /* For the unlinked path of goto_tb, we need to reset\n+ TCG_REG_TB to the beginning of this TB. */\n+ if (USE_REG_TB) {\n+ int ofs = -tcg_current_code_size(s);\n+ assert(ofs == (int16_t)ofs);\n+ tcg_out_insn(s, RI, AGHI, TCG_REG_TB, ofs);\n }\n- s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);\n break;\n \n case INDEX_op_goto_ptr:\n- tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, args[0]);\n+ a0 = args[0];\n+ if (USE_REG_TB) {\n+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0);\n+ }\n+ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0);\n break;\n \n OP_32_64(ld8u):\n@@ -2476,6 +2517,9 @@ static void tcg_target_init(TCGContext *s)\n /* XXX many insns can't be used with R0, so we better avoid it for now */\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);\n+ if (USE_REG_TB) {\n+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB);\n+ }\n }\n \n #define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \\\n@@ -2496,12 +2540,17 @@ static void tcg_target_qemu_prologue(TCGContext *s)\n \n #ifndef CONFIG_SOFTMMU\n if (guest_base >= 0x80000) {\n- tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);\n+ tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);\n tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);\n }\n #endif\n \n tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);\n+ if (USE_REG_TB) {\n+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB,\n+ tcg_target_call_iarg_regs[1]);\n+ }\n+\n /* br %r3 (go to TB) */\n tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]);\n \n", "prefixes": [ "PULL", "05/23" ] }