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GET /api/1.2/patches/810709/?format=api
{ "id": 810709, "url": "http://patchwork.ozlabs.org/api/1.2/patches/810709/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-19-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906160612.22769-19-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T16:05:58", "name": "[PULL,18/32] target/arm: [tcg] Port to tb_start", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "cb30b05bd2c7a234bcc47cb2a967187df5cfd069", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-19-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1847, "url": "http://patchwork.ozlabs.org/api/1.2/series/1847/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847", "date": "2017-09-06T16:05:41", "name": "[PULL,01/32] tcg: Add generic DISAS_NORETURN", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1847/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810709/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810709/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"kWQ1BaLl\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnTKB4bVmz9s7F\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 02:18:22 +1000 (AEST)", "from localhost ([::1]:37004 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpd1w-0001Lu-Jx\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 12:18:20 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:41776)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqf-0000DA-UX\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:48 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqe-0002T5-LT\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:41 -0400", "from mail-pg0-x235.google.com ([2607:f8b0:400e:c05::235]:38905)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpcqe-0002Ss-Ck\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:40 -0400", "by mail-pg0-x235.google.com with SMTP id v66so15891614pgb.5\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 09:06:40 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tt65sm262863pfk.59.2017.09.06.09.06.37\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 09:06:38 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=RBpPMCfof5ruZ/5aJuF/nc5V26lehfTdsSHm+aLUbHg=;\n\tb=kWQ1BaLlERsbz7Ey1Y9RJALRZYvkSSw/YWk/PdOLQq4BeP9iw9AxLJ3A7om0Cz/aMz\n\thtYwoK20j8eNrXJVH8zMP0WRc61/pyc5dZy8JwWcHRBnnBIIjHxXkwOvblB5UzltHHE+\n\tkQnD5rXGRoTtmRw05iOSuch36gEAgDSPjnBrE=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=RBpPMCfof5ruZ/5aJuF/nc5V26lehfTdsSHm+aLUbHg=;\n\tb=qnSQ6ZLd/0GC4wN2RUy5KaiTwXnqy0c7A5nZm9IGJU+S5yfTRccnW4btKTUkbjytQe\n\tweWsohKNd4gzcN5QyakfJIXnA5STS1krj9EY+Vnxru11VLo0uQxDXJ0NCAMzSR9aAy+p\n\tzbtGt3cAmFC6W1M5wWo+95oONxIxuka3GKUZqQruEODt7tFRyKhZIDe89Ypyd71ng8Xx\n\tJO3/c4OD6x37I3dnbKx/n1u1YSHfx6m0fyN1qmfE1l70VMHBTti/ubHkdeZ/gEl8csXL\n\tPgBBJnARscHB4zcN6Q+R0iKP+kQEeeLVRyRX1anr2ffKBvpcNpuPMLDyHaPi0aMNTVNh\n\tNYew==", "X-Gm-Message-State": "AHPjjUhv8u6oVK7kYC1TvOTjsE5/3abGC98SYP6xbOQesOu4N+pQDToc\n\tp26kiuEQ+UvgVWBOHGUrGA==", "X-Google-Smtp-Source": "ADKCNb7EdBDftqeTlNT6qU2yshBr6Fod5ttKsPvQ9S9nFhBAA+Md7WRw8mdEWiULxVO1X2xzvfIQoQ==", "X-Received": "by 10.84.130.42 with SMTP id 39mr9090288plc.239.1504713999160;\n\tWed, 06 Sep 2017 09:06:39 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 09:05:58 -0700", "Message-Id": "<20170906160612.22769-19-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906160612.22769-1-richard.henderson@linaro.org>", "References": "<20170906160612.22769-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::235", "Subject": "[Qemu-devel] [PULL 18/32] target/arm: [tcg] Port to tb_start", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t<vilanova@ac.upc.edu>, \tRichard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Lluís Vilanova <vilanova@ac.upc.edu>\n\nIncrementally paves the way towards using the generic instruction translation\nloop.\n\nSigned-off-by: Lluís Vilanova <vilanova@ac.upc.edu>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nReviewed-by: Alex Benneé <alex.benee@linaro.org>\nMessage-Id: <150002364681.22386.1701754996184325808.stgit@frigg.lan>\n[rth: Adjust for tb_start interface change.]\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/arm/translate.c | 82 +++++++++++++++++++++++++++-----------------------\n 1 file changed, 44 insertions(+), 38 deletions(-)", "diff": "diff --git a/target/arm/translate.c b/target/arm/translate.c\nindex a95c183cee..3138a23e0c 100644\n--- a/target/arm/translate.c\n+++ b/target/arm/translate.c\n@@ -11893,6 +11893,49 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase,\n return max_insns;\n }\n \n+static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)\n+{\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n+\n+ /* A note on handling of the condexec (IT) bits:\n+ *\n+ * We want to avoid the overhead of having to write the updated condexec\n+ * bits back to the CPUARMState for every instruction in an IT block. So:\n+ * (1) if the condexec bits are not already zero then we write\n+ * zero back into the CPUARMState now. This avoids complications trying\n+ * to do it at the end of the block. (For example if we don't do this\n+ * it's hard to identify whether we can safely skip writing condexec\n+ * at the end of the TB, which we definitely want to do for the case\n+ * where a TB doesn't do anything with the IT state at all.)\n+ * (2) if we are going to leave the TB then we call gen_set_condexec()\n+ * which will write the correct value into CPUARMState if zero is wrong.\n+ * This is done both for leaving the TB at the end, and for leaving\n+ * it because of an exception we know will happen, which is done in\n+ * gen_exception_insn(). The latter is necessary because we need to\n+ * leave the TB with the PC/IT state just prior to execution of the\n+ * instruction which caused the exception.\n+ * (3) if we leave the TB unexpectedly (eg a data abort on a load)\n+ * then the CPUARMState will be wrong and we need to reset it.\n+ * This is handled in the same way as restoration of the\n+ * PC in these situations; we save the value of the condexec bits\n+ * for each PC via tcg_gen_insn_start(), and restore_state_to_opc()\n+ * then uses this to restore them after an exception.\n+ *\n+ * Note that there are no instructions which can read the condexec\n+ * bits, and none which can write non-static values to them, so\n+ * we don't need to care about whether CPUARMState is correct in the\n+ * middle of a TB.\n+ */\n+\n+ /* Reset the conditional execution bits immediately. This avoids\n+ complications trying to do it at the end of the block. */\n+ if (dc->condexec_mask || dc->condexec_cond) {\n+ TCGv_i32 tmp = tcg_temp_new_i32();\n+ tcg_gen_movi_i32(tmp, 0);\n+ store_cpu_field(tmp, condexec_bits);\n+ }\n+}\n+\n /* generate intermediate code for basic block 'tb'. */\n void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n {\n@@ -11932,45 +11975,8 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n gen_tb_start(tb);\n \n tcg_clear_temp_count();\n+ arm_tr_tb_start(&dc->base, cs);\n \n- /* A note on handling of the condexec (IT) bits:\n- *\n- * We want to avoid the overhead of having to write the updated condexec\n- * bits back to the CPUARMState for every instruction in an IT block. So:\n- * (1) if the condexec bits are not already zero then we write\n- * zero back into the CPUARMState now. This avoids complications trying\n- * to do it at the end of the block. (For example if we don't do this\n- * it's hard to identify whether we can safely skip writing condexec\n- * at the end of the TB, which we definitely want to do for the case\n- * where a TB doesn't do anything with the IT state at all.)\n- * (2) if we are going to leave the TB then we call gen_set_condexec()\n- * which will write the correct value into CPUARMState if zero is wrong.\n- * This is done both for leaving the TB at the end, and for leaving\n- * it because of an exception we know will happen, which is done in\n- * gen_exception_insn(). The latter is necessary because we need to\n- * leave the TB with the PC/IT state just prior to execution of the\n- * instruction which caused the exception.\n- * (3) if we leave the TB unexpectedly (eg a data abort on a load)\n- * then the CPUARMState will be wrong and we need to reset it.\n- * This is handled in the same way as restoration of the\n- * PC in these situations; we save the value of the condexec bits\n- * for each PC via tcg_gen_insn_start(), and restore_state_to_opc()\n- * then uses this to restore them after an exception.\n- *\n- * Note that there are no instructions which can read the condexec\n- * bits, and none which can write non-static values to them, so\n- * we don't need to care about whether CPUARMState is correct in the\n- * middle of a TB.\n- */\n-\n- /* Reset the conditional execution bits immediately. This avoids\n- complications trying to do it at the end of the block. */\n- if (dc->condexec_mask || dc->condexec_cond)\n- {\n- TCGv_i32 tmp = tcg_temp_new_i32();\n- tcg_gen_movi_i32(tmp, 0);\n- store_cpu_field(tmp, condexec_bits);\n- }\n do {\n dc->base.num_insns++;\n dc->insn_start_idx = tcg_op_buf_count();\n", "prefixes": [ "PULL", "18/32" ] }