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GET /api/1.2/patches/810707/?format=api
{ "id": 810707, "url": "http://patchwork.ozlabs.org/api/1.2/patches/810707/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-15-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906160612.22769-15-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T16:05:54", "name": "[PULL,14/32] target/i386: [tcg] Port to generic translation framework", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "06aa10042ada036d5e303d1245fce0ff06402b0a", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-15-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1847, "url": "http://patchwork.ozlabs.org/api/1.2/series/1847/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847", "date": "2017-09-06T16:05:41", "name": "[PULL,01/32] tcg: Add generic DISAS_NORETURN", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1847/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810707/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810707/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"i9pEc6uj\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnTJn2FQYz9s7c\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 02:18:01 +1000 (AEST)", "from localhost ([::1]:36999 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpd1b-000136-BJ\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 12:17:59 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:41700)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqa-0008W7-J3\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:42 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqZ-0002BM-7u\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:36 -0400", "from mail-pf0-x22c.google.com ([2607:f8b0:400e:c00::22c]:33132)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpcqY-0002A9-Vs\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:35 -0400", "by mail-pf0-x22c.google.com with SMTP id y68so13495970pfd.0\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 09:06:34 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tt65sm262863pfk.59.2017.09.06.09.06.32\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 09:06:32 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=4K6BNYHQcpNHFmj0sguQnGWsFAoO7efRcTcbeP5LdLw=;\n\tb=i9pEc6ujcmxqGr4fwFoufTuOdzbBcEzFM3rz1/cKLG0CVnxt+DNkKuaFUt6CAMZCmi\n\tDy7xn4zZT8EAVzwdp3nZpFboe2P2v9/jutXOm8QFkOds8sIk6IHgsSlGLgw8+qongvrK\n\t07ABZdNGFlWkZYOxbf6Fcw6uwlWsHzOJIUnWw=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=4K6BNYHQcpNHFmj0sguQnGWsFAoO7efRcTcbeP5LdLw=;\n\tb=TNqTv4F13O0ZQijkOFpVFtcIJDHIv+6bn2e2ky8uCWH9myzL3WwYaasAhIgctzwAzF\n\tVnsKtZuyYHpcJ1Ke9SBE/9oRFnfBxt7+FKNM+GSu9bNkJN8bTnYPb2jgdERapn8MOv09\n\tdfAIkR4P98emTf6j5sQ3qLWP+25sKBO5EgPtxx3kbeVFWdtwWqAbqhYvJuOcDCNGy+PS\n\tH6w11+K2ddnVbs+N80vWlwvoNJdiFiPEmXEUQ00harLkxL4vgWebOuZydgl7b40txgzb\n\t0s7s7ooZP+d0Ebs7p32kM4RJ3aIZPJcugxuEFAi29h2WSM/ZEuxfFyA69qgwy2Ko4ua/\n\tREZQ==", "X-Gm-Message-State": "AHPjjUiHvbMDKlewk2TUtbrfRxoedOPJvvFaE2nn+zwzBCvMWzLLDBmH\n\t+k3OMTGm3BIEI8eOn5kCAw==", "X-Google-Smtp-Source": "ADKCNb7Q7cJhbqusd6W9F1bdFca+Brk1NhcAZOwH0jzxCwvoH8VZULjGDOutbjELIgd4naZ0/bw9CQ==", "X-Received": "by 10.99.0.73 with SMTP id 70mr8193748pga.289.1504713993772;\n\tWed, 06 Sep 2017 09:06:33 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 09:05:54 -0700", "Message-Id": "<20170906160612.22769-15-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906160612.22769-1-richard.henderson@linaro.org>", "References": "<20170906160612.22769-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c00::22c", "Subject": "[Qemu-devel] [PULL 14/32] target/i386: [tcg] Port to generic\n\ttranslation framework", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t<vilanova@ac.upc.edu>, \tRichard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Lluís Vilanova <vilanova@ac.upc.edu>\n\nSigned-off-by: Lluís Vilanova <vilanova@ac.upc.edu>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nReviewed-by: Emilio G. Cota <cota@braap.org>\nTested-by: Emilio G. Cota <cota@braap.org>\nMessage-Id: <150002267714.22386.5095442346868988808.stgit@frigg.lan>\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/i386/translate.c | 106 +++++++++---------------------------------------\n 1 file changed, 19 insertions(+), 87 deletions(-)", "diff": "diff --git a/target/i386/translate.c b/target/i386/translate.c\nindex ad4b2735f4..de0c989763 100644\n--- a/target/i386/translate.c\n+++ b/target/i386/translate.c\n@@ -8450,6 +8450,10 @@ static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu,\n return max_insns;\n }\n \n+static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu)\n+{\n+}\n+\n static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n {\n DisasContext *dc = container_of(dcbase, DisasContext, base);\n@@ -8469,7 +8473,7 @@ static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,\n /* The address covered by the breakpoint must be included in\n [tb->pc, tb->pc + tb->size) in order to for it to be\n properly cleared -- thus we increment the PC here so that\n- the logic setting tb->size below does the right thing. */\n+ the generic logic setting tb->size later does the right thing. */\n dc->base.pc_next += 1;\n return true;\n } else {\n@@ -8533,94 +8537,22 @@ static void i386_tr_disas_log(const DisasContextBase *dcbase,\n log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, disas_flags);\n }\n \n-/* generate intermediate code for basic block 'tb'. */\n-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n-{\n- DisasContext dc1, *dc = &dc1;\n- int num_insns;\n- int max_insns;\n-\n- /* generate intermediate code */\n- dc->base.singlestep_enabled = cs->singlestep_enabled;\n- dc->base.tb = tb;\n- dc->base.is_jmp = DISAS_NEXT;\n- dc->base.pc_first = tb->pc;\n- dc->base.pc_next = dc->base.pc_first;\n-\n- max_insns = tb->cflags & CF_COUNT_MASK;\n- if (max_insns == 0) {\n- max_insns = CF_COUNT_MASK;\n- }\n- if (max_insns > TCG_MAX_INSNS) {\n- max_insns = TCG_MAX_INSNS;\n- }\n- max_insns = i386_tr_init_disas_context(&dc->base, cs, max_insns);\n-\n- num_insns = 0;\n- gen_tb_start(tb);\n- for(;;) {\n- i386_tr_insn_start(&dc->base, cs);\n- num_insns++;\n-\n- if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {\n- CPUBreakpoint *bp;\n- QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {\n- if (bp->pc == dc->base.pc_next) {\n- if (i386_tr_breakpoint_check(&dc->base, cs, bp)) {\n- break;\n- }\n- }\n- }\n-\n- if (dc->base.is_jmp == DISAS_NORETURN) {\n- break;\n- }\n- }\n-\n- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {\n- gen_io_start();\n- }\n-\n- i386_tr_translate_insn(&dc->base, cs);\n- /* stop translation if indicated */\n- if (dc->base.is_jmp) {\n- break;\n- }\n- /* if single step mode, we generate only one instruction and\n- generate an exception */\n- if (dc->base.singlestep_enabled) {\n- dc->base.is_jmp = DISAS_TOO_MANY;\n- break;\n- }\n- /* if too long translation, stop generation too */\n- if (tcg_op_buf_full() ||\n- num_insns >= max_insns) {\n- dc->base.is_jmp = DISAS_TOO_MANY;\n- break;\n- }\n- if (singlestep) {\n- dc->base.is_jmp = DISAS_TOO_MANY;\n- break;\n- }\n- }\n- i386_tr_tb_stop(&dc->base, cs);\n- if (tb->cflags & CF_LAST_IO)\n- gen_io_end();\n- gen_tb_end(tb, num_insns);\n+static const TranslatorOps i386_tr_ops = {\n+ .init_disas_context = i386_tr_init_disas_context,\n+ .tb_start = i386_tr_tb_start,\n+ .insn_start = i386_tr_insn_start,\n+ .breakpoint_check = i386_tr_breakpoint_check,\n+ .translate_insn = i386_tr_translate_insn,\n+ .tb_stop = i386_tr_tb_stop,\n+ .disas_log = i386_tr_disas_log,\n+};\n \n- tb->size = dc->base.pc_next - dc->base.pc_first;\n- tb->icount = num_insns;\n+/* generate intermediate code for basic block 'tb'. */\n+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)\n+{\n+ DisasContext dc;\n \n-#ifdef DEBUG_DISAS\n- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)\n- && qemu_log_in_addr_range(dc->base.pc_first)) {\n- qemu_log_lock();\n- qemu_log(\"----------------\\n\");\n- i386_tr_disas_log(&dc->base, cs);\n- qemu_log(\"\\n\");\n- qemu_log_unlock();\n- }\n-#endif\n+ translator_loop(&i386_tr_ops, &dc.base, cpu, tb);\n }\n \n void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb,\n", "prefixes": [ "PULL", "14/32" ] }