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GET /api/1.2/patches/810705/?format=api
{ "id": 810705, "url": "http://patchwork.ozlabs.org/api/1.2/patches/810705/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-8-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906160612.22769-8-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T16:05:47", "name": "[PULL,07/32] target/i386: [tcg] Port to DisasContextBase", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4787374a0cf880d8a95e16cc1ae3bd539a3f1666", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-8-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1847, "url": "http://patchwork.ozlabs.org/api/1.2/series/1847/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847", "date": "2017-09-06T16:05:41", "name": "[PULL,01/32] tcg: Add generic DISAS_NORETURN", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1847/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810705/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810705/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"D5kqiBHk\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnTFz2F8Zz9s7F\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 02:15:35 +1000 (AEST)", "from localhost ([::1]:36989 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpczF-0007R3-8j\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 12:15:33 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:41659)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqX-0008SD-7w\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:39 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqP-0001kY-OJ\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:33 -0400", "from mail-pg0-x22c.google.com ([2607:f8b0:400e:c05::22c]:37870)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpcqP-0001ie-Ew\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:25 -0400", "by mail-pg0-x22c.google.com with SMTP id d8so15974157pgt.4\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 09:06:25 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tt65sm262863pfk.59.2017.09.06.09.06.22\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 09:06:22 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=cXA05z5fG9qfN0kUotbukGjmdFLQPzYcmOBDIAbbPvM=;\n\tb=D5kqiBHk1MHowei7daC310KcVMEG2CuSjqOCPwdaRsaPVYNhKrdNZzA6X0HGMA2UOt\n\tcvaN80pTcem79OD8K1e4vSj5IAysv7aYVUTkNWglSQpLDiM/c1o2wZj2QLLBncfXFvZl\n\t6W9SFjT7HBPqWXA+6oEHt4vbgud2vw/J4ZJcE=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=cXA05z5fG9qfN0kUotbukGjmdFLQPzYcmOBDIAbbPvM=;\n\tb=PppTtlPekJWidrkt27WEAuwUkAk1yG8A2LgkdzMuaek0vZO9xbeWaDxZiTMj3Zcrxq\n\tAb+FYX0gZLNUwQmTKS2NCRptpD8Ky8tsDLswFUTy3o9OR1sJBJS0MNL1glnyhii4XBi2\n\tI+/+qFbtr3D0qEENGMmY9EwlapHYKidJyBICV+9wpJx8CXZ8ZP3AAQH3MTpk9V5l9kS2\n\tGXqNLNlj8DDLE1LiZo5vsYdR5MRXgCKKV7gIzClKKatIUvbmQZaM6As9NMbi9SSFTC0q\n\t37bIaEKJ3MPl7bQqgwdkQbryjylFOxngIQFSZ8e3bb8LghsnM983AhE5t4t4pl+dPdCV\n\tgJuw==", "X-Gm-Message-State": "AHPjjUgjjmEmLl1fMlmc8DLTOoqWPm7UprGjqHwl5zeFYRdizYPEQ84m\n\tOzEBlP0zivKiqncf/fr91A==", "X-Google-Smtp-Source": "ADKCNb7dDu367SwwgxtV6np56U30dIJ3lAb++fLl74idTS9ic7b2tlWU7e+kSTMKYENv+cTtDulT+g==", "X-Received": "by 10.99.110.141 with SMTP id j135mr8396746pgc.242.1504713983821;\n\tWed, 06 Sep 2017 09:06:23 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 09:05:47 -0700", "Message-Id": "<20170906160612.22769-8-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906160612.22769-1-richard.henderson@linaro.org>", "References": "<20170906160612.22769-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::22c", "Subject": "[Qemu-devel] [PULL 07/32] target/i386: [tcg] Port to\n\tDisasContextBase", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t<vilanova@ac.upc.edu>, \tRichard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Lluís Vilanova <vilanova@ac.upc.edu>\n\nIncrementally paves the way towards using the generic instruction translation\nloop.\n\nSigned-off-by: Lluís Vilanova <vilanova@ac.upc.edu>\nReviewed-by: Emilio G. Cota <cota@braap.org>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nReviewed-by: Alex Benneé <alex.benee@linaro.org>\nMessage-Id: <150002098212.22386.17313318023406046314.stgit@frigg.lan>\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/i386/translate.c | 140 ++++++++++++++++++++++++------------------------\n 1 file changed, 69 insertions(+), 71 deletions(-)", "diff": "diff --git a/target/i386/translate.c b/target/i386/translate.c\nindex a0d8788c57..3a3d91c4d7 100644\n--- a/target/i386/translate.c\n+++ b/target/i386/translate.c\n@@ -95,6 +95,8 @@ static int x86_64_hregs;\n #endif\n \n typedef struct DisasContext {\n+ DisasContextBase base;\n+\n /* current insn context */\n int override; /* -1 if no override */\n int prefix;\n@@ -102,8 +104,6 @@ typedef struct DisasContext {\n TCGMemOp dflag;\n target_ulong pc_start;\n target_ulong pc; /* pc = eip + cs_base */\n- int is_jmp; /* 1 = means jump (stop translation), 2 means CPU\n- static state change (stop translation) */\n /* current block context */\n target_ulong cs_base; /* base of CS segment */\n int pe; /* protected mode */\n@@ -124,12 +124,10 @@ typedef struct DisasContext {\n int cpl;\n int iopl;\n int tf; /* TF cpu flag */\n- int singlestep_enabled; /* \"hardware\" single step enabled */\n int jmp_opt; /* use direct block chaining for direct jumps */\n int repz_opt; /* optimize jumps within repz instructions */\n int mem_index; /* select memory access functions */\n uint64_t flags; /* all execution flags */\n- struct TranslationBlock *tb;\n int popl_esp_hack; /* for correct popl with esp base handling */\n int rip_offset; /* only used in x86_64, but left for simplicity */\n int cpuid_features;\n@@ -1119,7 +1117,7 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_port, int ot)\n \n static inline void gen_ins(DisasContext *s, TCGMemOp ot)\n {\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_start();\n }\n gen_string_movl_A0_EDI(s);\n@@ -1134,14 +1132,14 @@ static inline void gen_ins(DisasContext *s, TCGMemOp ot)\n gen_op_movl_T0_Dshift(ot);\n gen_op_add_reg_T0(s->aflag, R_EDI);\n gen_bpt_io(s, cpu_tmp2_i32, ot);\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_end();\n }\n }\n \n static inline void gen_outs(DisasContext *s, TCGMemOp ot)\n {\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_start();\n }\n gen_string_movl_A0_ESI(s);\n@@ -1154,7 +1152,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp ot)\n gen_op_movl_T0_Dshift(ot);\n gen_op_add_reg_T0(s->aflag, R_ESI);\n gen_bpt_io(s, cpu_tmp2_i32, ot);\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_end();\n }\n }\n@@ -2137,7 +2135,7 @@ static inline int insn_const_size(TCGMemOp ot)\n static inline bool use_goto_tb(DisasContext *s, target_ulong pc)\n {\n #ifndef CONFIG_USER_ONLY\n- return (pc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK) ||\n+ return (pc & TARGET_PAGE_MASK) == (s->base.tb->pc & TARGET_PAGE_MASK) ||\n (pc & TARGET_PAGE_MASK) == (s->pc_start & TARGET_PAGE_MASK);\n #else\n return true;\n@@ -2152,8 +2150,8 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)\n /* jump to same page: we can use a direct jump */\n tcg_gen_goto_tb(tb_num);\n gen_jmp_im(eip);\n- tcg_gen_exit_tb((uintptr_t)s->tb + tb_num);\n- s->is_jmp = DISAS_NORETURN;\n+ tcg_gen_exit_tb((uintptr_t)s->base.tb + tb_num);\n+ s->base.is_jmp = DISAS_NORETURN;\n } else {\n /* jump to another page */\n gen_jmp_im(eip);\n@@ -2244,12 +2242,12 @@ static void gen_movl_seg_T0(DisasContext *s, int seg_reg)\n stop as a special handling must be done to disable hardware\n interrupts for the next instruction */\n if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS)) {\n- s->is_jmp = DISAS_TOO_MANY;\n+ s->base.is_jmp = DISAS_TOO_MANY;\n }\n } else {\n gen_op_movl_seg_T0_vm(seg_reg);\n if (seg_reg == R_SS) {\n- s->is_jmp = DISAS_TOO_MANY;\n+ s->base.is_jmp = DISAS_TOO_MANY;\n }\n }\n }\n@@ -2422,7 +2420,7 @@ static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)\n gen_update_cc_op(s);\n gen_jmp_im(cur_eip);\n gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno));\n- s->is_jmp = DISAS_NORETURN;\n+ s->base.is_jmp = DISAS_NORETURN;\n }\n \n /* Generate #UD for the current instruction. The assumption here is that\n@@ -2460,7 +2458,7 @@ static void gen_interrupt(DisasContext *s, int intno,\n gen_jmp_im(cur_eip);\n gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno),\n tcg_const_i32(next_eip - cur_eip));\n- s->is_jmp = DISAS_NORETURN;\n+ s->base.is_jmp = DISAS_NORETURN;\n }\n \n static void gen_debug(DisasContext *s, target_ulong cur_eip)\n@@ -2468,7 +2466,7 @@ static void gen_debug(DisasContext *s, target_ulong cur_eip)\n gen_update_cc_op(s);\n gen_jmp_im(cur_eip);\n gen_helper_debug(cpu_env);\n- s->is_jmp = DISAS_NORETURN;\n+ s->base.is_jmp = DISAS_NORETURN;\n }\n \n static void gen_set_hflag(DisasContext *s, uint32_t mask)\n@@ -2524,10 +2522,10 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, TCGv jr)\n gen_reset_hflag(s, HF_INHIBIT_IRQ_MASK);\n }\n \n- if (s->tb->flags & HF_RF_MASK) {\n+ if (s->base.tb->flags & HF_RF_MASK) {\n gen_helper_reset_rf(cpu_env);\n }\n- if (s->singlestep_enabled) {\n+ if (s->base.singlestep_enabled) {\n gen_helper_debug(cpu_env);\n } else if (recheck_tf) {\n gen_helper_rechecking_single_step(cpu_env);\n@@ -2543,7 +2541,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, TCGv jr)\n } else {\n tcg_gen_exit_tb(0);\n }\n- s->is_jmp = DISAS_NORETURN;\n+ s->base.is_jmp = DISAS_NORETURN;\n }\n \n static inline void\n@@ -4417,7 +4415,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,\n }\n }\n \n-/* convert one instruction. s->is_jmp is set if the translation must\n+/* convert one instruction. s->base.is_jmp is set if the translation must\n be stopped. Return the next pc value */\n static target_ulong disas_insn(CPUX86State *env, DisasContext *s,\n target_ulong pc_start)\n@@ -5377,7 +5375,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,\n gen_movl_seg_T0(s, reg);\n gen_pop_update(s, ot);\n /* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp. */\n- if (s->is_jmp) {\n+ if (s->base.is_jmp) {\n gen_jmp_im(s->pc - s->cs_base);\n if (reg == R_SS) {\n s->tf = 0;\n@@ -5392,7 +5390,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,\n ot = gen_pop_T0(s);\n gen_movl_seg_T0(s, (b >> 3) & 7);\n gen_pop_update(s, ot);\n- if (s->is_jmp) {\n+ if (s->base.is_jmp) {\n gen_jmp_im(s->pc - s->cs_base);\n gen_eob(s);\n }\n@@ -5443,7 +5441,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,\n gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);\n gen_movl_seg_T0(s, reg);\n /* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp. */\n- if (s->is_jmp) {\n+ if (s->base.is_jmp) {\n gen_jmp_im(s->pc - s->cs_base);\n if (reg == R_SS) {\n s->tf = 0;\n@@ -5652,7 +5650,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,\n gen_movl_seg_T0(s, op);\n /* then put the data */\n gen_op_mov_reg_v(ot, reg, cpu_T1);\n- if (s->is_jmp) {\n+ if (s->base.is_jmp) {\n gen_jmp_im(s->pc - s->cs_base);\n gen_eob(s);\n }\n@@ -6308,7 +6306,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,\n gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);\n } else {\n gen_ins(s, ot);\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_jmp(s, s->pc - s->cs_base);\n }\n }\n@@ -6323,7 +6321,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,\n gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);\n } else {\n gen_outs(s, ot);\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_jmp(s, s->pc - s->cs_base);\n }\n }\n@@ -6339,14 +6337,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,\n tcg_gen_movi_tl(cpu_T0, val);\n gen_check_io(s, ot, pc_start - s->cs_base,\n SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_start();\n \t}\n tcg_gen_movi_i32(cpu_tmp2_i32, val);\n gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32);\n gen_op_mov_reg_v(ot, R_EAX, cpu_T1);\n gen_bpt_io(s, cpu_tmp2_i32, ot);\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_end();\n gen_jmp(s, s->pc - s->cs_base);\n }\n@@ -6360,14 +6358,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,\n svm_is_rep(prefixes));\n gen_op_mov_v_reg(ot, cpu_T1, R_EAX);\n \n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_start();\n \t}\n tcg_gen_movi_i32(cpu_tmp2_i32, val);\n tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1);\n gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);\n gen_bpt_io(s, cpu_tmp2_i32, ot);\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_end();\n gen_jmp(s, s->pc - s->cs_base);\n }\n@@ -6378,14 +6376,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,\n tcg_gen_ext16u_tl(cpu_T0, cpu_regs[R_EDX]);\n gen_check_io(s, ot, pc_start - s->cs_base,\n SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_start();\n \t}\n tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);\n gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32);\n gen_op_mov_reg_v(ot, R_EAX, cpu_T1);\n gen_bpt_io(s, cpu_tmp2_i32, ot);\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_end();\n gen_jmp(s, s->pc - s->cs_base);\n }\n@@ -6398,14 +6396,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,\n svm_is_rep(prefixes));\n gen_op_mov_v_reg(ot, cpu_T1, R_EAX);\n \n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_start();\n \t}\n tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);\n tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1);\n gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);\n gen_bpt_io(s, cpu_tmp2_i32, ot);\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_end();\n gen_jmp(s, s->pc - s->cs_base);\n }\n@@ -6944,7 +6942,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,\n gen_update_cc_op(s);\n gen_jmp_im(pc_start - s->cs_base);\n gen_helper_pause(cpu_env, tcg_const_i32(s->pc - pc_start));\n- s->is_jmp = DISAS_NORETURN;\n+ s->base.is_jmp = DISAS_NORETURN;\n }\n break;\n case 0x9b: /* fwait */\n@@ -7113,11 +7111,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,\n case 0x131: /* rdtsc */\n gen_update_cc_op(s);\n gen_jmp_im(pc_start - s->cs_base);\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_start();\n \t}\n gen_helper_rdtsc(cpu_env);\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_end();\n gen_jmp(s, s->pc - s->cs_base);\n }\n@@ -7189,7 +7187,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,\n gen_update_cc_op(s);\n gen_jmp_im(pc_start - s->cs_base);\n gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start));\n- s->is_jmp = DISAS_NORETURN;\n+ s->base.is_jmp = DISAS_NORETURN;\n }\n break;\n case 0x100:\n@@ -7372,7 +7370,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,\n gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1),\n tcg_const_i32(s->pc - pc_start));\n tcg_gen_exit_tb(0);\n- s->is_jmp = DISAS_NORETURN;\n+ s->base.is_jmp = DISAS_NORETURN;\n break;\n \n case 0xd9: /* VMMCALL */\n@@ -7572,11 +7570,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,\n }\n gen_update_cc_op(s);\n gen_jmp_im(pc_start - s->cs_base);\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_start();\n }\n gen_helper_rdtscp(cpu_env);\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_end();\n gen_jmp(s, s->pc - s->cs_base);\n }\n@@ -7941,24 +7939,24 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,\n gen_update_cc_op(s);\n gen_jmp_im(pc_start - s->cs_base);\n if (b & 2) {\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_start();\n }\n gen_op_mov_v_reg(ot, cpu_T0, rm);\n gen_helper_write_crN(cpu_env, tcg_const_i32(reg),\n cpu_T0);\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_end();\n }\n gen_jmp_im(s->pc - s->cs_base);\n gen_eob(s);\n } else {\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_start();\n }\n gen_helper_read_crN(cpu_T0, cpu_env, tcg_const_i32(reg));\n gen_op_mov_reg_v(ot, rm, cpu_T0);\n- if (s->tb->cflags & CF_USE_ICOUNT) {\n+ if (s->base.tb->cflags & CF_USE_ICOUNT) {\n gen_io_end();\n }\n }\n@@ -8384,15 +8382,13 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n {\n CPUX86State *env = cs->env_ptr;\n DisasContext dc1, *dc = &dc1;\n- target_ulong pc_ptr;\n uint32_t flags;\n- target_ulong pc_start;\n target_ulong cs_base;\n int num_insns;\n int max_insns;\n \n /* generate intermediate code */\n- pc_start = tb->pc;\n+ dc->base.pc_first = tb->pc;\n cs_base = tb->cs_base;\n flags = tb->flags;\n \n@@ -8405,11 +8401,11 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n dc->cpl = (flags >> HF_CPL_SHIFT) & 3;\n dc->iopl = (flags >> IOPL_SHIFT) & 3;\n dc->tf = (flags >> TF_SHIFT) & 1;\n- dc->singlestep_enabled = cs->singlestep_enabled;\n+ dc->base.singlestep_enabled = cs->singlestep_enabled;\n dc->cc_op = CC_OP_DYNAMIC;\n dc->cc_op_dirty = false;\n dc->cs_base = cs_base;\n- dc->tb = tb;\n+ dc->base.tb = tb;\n dc->popl_esp_hack = 0;\n /* select memory access functions */\n dc->mem_index = 0;\n@@ -8459,8 +8455,8 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n cpu_ptr1 = tcg_temp_new_ptr();\n cpu_cc_srcT = tcg_temp_local_new();\n \n- dc->is_jmp = DISAS_NEXT;\n- pc_ptr = pc_start;\n+ dc->base.is_jmp = DISAS_NEXT;\n+ dc->base.pc_next = dc->base.pc_first;\n num_insns = 0;\n max_insns = tb->cflags & CF_COUNT_MASK;\n if (max_insns == 0) {\n@@ -8472,37 +8468,38 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n \n gen_tb_start(tb);\n for(;;) {\n- tcg_gen_insn_start(pc_ptr, dc->cc_op);\n+ tcg_gen_insn_start(dc->base.pc_next, dc->cc_op);\n num_insns++;\n \n /* If RF is set, suppress an internally generated breakpoint. */\n- if (unlikely(cpu_breakpoint_test(cs, pc_ptr,\n+ if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next,\n tb->flags & HF_RF_MASK\n ? BP_GDB : BP_ANY))) {\n- gen_debug(dc, pc_ptr - dc->cs_base);\n+ gen_debug(dc, dc->base.pc_next - dc->cs_base);\n /* The address covered by the breakpoint must be included in\n [tb->pc, tb->pc + tb->size) in order to for it to be\n properly cleared -- thus we increment the PC here so that\n the logic setting tb->size below does the right thing. */\n- pc_ptr += 1;\n+ dc->base.pc_next += 1;\n goto done_generating;\n }\n if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {\n gen_io_start();\n }\n \n- pc_ptr = disas_insn(env, dc, pc_ptr);\n+ dc->base.pc_next = disas_insn(env, dc, dc->base.pc_next);\n /* stop translation if indicated */\n- if (dc->is_jmp)\n+ if (dc->base.is_jmp) {\n break;\n+ }\n /* if single step mode, we generate only one instruction and\n generate an exception */\n /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear\n the flag and abort the translation to give the irqs a\n change to be happen */\n- if (dc->tf || dc->singlestep_enabled ||\n+ if (dc->tf || dc->base.singlestep_enabled ||\n (flags & HF_INHIBIT_IRQ_MASK)) {\n- gen_jmp_im(pc_ptr - dc->cs_base);\n+ gen_jmp_im(dc->base.pc_next - dc->cs_base);\n gen_eob(dc);\n break;\n }\n@@ -8513,23 +8510,23 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n because an exception hasn't stopped this code.\n */\n if ((tb->cflags & CF_USE_ICOUNT)\n- && ((pc_ptr & TARGET_PAGE_MASK)\n- != ((pc_ptr + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MASK)\n- || (pc_ptr & ~TARGET_PAGE_MASK) == 0)) {\n- gen_jmp_im(pc_ptr - dc->cs_base);\n+ && ((dc->base.pc_next & TARGET_PAGE_MASK)\n+ != ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MASK)\n+ || (dc->base.pc_next & ~TARGET_PAGE_MASK) == 0)) {\n+ gen_jmp_im(dc->base.pc_next - dc->cs_base);\n gen_eob(dc);\n break;\n }\n /* if too long translation, stop generation too */\n if (tcg_op_buf_full() ||\n- (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) ||\n+ (dc->base.pc_next - dc->base.pc_first) >= (TARGET_PAGE_SIZE - 32) ||\n num_insns >= max_insns) {\n- gen_jmp_im(pc_ptr - dc->cs_base);\n+ gen_jmp_im(dc->base.pc_next - dc->cs_base);\n gen_eob(dc);\n break;\n }\n if (singlestep) {\n- gen_jmp_im(pc_ptr - dc->cs_base);\n+ gen_jmp_im(dc->base.pc_next - dc->cs_base);\n gen_eob(dc);\n break;\n }\n@@ -8541,24 +8538,25 @@ done_generating:\n \n #ifdef DEBUG_DISAS\n if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)\n- && qemu_log_in_addr_range(pc_start)) {\n+ && qemu_log_in_addr_range(dc->base.pc_first)) {\n int disas_flags;\n qemu_log_lock();\n qemu_log(\"----------------\\n\");\n- qemu_log(\"IN: %s\\n\", lookup_symbol(pc_start));\n+ qemu_log(\"IN: %s\\n\", lookup_symbol(dc->base.pc_first));\n #ifdef TARGET_X86_64\n if (dc->code64)\n disas_flags = 2;\n else\n #endif\n disas_flags = !dc->code32;\n- log_target_disas(cs, pc_start, pc_ptr - pc_start, disas_flags);\n+ log_target_disas(cs, dc->base.pc_first, dc->base.pc_next - dc->base.pc_first,\n+ disas_flags);\n qemu_log(\"\\n\");\n qemu_log_unlock();\n }\n #endif\n \n- tb->size = pc_ptr - pc_start;\n+ tb->size = dc->base.pc_next - dc->base.pc_first;\n tb->icount = num_insns;\n }\n \n", "prefixes": [ "PULL", "07/32" ] }