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GET /api/1.2/patches/810700/?format=api
{ "id": 810700, "url": "http://patchwork.ozlabs.org/api/1.2/patches/810700/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-12-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906160612.22769-12-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T16:05:51", "name": "[PULL,11/32] target/i386: [tcg] Port to translate_insn", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4d1468ac8fe9c0c2b1ad2a9b1773f04d439c7b24", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-12-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1847, "url": "http://patchwork.ozlabs.org/api/1.2/series/1847/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847", "date": "2017-09-06T16:05:41", "name": "[PULL,01/32] tcg: Add generic DISAS_NORETURN", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1847/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810700/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810700/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"jenYaFh2\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnTBf3xkQz9s7F\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 02:12:42 +1000 (AEST)", "from localhost ([::1]:36978 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpcwS-0004oH-HS\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 12:12:40 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:41696)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqa-0008VA-1D\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:39 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqU-0001zM-Vv\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:36 -0400", "from mail-pg0-x22b.google.com ([2607:f8b0:400e:c05::22b]:37871)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpcqU-0001z0-Nv\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:30 -0400", "by mail-pg0-x22b.google.com with SMTP id d8so15974594pgt.4\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 09:06:30 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tt65sm262863pfk.59.2017.09.06.09.06.28\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 09:06:28 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=WCabe7Hfc5O/Az0W5815T3bKK8UwqfKSOQYFvQwn+WM=;\n\tb=jenYaFh2prpRPi5qTcx38Dt4Mv4lbjdYLBpPQ6OgYtCGM+oLwvCHe3/04xzOQhBn2s\n\tO6MC2PKGq4rwkXTFqu5mBYx1WOnXSbQij1UhNUlchEpdPn6i15kzDtFcChdEG5owAGmj\n\ti5ERpVzCFbsrM4s2QHWSZ2suxPvxV4VgP8Yl0=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=WCabe7Hfc5O/Az0W5815T3bKK8UwqfKSOQYFvQwn+WM=;\n\tb=GYpDQZVz2ggxuYY6vdnqGkybF48emdUcgRTYOKkJkey+fBsMk7KrTTnYU9cMKJYOY5\n\tNedOJ1jgaJ0BipWyqYg4WdxF4Q5eD2xQHHoWQZ+Z+YQgVRuqgLHNqd8L5KDmgx4GaAi5\n\tE1X904XyIIPSjYFqWmbGoN+ZkjoSFJasd87KhHFcCy1qvwhUjlOZvRZSsYDAGDhNPQ7K\n\toDzxjKV15ovL4Q9DI+9R4HCd4UMaiEkGxSMe/KJnLpNrvw+/BZaawxUAPnr4KsUj/UPY\n\tOXvgu2kCUKcof8AggU87STCgSkgMg9NzB+UuqnotcuWfyei/QX3sg5KioC4l5Oe25phv\n\tq9pw==", "X-Gm-Message-State": "AHPjjUgaVHpkvQBM00RKx6hYgvCnMlGvT6ocGEaOy8v6ZckOcVH0r2Og\n\tWg96zqDXqxJhJOalEGkVLg==", "X-Google-Smtp-Source": "ADKCNb4Hl45se9YWvwRg8cVP+JgRi+55Q/B1fCOIzDrA0GpRf9LUf6W7WGEhZRyHZwkI0xRdtnNUpg==", "X-Received": "by 10.98.19.75 with SMTP id b72mr7669365pfj.293.1504713989385;\n\tWed, 06 Sep 2017 09:06:29 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 09:05:51 -0700", "Message-Id": "<20170906160612.22769-12-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906160612.22769-1-richard.henderson@linaro.org>", "References": "<20170906160612.22769-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::22b", "Subject": "[Qemu-devel] [PULL 11/32] target/i386: [tcg] Port to translate_insn", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t<vilanova@ac.upc.edu>, \tRichard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Lluís Vilanova <vilanova@ac.upc.edu>\n\nIncrementally paves the way towards using the generic instruction translation\nloop.\n\nSigned-off-by: Lluís Vilanova <vilanova@ac.upc.edu>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nReviewed-by: Emilio G. Cota <cota@braap.org>\nMessage-Id: <150002195074.22386.16195894320027075398.stgit@frigg.lan>\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/i386/translate.c | 66 +++++++++++++++++++++++++++++++------------------\n 1 file changed, 42 insertions(+), 24 deletions(-)", "diff": "diff --git a/target/i386/translate.c b/target/i386/translate.c\nindex 4d4083fe30..0f38896f17 100644\n--- a/target/i386/translate.c\n+++ b/target/i386/translate.c\n@@ -4417,15 +4417,16 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,\n \n /* convert one instruction. s->base.is_jmp is set if the translation must\n be stopped. Return the next pc value */\n-static target_ulong disas_insn(CPUX86State *env, DisasContext *s,\n- target_ulong pc_start)\n+static target_ulong disas_insn(DisasContext *s, CPUState *cpu)\n {\n+ CPUX86State *env = cpu->env_ptr;\n int b, prefixes;\n int shift;\n TCGMemOp ot, aflag, dflag;\n int modrm, reg, rm, mod, op, opreg, val;\n target_ulong next_eip, tval;\n int rex_w, rex_r;\n+ target_ulong pc_start = s->base.pc_next;\n \n s->pc_start = s->pc = pc_start;\n prefixes = 0;\n@@ -8476,10 +8477,46 @@ static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,\n }\n }\n \n+static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n+{\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n+ target_ulong pc_next = disas_insn(dc, cpu);\n+\n+ if (dc->tf || (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) {\n+ /* if single step mode, we generate only one instruction and\n+ generate an exception */\n+ /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear\n+ the flag and abort the translation to give the irqs a\n+ chance to happen */\n+ gen_jmp_im(pc_next - dc->cs_base);\n+ gen_eob(dc);\n+ dc->base.is_jmp = DISAS_TOO_MANY;\n+ } else if ((dc->base.tb->cflags & CF_USE_ICOUNT)\n+ && ((dc->base.pc_next & TARGET_PAGE_MASK)\n+ != ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1)\n+ & TARGET_PAGE_MASK)\n+ || (dc->base.pc_next & ~TARGET_PAGE_MASK) == 0)) {\n+ /* Do not cross the boundary of the pages in icount mode,\n+ it can cause an exception. Do it only when boundary is\n+ crossed by the first instruction in the block.\n+ If current instruction already crossed the bound - it's ok,\n+ because an exception hasn't stopped this code.\n+ */\n+ gen_jmp_im(pc_next - dc->cs_base);\n+ gen_eob(dc);\n+ dc->base.is_jmp = DISAS_TOO_MANY;\n+ } else if ((pc_next - dc->base.pc_first) >= (TARGET_PAGE_SIZE - 32)) {\n+ gen_jmp_im(pc_next - dc->cs_base);\n+ gen_eob(dc);\n+ dc->base.is_jmp = DISAS_TOO_MANY;\n+ }\n+\n+ dc->base.pc_next = pc_next;\n+}\n+\n /* generate intermediate code for basic block 'tb'. */\n void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n {\n- CPUX86State *env = cs->env_ptr;\n DisasContext dc1, *dc = &dc1;\n int num_insns;\n int max_insns;\n@@ -8525,39 +8562,20 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n gen_io_start();\n }\n \n- dc->base.pc_next = disas_insn(env, dc, dc->base.pc_next);\n+ i386_tr_translate_insn(&dc->base, cs);\n /* stop translation if indicated */\n if (dc->base.is_jmp) {\n break;\n }\n /* if single step mode, we generate only one instruction and\n generate an exception */\n- /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear\n- the flag and abort the translation to give the irqs a\n- change to be happen */\n- if (dc->tf || dc->base.singlestep_enabled ||\n- (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) {\n- gen_jmp_im(dc->base.pc_next - dc->cs_base);\n- gen_eob(dc);\n- break;\n- }\n- /* Do not cross the boundary of the pages in icount mode,\n- it can cause an exception. Do it only when boundary is\n- crossed by the first instruction in the block.\n- If current instruction already crossed the bound - it's ok,\n- because an exception hasn't stopped this code.\n- */\n- if ((tb->cflags & CF_USE_ICOUNT)\n- && ((dc->base.pc_next & TARGET_PAGE_MASK)\n- != ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MASK)\n- || (dc->base.pc_next & ~TARGET_PAGE_MASK) == 0)) {\n+ if (dc->base.singlestep_enabled) {\n gen_jmp_im(dc->base.pc_next - dc->cs_base);\n gen_eob(dc);\n break;\n }\n /* if too long translation, stop generation too */\n if (tcg_op_buf_full() ||\n- (dc->base.pc_next - dc->base.pc_first) >= (TARGET_PAGE_SIZE - 32) ||\n num_insns >= max_insns) {\n gen_jmp_im(dc->base.pc_next - dc->cs_base);\n gen_eob(dc);\n", "prefixes": [ "PULL", "11/32" ] }