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GET /api/1.2/patches/810698/?format=api
{ "id": 810698, "url": "http://patchwork.ozlabs.org/api/1.2/patches/810698/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-21-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906160612.22769-21-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T16:06:00", "name": "[PULL,20/32] target/arm: [tcg, a64] Port to insn_start", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "55c35dc0220ecb32062bf7288d8e509f49d24a53", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-21-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1847, "url": "http://patchwork.ozlabs.org/api/1.2/series/1847/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847", "date": "2017-09-06T16:05:41", "name": "[PULL,01/32] tcg: Add generic DISAS_NORETURN", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1847/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810698/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810698/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"DvCXQqsu\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnT8y6q40z9sRV\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 02:11:14 +1000 (AEST)", "from localhost ([::1]:36972 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpcv2-0003YB-RX\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 12:11:12 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:41811)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqi-0000Hu-E2\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:47 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqh-0002b4-8D\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:44 -0400", "from mail-pf0-x233.google.com ([2607:f8b0:400e:c00::233]:33133)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpcqh-0002Yz-1G\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:43 -0400", "by mail-pf0-x233.google.com with SMTP id y68so13496497pfd.0\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 09:06:42 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tt65sm262863pfk.59.2017.09.06.09.06.40\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 09:06:40 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=rK5vcMmer/3Wux+HRmWMOMZFIkyWPjSSJlQhe5ZOLqw=;\n\tb=DvCXQqsuUJlIoLi1JUMTYobUzTnYw6mQhbXdDUHjNqkrZE+FAYcaC7kpT7kPs+oQ8V\n\tYA3nMuQz16+xu59WCF2El+QFXWsfYVFEVjwWMB7GVHPO3A9KbEw/y1cwJTp7MrHjNF45\n\tK8Kso7qsCxmxoctn0WsTLp+nXbH0svLWlOBHw=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=rK5vcMmer/3Wux+HRmWMOMZFIkyWPjSSJlQhe5ZOLqw=;\n\tb=cmE9aXB5SqpY9sTujft6PepHFDn41i8gF+FJYaPSTUrdn8JYNytjiehFnGS5fH5SDe\n\tssWFFHYQ2cMPy+HLrqB827bPd0Kbf4Xrhz6Q9hEqgJBIgyk9H7Oa2ns4N23SZMiZqVoB\n\t2HKR6GA+3Va00Zmfeeg5XMj1MClOS0FfN1P839TNDwG+EyULYz94h47GlUHqxlKXRZ9T\n\tPZ+LWT4jxJ6aKCVupXLkN3fFWVe69z4oNdTeeYrHYDAKcM3P3tmmAzJ0Iluk8240rjSy\n\tw39lHPHLffGpTFaDLN+85k7KZlEBLLPVgZdauyQwxzuo9YBoSpqPbF5QSjktfLysKHRt\n\touSg==", "X-Gm-Message-State": "AHPjjUh5Fe2jW2OiVAFR4WdJRhIgjfqiuE81hf5l80Aew7pYjGtoAhEn\n\tDUg1SVYLtgFrzBDHc3MJgQ==", "X-Google-Smtp-Source": "ADKCNb7wzgf1HF9Z/BUaBwMBrDuDTPjObMDZ9R1OW5FmrhI8MFJvYZtF69hYz/lNSTxsUpPT4Ic/UA==", "X-Received": "by 10.98.158.201 with SMTP id f70mr8035014pfk.162.1504714001862; \n\tWed, 06 Sep 2017 09:06:41 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 09:06:00 -0700", "Message-Id": "<20170906160612.22769-21-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906160612.22769-1-richard.henderson@linaro.org>", "References": "<20170906160612.22769-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c00::233", "Subject": "[Qemu-devel] [PULL 20/32] target/arm: [tcg, a64] Port to insn_start", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t<vilanova@ac.upc.edu>, \tRichard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Lluís Vilanova <vilanova@ac.upc.edu>\n\nIncrementally paves the way towards using the generic instruction translation\nloop.\n\nSigned-off-by: Lluís Vilanova <vilanova@ac.upc.edu>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nReviewed-by: Alex Benneé <alex.benee@linaro.org>\nMessage-Id: <150002413187.22386.156315485813606121.stgit@frigg.lan>\n[rth: Use DISAS_TOO_MANY for \"execute only one more\" after bp.]\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/arm/translate-a64.c | 11 ++++++++--\n target/arm/translate.c | 55 +++++++++++++++++++++++++++++-----------------\n 2 files changed, 44 insertions(+), 22 deletions(-)", "diff": "diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c\nindex e8dc96c28a..1eab10696c 100644\n--- a/target/arm/translate-a64.c\n+++ b/target/arm/translate-a64.c\n@@ -11259,6 +11259,14 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,\n return max_insns;\n }\n \n+static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n+{\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n+\n+ dc->insn_start_idx = tcg_op_buf_count();\n+ tcg_gen_insn_start(dc->pc, 0, 0);\n+}\n+\n void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n TranslationBlock *tb)\n {\n@@ -11290,8 +11298,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n \n do {\n dc->base.num_insns++;\n- dc->insn_start_idx = tcg_op_buf_count();\n- tcg_gen_insn_start(dc->pc, 0, 0);\n+ aarch64_tr_insn_start(&dc->base, cs);\n \n if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {\n CPUBreakpoint *bp;\ndiff --git a/target/arm/translate.c b/target/arm/translate.c\nindex 005157225c..2f5f65310d 100644\n--- a/target/arm/translate.c\n+++ b/target/arm/translate.c\n@@ -11946,6 +11946,33 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n 0);\n }\n \n+static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,\n+ const CPUBreakpoint *bp)\n+{\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n+\n+ if (bp->flags & BP_CPU) {\n+ gen_set_condexec(dc);\n+ gen_set_pc_im(dc, dc->pc);\n+ gen_helper_check_breakpoints(cpu_env);\n+ /* End the TB early; it's likely not going to be executed */\n+ dc->base.is_jmp = DISAS_TOO_MANY;\n+ } else {\n+ gen_exception_internal_insn(dc, 0, EXCP_DEBUG);\n+ /* The address covered by the breakpoint must be\n+ included in [tb->pc, tb->pc + tb->size) in order\n+ to for it to be properly cleared -- thus we\n+ increment the PC here so that the logic setting\n+ tb->size below does the right thing. */\n+ /* TODO: Advance PC by correct instruction length to\n+ * avoid disassembler error messages */\n+ dc->pc += 2;\n+ dc->base.is_jmp = DISAS_NORETURN;\n+ }\n+\n+ return true;\n+}\n+\n /* generate intermediate code for basic block 'tb'. */\n void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n {\n@@ -11994,28 +12021,15 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {\n CPUBreakpoint *bp;\n QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {\n- if (bp->pc == dc->pc) {\n- if (bp->flags & BP_CPU) {\n- gen_set_condexec(dc);\n- gen_set_pc_im(dc, dc->pc);\n- gen_helper_check_breakpoints(cpu_env);\n- /* End the TB early; it's likely not going to be executed */\n- dc->base.is_jmp = DISAS_UPDATE;\n- } else {\n- gen_exception_internal_insn(dc, 0, EXCP_DEBUG);\n- /* The address covered by the breakpoint must be\n- included in [tb->pc, tb->pc + tb->size) in order\n- to for it to be properly cleared -- thus we\n- increment the PC here so that the logic setting\n- tb->size below does the right thing. */\n- /* TODO: Advance PC by correct instruction length to\n- * avoid disassembler error messages */\n- dc->pc += 2;\n- goto done_generating;\n+ if (bp->pc == dc->base.pc_next) {\n+ if (arm_tr_breakpoint_check(&dc->base, cs, bp)) {\n+ break;\n }\n- break;\n }\n }\n+ if (dc->base.is_jmp > DISAS_TOO_MANY) {\n+ break;\n+ }\n }\n \n if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {\n@@ -12137,6 +12151,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n gen_exception(EXCP_SMC, syn_aa32_smc(), 3);\n break;\n case DISAS_NEXT:\n+ case DISAS_TOO_MANY:\n case DISAS_UPDATE:\n gen_set_pc_im(dc, dc->pc);\n /* fall through */\n@@ -12158,6 +12173,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n */\n switch(dc->base.is_jmp) {\n case DISAS_NEXT:\n+ case DISAS_TOO_MANY:\n gen_goto_tb(dc, 1, dc->pc);\n break;\n case DISAS_JUMP:\n@@ -12211,7 +12227,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n }\n }\n \n-done_generating:\n gen_tb_end(tb, dc->base.num_insns);\n \n #ifdef DEBUG_DISAS\n", "prefixes": [ "PULL", "20/32" ] }