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GET /api/1.2/patches/810697/?format=api
{ "id": 810697, "url": "http://patchwork.ozlabs.org/api/1.2/patches/810697/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-4-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906160612.22769-4-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T16:05:43", "name": "[PULL,03/32] target/arm: Use DISAS_NORETURN", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "33fe642bbe019c4eef8d37ed434f9ef8dd13d4e4", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-4-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1847, "url": "http://patchwork.ozlabs.org/api/1.2/series/1847/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847", "date": "2017-09-06T16:05:41", "name": "[PULL,01/32] tcg: Add generic DISAS_NORETURN", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1847/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810697/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810697/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"J/SiTef0\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnT7v631Dz9s76\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 02:10:19 +1000 (AEST)", "from localhost ([::1]:36969 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpcu9-0002mJ-Qa\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 12:10:17 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:41616)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqU-0008PF-2L\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:35 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqK-0001bI-5d\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:30 -0400", "from mail-pf0-x22a.google.com ([2607:f8b0:400e:c00::22a]:35362)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpcqJ-0001X0-T7\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:20 -0400", "by mail-pf0-x22a.google.com with SMTP id g13so13482162pfm.2\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 09:06:19 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tt65sm262863pfk.59.2017.09.06.09.06.17\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 09:06:17 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=l+8GeftkxPUaXtKmP8H3x4UyaNFhwhYJYRyE/2Xhemc=;\n\tb=J/SiTef0adAzAMrAKHufhcZAKXV0nCC67Uo8meXk6aAfOw1L5zpxVFsyQPm3frgphC\n\t/kFJUCjEZqn4SQeA2jT9BoOK8dlVvlf4MRtC3Lnef6pTWgLt/qmM3B9zd6jHpus3SZjJ\n\tcVvh1oXz49bWNjqikGEVy2nt5XSPUc6YO+rGk=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=l+8GeftkxPUaXtKmP8H3x4UyaNFhwhYJYRyE/2Xhemc=;\n\tb=Xcg2mlVA/cqBln0f1c+d82ty9xnpJFA54fp9uRgFdhY7yaVDp7+5lpE8/tL7bJnZd0\n\toRPNpe4pwx+yMJ4vwy38YqSwZSxQ7Xne28jxAtxp0AG04u9Ka8l913qtvIowZfLVwLtI\n\tXusKXZgNy6LLPcrp7EvZ6jgq2bNQPVNrj4M/BupYOj9vYlMM0Tdb2hV03B0cbDfI+ne+\n\tqGcXhQyR5t+ENGI9A3JnNnIu5VjSILDH4yZPrjO9+GCEmLVHxu7+y8SWwxAV/8ySUGu7\n\t8YY/VJVMkHZUqhg7UYsXuFKHk5I/hEQFZOsOW3YKE/CZCOg2wTqAp5+4SAmZcTm+QnoW\n\tgbtg==", "X-Gm-Message-State": "AHPjjUj41x6Nj/2Jy84T2s13x76MN+Pub2flMxEO0qTA45+K13lepp5d\n\t8Hs8QzLniwkynMr0oPL8hA==", "X-Google-Smtp-Source": "ADKCNb4c3C5poZzM2vw+9cHzXUxyOmivWqhUCoD5Ow/eiAOXQ4dLs6iweffpoPTPphiM/c3YKvFFKg==", "X-Received": "by 10.99.115.28 with SMTP id o28mr8351773pgc.374.1504713978512; \n\tWed, 06 Sep 2017 09:06:18 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 09:05:43 -0700", "Message-Id": "<20170906160612.22769-4-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906160612.22769-1-richard.henderson@linaro.org>", "References": "<20170906160612.22769-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c00::22a", "Subject": "[Qemu-devel] [PULL 03/32] target/arm: Use DISAS_NORETURN", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Richard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nFold DISAS_EXC and DISAS_TB_JUMP into DISAS_NORETURN.\n\nIn both cases all following code is dead. In the first\ncase because we have exited the TB via exception; in the\nsecond case because we have exited the TB via goto_tb\nand its associated machinery.\n\nReviewed-by: Emilio G. Cota <cota@braap.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/arm/translate.h | 8 ++------\n target/arm/translate-a64.c | 37 ++++++++++++++++++++-----------------\n target/arm/translate.c | 14 ++++++++------\n 3 files changed, 30 insertions(+), 29 deletions(-)", "diff": "diff --git a/target/arm/translate.h b/target/arm/translate.h\nindex 2fe144baa9..90f64d9716 100644\n--- a/target/arm/translate.h\n+++ b/target/arm/translate.h\n@@ -124,12 +124,8 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)\n * defer them until after the conditional execution state has been updated.\n * WFI also needs special handling when single-stepping.\n */\n-#define DISAS_WFI 4\n-#define DISAS_SWI 5\n-/* For instructions which unconditionally cause an exception we can skip\n- * emitting unreachable code at the end of the TB in the A64 decoder\n- */\n-#define DISAS_EXC 6\n+#define DISAS_WFI 5\n+#define DISAS_SWI 6\n /* WFE */\n #define DISAS_WFE 7\n #define DISAS_HVC 8\ndiff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c\nindex cb44632d16..881d3c0cbb 100644\n--- a/target/arm/translate-a64.c\n+++ b/target/arm/translate-a64.c\n@@ -304,7 +304,7 @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)\n {\n gen_a64_set_pc_im(s->pc - offset);\n gen_exception_internal(excp);\n- s->is_jmp = DISAS_EXC;\n+ s->is_jmp = DISAS_NORETURN;\n }\n \n static void gen_exception_insn(DisasContext *s, int offset, int excp,\n@@ -312,7 +312,7 @@ static void gen_exception_insn(DisasContext *s, int offset, int excp,\n {\n gen_a64_set_pc_im(s->pc - offset);\n gen_exception(excp, syndrome, target_el);\n- s->is_jmp = DISAS_EXC;\n+ s->is_jmp = DISAS_NORETURN;\n }\n \n static void gen_ss_advance(DisasContext *s)\n@@ -340,7 +340,7 @@ static void gen_step_complete_exception(DisasContext *s)\n gen_ss_advance(s);\n gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex),\n default_exception_el(s));\n- s->is_jmp = DISAS_EXC;\n+ s->is_jmp = DISAS_NORETURN;\n }\n \n static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest)\n@@ -371,7 +371,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)\n tcg_gen_goto_tb(n);\n gen_a64_set_pc_im(dest);\n tcg_gen_exit_tb((intptr_t)tb + n);\n- s->is_jmp = DISAS_TB_JUMP;\n+ s->is_jmp = DISAS_NORETURN;\n } else {\n gen_a64_set_pc_im(dest);\n if (s->ss_active) {\n@@ -380,7 +380,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)\n gen_exception_internal(EXCP_DEBUG);\n } else {\n tcg_gen_lookup_and_goto_ptr(cpu_pc);\n- s->is_jmp = DISAS_TB_JUMP;\n+ s->is_jmp = DISAS_NORETURN;\n }\n }\n }\n@@ -11326,7 +11326,7 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)\n assert(num_insns == 1);\n gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),\n default_exception_el(dc));\n- dc->is_jmp = DISAS_EXC;\n+ dc->is_jmp = DISAS_NORETURN;\n break;\n }\n \n@@ -11353,21 +11353,25 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)\n gen_io_end();\n }\n \n- if (unlikely(cs->singlestep_enabled || dc->ss_active)\n- && dc->is_jmp != DISAS_EXC) {\n+ if (unlikely(cs->singlestep_enabled || dc->ss_active)) {\n /* Note that this means single stepping WFI doesn't halt the CPU.\n * For conditional branch insns this is harmless unreachable code as\n * gen_goto_tb() has already handled emitting the debug exception\n * (and thus a tb-jump is not possible when singlestepping).\n */\n- assert(dc->is_jmp != DISAS_TB_JUMP);\n- if (dc->is_jmp != DISAS_JUMP) {\n+ switch (dc->is_jmp) {\n+ default:\n gen_a64_set_pc_im(dc->pc);\n- }\n- if (cs->singlestep_enabled) {\n- gen_exception_internal(EXCP_DEBUG);\n- } else {\n- gen_step_complete_exception(dc);\n+ /* fall through */\n+ case DISAS_JUMP:\n+ if (cs->singlestep_enabled) {\n+ gen_exception_internal(EXCP_DEBUG);\n+ } else {\n+ gen_step_complete_exception(dc);\n+ }\n+ break;\n+ case DISAS_NORETURN:\n+ break;\n }\n } else {\n switch (dc->is_jmp) {\n@@ -11377,8 +11381,7 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)\n case DISAS_JUMP:\n tcg_gen_lookup_and_goto_ptr(cpu_pc);\n break;\n- case DISAS_TB_JUMP:\n- case DISAS_EXC:\n+ case DISAS_NORETURN:\n case DISAS_SWI:\n break;\n case DISAS_WFE:\ndiff --git a/target/arm/translate.c b/target/arm/translate.c\nindex e52a6d7622..b14329dc27 100644\n--- a/target/arm/translate.c\n+++ b/target/arm/translate.c\n@@ -297,7 +297,7 @@ static void gen_step_complete_exception(DisasContext *s)\n gen_ss_advance(s);\n gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex),\n default_exception_el(s));\n- s->is_jmp = DISAS_EXC;\n+ s->is_jmp = DISAS_NORETURN;\n }\n \n static void gen_singlestep_exception(DisasContext *s)\n@@ -1184,7 +1184,7 @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)\n gen_set_condexec(s);\n gen_set_pc_im(s, s->pc - offset);\n gen_exception_internal(excp);\n- s->is_jmp = DISAS_EXC;\n+ s->is_jmp = DISAS_NORETURN;\n }\n \n static void gen_exception_insn(DisasContext *s, int offset, int excp,\n@@ -1193,7 +1193,7 @@ static void gen_exception_insn(DisasContext *s, int offset, int excp,\n gen_set_condexec(s);\n gen_set_pc_im(s, s->pc - offset);\n gen_exception(excp, syn, target_el);\n- s->is_jmp = DISAS_EXC;\n+ s->is_jmp = DISAS_NORETURN;\n }\n \n /* Force a TB lookup after an instruction that changes the CPU state. */\n@@ -11974,7 +11974,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n /* We always get here via a jump, so know we are not in a\n conditional execution block. */\n gen_exception_internal(EXCP_KERNEL_TRAP);\n- dc->is_jmp = DISAS_EXC;\n+ dc->is_jmp = DISAS_NORETURN;\n break;\n }\n #endif\n@@ -12119,6 +12119,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n default:\n /* FIXME: Single stepping a WFI insn will not halt the CPU. */\n gen_singlestep_exception(dc);\n+ break;\n+ case DISAS_NORETURN:\n+ break;\n }\n } else {\n /* While branches must always occur at the end of an IT block,\n@@ -12143,8 +12146,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n /* indicate that the hash table must be used to find the next TB */\n tcg_gen_exit_tb(0);\n break;\n- case DISAS_TB_JUMP:\n- case DISAS_EXC:\n+ case DISAS_NORETURN:\n /* nothing more to generate */\n break;\n case DISAS_WFI:\n", "prefixes": [ "PULL", "03/32" ] }