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GET /api/1.2/patches/810332/?format=api
{ "id": 810332, "url": "http://patchwork.ozlabs.org/api/1.2/patches/810332/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1504655479-26492-1-git-send-email-aford173@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504655479-26492-1-git-send-email-aford173@gmail.com>", "list_archive_url": null, "date": "2017-09-05T23:51:18", "name": "[U-Boot,V2,1/2] ARM: OMAP3: am3517_evm: Move header to ti_omap3_common.h", "commit_ref": null, "pull_url": null, "state": "deferred", "archived": false, "hash": "90e29ea99e142acb6e0b55c75f4bae51d3e013c2", "submitter": { "id": 67132, "url": "http://patchwork.ozlabs.org/api/1.2/people/67132/?format=api", "name": "Adam Ford", "email": "aford173@gmail.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/1.2/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1504655479-26492-1-git-send-email-aford173@gmail.com/mbox/", "series": [ { "id": 1669, "url": "http://patchwork.ozlabs.org/api/1.2/series/1669/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=1669", "date": "2017-09-05T23:51:18", "name": "[U-Boot,V2,1/2] ARM: OMAP3: am3517_evm: Move header to ti_omap3_common.h", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/1669/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810332/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810332/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"cCSeU+2W\"; dkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xn3Qm18gtz9t2W\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 6 Sep 2017 09:51:44 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid DFD1AC21DD9; Tue, 5 Sep 2017 23:51:40 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 97D06C21D7A;\n\tTue, 5 Sep 2017 23:51:37 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid B55DCC21C40; Tue, 5 Sep 2017 23:51:36 +0000 (UTC)", "from mail-it0-f65.google.com (mail-it0-f65.google.com\n\t[209.85.214.65])\n\tby lists.denx.de (Postfix) with ESMTPS id 24801C21C26\n\tfor <u-boot@lists.denx.de>; Tue, 5 Sep 2017 23:51:36 +0000 (UTC)", "by mail-it0-f65.google.com with SMTP id z81so825895itb.5\n\tfor <u-boot@lists.denx.de>; Tue, 05 Sep 2017 16:51:36 -0700 (PDT)", "from ubuntu16.lan (c-73-65-120-235.hsd1.mn.comcast.net.\n\t[73.65.120.235]) by smtp.gmail.com with ESMTPSA id\n\tg126sm33866ita.12.2017.09.05.16.51.33\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tTue, 05 Sep 2017 16:51:33 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=FREEMAIL_FROM,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id;\n\tbh=U7AsMiFh8mIp5g+gRNm0788f0gqB7AYbcM/yTs8jrMc=;\n\tb=cCSeU+2W9LFVAg440H73knZUwn9H7GfpXdSq5vosgUVEG4eKhk9oKH/NzW3BCD9VlV\n\tPFqqjnvWTSowmCSZTZcEv4NqP4Q/zsFrNJ3bbrqC0qp8MpXAeepcePTVCNPbxIk0Wqye\n\tKF9VPe1mfwB7ALldEouEa4/xvChNz76uUi1QPVKJlmFD1u19u0VhHHQRQ7aKBw/hrmAQ\n\thLqoowyoJW3cdx0kYBZPhE09Ufqata3IqWRa8zzPUE20JNOEerHKD+FL0aoniBK1AjmH\n\tZoIFIfYosG9kIZf5gPnOVAhfE47Ib4sDYOMiWcdr0n+bx1MAgSWqohPt8ersJwMnUiud\n\t7aqg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id;\n\tbh=U7AsMiFh8mIp5g+gRNm0788f0gqB7AYbcM/yTs8jrMc=;\n\tb=EaihjpQQ56OVsz61W77v6WBSMud9N4PJfx6Y9oLqqPaYsdn6XThOgOJZGaz7DPR+6E\n\tjnKnKNNneIt4bv3Z86NVDNjlxxxc3xtwVKsPhZD6D//JzF5pA3dussWP4F4G3z82RbcI\n\te9IYDbPWY/LrsRZcMVQpgm33QvBITTYj+9mVmIhrpf2Ua+GwL7KFRJ3rbZYZoNka1ruQ\n\tjZuxv/oy3yW6pfntpJRXmdV+eSuEbzMbdszNyQpBhFf6+ocX5iOIBvIkGqPWA1FeXdWc\n\t/uyllFteDn8J+gAfIcTuXi12sZmlDue8LhgBsNVVmYJrWCFb/oxYDvqU6uxgwDRGOf1W\n\t93aA==", "X-Gm-Message-State": "AHPjjUhhNJGg7WsJ6AbGnfBzpIzzXk2g5B3eW3ci6NmPFKcPJT0+m01z\n\tgDEhIPFbxmmpV2qX", "X-Google-Smtp-Source": "ADKCNb7jIi5vSQL5RcN/N679kuto8PBphWUCDFIfEZMtPMMW26QOcvdmnTnld+dP2acIBwk/LWDggw==", "X-Received": "by 10.36.237.140 with SMTP id r134mr1126779ith.121.1504655494419;\n\tTue, 05 Sep 2017 16:51:34 -0700 (PDT)", "From": "Adam Ford <aford173@gmail.com>", "To": "u-boot@lists.denx.de", "Date": "Tue, 5 Sep 2017 18:51:18 -0500", "Message-Id": "<1504655479-26492-1-git-send-email-aford173@gmail.com>", "X-Mailer": "git-send-email 2.7.4", "Cc": "hvaibhav@ti.com", "Subject": "[U-Boot] [PATCH V2 1/2] ARM: OMAP3: am3517_evm: Move header to\n\tti_omap3_common.h", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Much of the AM3517 functions are copies of the standard definitions\nused in ti_omap3_common.h. Moving to include a common file\nreduces the amount of duplicative code and clutter. A few\nAM3517 specific functions (like EMIF4) are explictly defined\nand a few items are undefined or redefined, but overall the number\nof lines of code shink.\n\nTested-by: Derald D. Woods <woods.technical@gmail.com>\nSigned-off-by: Adam Ford <aford173@gmail.com>\n---\nV2: Resync with 2017.09-RC4\n\n include/configs/am3517_evm.h | 50 ++++++--------------------------------------\n 1 file changed, 6 insertions(+), 44 deletions(-)", "diff": "diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h\nindex 5435ca8..022b8a3 100644\n--- a/include/configs/am3517_evm.h\n+++ b/include/configs/am3517_evm.h\n@@ -14,7 +14,6 @@\n #define __CONFIG_H\n \n #define CONFIG_NR_DRAM_BANKS\t2\t/* CS1 may or may not be populated */\n-\n #define CONFIG_EMIF4\t/* The chip has EMIF4 controller */\n \n /*\n@@ -27,39 +26,26 @@\n #define CONFIG_SYS_SPL_MALLOC_START\t0x80208000\n #define CONFIG_SYS_SPL_MALLOC_SIZE\t0x100000\n \n-#include <asm/arch/cpu.h>\t\t/* get chip and board defs */\n-#include <asm/arch/omap.h>\n+#include <configs/ti_omap3_common.h>\n+#undef CONFIG_SDRC\t\t\t/* Disable SDRC since we have EMIF4 */\n \n #define CONFIG_MISC_INIT_R\n-#define CONFIG_CMDLINE_TAG\t\t/* enable passing of ATAGs */\n-#define CONFIG_SETUP_MEMORY_TAGS\n-#define CONFIG_INITRD_TAG\n #define CONFIG_REVISION_TAG\n \n-/* Clock Defines */\n-#define V_OSCK\t\t\t26000000\t/* Clock output from T2 */\n-#define V_SCLK\t\t\t(V_OSCK >> 1)\n-\n-/* Size of malloc() pool */\n-#define CONFIG_SYS_MALLOC_LEN\t\t(16 << 20)\n-\n /* Hardware drivers */\n \n /* NS16550 Configuration */\n-#define V_NS16550_CLK\t\t\t48000000\t/* 48MHz (APLL96/2) */\n #define CONFIG_SYS_NS16550_SERIAL\n #define CONFIG_SYS_NS16550_REG_SIZE\t(-4)\n-#define CONFIG_SYS_NS16550_CLK\t\tV_NS16550_CLK\n \n /* select serial console configuration */\n #define CONFIG_CONS_INDEX\t\t3\n #define CONFIG_SYS_NS16550_COM3\t\tOMAP34XX_UART3\n #define CONFIG_SERIAL3\t\t\t3\t/* UART3 on AM3517 EVM */\n \n+\n /* allow to overwrite serial and ethaddr */\n #define CONFIG_ENV_OVERWRITE\n-#define CONFIG_SYS_BAUDRATE_TABLE\t{4800, 9600, 19200, 38400, 57600,\\\n-\t\t\t\t\t115200}\n \n /*\n * USB configuration\n@@ -103,15 +89,10 @@\n \n /* Board NAND Info. */\n #ifdef CONFIG_NAND\n-#define CONFIG_NAND_OMAP_GPMC\n #define CONFIG_NAND_OMAP_GPMC_PREFETCH\n #define CONFIG_SYS_NAND_ADDR\t\tNAND_BASE\t/* physical address */\n \t\t\t\t\t\t\t/* to access nand */\n-#define CONFIG_SYS_NAND_BASE\t\tNAND_BASE\t/* physical address */\n-\t\t\t\t\t\t\t/* to access */\n-\t\t\t\t\t\t\t/* nand at CS0 */\n-#define CONFIG_SYS_MAX_NAND_DEVICE\t1\t\t/* Max number of */\n-\t\t\t\t\t\t\t/* NAND devices */\n+\n #define CONFIG_SYS_NAND_BUSWIDTH_16BIT\n #define CONFIG_SYS_NAND_5_ADDR_CYCLE\n #define CONFIG_SYS_NAND_PAGE_COUNT\t64\n@@ -231,35 +212,15 @@\n /* We set the max number of command args high to avoid HUSH bugs. */\n #define CONFIG_SYS_MAXARGS\t\t64\n \n-/* Console I/O Buffer Size */\n-#define CONFIG_SYS_CBSIZE\t\t512\n-\n /* memtest works on */\n #define CONFIG_SYS_MEMTEST_START\t(OMAP34XX_SDRC_CS0)\n #define CONFIG_SYS_MEMTEST_END\t\t(OMAP34XX_SDRC_CS0 + \\\n \t\t\t\t\t0x01F00000) /* 31MB */\n \n-#define CONFIG_SYS_LOAD_ADDR\t\t(OMAP34XX_SDRC_CS0) /* default load */\n-\t\t\t\t\t\t\t\t/* address */\n-\n-/*\n- * AM3517 has 12 GP timers, they can be driven by the system clock\n- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).\n- * This rate is divided by a local divisor.\n- */\n-#define CONFIG_SYS_TIMERBASE\t\tOMAP34XX_GPT2\n-#define CONFIG_SYS_PTV\t\t\t2\t/* Divisor: 2^(PTV+1) => 8 */\n-\n /* Physical Memory Map */\n-#define PHYS_SDRAM_1\t\t\tOMAP34XX_SDRC_CS0\n-#define PHYS_SDRAM_2\t\t\tOMAP34XX_SDRC_CS1\n #define CONFIG_SYS_CS0_SIZE\t\t(256 * 1024 * 1024)\n-#define CONFIG_SYS_SDRAM_BASE\t\tPHYS_SDRAM_1\n #define CONFIG_SYS_INIT_RAM_ADDR\t0x4020f800\n #define CONFIG_SYS_INIT_RAM_SIZE\t0x800\n-#define CONFIG_SYS_INIT_SP_ADDR\t\t(CONFIG_SYS_INIT_RAM_ADDR + \\\n-\t\t\t\t\t CONFIG_SYS_INIT_RAM_SIZE - \\\n-\t\t\t\t\t GENERATED_GBL_DATA_SIZE)\n \n /* FLASH and environment organization */\n \n@@ -284,11 +245,12 @@\n \n /* Defines for SPL */\n #define CONFIG_SPL_FRAMEWORK\n-#define CONFIG_SPL_NAND_SIMPLE\n+#undef CONFIG_SPL_TEXT_BASE\n #define CONFIG_SPL_TEXT_BASE\t\t0x40200000\n #define CONFIG_SPL_MAX_SIZE\t\t(SRAM_SCRATCH_SPACE_ADDR - \\\n \t\t\t\t\t CONFIG_SPL_TEXT_BASE)\n \n+#undef CONFIG_SPL_BSS_START_ADDR\n #define CONFIG_SPL_BSS_START_ADDR\t0x80000000\n #define CONFIG_SPL_BSS_MAX_SIZE\t\t0x80000\t\t/* 512 KB */\n \n", "prefixes": [ "U-Boot", "V2", "1/2" ] }