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{
    "id": 809604,
    "url": "http://patchwork.ozlabs.org/api/1.2/patches/809604/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170904104655.29103-6-ran.wang_1@nxp.com/",
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        "name": "U-Boot",
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    "msgid": "<20170904104655.29103-6-ran.wang_1@nxp.com>",
    "list_archive_url": null,
    "date": "2017-09-04T10:46:52",
    "name": "[U-Boot,v5,6/9] armv7: Add workaround for USB erratum A-009008",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
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    "submitter": {
        "id": 71939,
        "url": "http://patchwork.ozlabs.org/api/1.2/people/71939/?format=api",
        "name": "Ran Wang",
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        "username": "yorksun",
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    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170904104655.29103-6-ran.wang_1@nxp.com/mbox/",
    "series": [
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            "id": 1355,
            "url": "http://patchwork.ozlabs.org/api/1.2/series/1355/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=1355",
            "date": "2017-09-04T10:46:47",
            "name": "[U-Boot,v5,1/9] armv8: Add scfg_clrsetbits_32(), scfg_clrbits_32()",
            "version": 5,
            "mbox": "http://patchwork.ozlabs.org/series/1355/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/809604/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/809604/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Ran Wang <ran.wang_1@nxp.com>",
        "To": "open list <u-boot@lists.denx.de>, York Sun <york.sun@nxp.com>",
        "Date": "Mon, 4 Sep 2017 18:46:52 +0800",
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        "References": "<20170904104655.29103-1-ran.wang_1@nxp.com>",
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        "Cc": "Priyanka Jain <priyanka.jain@nxp.com>,\n\tSuresh Gupta <suresh.bhagat@nxp.com>, ran.wang_1@nxp.com",
        "Subject": "[U-Boot] [PATCH v5 6/9] armv7: Add workaround for USB erratum\n\tA-009008",
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    },
    "content": "USB High Speed (HS) EYE Height Adjustment\nUSB HS speed eye diagram fails with the default value at\nmany corners, particularly at a high temperature\n\nOptimal eye at TXREFTUNE value to 0x9 is observed, change\nset the same value.\n\nSigned-off-by: Sriram Dash <sriram.dash@nxp.com>\nSigned-off-by: Suresh Gupta <suresh.gupta@nxp.com>\nSigned-off-by: Ran Wang <ran.wang_1@nxp.com>\n---\nChange in v4:\n\tUse clrsetbits_be32() instead.\n\nChange in v4:\n\tChange 1001 to 0x9 in the commit message to match the code.\n\tClean up the math in register setting.\n\tRename USB_TXVREFTUNE TO SCFG_USB_TXVREFTUNE.\n\nChange in v3:\n- none\n\nChange in v2:\n\tIn function erratum_a009008():\n\t1.Put a blank line after variable declaration.\n\n arch/arm/cpu/armv7/ls102xa/Kconfig                |  6 ++++++\n arch/arm/cpu/armv7/ls102xa/soc.c                  | 15 +++++++++++++++\n arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  4 ++++\n 3 files changed, 25 insertions(+)",
    "diff": "diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig\nindex fadfce4f05..599cc28249 100644\n--- a/arch/arm/cpu/armv7/ls102xa/Kconfig\n+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig\n@@ -5,6 +5,7 @@ config ARCH_LS1021A\n \tselect SYS_FSL_ERRATUM_A009663\n \tselect SYS_FSL_ERRATUM_A009942\n \tselect SYS_FSL_ERRATUM_A010315\n+\tselect SYS_FSL_ERRATUM_A009008\n \tselect SYS_FSL_SRDS_1\n \tselect SYS_HAS_SERDES\n \tselect SYS_FSL_DDR_BE if SYS_FSL_DDR\n@@ -52,6 +53,11 @@ config SECURE_BOOT\n config SYS_FSL_ERRATUM_A010315\n \tbool \"Workaround for PCIe erratum A010315\"\n \n+config SYS_FSL_ERRATUM_A009008\n+\tbool\n+\thelp\n+\t\tWorkaround for USB erratum A009008\n+\n config SYS_FSL_SRDS_1\n \tbool\n \ndiff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c\nindex b84a1a686a..1c59a62a0e 100644\n--- a/arch/arm/cpu/armv7/ls102xa/soc.c\n+++ b/arch/arm/cpu/armv7/ls102xa/soc.c\n@@ -60,6 +60,18 @@ unsigned int get_soc_major_rev(void)\n \treturn major;\n }\n \n+static void erratum_a009008(void)\n+{\n+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008\n+\tu32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;\n+\n+\tclrsetbits_be32(scfg + SCFG_USB3PRM1CR / 4,\n+\t\t\t0xF << 6,\n+\t\t\tSCFG_USB_TXVREFTUNE << 6);\n+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */\n+}\n+\n+\n void s_init(void)\n {\n }\n@@ -146,6 +158,9 @@ int arch_soc_init(void)\n \t */\n \tout_be32(&scfg->eddrtqcfg, 0x63b20042);\n \n+\t/* Erratum */\n+\terratum_a009008();\n+\n \treturn 0;\n }\n \ndiff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\nindex c34fd63e66..ba59f40382 100644\n--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\n+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\n@@ -173,6 +173,10 @@ struct ccsr_gur {\n #define SCFG_PMCINTECR_ETSECERRG1\t0x00040000\n #define SCFG_CLUSTERPMCR_WFIL2EN\t0x80000000\n \n+#define SCFG_BASE\t\t\t0x01570000\n+#define SCFG_USB3PRM1CR\t\t\t0x070\n+#define SCFG_USB_TXVREFTUNE\t\t0x9\n+\n /* Supplemental Configuration Unit */\n struct ccsr_scfg {\n \tu32 dpslpcr;\n",
    "prefixes": [
        "U-Boot",
        "v5",
        "6/9"
    ]
}