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{
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    "url": "http://patchwork.ozlabs.org/api/1.2/patches/809600/?format=api",
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    "date": "2017-09-04T10:46:53",
    "name": "[U-Boot,v5,7/9] armv7: Add workaround for USB erratum A-009798",
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        "name": "Ran Wang",
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            "date": "2017-09-04T10:46:47",
            "name": "[U-Boot,v5,1/9] armv8: Add scfg_clrsetbits_32(), scfg_clrbits_32()",
            "version": 5,
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    "tags": {},
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        "From": "Ran Wang <ran.wang_1@nxp.com>",
        "To": "open list <u-boot@lists.denx.de>, York Sun <york.sun@nxp.com>",
        "Date": "Mon, 4 Sep 2017 18:46:53 +0800",
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        "Cc": "Priyanka Jain <priyanka.jain@nxp.com>,\n\tSuresh Gupta <suresh.bhagat@nxp.com>, ran.wang_1@nxp.com",
        "Subject": "[U-Boot] [PATCH v5 7/9] armv7: Add workaround for USB erratum\n\tA-009798",
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    },
    "content": "The default setting for USB High Speed Squelch Threshold results\nin a threshold close to or lower than 100mV. This leads to Receive\nCompliance test failure for a 100mV threshold.\n\nShift the threshold from ~100mV towards ~130mV by setting SQRXTUNE\nto 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.\n\nSigned-off-by: Sriram Dash <sriram.dash@nxp.com>\nSigned-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>\nSigned-off-by: Suresh Gupta <suresh.gupta@nxp.com>\nSigned-off-by: Ran Wang <ran.wang_1@nxp.com>\n---\nChange in v5:\n\tUse clrbits_be32() instead.\n\nChange in v4:\n\tUpdate commit message about register setting.\n\tClean up the math in register setting.\n\tRedefine SQRXTUNE to make code clearer.\n\nChange in v3:\n- none\n\nChange in v2:\n\tIn function erratum_a009798():\n\t1.Put a blank line after variable declaration.\n\n arch/arm/cpu/armv7/ls102xa/Kconfig                |  8 +++++++-\n arch/arm/cpu/armv7/ls102xa/soc.c                  | 10 ++++++++++\n arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  1 +\n 3 files changed, 18 insertions(+), 1 deletion(-)",
    "diff": "diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig\nindex 599cc28249..f09766cf03 100644\n--- a/arch/arm/cpu/armv7/ls102xa/Kconfig\n+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig\n@@ -6,6 +6,7 @@ config ARCH_LS1021A\n \tselect SYS_FSL_ERRATUM_A009942\n \tselect SYS_FSL_ERRATUM_A010315\n \tselect SYS_FSL_ERRATUM_A009008\n+\tselect SYS_FSL_ERRATUM_A009798\n \tselect SYS_FSL_SRDS_1\n \tselect SYS_HAS_SERDES\n \tselect SYS_FSL_DDR_BE if SYS_FSL_DDR\n@@ -56,7 +57,12 @@ config SYS_FSL_ERRATUM_A010315\n config SYS_FSL_ERRATUM_A009008\n \tbool\n \thelp\n-\t\tWorkaround for USB erratum A009008\n+\t\tWorkaround for USB PHY erratum A009008\n+\n+config SYS_FSL_ERRATUM_A009798\n+\tbool\n+\thelp\n+\t\tWorkaround for USB PHY erratum A009798\n \n config SYS_FSL_SRDS_1\n \tbool\ndiff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c\nindex 1c59a62a0e..a0e3c85421 100644\n--- a/arch/arm/cpu/armv7/ls102xa/soc.c\n+++ b/arch/arm/cpu/armv7/ls102xa/soc.c\n@@ -71,6 +71,15 @@ static void erratum_a009008(void)\n #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */\n }\n \n+static void erratum_a009798(void)\n+{\n+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798\n+\tu32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;\n+\n+\tclrbits_be32(scfg + SCFG_USB3PRM1CR / 4,\n+\t\t\tSCFG_USB_SQRXTUNE_MASK << 23);\n+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */\n+}\n \n void s_init(void)\n {\n@@ -160,6 +169,7 @@ int arch_soc_init(void)\n \n \t/* Erratum */\n \terratum_a009008();\n+\terratum_a009798();\n \n \treturn 0;\n }\ndiff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\nindex ba59f40382..5762d3308a 100644\n--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\n+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\n@@ -176,6 +176,7 @@ struct ccsr_gur {\n #define SCFG_BASE\t\t\t0x01570000\n #define SCFG_USB3PRM1CR\t\t\t0x070\n #define SCFG_USB_TXVREFTUNE\t\t0x9\n+#define SCFG_USB_SQRXTUNE_MASK\t\t0x7\n \n /* Supplemental Configuration Unit */\n struct ccsr_scfg {\n",
    "prefixes": [
        "U-Boot",
        "v5",
        "7/9"
    ]
}