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{
    "id": 809599,
    "url": "http://patchwork.ozlabs.org/api/1.2/patches/809599/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170904104655.29103-5-ran.wang_1@nxp.com/",
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    "msgid": "<20170904104655.29103-5-ran.wang_1@nxp.com>",
    "list_archive_url": null,
    "date": "2017-09-04T10:46:51",
    "name": "[U-Boot,v5,5/9] armv8: Add workaround for USB erratum A-009007",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "bff937ab194eeb0ba9b0f50e666efd12dd95a8e4",
    "submitter": {
        "id": 71939,
        "url": "http://patchwork.ozlabs.org/api/1.2/people/71939/?format=api",
        "name": "Ran Wang",
        "email": "ran.wang_1@nxp.com"
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        "username": "yorksun",
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        "last_name": "Sun",
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    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170904104655.29103-5-ran.wang_1@nxp.com/mbox/",
    "series": [
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            "url": "http://patchwork.ozlabs.org/api/1.2/series/1355/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=1355",
            "date": "2017-09-04T10:46:47",
            "name": "[U-Boot,v5,1/9] armv8: Add scfg_clrsetbits_32(), scfg_clrbits_32()",
            "version": 5,
            "mbox": "http://patchwork.ozlabs.org/series/1355/mbox/"
        }
    ],
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    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/809599/checks/",
    "tags": {},
    "related": [],
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        "From": "Ran Wang <ran.wang_1@nxp.com>",
        "To": "open list <u-boot@lists.denx.de>, York Sun <york.sun@nxp.com>",
        "Date": "Mon, 4 Sep 2017 18:46:51 +0800",
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        "Cc": "Priyanka Jain <priyanka.jain@nxp.com>,\n\tSuresh Gupta <suresh.bhagat@nxp.com>, ran.wang_1@nxp.com",
        "Subject": "[U-Boot] [PATCH v5 5/9] armv8: Add workaround for USB erratum\n\tA-009007",
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    },
    "content": "Rx Compliance tests may fail intermittently at high\njitter frequencies using default register values.\n\nProgram register USB_PHY_RX_OVRD_IN_HI in certain sequence\nto make the Rx compliance test pass.\n\nSigned-off-by: Sriram Dash <sriram.dash@nxp.com>\nSigned-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>\nSigned-off-by: Suresh Gupta <suresh.bhagat@nxp.com>\nSigned-off-by: Ran Wang <ran.wang_1@nxp.com>\n---\nChange in v5:\n- none\n\nChange in v4:\n\tUpdate commit message about register setting.\n\tRename some registers which belong to SCFG.\n\nChange in v3:\n- none\n\nChange in v2:\n\tIn function erratum_a009007():\n\t1.Put a blank line after variable declaration.\n\t2.Create a mcro to run for each USB for easier to read and maintain.\n\n arch/arm/cpu/armv8/fsl-layerscape/Kconfig          | 12 ++++++-\n arch/arm/cpu/armv8/fsl-layerscape/soc.c            | 40 ++++++++++++++++++++++\n .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  8 +++++\n .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  9 +++++\n 4 files changed, 68 insertions(+), 1 deletion(-)",
    "diff": "diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\nindex 9449d629ea..c5c5f4e130 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n@@ -25,6 +25,7 @@ config ARCH_LS1043A\n \tselect SYS_FSL_ERRATUM_A009008\n \tselect SYS_FSL_ERRATUM_A009798\n \tselect SYS_FSL_ERRATUM_A008997\n+\tselect SYS_FSL_ERRATUM_A009007\n \tselect SYS_FSL_HAS_DDR3\n \tselect SYS_FSL_HAS_DDR4\n \tselect ARCH_EARLY_INIT_R\n@@ -50,6 +51,7 @@ config ARCH_LS1046A\n \tselect SYS_FSL_ERRATUM_A009008\n \tselect SYS_FSL_ERRATUM_A009798\n \tselect SYS_FSL_ERRATUM_A008997\n+\tselect SYS_FSL_ERRATUM_A009007\n \tselect SYS_FSL_HAS_DDR4\n \tselect SYS_FSL_SRDS_2\n \tselect ARCH_EARLY_INIT_R\n@@ -89,6 +91,7 @@ config ARCH_LS2080A\n \tselect SYS_FSL_ERRATUM_A009008\n \tselect SYS_FSL_ERRATUM_A009798\n \tselect SYS_FSL_ERRATUM_A008997\n+\tselect SYS_FSL_ERRATUM_A009007\n \tselect ARCH_EARLY_INIT_R\n \tselect BOARD_EARLY_INIT_F\n \n@@ -239,7 +242,14 @@ config SYS_FSL_ERRATUM_A009798\n \tbool \"Workaround for USB PHY erratum A009798\"\n \n config SYS_FSL_ERRATUM_A008997\n-\tbool \"Workaround for USB PHY erratum A008997\"\n+\tbool\n+\thelp\n+\t\tWorkaround for USB PHY erratum A008997\n+\n+config SYS_FSL_ERRATUM_A009007\n+\tbool\n+\thelp\n+\t\tWorkaround for USB PHY erratum A009007\n \n config MAX_CPUS\n \tint \"Maximum number of CPUs permitted for Layerscape\"\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\nindex 99fba5fcaa..dce6912166 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n@@ -117,6 +117,44 @@ static void erratum_a008997(void)\n #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */\n }\n \n+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)\n+\n+#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy)\t\\\n+\tout_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);\t\\\n+\tout_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);\t\\\n+\tout_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);\t\\\n+\tout_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)\n+\n+#elif defined(CONFIG_ARCH_LS2080A)\n+\n+#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy)\t\\\n+\tout_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \\\n+\tout_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \\\n+\tout_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \\\n+\tout_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)\n+\n+#endif\n+\n+static void erratum_a009007(void)\n+{\n+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)\n+\tvoid __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;\n+\n+\tPROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);\n+\n+\tusb_phy = (void __iomem *)SCFG_USB_PHY2;\n+\tPROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);\n+\n+\tusb_phy = (void __iomem *)SCFG_USB_PHY3;\n+\tPROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);\n+#elif defined(CONFIG_ARCH_LS2080A)\n+\tvoid __iomem *dcsr = (void __iomem *)DCSR_BASE;\n+\n+\tPROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);\n+\tPROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);\n+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */\n+}\n+\n #if defined(CONFIG_FSL_LSCH3)\n /*\n  * This erratum requires setting a value to eddrtqcr1 to\n@@ -266,6 +304,7 @@ void fsl_lsch3_early_init_f(void)\n \terratum_a009008();\n \terratum_a009798();\n \terratum_a008997();\n+\terratum_a009007();\n #ifdef CONFIG_CHAIN_OF_TRUST\n \t/* In case of Secure Boot, the IBR configures the SMMU\n \t* to allow only Secure transactions.\n@@ -544,6 +583,7 @@ void fsl_lsch2_early_init_f(void)\n \terratum_a009008();\n \terratum_a009798();\n \terratum_a008997();\n+\terratum_a009007();\n }\n #endif\n \ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\nindex 1601ec6baa..130dc4bfbe 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\n@@ -348,6 +348,14 @@ struct ccsr_gur {\n #define SCFG_USB_TXVREFTUNE\t\t\t0x9\n #define SCFG_USB_SQRXTUNE_MASK\t\t0x7\n #define SCFG_USB_PCSTXSWINGFULL\t\t0x47\n+#define SCFG_USB_PHY1\t\t\t0x084F0000\n+#define SCFG_USB_PHY2\t\t\t0x08500000\n+#define SCFG_USB_PHY3\t\t\t0x08510000\n+#define SCFG_USB_PHY_RX_OVRD_IN_HI\t\t0x200c\n+#define USB_PHY_RX_EQ_VAL_1\t\t0x0000\n+#define USB_PHY_RX_EQ_VAL_2\t\t0x0080\n+#define USB_PHY_RX_EQ_VAL_3\t\t0x0380\n+#define USB_PHY_RX_EQ_VAL_4\t\t0x0b80\n \n #define SCFG_SNPCNFGCR_SECRDSNP\t\t0x80000000\n #define SCFG_SNPCNFGCR_SECWRSNP\t\t0x40000000\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\nindex 3b2e9eaa8b..3e03d7b4c3 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n@@ -137,6 +137,15 @@\n #define SCFG_USB_SQRXTUNE_MASK\t0x7\n #define SCFG_QSPICLKCTLR\t0x10\n \n+#define DCSR_BASE\t\t0x700000000ULL\n+#define DCSR_USB_PHY1\t\t\t0x4600000\n+#define DCSR_USB_PHY2\t\t\t0x4610000\n+#define DCSR_USB_PHY_RX_OVRD_IN_HI\t0x200C\n+#define USB_PHY_RX_EQ_VAL_1\t\t0x0000\n+#define USB_PHY_RX_EQ_VAL_2\t\t0x0080\n+#define USB_PHY_RX_EQ_VAL_3\t\t0x0380\n+#define USB_PHY_RX_EQ_VAL_4\t\t0x0b80\n+\n #define TP_ITYP_AV\t\t0x00000001\t/* Initiator available */\n #define TP_ITYP_TYPE(x)\t(((x) & 0x6) >> 1)\t/* Initiator Type */\n #define TP_ITYP_TYPE_ARM\t0x0\n",
    "prefixes": [
        "U-Boot",
        "v5",
        "5/9"
    ]
}