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GET /api/1.2/patches/809598/?format=api
{ "id": 809598, "url": "http://patchwork.ozlabs.org/api/1.2/patches/809598/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170904104655.29103-3-ran.wang_1@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170904104655.29103-3-ran.wang_1@nxp.com>", "list_archive_url": null, "date": "2017-09-04T10:46:49", "name": "[U-Boot,v5,3/9] armv8: Add workaround for USB erratum A-009798", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "0441ee9de6be91d57653cdba72c8b3cc7e458ff6", "submitter": { "id": 71939, "url": "http://patchwork.ozlabs.org/api/1.2/people/71939/?format=api", "name": "Ran Wang", "email": "ran.wang_1@nxp.com" }, "delegate": { "id": 2666, "url": "http://patchwork.ozlabs.org/api/1.2/users/2666/?format=api", "username": "yorksun", "first_name": "York", "last_name": "Sun", "email": "yorksun@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170904104655.29103-3-ran.wang_1@nxp.com/mbox/", "series": [ { "id": 1355, "url": "http://patchwork.ozlabs.org/api/1.2/series/1355/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=1355", "date": "2017-09-04T10:46:47", "name": "[U-Boot,v5,1/9] armv8: Add scfg_clrsetbits_32(), scfg_clrbits_32()", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/1355/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/809598/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/809598/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Mon, 4 Sep 2017 04:04:14 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=BAD_ENC_HEADER,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tSPF_HELO_PASS\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.158.2 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.158.2; helo=az84smr01.freescale.net;", "From": "Ran Wang <ran.wang_1@nxp.com>", "To": "open list <u-boot@lists.denx.de>, York Sun <york.sun@nxp.com>", "Date": "Mon, 4 Sep 2017 18:46:49 +0800", "Message-ID": "<20170904104655.29103-3-ran.wang_1@nxp.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170904104655.29103-1-ran.wang_1@nxp.com>", "References": "<20170904104655.29103-1-ran.wang_1@nxp.com>", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131489966583833377;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); 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BCL:0; PCL:0;\n\tRULEID:(300000500095)(300135000095)(300000501095)(300135300095)(300000502095)(300135100095)(22001)(300000503095)(300135400095)(2017052603199)(201703131430075)(201703131517081)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);\n\tSRVR:BN3PR03MB2259; ", "X-MS-TrafficTypeDiagnostic": "BN3PR03MB2259:", "X-Exchange-Antispam-Report-Test": "UriScan:(185117386973197);", "X-Microsoft-Antispam-PRVS": "<BN3PR03MB22593105752A976E1866A725F1910@BN3PR03MB2259.namprd03.prod.outlook.com>", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6095135)(2401047)(8121501046)(5005006)(3002001)(10201501046)(93006095)(93001095)(100000703101)(100105400095)(6055026)(6096035)(20161123563025)(20161123565025)(20161123559100)(201703131430075)(201703131433075)(201703131448075)(201703161259150)(201703151042153)(20161123556025)(20161123561025)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:BN3PR03MB2259; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:BN3PR03MB2259; ", "X-Forefront-PRVS": "0420213CCD", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 Sep 2017 11:04:18.1493\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.158.2]; \n\tHelo=[az84smr01.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN3PR03MB2259", "Cc": "Priyanka Jain <priyanka.jain@nxp.com>,\n\tSuresh Gupta <suresh.bhagat@nxp.com>, ran.wang_1@nxp.com", "Subject": "[U-Boot] [PATCH v5 3/9] armv8: Add workaround for USB erratum\n\tA-009798", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "The default setting for USB High Speed Squelch Threshold results\nin a threshold close to or lower than 100mV. This leads to Receiver\nCompliance test failure for a 100mV threshold.\n\nShift the threshold from ~100mV towards ~130mV by setting SQRXTUNE\nto 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.\n\nSigned-off-by: Sriram Dash <sriram.dash@nxp.com>\nSigned-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>\nSigned-off-by: Suresh Gupta <suresh.gupta@nxp.com>\nSigned-off-by: Ran Wang <ran.wang_1@nxp.com>\n---\nChange in v5:\n\tUse scfg_clrbits32() instead.\n\nChange in v4:\n\tUpdate commit message about register setting.\n\tClean up the math in set_usb_sqrxtune().\n\tRename USB_TXVREFTUNE to SCFG_USB_TXVREFTUNE.\n\nChange in v3:\n\tUse inline function to make code cleaner.\n\nChange in v2:\n\tIn function erratum_a009798():\n\t1.Put a blank line after variable declaration.\n\t2.Move common code together.\n\n arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 5 +++++\n arch/arm/cpu/armv8/fsl-layerscape/soc.c | 24 ++++++++++++++++++++++\n .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 +\n .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +\n 4 files changed, 31 insertions(+)", "diff": "diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\nindex d8936a4334..6677f2309a 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n@@ -23,6 +23,7 @@ config ARCH_LS1043A\n \tselect SYS_FSL_ERRATUM_A010315\n \tselect SYS_FSL_ERRATUM_A010539\n \tselect SYS_FSL_ERRATUM_A009008\n+\tselect SYS_FSL_ERRATUM_A009798\n \tselect SYS_FSL_HAS_DDR3\n \tselect SYS_FSL_HAS_DDR4\n \tselect ARCH_EARLY_INIT_R\n@@ -46,6 +47,7 @@ config ARCH_LS1046A\n \tselect SYS_FSL_ERRATUM_A010165\n \tselect SYS_FSL_ERRATUM_A010539\n \tselect SYS_FSL_ERRATUM_A009008\n+\tselect SYS_FSL_ERRATUM_A009798\n \tselect SYS_FSL_HAS_DDR4\n \tselect SYS_FSL_SRDS_2\n \tselect ARCH_EARLY_INIT_R\n@@ -83,6 +85,7 @@ config ARCH_LS2080A\n \tselect SYS_FSL_ERRATUM_A010165\n \tselect SYS_FSL_ERRATUM_A009203\n \tselect SYS_FSL_ERRATUM_A009008\n+\tselect SYS_FSL_ERRATUM_A009798\n \tselect ARCH_EARLY_INIT_R\n \tselect BOARD_EARLY_INIT_F\n \n@@ -229,6 +232,8 @@ config SYS_FSL_ERRATUM_A010539\n config SYS_FSL_ERRATUM_A009008\n \tbool \"Workaround for USB PHY erratum A009008\"\n \n+config SYS_FSL_ERRATUM_A009798\n+\tbool \"Workaround for USB PHY erratum A009798\"\n \n config MAX_CPUS\n \tint \"Maximum number of CPUs permitted for Layerscape\"\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\nindex ea71fa0dc7..6238953658 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n@@ -63,6 +63,7 @@ static void erratum_a009008(void)\n {\n #ifdef CONFIG_SYS_FSL_ERRATUM_A009008\n \tu32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;\n+\n #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)\n \tset_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);\n \tset_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);\n@@ -73,6 +74,27 @@ static void erratum_a009008(void)\n #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */\n }\n \n+static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)\n+{\n+\tscfg_clrbits32(scfg + offset / 4,\n+\t\t\tSCFG_USB_SQRXTUNE_MASK << 23);\n+}\n+\n+static void erratum_a009798(void)\n+{\n+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798\n+\tu32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;\n+\n+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)\n+\tset_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);\n+\tset_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);\n+\tset_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);\n+#elif defined(CONFIG_ARCH_LS2080A)\n+\tset_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);\n+#endif\n+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */\n+}\n+\n #if defined(CONFIG_FSL_LSCH3)\n /*\n * This erratum requires setting a value to eddrtqcr1 to\n@@ -220,6 +242,7 @@ void fsl_lsch3_early_init_f(void)\n \terratum_a008514();\n \terratum_a008336();\n \terratum_a009008();\n+\terratum_a009798();\n #ifdef CONFIG_CHAIN_OF_TRUST\n \t/* In case of Secure Boot, the IBR configures the SMMU\n \t* to allow only Secure transactions.\n@@ -496,6 +519,7 @@ void fsl_lsch2_early_init_f(void)\n \terratum_a009660();\n \terratum_a010539();\n \terratum_a009008();\n+\terratum_a009798();\n }\n #endif\n \ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\nindex c60d8ddfa2..323c098888 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\n@@ -343,6 +343,7 @@ struct ccsr_gur {\n #define SCFG_USB3PRM1CR_USB2\t\t0x07C\n #define SCFG_USB3PRM1CR_USB3\t\t0x088\n #define SCFG_USB_TXVREFTUNE\t\t\t0x9\n+#define SCFG_USB_SQRXTUNE_MASK\t\t0x7\n \n #define SCFG_SNPCNFGCR_SECRDSNP\t\t0x80000000\n #define SCFG_SNPCNFGCR_SECWRSNP\t\t0x40000000\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\nindex 01b24d03f1..3b2e9eaa8b 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n@@ -134,6 +134,7 @@\n #define SCFG_USB3PRM1CR\t\t\t0x000\n #define SCFG_USB3PRM1CR_INIT\t\t0x27672b2a\n #define SCFG_USB_TXVREFTUNE\t\t0x9\n+#define SCFG_USB_SQRXTUNE_MASK\t0x7\n #define SCFG_QSPICLKCTLR\t0x10\n \n #define TP_ITYP_AV\t\t0x00000001\t/* Initiator available */\n", "prefixes": [ "U-Boot", "v5", "3/9" ] }