Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.2/patches/809207/?format=api
{ "id": 809207, "url": "http://patchwork.ozlabs.org/api/1.2/patches/809207/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/20170903042117.28923-12-saeedm@mellanox.com/", "project": { "id": 7, "url": "http://patchwork.ozlabs.org/api/1.2/projects/7/?format=api", "name": "Linux network development", "link_name": "netdev", "list_id": "netdev.vger.kernel.org", "list_email": "netdev@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170903042117.28923-12-saeedm@mellanox.com>", "list_archive_url": null, "date": "2017-09-03T04:21:11", "name": "[net-next,11/17] net/mlx5e: Type-specific optimizations for RX post WQEs function", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a75f3eaebc6ac673093004a410884c19e126f3a5", "submitter": { "id": 65299, "url": "http://patchwork.ozlabs.org/api/1.2/people/65299/?format=api", "name": "Saeed Mahameed", "email": "saeedm@mellanox.com" }, "delegate": { "id": 34, "url": "http://patchwork.ozlabs.org/api/1.2/users/34/?format=api", "username": "davem", "first_name": "David", "last_name": "Miller", "email": "davem@davemloft.net" }, "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/20170903042117.28923-12-saeedm@mellanox.com/mbox/", "series": [ { "id": 1196, "url": "http://patchwork.ozlabs.org/api/1.2/series/1196/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/list/?series=1196", "date": "2017-09-03T04:21:09", "name": "[net-next,01/17] net/mlx5e: Reorganize struct mlx5e_rq", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1196/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/809207/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/809207/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<netdev-owner@vger.kernel.org>", "X-Original-To": "patchwork-incoming@ozlabs.org", "Delivered-To": "patchwork-incoming@ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xlKbH2PR4z9s7C\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSun, 3 Sep 2017 14:23:07 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752157AbdICEXF (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tSun, 3 Sep 2017 00:23:05 -0400", "from mail-il-dmz.mellanox.com ([193.47.165.129]:60072 \"EHLO\n\tmellanox.co.il\" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org\n\twith ESMTP id S1751287AbdICEWN (ORCPT\n\t<rfc822;netdev@vger.kernel.org>); Sun, 3 Sep 2017 00:22:13 -0400", "from Internal Mail-Server by MTLPINE1 (envelope-from\n\tsaeedm@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 3 Sep 2017 07:22:06 +0300", "from sws.mtl.labs.mlnx (reg-l-vrt-045-015.mtl.labs.mlnx\n\t[10.135.45.15])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id v834M5lC017672;\n\tSun, 3 Sep 2017 07:22:06 +0300" ], "From": "Saeed Mahameed <saeedm@mellanox.com>", "To": "\"David S. Miller\" <davem@davemloft.net>", "Cc": "netdev@vger.kernel.org, kernel-team@fb.com,\n\tTariq Toukan <tariqt@mellanox.com>, Saeed Mahameed <saeedm@mellanox.com>", "Subject": "[net-next 11/17] net/mlx5e: Type-specific optimizations for RX post\n\tWQEs function", "Date": "Sun, 3 Sep 2017 07:21:11 +0300", "Message-Id": "<20170903042117.28923-12-saeedm@mellanox.com>", "X-Mailer": "git-send-email 2.13.0", "In-Reply-To": "<20170903042117.28923-1-saeedm@mellanox.com>", "References": "<20170903042117.28923-1-saeedm@mellanox.com>", "Sender": "netdev-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<netdev.vger.kernel.org>", "X-Mailing-List": "netdev@vger.kernel.org" }, "content": "From: Tariq Toukan <tariqt@mellanox.com>\n\nSeparate the RX post WQEs function of the different RQ types.\nThis enables RQ type-specific optimizations in data-path.\n\nPoll the ICOSQ completion queue only for Striding RQ,\nand only when a UMR post completion could be possibly available.\n\nSigned-off-by: Tariq Toukan <tariqt@mellanox.com>\nSigned-off-by: Saeed Mahameed <saeedm@mellanox.com>\n---\n drivers/net/ethernet/mellanox/mlx5/core/en.h | 10 +--\n drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 4 +-\n drivers/net/ethernet/mellanox/mlx5/core/en_rx.c | 101 ++++++++++++++++++----\n drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c | 64 +-------------\n 4 files changed, 92 insertions(+), 87 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h\nindex bce2080eb86a..8d29a6eb9406 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/en.h\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h\n@@ -517,7 +517,7 @@ struct mlx5e_page_cache {\n \n struct mlx5e_rq;\n typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);\n-typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq*, struct mlx5e_rx_wqe*, u16);\n+typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);\n typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);\n \n struct mlx5e_rq {\n@@ -547,6 +547,7 @@ struct mlx5e_rq {\n \t\tu8 map_dir; /* dma map direction */\n \t} buff;\n \n+\tstruct mlx5e_channel *channel;\n \tstruct device *pdev;\n \tstruct net_device *netdev;\n \tstruct mlx5e_tstamp *tstamp;\n@@ -555,7 +556,7 @@ struct mlx5e_rq {\n \tstruct mlx5e_page_cache page_cache;\n \n \tmlx5e_fp_handle_rx_cqe handle_rx_cqe;\n-\tmlx5e_fp_alloc_wqe alloc_wqe;\n+\tmlx5e_fp_post_rx_wqes post_wqes;\n \tmlx5e_fp_dealloc_wqe dealloc_wqe;\n \n \tunsigned long state;\n@@ -572,7 +573,6 @@ struct mlx5e_rq {\n \t__be32 mkey_be;\n \tu8 wq_type;\n \tu32 rqn;\n-\tstruct mlx5e_channel *channel;\n \tstruct mlx5_core_dev *mdev;\n \tstruct mlx5_core_mkey umr_mkey;\n } ____cacheline_aligned_in_smp;\n@@ -853,11 +853,9 @@ void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,\n void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);\n void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);\n bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);\n-int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);\n-int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,\tu16 ix);\n+bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq);\n void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);\n void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);\n-void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq);\n void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);\n \n void mlx5e_rx_am(struct mlx5e_rq *rq);\ndiff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c\nindex 2767a3ee81bc..162ba6ab749a 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c\n@@ -598,7 +598,7 @@ static int mlx5e_alloc_rq(struct mlx5e_channel *c,\n \tswitch (rq->wq_type) {\n \tcase MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:\n \n-\t\trq->alloc_wqe = mlx5e_alloc_rx_mpwqe;\n+\t\trq->post_wqes = mlx5e_post_rx_mpwqes;\n \t\trq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;\n \n \t\trq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;\n@@ -637,7 +637,7 @@ static int mlx5e_alloc_rq(struct mlx5e_channel *c,\n \t\t\terr = -ENOMEM;\n \t\t\tgoto err_rq_wq_destroy;\n \t\t}\n-\t\trq->alloc_wqe = mlx5e_alloc_rx_wqe;\n+\t\trq->post_wqes = mlx5e_post_rx_wqes;\n \t\trq->dealloc_wqe = mlx5e_dealloc_rx_wqe;\n \n #ifdef CONFIG_MLX5_EN_IPSEC\ndiff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c\nindex 11dba9940029..b236dfd71c18 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c\n@@ -252,7 +252,7 @@ static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq,\n \t\t!mlx5e_page_is_reserved(wi->di.page);\n }\n \n-int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)\n+static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)\n {\n \tstruct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];\n \n@@ -417,18 +417,13 @@ void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)\n \t}\n }\n \n-void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)\n+static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)\n {\n \tstruct mlx5_wq_ll *wq = &rq->wq;\n \tstruct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);\n \n \trq->mpwqe.umr_in_progress = false;\n \n-\tif (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) {\n-\t\tmlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);\n-\t\treturn;\n-\t}\n-\n \tmlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));\n \n \t/* ensure wqes are visible to device before updating doorbell record */\n@@ -437,19 +432,18 @@ void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)\n \tmlx5_wq_ll_update_db_record(wq);\n }\n \n-int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)\n+static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)\n {\n \tint err;\n \n-\tif (rq->mpwqe.umr_in_progress)\n-\t\treturn -EBUSY;\n-\n \terr = mlx5e_alloc_rx_umr_mpwqe(rq, ix);\n-\tif (unlikely(err))\n+\tif (unlikely(err)) {\n+\t\trq->stats.buff_alloc_err++;\n \t\treturn err;\n+\t}\n \trq->mpwqe.umr_in_progress = true;\n \tmlx5e_post_umr_wqe(rq, ix);\n-\treturn -EBUSY;\n+\treturn 0;\n }\n \n void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)\n@@ -473,9 +467,7 @@ bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)\n \tdo {\n \t\tstruct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);\n \n-\t\terr = rq->alloc_wqe(rq, wqe, wq->head);\n-\t\tif (err == -EBUSY)\n-\t\t\treturn true;\n+\t\terr = mlx5e_alloc_rx_wqe(rq, wqe, wq->head);\n \t\tif (unlikely(err)) {\n \t\t\trq->stats.buff_alloc_err++;\n \t\t\tbreak;\n@@ -492,6 +484,83 @@ bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)\n \treturn !!err;\n }\n \n+static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,\n+\t\t\t\t\t struct mlx5e_icosq *sq,\n+\t\t\t\t\t struct mlx5e_rq *rq,\n+\t\t\t\t\t struct mlx5_cqe64 *cqe,\n+\t\t\t\t\t u16 *sqcc)\n+{\n+\tstruct mlx5_wq_cyc *wq = &sq->wq;\n+\tu16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1;\n+\tstruct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];\n+\n+\tmlx5_cqwq_pop(&cq->wq);\n+\t*sqcc += icowi->num_wqebbs;\n+\n+\tif (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {\n+\t\tWARN_ONCE(true, \"mlx5e: Bad OP in ICOSQ CQE: 0x%x\\n\",\n+\t\t\t cqe->op_own);\n+\t\treturn;\n+\t}\n+\n+\tif (likely(icowi->opcode == MLX5_OPCODE_UMR)) {\n+\t\tmlx5e_post_rx_mpwqe(rq);\n+\t\treturn;\n+\t}\n+\n+\tif (unlikely(icowi->opcode != MLX5_OPCODE_NOP))\n+\t\tWARN_ONCE(true,\n+\t\t\t \"mlx5e: Bad OPCODE in ICOSQ WQE info: 0x%x\\n\",\n+\t\t\t icowi->opcode);\n+}\n+\n+static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)\n+{\n+\tstruct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);\n+\tstruct mlx5_cqe64 *cqe;\n+\tu16 sqcc;\n+\n+\tif (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))\n+\t\treturn;\n+\n+\tcqe = mlx5_cqwq_get_cqe(&cq->wq);\n+\tif (likely(!cqe))\n+\t\treturn;\n+\n+\t/* sq->cc must be updated only after mlx5_cqwq_update_db_record(),\n+\t * otherwise a cq overrun may occur\n+\t */\n+\tsqcc = sq->cc;\n+\n+\t/* by design, there's only a single cqe */\n+\tmlx5e_poll_ico_single_cqe(cq, sq, rq, cqe, &sqcc);\n+\n+\tmlx5_cqwq_update_db_record(&cq->wq);\n+\n+\t/* ensure cq space is freed before enabling more cqes */\n+\twmb();\n+\n+\tsq->cc = sqcc;\n+}\n+\n+bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)\n+{\n+\tstruct mlx5_wq_ll *wq = &rq->wq;\n+\n+\tif (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))\n+\t\treturn false;\n+\n+\tmlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);\n+\n+\tif (mlx5_wq_ll_is_full(wq))\n+\t\treturn false;\n+\n+\tif (!rq->mpwqe.umr_in_progress)\n+\t\tmlx5e_alloc_rx_mpwqe(rq, wq->head);\n+\n+\treturn true;\n+}\n+\n static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,\n \t\t\t\t u32 cqe_bcnt)\n {\ndiff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c\nindex 7311b937e434..439ba1f2ffbc 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c\n@@ -32,66 +32,6 @@\n \n #include \"en.h\"\n \n-static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,\n-\t\t\t\t\t struct mlx5e_icosq *sq,\n-\t\t\t\t\t struct mlx5_cqe64 *cqe,\n-\t\t\t\t\t u16 *sqcc)\n-{\n-\tstruct mlx5_wq_cyc *wq = &sq->wq;\n-\tu16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1;\n-\tstruct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];\n-\tstruct mlx5e_rq *rq = &sq->channel->rq;\n-\n-\tprefetch(rq);\n-\tmlx5_cqwq_pop(&cq->wq);\n-\t*sqcc += icowi->num_wqebbs;\n-\n-\tif (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {\n-\t\tWARN_ONCE(true, \"mlx5e: Bad OP in ICOSQ CQE: 0x%x\\n\",\n-\t\t\t cqe->op_own);\n-\t\treturn;\n-\t}\n-\n-\tif (likely(icowi->opcode == MLX5_OPCODE_UMR)) {\n-\t\tmlx5e_post_rx_mpwqe(rq);\n-\t\treturn;\n-\t}\n-\n-\tif (unlikely(icowi->opcode != MLX5_OPCODE_NOP))\n-\t\tWARN_ONCE(true,\n-\t\t\t \"mlx5e: Bad OPCODE in ICOSQ WQE info: 0x%x\\n\",\n-\t\t\t icowi->opcode);\n-}\n-\n-static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq)\n-{\n-\tstruct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);\n-\tstruct mlx5_cqe64 *cqe;\n-\tu16 sqcc;\n-\n-\tif (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))\n-\t\treturn;\n-\n-\tcqe = mlx5_cqwq_get_cqe(&cq->wq);\n-\tif (likely(!cqe))\n-\t\treturn;\n-\n-\t/* sq->cc must be updated only after mlx5_cqwq_update_db_record(),\n-\t * otherwise a cq overrun may occur\n-\t */\n-\tsqcc = sq->cc;\n-\n-\t/* by design, there's only a single cqe */\n-\tmlx5e_poll_ico_single_cqe(cq, sq, cqe, &sqcc);\n-\n-\tmlx5_cqwq_update_db_record(&cq->wq);\n-\n-\t/* ensure cq space is freed before enabling more cqes */\n-\twmb();\n-\n-\tsq->cc = sqcc;\n-}\n-\n int mlx5e_napi_poll(struct napi_struct *napi, int budget)\n {\n \tstruct mlx5e_channel *c = container_of(napi, struct mlx5e_channel,\n@@ -111,9 +51,7 @@ int mlx5e_napi_poll(struct napi_struct *napi, int budget)\n \twork_done = mlx5e_poll_rx_cq(&c->rq.cq, budget);\n \tbusy |= work_done == budget;\n \n-\tmlx5e_poll_ico_cq(&c->icosq.cq);\n-\n-\tbusy |= mlx5e_post_rx_wqes(&c->rq);\n+\tbusy |= c->rq.post_wqes(&c->rq);\n \n \tif (busy)\n \t\treturn budget;\n", "prefixes": [ "net-next", "11/17" ] }