Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.2/patches/807972/?format=api
{ "id": 807972, "url": "http://patchwork.ozlabs.org/api/1.2/patches/807972/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/20170830230409.15176-4-saeedm@mellanox.com/", "project": { "id": 7, "url": "http://patchwork.ozlabs.org/api/1.2/projects/7/?format=api", "name": "Linux network development", "link_name": "netdev", "list_id": "netdev.vger.kernel.org", "list_email": "netdev@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170830230409.15176-4-saeedm@mellanox.com>", "list_archive_url": null, "date": "2017-08-30T23:04:09", "name": "[net-next,3/3] net/mlx5e: Support RSS for GRE tunneled packets", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "24b20fbaf0476a76364827c0d8ba04c11f0194e9", "submitter": { "id": 65299, "url": "http://patchwork.ozlabs.org/api/1.2/people/65299/?format=api", "name": "Saeed Mahameed", "email": "saeedm@mellanox.com" }, "delegate": { "id": 34, "url": "http://patchwork.ozlabs.org/api/1.2/users/34/?format=api", "username": "davem", "first_name": "David", "last_name": "Miller", "email": "davem@davemloft.net" }, "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/20170830230409.15176-4-saeedm@mellanox.com/mbox/", "series": [ { "id": 721, "url": "http://patchwork.ozlabs.org/api/1.2/series/721/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/list/?series=721", "date": "2017-08-30T23:04:06", "name": "[net-next,1/3] net/mlx5e: Use IP version matching to classify IP traffic", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/721/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807972/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807972/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<netdev-owner@vger.kernel.org>", "X-Original-To": "patchwork-incoming@ozlabs.org", "Delivered-To": "patchwork-incoming@ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xjLgT35jkz9s7C\n\tfor <patchwork-incoming@ozlabs.org>;\n\tThu, 31 Aug 2017 09:04:53 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751415AbdH3XEw (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tWed, 30 Aug 2017 19:04:52 -0400", "from mail-il-dmz.mellanox.com ([193.47.165.129]:34554 \"EHLO\n\tmellanox.co.il\" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org\n\twith ESMTP id S1751283AbdH3XEV (ORCPT\n\t<rfc822;netdev@vger.kernel.org>); Wed, 30 Aug 2017 19:04:21 -0400", "from Internal Mail-Server by MTLPINE1 (envelope-from\n\tsaeedm@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 31 Aug 2017 02:04:17 +0300", "from sws.mtl.labs.mlnx (reg-l-vrt-045-015.mtl.labs.mlnx\n\t[10.135.45.15])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id v7UN4HFm017137;\n\tThu, 31 Aug 2017 02:04:17 +0300" ], "From": "Saeed Mahameed <saeedm@mellanox.com>", "To": "\"David S. Miller\" <davem@davemloft.net>", "Cc": "netdev@vger.kernel.org, Gal Pressman <galp@mellanox.com>,\n\tSaeed Mahameed <saeedm@mellanox.com>", "Subject": "[net-next 3/3] net/mlx5e: Support RSS for GRE tunneled packets", "Date": "Thu, 31 Aug 2017 02:04:09 +0300", "Message-Id": "<20170830230409.15176-4-saeedm@mellanox.com>", "X-Mailer": "git-send-email 2.13.0", "In-Reply-To": "<20170830230409.15176-1-saeedm@mellanox.com>", "References": "<20170830230409.15176-1-saeedm@mellanox.com>", "Sender": "netdev-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<netdev.vger.kernel.org>", "X-Mailing-List": "netdev@vger.kernel.org" }, "content": "From: Gal Pressman <galp@mellanox.com>\n\nIntroduce a new flow table and indirect TIRs which are used to hash the\ninner packet headers of GRE tunneled packets.\n\nWhen a GRE tunneled packet is received, the TTC flow table will match\nthe new IPv4/6->GRE rules which will forward it to the inner TTC table.\nThe inner TTC is similar to its counterpart outer TTC table, but\nmatching the inner packet headers instead of the outer ones (and does\nnot include the new IPv4/6->GRE rules).\nThe new rules will not add steering hops since they are added to an\nalready existing flow group which will be matched regardless of this\npatch. Non GRE traffic will not be affected.\n\nThe inner flow table will forward the packet to inner indirect TIRs\nwhich hash the inner packet and thus result in RSS for the tunneled\npackets.\n\nTesting 8 TCP streams bandwidth over GRE:\nSystem: Intel(R) Xeon(R) CPU E5-2680 v3 @ 2.50GHz\nNIC: Mellanox Technologies MT28800 Family [ConnectX-5 Ex]\nBefore: 21.3 Gbps (Single RQ)\nNow : 90.5 Gbps (RSS spread on 8 RQs)\n\nSigned-off-by: Gal Pressman <galp@mellanox.com>\nReviewed-by: Or Gerlitz <ogerlitz@mellanox.com>\nSigned-off-by: Saeed Mahameed <saeedm@mellanox.com>\n---\n drivers/net/ethernet/mellanox/mlx5/core/en.h | 18 +-\n .../net/ethernet/mellanox/mlx5/core/en_ethtool.c | 11 +-\n drivers/net/ethernet/mellanox/mlx5/core/en_fs.c | 248 ++++++++++++++++++++-\n drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 57 ++++-\n drivers/net/ethernet/mellanox/mlx5/core/fs_core.c | 4 +-\n 5 files changed, 321 insertions(+), 17 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h\nindex 0039b4725405..a31912415264 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/en.h\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h\n@@ -620,6 +620,12 @@ enum mlx5e_traffic_types {\n \tMLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,\n };\n \n+enum mlx5e_tunnel_types {\n+\tMLX5E_TT_IPV4_GRE,\n+\tMLX5E_TT_IPV6_GRE,\n+\tMLX5E_NUM_TUNNEL_TT,\n+};\n+\n enum {\n \tMLX5E_STATE_ASYNC_EVENTS_ENABLED,\n \tMLX5E_STATE_OPENED,\n@@ -679,6 +685,7 @@ struct mlx5e_l2_table {\n struct mlx5e_ttc_table {\n \tstruct mlx5e_flow_table ft;\n \tstruct mlx5_flow_handle\t *rules[MLX5E_NUM_TT];\n+\tstruct mlx5_flow_handle *tunnel_rules[MLX5E_NUM_TUNNEL_TT];\n };\n \n #define ARFS_HASH_SHIFT BITS_PER_BYTE\n@@ -711,6 +718,7 @@ enum {\n \tMLX5E_VLAN_FT_LEVEL = 0,\n \tMLX5E_L2_FT_LEVEL,\n \tMLX5E_TTC_FT_LEVEL,\n+\tMLX5E_INNER_TTC_FT_LEVEL,\n \tMLX5E_ARFS_FT_LEVEL\n };\n \n@@ -736,6 +744,7 @@ struct mlx5e_flow_steering {\n \tstruct mlx5e_vlan_table vlan;\n \tstruct mlx5e_l2_table l2;\n \tstruct mlx5e_ttc_table ttc;\n+\tstruct mlx5e_ttc_table inner_ttc;\n \tstruct mlx5e_arfs_tables arfs;\n };\n \n@@ -769,6 +778,7 @@ struct mlx5e_priv {\n \tu32 tisn[MLX5E_MAX_NUM_TC];\n \tstruct mlx5e_rqt indir_rqt;\n \tstruct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];\n+\tstruct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS];\n \tstruct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];\n \tu32 tx_rates[MLX5E_MAX_NUM_SQS];\n \tint hard_mtu;\n@@ -903,7 +913,7 @@ int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,\n \t\t struct mlx5e_redirect_rqt_param rrp);\n void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,\n \t\t\t\t enum mlx5e_traffic_types tt,\n-\t\t\t\t void *tirc);\n+\t\t\t\t void *tirc, bool inner);\n \n int mlx5e_open_locked(struct net_device *netdev);\n int mlx5e_close_locked(struct net_device *netdev);\n@@ -932,6 +942,12 @@ void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,\n void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,\n \t\t\t struct mlx5e_params *params, u8 rq_type);\n \n+static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev)\n+{\n+\treturn (MLX5_CAP_ETH(mdev, tunnel_stateless_gre) &&\n+\t\tMLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version));\n+}\n+\n static inline\n struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc)\n {\ndiff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c\nindex 0dd7e9caf150..c6ec90e9c95b 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c\n@@ -1212,9 +1212,18 @@ static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)\n \n \tfor (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {\n \t\tmemset(tirc, 0, ctxlen);\n-\t\tmlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);\n+\t\tmlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);\n \t\tmlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);\n \t}\n+\n+\tif (!mlx5e_tunnel_inner_ft_supported(priv->mdev))\n+\t\treturn;\n+\n+\tfor (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {\n+\t\tmemset(tirc, 0, ctxlen);\n+\t\tmlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);\n+\t\tmlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in, inlen);\n+\t}\n }\n \n static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,\ndiff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_fs.c b/drivers/net/ethernet/mellanox/mlx5/core/en_fs.c\nindex 85e6226dacfb..f11fd07ac4dd 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/en_fs.c\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_fs.c\n@@ -608,12 +608,21 @@ static void mlx5e_cleanup_ttc_rules(struct mlx5e_ttc_table *ttc)\n \t\t\tttc->rules[i] = NULL;\n \t\t}\n \t}\n+\n+\tfor (i = 0; i < MLX5E_NUM_TUNNEL_TT; i++) {\n+\t\tif (!IS_ERR_OR_NULL(ttc->tunnel_rules[i])) {\n+\t\t\tmlx5_del_flow_rules(ttc->tunnel_rules[i]);\n+\t\t\tttc->tunnel_rules[i] = NULL;\n+\t\t}\n+\t}\n }\n \n-static struct {\n+struct mlx5e_etype_proto {\n \tu16 etype;\n \tu8 proto;\n-} ttc_rules[] = {\n+};\n+\n+static struct mlx5e_etype_proto ttc_rules[] = {\n \t[MLX5E_TT_IPV4_TCP] = {\n \t\t.etype = ETH_P_IP,\n \t\t.proto = IPPROTO_TCP,\n@@ -660,6 +669,17 @@ static struct {\n \t},\n };\n \n+static struct mlx5e_etype_proto ttc_tunnel_rules[] = {\n+\t[MLX5E_TT_IPV4_GRE] = {\n+\t\t.etype = ETH_P_IP,\n+\t\t.proto = IPPROTO_GRE,\n+\t},\n+\t[MLX5E_TT_IPV6_GRE] = {\n+\t\t.etype = ETH_P_IPV6,\n+\t\t.proto = IPPROTO_GRE,\n+\t},\n+};\n+\n static u8 mlx5e_etype_to_ipv(u16 ethertype)\n {\n \tif (ethertype == ETH_P_IP)\n@@ -742,6 +762,20 @@ static int mlx5e_generate_ttc_table_rules(struct mlx5e_priv *priv)\n \t\t\tgoto del_rules;\n \t}\n \n+\tif (!mlx5e_tunnel_inner_ft_supported(priv->mdev))\n+\t\treturn 0;\n+\n+\trules = ttc->tunnel_rules;\n+\tdest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;\n+\tdest.ft = priv->fs.inner_ttc.ft.t;\n+\tfor (tt = 0; tt < MLX5E_NUM_TUNNEL_TT; tt++) {\n+\t\trules[tt] = mlx5e_generate_ttc_rule(priv, ft, &dest,\n+\t\t\t\t\t\t ttc_tunnel_rules[tt].etype,\n+\t\t\t\t\t\t ttc_tunnel_rules[tt].proto);\n+\t\tif (IS_ERR(rules[tt]))\n+\t\t\tgoto del_rules;\n+\t}\n+\n \treturn 0;\n \n del_rules:\n@@ -752,13 +786,21 @@ static int mlx5e_generate_ttc_table_rules(struct mlx5e_priv *priv)\n }\n \n #define MLX5E_TTC_NUM_GROUPS\t3\n-#define MLX5E_TTC_GROUP1_SIZE\tBIT(3)\n-#define MLX5E_TTC_GROUP2_SIZE\tBIT(1)\n-#define MLX5E_TTC_GROUP3_SIZE\tBIT(0)\n+#define MLX5E_TTC_GROUP1_SIZE\t(BIT(3) + MLX5E_NUM_TUNNEL_TT)\n+#define MLX5E_TTC_GROUP2_SIZE\t BIT(1)\n+#define MLX5E_TTC_GROUP3_SIZE\t BIT(0)\n #define MLX5E_TTC_TABLE_SIZE\t(MLX5E_TTC_GROUP1_SIZE +\\\n \t\t\t\t MLX5E_TTC_GROUP2_SIZE +\\\n \t\t\t\t MLX5E_TTC_GROUP3_SIZE)\n \n+#define MLX5E_INNER_TTC_NUM_GROUPS\t3\n+#define MLX5E_INNER_TTC_GROUP1_SIZE\tBIT(3)\n+#define MLX5E_INNER_TTC_GROUP2_SIZE\tBIT(1)\n+#define MLX5E_INNER_TTC_GROUP3_SIZE\tBIT(0)\n+#define MLX5E_INNER_TTC_TABLE_SIZE\t(MLX5E_INNER_TTC_GROUP1_SIZE +\\\n+\t\t\t\t\t MLX5E_INNER_TTC_GROUP2_SIZE +\\\n+\t\t\t\t\t MLX5E_INNER_TTC_GROUP3_SIZE)\n+\n static int mlx5e_create_ttc_table_groups(struct mlx5e_ttc_table *ttc,\n \t\t\t\t\t bool use_ipv)\n {\n@@ -826,6 +868,190 @@ static int mlx5e_create_ttc_table_groups(struct mlx5e_ttc_table *ttc,\n \treturn err;\n }\n \n+static struct mlx5_flow_handle *\n+mlx5e_generate_inner_ttc_rule(struct mlx5e_priv *priv,\n+\t\t\t struct mlx5_flow_table *ft,\n+\t\t\t struct mlx5_flow_destination *dest,\n+\t\t\t u16 etype, u8 proto)\n+{\n+\tMLX5_DECLARE_FLOW_ACT(flow_act);\n+\tstruct mlx5_flow_handle *rule;\n+\tstruct mlx5_flow_spec *spec;\n+\tint err = 0;\n+\tu8 ipv;\n+\n+\tspec = kvzalloc(sizeof(*spec), GFP_KERNEL);\n+\tif (!spec)\n+\t\treturn ERR_PTR(-ENOMEM);\n+\n+\tipv = mlx5e_etype_to_ipv(etype);\n+\tif (etype && ipv) {\n+\t\tspec->match_criteria_enable = MLX5_MATCH_INNER_HEADERS;\n+\t\tMLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, inner_headers.ip_version);\n+\t\tMLX5_SET(fte_match_param, spec->match_value, inner_headers.ip_version, ipv);\n+\t}\n+\n+\tif (proto) {\n+\t\tspec->match_criteria_enable = MLX5_MATCH_INNER_HEADERS;\n+\t\tMLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, inner_headers.ip_protocol);\n+\t\tMLX5_SET(fte_match_param, spec->match_value, inner_headers.ip_protocol, proto);\n+\t}\n+\n+\trule = mlx5_add_flow_rules(ft, spec, &flow_act, dest, 1);\n+\tif (IS_ERR(rule)) {\n+\t\terr = PTR_ERR(rule);\n+\t\tnetdev_err(priv->netdev, \"%s: add rule failed\\n\", __func__);\n+\t}\n+\n+\tkvfree(spec);\n+\treturn err ? ERR_PTR(err) : rule;\n+}\n+\n+static int mlx5e_generate_inner_ttc_table_rules(struct mlx5e_priv *priv)\n+{\n+\tstruct mlx5_flow_destination dest;\n+\tstruct mlx5_flow_handle **rules;\n+\tstruct mlx5e_ttc_table *ttc;\n+\tstruct mlx5_flow_table *ft;\n+\tint err;\n+\tint tt;\n+\n+\tttc = &priv->fs.inner_ttc;\n+\tft = ttc->ft.t;\n+\trules = ttc->rules;\n+\n+\tdest.type = MLX5_FLOW_DESTINATION_TYPE_TIR;\n+\tfor (tt = 0; tt < MLX5E_NUM_TT; tt++) {\n+\t\tif (tt == MLX5E_TT_ANY)\n+\t\t\tdest.tir_num = priv->direct_tir[0].tirn;\n+\t\telse\n+\t\t\tdest.tir_num = priv->inner_indir_tir[tt].tirn;\n+\n+\t\trules[tt] = mlx5e_generate_inner_ttc_rule(priv, ft, &dest,\n+\t\t\t\t\t\t\t ttc_rules[tt].etype,\n+\t\t\t\t\t\t\t ttc_rules[tt].proto);\n+\t\tif (IS_ERR(rules[tt]))\n+\t\t\tgoto del_rules;\n+\t}\n+\n+\treturn 0;\n+\n+del_rules:\n+\terr = PTR_ERR(rules[tt]);\n+\trules[tt] = NULL;\n+\tmlx5e_cleanup_ttc_rules(ttc);\n+\treturn err;\n+}\n+\n+static int mlx5e_create_inner_ttc_table_groups(struct mlx5e_ttc_table *ttc)\n+{\n+\tint inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);\n+\tstruct mlx5e_flow_table *ft = &ttc->ft;\n+\tint ix = 0;\n+\tu32 *in;\n+\tint err;\n+\tu8 *mc;\n+\n+\tft->g = kcalloc(MLX5E_INNER_TTC_NUM_GROUPS, sizeof(*ft->g), GFP_KERNEL);\n+\tif (!ft->g)\n+\t\treturn -ENOMEM;\n+\tin = kvzalloc(inlen, GFP_KERNEL);\n+\tif (!in) {\n+\t\tkfree(ft->g);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* L4 Group */\n+\tmc = MLX5_ADDR_OF(create_flow_group_in, in, match_criteria);\n+\tMLX5_SET_TO_ONES(fte_match_param, mc, inner_headers.ip_protocol);\n+\tMLX5_SET_TO_ONES(fte_match_param, mc, inner_headers.ip_version);\n+\tMLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_INNER_HEADERS);\n+\tMLX5_SET_CFG(in, start_flow_index, ix);\n+\tix += MLX5E_INNER_TTC_GROUP1_SIZE;\n+\tMLX5_SET_CFG(in, end_flow_index, ix - 1);\n+\tft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in);\n+\tif (IS_ERR(ft->g[ft->num_groups]))\n+\t\tgoto err;\n+\tft->num_groups++;\n+\n+\t/* L3 Group */\n+\tMLX5_SET(fte_match_param, mc, inner_headers.ip_protocol, 0);\n+\tMLX5_SET_CFG(in, start_flow_index, ix);\n+\tix += MLX5E_INNER_TTC_GROUP2_SIZE;\n+\tMLX5_SET_CFG(in, end_flow_index, ix - 1);\n+\tft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in);\n+\tif (IS_ERR(ft->g[ft->num_groups]))\n+\t\tgoto err;\n+\tft->num_groups++;\n+\n+\t/* Any Group */\n+\tmemset(in, 0, inlen);\n+\tMLX5_SET_CFG(in, start_flow_index, ix);\n+\tix += MLX5E_INNER_TTC_GROUP3_SIZE;\n+\tMLX5_SET_CFG(in, end_flow_index, ix - 1);\n+\tft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in);\n+\tif (IS_ERR(ft->g[ft->num_groups]))\n+\t\tgoto err;\n+\tft->num_groups++;\n+\n+\tkvfree(in);\n+\treturn 0;\n+\n+err:\n+\terr = PTR_ERR(ft->g[ft->num_groups]);\n+\tft->g[ft->num_groups] = NULL;\n+\tkvfree(in);\n+\n+\treturn err;\n+}\n+\n+static int mlx5e_create_inner_ttc_table(struct mlx5e_priv *priv)\n+{\n+\tstruct mlx5e_ttc_table *ttc = &priv->fs.inner_ttc;\n+\tstruct mlx5_flow_table_attr ft_attr = {};\n+\tstruct mlx5e_flow_table *ft = &ttc->ft;\n+\tint err;\n+\n+\tif (!mlx5e_tunnel_inner_ft_supported(priv->mdev))\n+\t\treturn 0;\n+\n+\tft_attr.max_fte = MLX5E_INNER_TTC_TABLE_SIZE;\n+\tft_attr.level = MLX5E_INNER_TTC_FT_LEVEL;\n+\tft_attr.prio = MLX5E_NIC_PRIO;\n+\n+\tft->t = mlx5_create_flow_table(priv->fs.ns, &ft_attr);\n+\tif (IS_ERR(ft->t)) {\n+\t\terr = PTR_ERR(ft->t);\n+\t\tft->t = NULL;\n+\t\treturn err;\n+\t}\n+\n+\terr = mlx5e_create_inner_ttc_table_groups(ttc);\n+\tif (err)\n+\t\tgoto err;\n+\n+\terr = mlx5e_generate_inner_ttc_table_rules(priv);\n+\tif (err)\n+\t\tgoto err;\n+\n+\treturn 0;\n+\n+err:\n+\tmlx5e_destroy_flow_table(ft);\n+\treturn err;\n+}\n+\n+static void mlx5e_destroy_inner_ttc_table(struct mlx5e_priv *priv)\n+{\n+\tstruct mlx5e_ttc_table *ttc = &priv->fs.inner_ttc;\n+\n+\tif (!mlx5e_tunnel_inner_ft_supported(priv->mdev))\n+\t\treturn;\n+\n+\tmlx5e_cleanup_ttc_rules(ttc);\n+\tmlx5e_destroy_flow_table(&ttc->ft);\n+}\n+\n void mlx5e_destroy_ttc_table(struct mlx5e_priv *priv)\n {\n \tstruct mlx5e_ttc_table *ttc = &priv->fs.ttc;\n@@ -1179,11 +1405,18 @@ int mlx5e_create_flow_steering(struct mlx5e_priv *priv)\n \t\tpriv->netdev->hw_features &= ~NETIF_F_NTUPLE;\n \t}\n \n+\terr = mlx5e_create_inner_ttc_table(priv);\n+\tif (err) {\n+\t\tnetdev_err(priv->netdev, \"Failed to create inner ttc table, err=%d\\n\",\n+\t\t\t err);\n+\t\tgoto err_destroy_arfs_tables;\n+\t}\n+\n \terr = mlx5e_create_ttc_table(priv);\n \tif (err) {\n \t\tnetdev_err(priv->netdev, \"Failed to create ttc table, err=%d\\n\",\n \t\t\t err);\n-\t\tgoto err_destroy_arfs_tables;\n+\t\tgoto err_destroy_inner_ttc_table;\n \t}\n \n \terr = mlx5e_create_l2_table(priv);\n@@ -1208,6 +1441,8 @@ int mlx5e_create_flow_steering(struct mlx5e_priv *priv)\n \tmlx5e_destroy_l2_table(priv);\n err_destroy_ttc_table:\n \tmlx5e_destroy_ttc_table(priv);\n+err_destroy_inner_ttc_table:\n+\tmlx5e_destroy_inner_ttc_table(priv);\n err_destroy_arfs_tables:\n \tmlx5e_arfs_destroy_tables(priv);\n \n@@ -1219,6 +1454,7 @@ void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv)\n \tmlx5e_destroy_vlan_table(priv);\n \tmlx5e_destroy_l2_table(priv);\n \tmlx5e_destroy_ttc_table(priv);\n+\tmlx5e_destroy_inner_ttc_table(priv);\n \tmlx5e_arfs_destroy_tables(priv);\n \tmlx5e_ethtool_cleanup_steering(priv);\n }\ndiff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c\nindex 9475fb89a744..111c7523d448 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c\n@@ -2349,9 +2349,10 @@ static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)\n \n void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,\n \t\t\t\t enum mlx5e_traffic_types tt,\n-\t\t\t\t void *tirc)\n+\t\t\t\t void *tirc, bool inner)\n {\n-\tvoid *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);\n+\tvoid *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :\n+\t\t\t MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);\n \n #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\\\n \t\t\t\t MLX5_HASH_FIELD_SEL_DST_IP)\n@@ -2500,6 +2501,21 @@ static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)\n \treturn err;\n }\n \n+static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,\n+\t\t\t\t\t enum mlx5e_traffic_types tt,\n+\t\t\t\t\t u32 *tirc)\n+{\n+\tMLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);\n+\n+\tmlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);\n+\n+\tMLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);\n+\tMLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);\n+\tMLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);\n+\n+\tmlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);\n+}\n+\n static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)\n {\n \tstruct mlx5_core_dev *mdev = priv->mdev;\n@@ -2865,7 +2881,7 @@ static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,\n \n \tMLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);\n \tMLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);\n-\tmlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);\n+\tmlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);\n }\n \n static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)\n@@ -2884,6 +2900,7 @@ int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)\n \tstruct mlx5e_tir *tir;\n \tvoid *tirc;\n \tint inlen;\n+\tint i = 0;\n \tint err;\n \tu32 *in;\n \tint tt;\n@@ -2899,16 +2916,36 @@ int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)\n \t\ttirc = MLX5_ADDR_OF(create_tir_in, in, ctx);\n \t\tmlx5e_build_indir_tir_ctx(priv, tt, tirc);\n \t\terr = mlx5e_create_tir(priv->mdev, tir, in, inlen);\n-\t\tif (err)\n-\t\t\tgoto err_destroy_tirs;\n+\t\tif (err) {\n+\t\t\tmlx5_core_warn(priv->mdev, \"create indirect tirs failed, %d\\n\", err);\n+\t\t\tgoto err_destroy_inner_tirs;\n+\t\t}\n \t}\n \n+\tif (!mlx5e_tunnel_inner_ft_supported(priv->mdev))\n+\t\tgoto out;\n+\n+\tfor (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {\n+\t\tmemset(in, 0, inlen);\n+\t\ttir = &priv->inner_indir_tir[i];\n+\t\ttirc = MLX5_ADDR_OF(create_tir_in, in, ctx);\n+\t\tmlx5e_build_inner_indir_tir_ctx(priv, i, tirc);\n+\t\terr = mlx5e_create_tir(priv->mdev, tir, in, inlen);\n+\t\tif (err) {\n+\t\t\tmlx5_core_warn(priv->mdev, \"create inner indirect tirs failed, %d\\n\", err);\n+\t\t\tgoto err_destroy_inner_tirs;\n+\t\t}\n+\t}\n+\n+out:\n \tkvfree(in);\n \n \treturn 0;\n \n-err_destroy_tirs:\n-\tmlx5_core_warn(priv->mdev, \"create indirect tirs failed, %d\\n\", err);\n+err_destroy_inner_tirs:\n+\tfor (i--; i >= 0; i--)\n+\t\tmlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);\n+\n \tfor (tt--; tt >= 0; tt--)\n \t\tmlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);\n \n@@ -2962,6 +2999,12 @@ void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)\n \n \tfor (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)\n \t\tmlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);\n+\n+\tif (!mlx5e_tunnel_inner_ft_supported(priv->mdev))\n+\t\treturn;\n+\n+\tfor (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)\n+\t\tmlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);\n }\n \n void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)\ndiff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c\nindex d731d57a996a..5a7bea688ec8 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c\n@@ -83,8 +83,8 @@\n #define ETHTOOL_PRIO_NUM_LEVELS 1\n #define ETHTOOL_NUM_PRIOS 11\n #define ETHTOOL_MIN_LEVEL (KERNEL_MIN_LEVEL + ETHTOOL_NUM_PRIOS)\n-/* Vlan, mac, ttc, aRFS */\n-#define KERNEL_NIC_PRIO_NUM_LEVELS 4\n+/* Vlan, mac, ttc, inner ttc, aRFS */\n+#define KERNEL_NIC_PRIO_NUM_LEVELS 5\n #define KERNEL_NIC_NUM_PRIOS 1\n /* One more level for tc */\n #define KERNEL_MIN_LEVEL (KERNEL_NIC_PRIO_NUM_LEVELS + 1)\n", "prefixes": [ "net-next", "3/3" ] }