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GET /api/1.2/patches/807438/?format=api
{ "id": 807438, "url": "http://patchwork.ozlabs.org/api/1.2/patches/807438/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1504073693-16900-11-git-send-email-peng.fan@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504073693-16900-11-git-send-email-peng.fan@nxp.com>", "list_archive_url": null, "date": "2017-08-30T06:14:52", "name": "[U-Boot,V4,11/12] imx: mx6sabresd: enable dm drivers", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "f6980d5f45cdaa9e9148374b0a5b42ace0e0862a", "submitter": { "id": 67896, "url": "http://patchwork.ozlabs.org/api/1.2/people/67896/?format=api", "name": "Peng Fan", "email": "peng.fan@nxp.com" }, "delegate": { "id": 1693, "url": "http://patchwork.ozlabs.org/api/1.2/users/1693/?format=api", "username": "sbabic", "first_name": "Stefano", "last_name": "Babic", "email": "sbabic@denx.de" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1504073693-16900-11-git-send-email-peng.fan@nxp.com/mbox/", "series": [ { "id": 530, "url": "http://patchwork.ozlabs.org/api/1.2/series/530/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=530", "date": "2017-08-30T06:14:42", "name": "[U-Boot,V4,01/12] scripts: spl: fix typo", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/530/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807438/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807438/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": 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105)\n\tid 829DEC226B6; Wed, 30 Aug 2017 06:18:22 +0000 (UTC)", "from EUR01-HE1-obe.outbound.protection.outlook.com\n\t(mail-he1eur01on0063.outbound.protection.outlook.com [104.47.0.63])\n\tby lists.denx.de (Postfix) with ESMTPS id AE39CC22747\n\tfor <u-boot@lists.denx.de>; Wed, 30 Aug 2017 06:17:39 +0000 (UTC)", "from linux-u7w5.ap.freescale.net (199.59.231.64) by\n\tAM5PR04MB3217.eurprd04.prod.outlook.com (2603:10a6:206:7::14) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1385.9;\n\tWed, 30 Aug 2017 06:17:21 +0000" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=BAD_ENC_HEADER,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tSPF_HELO_PASS, \n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=QBKoY96D+Q4qFLPVuwQtSKzWOUJHAQ43czuYZMeFSJ0=;\n\tb=pRtywFnKYgKW43ThaoUEmr2LyFJmNSwu8Ordv4+zD4NENOwxqc0Fx8vNC/b/mFqjiyixWBOgXqzZfVhyECixhQujSVrn4RFhzo+HWYU5pCuqMlph7ljvCmV46GTM2Valg9RTR8lAyZ0ptkGRhYh2WRnAcu+pnmNtqkfW+CKwtfs=", "From": "Peng Fan <peng.fan@nxp.com>", "To": "sbabic@denx.de", "Date": "Wed, 30 Aug 2017 14:14:52 +0800", "Message-Id": "<1504073693-16900-11-git-send-email-peng.fan@nxp.com>", "X-Mailer": "git-send-email 2.6.6", "In-Reply-To": "<1504073693-16900-1-git-send-email-peng.fan@nxp.com>", "References": "<1504073693-16900-1-git-send-email-peng.fan@nxp.com>", "MIME-Version": "1.0", "X-Originating-IP": "[199.59.231.64]", "X-ClientProxiedBy": "HK2PR02CA0139.apcprd02.prod.outlook.com\n\t(2603:1096:202:16::23) To AM5PR04MB3217.eurprd04.prod.outlook.com\n\t(2603:10a6:206:7::14)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "f1f68c14-4e5e-4c22-3a30-08d4ef6ecf6d", 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"X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM5PR04MB3217", "Cc": "u-boot@lists.denx.de, Fabio Estevam <fabio.estevam@nxp.com>", "Subject": "[U-Boot] [PATCH V4 11/12] imx: mx6sabresd: enable dm drivers", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Enable DM MMC/I2C/PMIC/GPIO/REGULATOR.\n\nSigned-off-by: Peng Fan <peng.fan@nxp.com>\nCc: Fabio Estevam <fabio.estevam@nxp.com>\nCc: Stefano Babic <sbabic@denx.de>\n---\n\nV2->V4: none\n\n board/freescale/mx6sabresd/mx6sabresd.c | 326 +++++++++++++-------------------\n configs/mx6sabresd_defconfig | 15 ++\n include/configs/mx6sabresd.h | 15 +-\n 3 files changed, 146 insertions(+), 210 deletions(-)", "diff": "diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c\nindex fa75ab0..2123a9d 100644\n--- a/board/freescale/mx6sabresd/mx6sabresd.c\n+++ b/board/freescale/mx6sabresd/mx6sabresd.c\n@@ -12,7 +12,6 @@\n #include <asm/arch/mx6-pins.h>\n #include <linux/errno.h>\n #include <asm/gpio.h>\n-#include <asm/mach-imx/mxc_i2c.h>\n #include <asm/mach-imx/iomux-v3.h>\n #include <asm/mach-imx/boot_mode.h>\n #include <asm/mach-imx/video.h>\n@@ -24,7 +23,6 @@\n #include <asm/arch/crm_regs.h>\n #include <asm/io.h>\n #include <asm/arch/sys_proto.h>\n-#include <i2c.h>\n #include <power/pmic.h>\n #include <power/pfuze100_pmic.h>\n #include \"../common/pfuze.h\"\n@@ -46,14 +44,6 @@ DECLARE_GLOBAL_DATA_PTR;\n #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \\\n \t\t PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)\n \n-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP |\t\t\t\\\n-\tPAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |\t\\\n-\tPAD_CTL_ODE | PAD_CTL_SRE_FAST)\n-\n-#define I2C_PMIC\t1\n-\n-#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)\n-\n #define DISP0_PWR_EN\tIMX_GPIO_NR(1, 21)\n \n #define KEY_VOL_UP\tIMX_GPIO_NR(1, 4)\n@@ -93,6 +83,7 @@ static void setup_iomux_enet(void)\n {\n \tSETUP_IOMUX_PADS(enet_pads);\n \n+\tgpio_request(IMX_GPIO_NR(1, 25), \"phy_rst\");\n \t/* Reset AR8031 PHY */\n \tgpio_direction_output(IMX_GPIO_NR(1, 25) , 0);\n \tmdelay(10);\n@@ -100,47 +91,6 @@ static void setup_iomux_enet(void)\n \tudelay(100);\n }\n \n-static iomux_v3_cfg_t const usdhc2_pads[] = {\n-\tIOMUX_PADS(PAD_SD2_CLK__SD2_CLK\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD2_CMD__SD2_CMD\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_NANDF_D4__SD2_DATA4\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_NANDF_D5__SD2_DATA5\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_NANDF_D6__SD2_DATA6\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_NANDF_D7__SD2_DATA7\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02\t| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */\n-};\n-\n-static iomux_v3_cfg_t const usdhc3_pads[] = {\n-\tIOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */\n-};\n-\n-static iomux_v3_cfg_t const usdhc4_pads[] = {\n-\tIOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-};\n-\n static iomux_v3_cfg_t const ecspi1_pads[] = {\n \tIOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),\n \tIOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),\n@@ -187,6 +137,7 @@ static iomux_v3_cfg_t const bl_pads[] = {\n static void enable_backlight(void)\n {\n \tSETUP_IOMUX_PADS(bl_pads);\n+\tgpio_request(DISP0_PWR_EN, \"disp0_pwr_en\");\n \tgpio_direction_output(DISP0_PWR_EN, 1);\n }\n \n@@ -201,32 +152,6 @@ static void enable_lvds(struct display_info_t const *dev)\n \tenable_backlight();\n }\n \n-static struct i2c_pads_info mx6q_i2c_pad_info1 = {\n-\t.scl = {\n-\t\t.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,\n-\t\t.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,\n-\t\t.gp = IMX_GPIO_NR(4, 12)\n-\t},\n-\t.sda = {\n-\t\t.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,\n-\t\t.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,\n-\t\t.gp = IMX_GPIO_NR(4, 13)\n-\t}\n-};\n-\n-static struct i2c_pads_info mx6dl_i2c_pad_info1 = {\n-\t.scl = {\n-\t\t.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,\n-\t\t.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,\n-\t\t.gp = IMX_GPIO_NR(4, 12)\n-\t},\n-\t.sda = {\n-\t\t.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,\n-\t\t.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,\n-\t\t.gp = IMX_GPIO_NR(4, 13)\n-\t}\n-};\n-\n static void setup_spi(void)\n {\n \tSETUP_IOMUX_PADS(ecspi1_pads);\n@@ -253,121 +178,11 @@ static void setup_iomux_uart(void)\n \tSETUP_IOMUX_PADS(uart1_pads);\n }\n \n-#ifdef CONFIG_FSL_ESDHC\n-struct fsl_esdhc_cfg usdhc_cfg[3] = {\n-\t{USDHC2_BASE_ADDR},\n-\t{USDHC3_BASE_ADDR},\n-\t{USDHC4_BASE_ADDR},\n-};\n-\n-#define USDHC2_CD_GPIO\tIMX_GPIO_NR(2, 2)\n-#define USDHC3_CD_GPIO\tIMX_GPIO_NR(2, 0)\n-\n int board_mmc_get_env_dev(int devno)\n {\n \treturn devno - 1;\n }\n \n-int board_mmc_getcd(struct mmc *mmc)\n-{\n-\tstruct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;\n-\tint ret = 0;\n-\n-\tswitch (cfg->esdhc_base) {\n-\tcase USDHC2_BASE_ADDR:\n-\t\tret = !gpio_get_value(USDHC2_CD_GPIO);\n-\t\tbreak;\n-\tcase USDHC3_BASE_ADDR:\n-\t\tret = !gpio_get_value(USDHC3_CD_GPIO);\n-\t\tbreak;\n-\tcase USDHC4_BASE_ADDR:\n-\t\tret = 1; /* eMMC/uSDHC4 is always present */\n-\t\tbreak;\n-\t}\n-\n-\treturn ret;\n-}\n-\n-int board_mmc_init(bd_t *bis)\n-{\n-#ifndef CONFIG_SPL_BUILD\n-\tint ret;\n-\tint i;\n-\n-\t/*\n-\t * According to the board_mmc_init() the following map is done:\n-\t * (U-Boot device node) (Physical Port)\n-\t * mmc0 SD2\n-\t * mmc1 SD3\n-\t * mmc2 eMMC\n-\t */\n-\tfor (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {\n-\t\tswitch (i) {\n-\t\tcase 0:\n-\t\t\tSETUP_IOMUX_PADS(usdhc2_pads);\n-\t\t\tgpio_direction_input(USDHC2_CD_GPIO);\n-\t\t\tusdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);\n-\t\t\tbreak;\n-\t\tcase 1:\n-\t\t\tSETUP_IOMUX_PADS(usdhc3_pads);\n-\t\t\tgpio_direction_input(USDHC3_CD_GPIO);\n-\t\t\tusdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);\n-\t\t\tbreak;\n-\t\tcase 2:\n-\t\t\tSETUP_IOMUX_PADS(usdhc4_pads);\n-\t\t\tusdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tprintf(\"Warning: you configured more USDHC controllers\"\n-\t\t\t \"(%d) then supported by the board (%d)\\n\",\n-\t\t\t i + 1, CONFIG_SYS_FSL_USDHC_NUM);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\n-\t\tret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t}\n-\n-\treturn 0;\n-#else\n-\tstruct src *psrc = (struct src *)SRC_BASE_ADDR;\n-\tunsigned reg = readl(&psrc->sbmr1) >> 11;\n-\t/*\n-\t * Upon reading BOOT_CFG register the following map is done:\n-\t * Bit 11 and 12 of BOOT_CFG register can determine the current\n-\t * mmc port\n-\t * 0x1 SD1\n-\t * 0x2 SD2\n-\t * 0x3 SD4\n-\t */\n-\n-\tswitch (reg & 0x3) {\n-\tcase 0x1:\n-\t\tSETUP_IOMUX_PADS(usdhc2_pads);\n-\t\tusdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;\n-\t\tusdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);\n-\t\tgd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;\n-\t\tbreak;\n-\tcase 0x2:\n-\t\tSETUP_IOMUX_PADS(usdhc3_pads);\n-\t\tusdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;\n-\t\tusdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);\n-\t\tgd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;\n-\t\tbreak;\n-\tcase 0x3:\n-\t\tSETUP_IOMUX_PADS(usdhc4_pads);\n-\t\tusdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;\n-\t\tusdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);\n-\t\tgd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;\n-\t\tbreak;\n-\t}\n-\n-\treturn fsl_esdhc_initialize(bis, &usdhc_cfg[0]);\n-#endif\n-}\n-#endif\n-\n static int ar8031_phy_fixup(struct phy_device *phydev)\n {\n \tunsigned short val;\n@@ -580,6 +395,8 @@ static void setup_usb(void)\n \timx_iomux_set_gpr_register(1, 13, 1, 0);\n \n \tSETUP_IOMUX_PADS(usb_hc1_pads);\n+\n+\tgpio_request(IMX_GPIO_NR(1, 29), \"usb1\");\n }\n \n int board_ehci_hcd_init(int port)\n@@ -632,13 +449,13 @@ int board_init(void)\n \t/* address of boot parameters */\n \tgd->bd->bi_boot_params = PHYS_SDRAM + 0x100;\n \n+\tgpio_request(IMX_GPIO_NR(3, 19), \"pcie_power\");\n+\tgpio_request(IMX_GPIO_NR(7, 12), \"pcie_reset\");\n+\n #ifdef CONFIG_MXC_SPI\n \tsetup_spi();\n #endif\n-\tif (is_mx6dq() || is_mx6dqp())\n-\t\tsetup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);\n-\telse\n-\t\tsetup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);\n+\n #ifdef CONFIG_USB_EHCI_MX6\n \tsetup_usb();\n #endif\n@@ -646,34 +463,36 @@ int board_init(void)\n \treturn 0;\n }\n \n+#ifndef CONFIG_SPL_BUILD\n int power_init_board(void)\n {\n-\tstruct pmic *p;\n+\tstruct udevice *dev;\n \tunsigned int reg;\n \tint ret;\n \n-\tp = pfuze_common_init(I2C_PMIC);\n-\tif (!p)\n+\tdev = pfuze_common_init();\n+\tif (!dev)\n \t\treturn -ENODEV;\n \n-\tret = pfuze_mode_init(p, APS_PFM);\n+\tret = pfuze_mode_init(dev, APS_PFM);\n \tif (ret < 0)\n \t\treturn ret;\n \n \t/* Increase VGEN3 from 2.5 to 2.8V */\n-\tpmic_reg_read(p, PFUZE100_VGEN3VOL, ®);\n+\treg = pmic_reg_read(dev, PFUZE100_VGEN3VOL);\n \treg &= ~LDO_VOL_MASK;\n \treg |= LDOB_2_80V;\n-\tpmic_reg_write(p, PFUZE100_VGEN3VOL, reg);\n+\tpmic_reg_write(dev, PFUZE100_VGEN3VOL, reg);\n \n \t/* Increase VGEN5 from 2.8 to 3V */\n-\tpmic_reg_read(p, PFUZE100_VGEN5VOL, ®);\n+\treg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);\n \treg &= ~LDO_VOL_MASK;\n \treg |= LDOB_3_00V;\n-\tpmic_reg_write(p, PFUZE100_VGEN5VOL, reg);\n+\tpmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);\n \n \treturn 0;\n }\n+#endif\n \n #ifdef CONFIG_MXC_SPI\n int board_spi_cs_gpio(unsigned bus, unsigned cs)\n@@ -747,6 +566,115 @@ int board_fit_config_name_match(const char *name)\n }\n #endif\n \n+#ifdef CONFIG_FSL_ESDHC\n+static iomux_v3_cfg_t const usdhc2_pads[] = {\n+\tIOMUX_PADS(PAD_SD2_CLK__SD2_CLK\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD2_CMD__SD2_CMD\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_NANDF_D4__SD2_DATA4\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_NANDF_D5__SD2_DATA5\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_NANDF_D6__SD2_DATA6\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_NANDF_D7__SD2_DATA7\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02\t| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */\n+};\n+\n+static iomux_v3_cfg_t const usdhc3_pads[] = {\n+\tIOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */\n+};\n+\n+static iomux_v3_cfg_t const usdhc4_pads[] = {\n+\tIOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+};\n+\n+struct fsl_esdhc_cfg usdhc_cfg[3] = {\n+\t{USDHC2_BASE_ADDR},\n+\t{USDHC3_BASE_ADDR},\n+\t{USDHC4_BASE_ADDR},\n+};\n+\n+#define USDHC2_CD_GPIO\tIMX_GPIO_NR(2, 2)\n+#define USDHC3_CD_GPIO\tIMX_GPIO_NR(2, 0)\n+\n+int board_mmc_getcd(struct mmc *mmc)\n+{\n+\tstruct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;\n+\tint ret = 0;\n+\n+\tswitch (cfg->esdhc_base) {\n+\tcase USDHC2_BASE_ADDR:\n+\t\tret = !gpio_get_value(USDHC2_CD_GPIO);\n+\t\tbreak;\n+\tcase USDHC3_BASE_ADDR:\n+\t\tret = !gpio_get_value(USDHC3_CD_GPIO);\n+\t\tbreak;\n+\tcase USDHC4_BASE_ADDR:\n+\t\tret = 1; /* eMMC/uSDHC4 is always present */\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+int board_mmc_init(bd_t *bis)\n+{\n+\tstruct src *psrc = (struct src *)SRC_BASE_ADDR;\n+\tunsigned reg = readl(&psrc->sbmr1) >> 11;\n+\t/*\n+\t * Upon reading BOOT_CFG register the following map is done:\n+\t * Bit 11 and 12 of BOOT_CFG register can determine the current\n+\t * mmc port\n+\t * 0x1 SD1\n+\t * 0x2 SD2\n+\t * 0x3 SD4\n+\t */\n+\n+\tswitch (reg & 0x3) {\n+\tcase 0x1:\n+\t\tSETUP_IOMUX_PADS(usdhc2_pads);\n+\t\tusdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;\n+\t\tusdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);\n+\t\tgd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;\n+\t\tbreak;\n+\tcase 0x2:\n+\t\tSETUP_IOMUX_PADS(usdhc3_pads);\n+\t\tusdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;\n+\t\tusdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);\n+\t\tgd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;\n+\t\tbreak;\n+\tcase 0x3:\n+\t\tSETUP_IOMUX_PADS(usdhc4_pads);\n+\t\tusdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;\n+\t\tusdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);\n+\t\tgd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;\n+\t\tbreak;\n+\t}\n+\n+\treturn fsl_esdhc_initialize(bis, &usdhc_cfg[0]);\n+}\n+#endif\n+\n static void ccgr_init(void)\n {\n \tstruct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;\ndiff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig\nindex 7491e9c..3eab67e 100644\n--- a/configs/mx6sabresd_defconfig\n+++ b/configs/mx6sabresd_defconfig\n@@ -40,6 +40,8 @@ CONFIG_CMD_DHCP=y\n CONFIG_CMD_MII=y\n CONFIG_CMD_PING=y\n CONFIG_CMD_CACHE=y\n+CONFIG_CMD_PMIC=y\n+CONFIG_CMD_REGULATOR=y\n CONFIG_CMD_EXT2=y\n CONFIG_CMD_EXT4=y\n CONFIG_CMD_EXT4_WRITE=y\n@@ -47,10 +49,23 @@ CONFIG_CMD_FAT=y\n CONFIG_CMD_FS_GENERIC=y\n CONFIG_OF_CONTROL=y\n CONFIG_OF_LIST=\"imx6q-sabresd imx6dl-sabresd imx6qp-sabresd\"\n+# CONFIG_BLK is not set\n+CONFIG_DM_GPIO=y\n+CONFIG_DM_I2C=y\n+CONFIG_DM_MMC=y\n+# CONFIG_DM_MMC_OPS is not set\n CONFIG_SPI_FLASH=y\n CONFIG_SPI_FLASH_STMICRO=y\n CONFIG_PHYLIB=y\n CONFIG_PCI=y\n+CONFIG_PINCTRL=y\n+CONFIG_PINCTRL_IMX6=y\n+CONFIG_DM_PMIC=y\n+CONFIG_DM_PMIC_PFUZE100=y\n+CONFIG_DM_REGULATOR=y\n+CONFIG_DM_REGULATOR_PFUZE100=y\n+CONFIG_DM_REGULATOR_FIXED=y\n+CONFIG_DM_REGULATOR_GPIO=y\n CONFIG_USB=y\n CONFIG_USB_STORAGE=y\n CONFIG_USB_GADGET=y\ndiff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h\nindex 5410881..a945641 100644\n--- a/include/configs/mx6sabresd.h\n+++ b/include/configs/mx6sabresd.h\n@@ -43,20 +43,9 @@\n #define CONFIG_PCIE_IMX_POWER_GPIO\tIMX_GPIO_NR(3, 19)\n #endif\n \n-/* I2C Configs */\n-#define CONFIG_SYS_I2C\n #define CONFIG_SYS_I2C_MXC\n-#define CONFIG_SYS_I2C_MXC_I2C1\t\t/* enable I2C bus 1 */\n-#define CONFIG_SYS_I2C_MXC_I2C2\t\t/* enable I2C bus 2 */\n-#define CONFIG_SYS_I2C_MXC_I2C3\t\t/* enable I2C bus 3 */\n #define CONFIG_SYS_I2C_SPEED\t\t 100000\n \n-/* PMIC */\n-#define CONFIG_POWER\n-#define CONFIG_POWER_I2C\n-#define CONFIG_POWER_PFUZE100\n-#define CONFIG_POWER_PFUZE100_I2C_ADDR\t0x08\n-\n /* USB Configs */\n #ifdef CONFIG_CMD_USB\n #define CONFIG_EHCI_HCD_INIT_AFTER_RESET\n@@ -67,4 +56,8 @@\n #define CONFIG_USB_MAX_CONTROLLER_COUNT\t1 /* Enabled USB controller number */\n #endif\n \n+#ifdef CONFIG_SPL_BUILD\n+#undef CONFIG_SYS_I2C_MXC\n+#endif\n+\n #endif /* __MX6SABRESD_CONFIG_H */\n", "prefixes": [ "U-Boot", "V4", "11/12" ] }