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GET /api/1.2/patches/807315/?format=api
{ "id": 807315, "url": "http://patchwork.ozlabs.org/api/1.2/patches/807315/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/patch/1504041387.5204.20.camel@cavium.com/", "project": { "id": 41, "url": "http://patchwork.ozlabs.org/api/1.2/projects/41/?format=api", "name": "GNU C Library", "link_name": "glibc", "list_id": "libc-alpha.sourceware.org", "list_email": "libc-alpha@sourceware.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504041387.5204.20.camel@cavium.com>", "list_archive_url": null, "date": "2017-08-29T21:16:27", "name": "[AArch64] ILP32 math changes", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8d39bde1a7d81a180acd3dd95cda65d2aec948e2", "submitter": { "id": 70332, "url": "http://patchwork.ozlabs.org/api/1.2/people/70332/?format=api", "name": "Steve Ellcey", "email": "sellcey@cavium.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/glibc/patch/1504041387.5204.20.camel@cavium.com/mbox/", "series": [ { "id": 479, "url": "http://patchwork.ozlabs.org/api/1.2/series/479/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/list/?series=479", "date": "2017-08-29T21:16:27", "name": "[AArch64] ILP32 math changes", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/479/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807315/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807315/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<libc-alpha-return-83849-incoming=patchwork.ozlabs.org@sourceware.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list libc-alpha@sourceware.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-83849-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"CPbvIIx1\"; dkim-atps=neutral", "sourceware.org; auth=none", "spf=none (sender IP is )\n\tsmtp.mailfrom=Steve.Ellcey@cavium.com; " ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhhKL3yKbz9sNr\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 30 Aug 2017 07:16:54 +1000 (AEST)", "(qmail 8397 invoked by alias); 29 Aug 2017 21:16:46 -0000", "(qmail 8388 invoked by uid 89); 29 Aug 2017 21:16:46 -0000" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:message-id:subject:from:reply-to:to:cc:date\n\t:content-type:mime-version; q=dns; s=default; b=qAWt5eHzlXW5xuDy\n\tujaEOII/zIK/v3peEKWSH5xt/S+A8KAiyNGHMA6YtW7jb4Nv0mtCEHDW7lmfUVfb\n\tJvrzWSzSv0G2SLCNZ4jBkMaAkBUgQVAZEtM+upidfa0OUhyjfWfx1PnOhOAPyJ/J\n\t4c4Ml1q2T63D+BE/OcpxIWqM2wg=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:message-id:subject:from:reply-to:to:cc:date\n\t:content-type:mime-version; s=default; bh=fg0rKHcScLJtLpkuTIMbEL\n\tyTwEI=; b=CPbvIIx1KRoXAVOTyq5X9yxNA2IPB4HzgRXx00vS9LAcC/QI86RskM\n\tdYj3seJ8wmkf7DW5wPB+HI+Fw1M1nVqkDyoMQc0JuIp7C2dBX1x80wiYfPx89P5j\n\tXolkTVe29HHfOdTZlQT0mwxc1+fXqiEi4N1uHUGVHO2s2yN789L3Y=", "Mailing-List": "contact libc-alpha-help@sourceware.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<libc-alpha.sourceware.org>", "List-Unsubscribe": "<mailto:libc-alpha-unsubscribe-incoming=patchwork.ozlabs.org@sourceware.org>", "List-Subscribe": "<mailto:libc-alpha-subscribe@sourceware.org>", "List-Archive": "<http://sourceware.org/ml/libc-alpha/>", "List-Post": "<mailto:libc-alpha@sourceware.org>", "List-Help": "<mailto:libc-alpha-help@sourceware.org>,\n\t<http://sourceware.org/ml/#faqs>", "Sender": "libc-alpha-owner@sourceware.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-25.2 required=5.0 tests=AWL, BAYES_00,\n\tGIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tRCVD_IN_DNSWL_NONE,\n\tSPF_HELO_PASS autolearn=ham version=3.3.2 spammy=U*rth,\n\tHX-ClientProxiedBy:sk:MWHPR04", "X-HELO": "NAM01-BY2-obe.outbound.protection.outlook.com", "Message-ID": "<1504041387.5204.20.camel@cavium.com>", "Subject": "[PATCH] [AArch64] ILP32 math changes", "From": "Steve Ellcey <sellcey@cavium.com>", "Reply-To": "sellcey@cavium.com", "To": "libc-alpha <libc-alpha@sourceware.org>", "Cc": "Szabolcs Nagy <szabolcs.nagy@arm.com>, rth@twiddle.net, Joseph Myers\n\t<joseph@codesourcery.com>, Wilco Dijkstra <Wilco.Dijkstra@arm.com>, nd\n\t<nd@arm.com>", "Date": "Tue, 29 Aug 2017 14:16:27 -0700", "Content-Type": "multipart/mixed; boundary=\"=-oP8RJdvOHSaWUrc2/8hU\"", "Mime-Version": "1.0", "X-ClientProxiedBy": "MWHPR04CA0037.namprd04.prod.outlook.com (10.172.163.23) To\n\tMWHPR07MB3549.namprd07.prod.outlook.com (10.164.192.138)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "209627fe-4024-47ca-40aa-08d4ef233788", "X-Microsoft-Antispam": "UriScan:; BCL:0; PCL:0;\n\tRULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254152)(300000503095)(300135400095)(49563074)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);\n\tSRVR:MWHPR07MB3549; ", "X-Microsoft-Exchange-Diagnostics": [ "1; MWHPR07MB3549;\n\t3:mr/zpdym9ETpiz9zyX4H45dIMSYQYbgNPoPOex25bJe+LszDABTZ+sjMlZUxzqMIyMff1iU2YyE1Ge6pSB90SvVcifoRcK0h9o0x0s88ObhK2psdUDbEmCTfnGLukkVOcG6dQn+KFTw62mCIqgq+o7EvYz8Q5/u+RhgRfQLXqTBoepkejb0h9ijyLAgrU4h4wrm7jgWw6tmGmOMmTpgaj7gTiOCdscRrJgFsFNSLVSN2P6xAIXfrdLjrEh7hiWJ/;\n\t25:mlZgxQ44GH6Af20BCpycenZz/VCEcHhJq8fwQR5dYJdKIvsynPfZJMpYN4P/R4y0U03sFMeNLJ1g3WT15kKas1uEQTnw8fzNSpUJrlo3XeAJT7rdU8lySOwTEyNRgItVU0SLlBw7Xm6CAIO/U8LCzGqoEeEUSU+EKaQi+5B57sWFm4LQT8Ij/xlnVx3FTlyOXswlmserz0FZRKTMKi+n+8o+jdtX3PqWvu1zz7uU0xgx/VDXkbWNVo01gTH2+dlcJi5kOfyqGRbNUFp6SpK+641LKdlOUH4o6l3dXYze3sXcW7dR9EwpnfaXlFnGO29Xv6QEIXMdpJ6OY6/K30FbBg==;\n\t31:PWHobFEqEQRavwUyt/J2HJr2nrBuVa/ZuOIjLsk+t1ZAgSu+27yzL4PxKf8c20Q2lURkRenwNu7wf2e5TJDsNdIZlrnZrE6eiuzp+8tHvW/bSBFqROoC7ptBPpIh2Wr0ZxpmARJY1epdbMqzkRDmC/CWe7t/iRKZObWuU4MQOR2wLUEuS/UvpGSzXc02iLuA3ntO7NBE0opAXngLdHo+nPTWa5hnW7WlhnKXsmYWCvA=", "1; MWHPR07MB3549;\n\t20:pqDfqMS+YdA3HULSAnFhYOsopstawC1vBeG/vX6bZFr2oBtVZueqbdcOD84qMMaZzEgp4J7/4FzUQQbfxh8lhTEh6ZZe1hzYd22cshovBKxomKryFVvJb2B1ktTF8QxXtvCOU1PF/Syrwt7CO/K5H1xjXSWXrbTzESpcrduvBAGHSrTNE1T+4ZTH6hoh5lJKFo3V5U7LDUzrFoS9Pxhb5NgOuPCXLbJGoPCXid/bWmsAkLymjQ2LnuqYz5cIgmi9tv0uXZ+NfZgNgVN727FLirJz0yauV5s4c+s9ovnaTxHhxvH0qhhUc3/teGqVdcp3sSYqlIIuSJtrmkJ6qYMY9jJ1AVkp1PCXXIJSdNSQ4e5HPe098dvY09WuC65j0wg+oTzs1eTtSdY2BKIhti4YMwDtfWCdckjvt0Q85eCIgs1OYM85VS9Bv7asKxgWDEnKa7lSm3OX4a5jdwpi+jInVO6lMfRaNh71DnfEGiyXKYVDzti3DDdg/rLkLu8cj8xx;\n\t4:AEjI4h1fkNinn1V9XVZcspUkTzrPRN9MHGPmPdXwtofXfORZMrjfwfLbO1Fj5opzx2SRjzUB9zIfUGE56BGTwXJHIB1uz/rd9lSaVfQBYNxbrQVGoS+cn7PTJv87YGze8o30uorlw6R6seFFUDSKmZzxyUX42DcVw+DVOnonjt4pvSCVROWgzrY0yenkVhsI8ifLTqyy1cgJsJZmOYmQtdpaq2yJRbYRAICeGam62JroMDorP8y1QKopG9wQoUlE", "1; MWHPR07MB3549;\n\t23:w9mZCt2DPpfPtPPt2ap7CEz7I0gZLJP96jM919Z7Ro5Dmn3oBVYLruEjS2o8F3gBOg9z4wV/qpvTvSzC5ZdiZOqB5N4zMq6s3xEDaxsWfIaXU7E9y2us3GIbjXlSEQapiAbOrlJEoxdnut3dQ5O+CxtM5Um1N0UhuK5UusSB6JYZ10mIUhLslPfwq6rZ1/kq0PZsTBAGy93tbgmWPEZN/OA5qWwFqie6fTqdHEi1egtxGsiJYJcJZ6zhTTh9GYBYRbv97GBCJF6PWHx4IYdr6RMrJdowgGx4u/MQDhcHtbAqUqN2qDT4KrWF3dor/khhTHwlidnVh92KDfhv6m5kCLcZ/Ql51Hl6uom87AJzPylRaxmI4D8/wJNpuHKfdzMVBWEM5Jd9zo+kEZG07DhVBLEMd2uGjBXrjwD4u0TMn8ob5P2M4uEP4vbbdbtILAIFBF2/7moSijT9wvlUV7pQvtMF+oLbFsmGR6AvwHBk+G+S9MCbEzibJ9L+/0G09Yjsot5lbPpXKHCVYzM0n+vG71WOlpTcXXj95CJqJ3vQI7v7cqGTUUVJIJllwFSP9iCOtKS8Pq406CrdDmOUgj8vP/bsq6ztl560QejltKXfoWY/nXifRrsPpfOcCGRHBkS0NoRvWTncqQSyBol7NDVw2ph+egvZuM/T2IhwMjZ1apavHHI4PZvaUVJ/7SJP5tAlSBdWdEVztCQVJ57u91mLgwZRu6tPf5vxEJF/zd1e2LxLymrlhxZx3gTVe424k8J50M0cDeg5faMNv+2DO7JAJ+nE/s59SaRAsUFRtHtYbUtqYVz0gpTB0C/Llym6yIdFH+CPU0G4qFI7dPlI+8nxgPOiozpRC/1nOfkKlH7z+aIqUcOI2Uq8lZl+7zuqB5IrqXjVb0h2kn+7wIKHYAxkWW8wUVWIoA4o9Z9a2KydaI/Bk4NpMUme9A9Yu3LREJX6MYrb151uyCAANQD0C35enXxNLQSlopKsPV2aJeud6JIo/wnRey33xAYJzYxT/IatMx+kQ+NsX9OpEXS3+R2C5V2nUZh/2I+/3BFkRp/XKt19PigMpSn/cd5XM2lHb1c9PMBLwj9GnVtCS6C0YvNtf74w+OV6QRpdLXczuh1FHmybJrBeJZpV6+atdrMWV6BvgwzaKzsEzUcbd7+AELvn8aNQTot3gp/p5Y2QiRSXP9e2M1NzhphIKXOwa7JPxAQ2HW93MHxCJE9L7FA7z2hL+N2//HpJnR498EdbBuKgyGA=", "1; MWHPR07MB3549;\n\t6:EuHq+ItyWMxhfRQce5KMdpk7ujxXlb4pOUv2OIGpAKozUjlw3MZ9fcI3PrcXMshDV2I+Pb42WIj9MyIWuaL6tTPDEPL4w1cCX1+tRXmDYer1UYC93EDg9OQBys9wsmkQ3QnggkNHisaPGb2MLvSq1nLA+Ie66sHqdl1bTcZiPxEh0IoophgNh0m1PjMGwWWQaig3L+qdmhVCZR1JZ0jjNFnN8rTdyV6n9dRHe/QPIxZ+YXPNe6xwosUmahjMzckfNvFZOSMoRhSFKjKz47VEKNpFU2aEoKf231QcGu4uq/ZrEyV24BiTh762FXy747vsoDkuXftnwSblWEe40X8Vzg==;\n\t5:SUpexMR7RItC9CArxFXlDzy2xc9oyeGWDSBD+Ad9kE16f59o8zxxhv5Okfc/1ZiWZ0omJ0NdsUfuQAsB89eCeCCa1iQzSsGb5oYr9TNSeTDFJGvftso3BpLDULCwMWtztim+VYxKuFUVsMyomvS2JA==;\n\t24:sIuW+0tN/I13AgEg+QGwsCiRN+Shj7DNW6gSMF8rcOOE7GPYf+dMkE5gHkpckiXQjv2svp5bqfjT3QKxvQjNN2R3IltL95P10OybXxKBlSs=;\n\t7:dezWKO/aF6b8VwChua7+BsNf4rVX9oa4gJrtfOXU42otCptn1NeKzWRpk85VfQyrGL5AdDXpgmKTkEc+Nv2Pa7js0t/NjaBnZf/SgHQLHPj00mreDeAFUZfJoTrYw6yAqqlFO/X55moKvCFZsZucp4t8FQWzh0MvlOZBB7jwlpXxyDKk+O0ZctZOpvvigrpGszBl1GEBa6tu46jrMmMXQAXF20QIs5pl0+DTXliIqQw=" ], "X-MS-TrafficTypeDiagnostic": "MWHPR07MB3549:", "X-Exchange-Antispam-Report-Test": "UriScan:;", "X-Microsoft-Antispam-PRVS": "<MWHPR07MB3549281050E652E77A6A57CAF59F0@MWHPR07MB3549.namprd07.prod.outlook.com>", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(102415395)(6040450)(601004)(2401047)(5005006)(8121501046)(100000703101)(100105400095)(93006095)(93001095)(10201501046)(3002001)(6041248)(20161123558100)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123564025)(20161123562025)(20161123555025)(20161123560025)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:MWHPR07MB3549; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:MWHPR07MB3549; ", "X-Forefront-PRVS": "0414DF926F", "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(4630300001)(7370300001)(6009001)(199003)(377424004)(189002)(54906002)(8676002)(3846002)(103116003)(81166006)(68736007)(6506006)(7350300001)(81156014)(4326008)(84326002)(69596002)(5660300001)(305945005)(6916009)(36756003)(512874002)(50226002)(6486002)(6116002)(7736002)(5890100001)(6512007)(25786009)(106356001)(105586002)(72206003)(110136004)(66066001)(53936002)(50986999)(2476003)(2906002)(4610100001)(478600001)(568964002)(42186005)(33646002)(101416001)(189998001)(97736004)(53416004)(43066003)(3450700001)(99106002);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:MWHPR07MB3549;\n\tH:sellcey-dt.caveonetworks.com; FPR:; SPF:None;\n\tPTR:InfoNoRecords; A:1; MX:1; LANG:en; ", "Received-SPF": "None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "cavium.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "29 Aug 2017 21:16:29.8308\n\t(UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR07MB3549" }, "content": "Since Szabolcs has expressed interest in getting some aarch64 ILP32\nchanges into glibc mainline (if they don't affect the kernel or glibc\nABI) I am resubmitting this patch for approval in advance of the main\nILP32 support patches. I updated it with Richard Henderson's code (but\nonly doing it when the incoming argument is large). I tested it on\naarch64 ILP32 and LP64 with no regressions.\n\nIs this something that can be checked in now withnout waiting for the\nkernel ILP32 support?\n\nSteve Ellcey\nsellcey@cavium.com\n\n\n2017-08-29 Steve Ellcey <sellcey@cavium.com>\n\t Richard Henderson <rth@twiddle.net>\n\n\t* sysdeps/aarch64/fpu/s_llrint.c (OREG_SIZE): New macro.\n\t* sysdeps/aarch64/fpu/s_llround.c (OREG_SIZE): Likewise.\n\t* sysdeps/aarch64/fpu/s_llrintf.c (OREGS, IREGS): Remove.\n\t(IREG_SIZE, OREG_SIZE): New macros.\n\t* sysdeps/aarch64/fpu/s_llroundf.c: (OREGS, IREGS): Remove.\n\t(IREG_SIZE, OREG_SIZE): New macros.\n\t* sysdeps/aarch64/fpu/s_lrintf.c (IREGS): Remove.\n\t(IREG_SIZE): New macro.\n\t* sysdeps/aarch64/fpu/s_lroundf.c (IREGS): Remove.\n\t(IREG_SIZE): New macro.\n\t* sysdeps/aarch64/fpu/s_lrint.c (get-rounding-mode.h, stdint.h):\n\tNew includes.\n\t(IREG_SIZE, OREG_SIZE): Initialize if not already set.\n\t(OREGS, IREGS): Set based on IREG_SIZE and OREG_SIZE.\n\t(__CONCATX): Handle exceptions correctly on large values that may\n\tset FE_INVALID.\n\t* sysdeps/aarch64/fpu/s_lround.c (IREG_SIZE, OREG_SIZE):\n\tInitialize if not already set.\n (OREGS, IREGS): Set based on IREG_SIZE and OREG_SIZE.", "diff": "diff --git a/sysdeps/aarch64/fpu/s_llrint.c b/sysdeps/aarch64/fpu/s_llrint.c\nindex c0d0d0e..57821c0 100644\n--- a/sysdeps/aarch64/fpu/s_llrint.c\n+++ b/sysdeps/aarch64/fpu/s_llrint.c\n@@ -18,4 +18,5 @@\n \n #define FUNC llrint\n #define OTYPE long long int\n+#define OREG_SIZE 64\n #include <s_lrint.c>\ndiff --git a/sysdeps/aarch64/fpu/s_llrintf.c b/sysdeps/aarch64/fpu/s_llrintf.c\nindex 67724c6..98ed4f8 100644\n--- a/sysdeps/aarch64/fpu/s_llrintf.c\n+++ b/sysdeps/aarch64/fpu/s_llrintf.c\n@@ -18,6 +18,7 @@\n \n #define FUNC llrintf\n #define ITYPE float\n-#define IREGS \"s\"\n+#define IREG_SIZE 32\n #define OTYPE long long int\n+#define OREG_SIZE 64\n #include <s_lrint.c>\ndiff --git a/sysdeps/aarch64/fpu/s_llround.c b/sysdeps/aarch64/fpu/s_llround.c\nindex ed4b192..ef7aedf 100644\n--- a/sysdeps/aarch64/fpu/s_llround.c\n+++ b/sysdeps/aarch64/fpu/s_llround.c\n@@ -18,4 +18,5 @@\n \n #define FUNC llround\n #define OTYPE long long int\n+#define OREG_SIZE 64\n #include <s_lround.c>\ndiff --git a/sysdeps/aarch64/fpu/s_llroundf.c b/sysdeps/aarch64/fpu/s_llroundf.c\nindex 360ce8b..294f0f4 100644\n--- a/sysdeps/aarch64/fpu/s_llroundf.c\n+++ b/sysdeps/aarch64/fpu/s_llroundf.c\n@@ -18,6 +18,7 @@\n \n #define FUNC llroundf\n #define ITYPE float\n-#define IREGS \"s\"\n+#define IREG_SIZE 32\n #define OTYPE long long int\n+#define OREG_SIZE 64\n #include <s_lround.c>\ndiff --git a/sysdeps/aarch64/fpu/s_lrint.c b/sysdeps/aarch64/fpu/s_lrint.c\nindex 8c61a03..6ef64e2 100644\n--- a/sysdeps/aarch64/fpu/s_lrint.c\n+++ b/sysdeps/aarch64/fpu/s_lrint.c\n@@ -17,6 +17,8 @@\n <http://www.gnu.org/licenses/>. */\n \n #include <math.h>\n+#include <get-rounding-mode.h>\n+#include <stdint.h>\n \n #ifndef FUNC\n # define FUNC lrint\n@@ -24,18 +26,37 @@\n \n #ifndef ITYPE\n # define ITYPE double\n-# define IREGS \"d\"\n+# define IREG_SIZE 64\n #else\n-# ifndef IREGS\n-# error IREGS not defined\n+# ifndef IREG_SIZE\n+# error IREG_SIZE not defined\n # endif\n #endif\n \n #ifndef OTYPE\n # define OTYPE long int\n+# ifdef __ILP32__\n+# define OREG_SIZE 32\n+# else\n+# define OREG_SIZE 64\n+# endif\n+#else\n+# ifndef OREG_SIZE\n+# error OREG_SIZE not defined\n+# endif\n #endif\n \n-#define OREGS \"x\"\n+#if IREG_SIZE == 32\n+# define IREGS \"s\"\n+#else\n+# define IREGS \"d\"\n+#endif\n+\n+#if OREG_SIZE == 32\n+# define OREGS \"w\"\n+#else\n+# define OREGS \"x\"\n+#endif\n \n #define __CONCATX(a,b) __CONCAT(a,b)\n \n@@ -44,6 +65,37 @@ __CONCATX(__,FUNC) (ITYPE x)\n {\n OTYPE result;\n ITYPE temp;\n+\n+#if IREG_SIZE == 64 && OREG_SIZE == 32\n+ if (__builtin_fabs (x) > INT32_MAX)\n+ {\n+ /* Converting large values to a 32 bit int may cause the frintx/fcvtza\n+\t sequence to set both FE_INVALID and FE_INEXACT. To avoid this\n+\t check the rounding mode and do a single instruction with the\n+\t appropriate rounding mode. */\n+\n+ switch (get_rounding_mode ())\n+\t{\n+\tcase FE_TONEAREST:\n+\t asm volatile (\"fcvtns\" \"\\t%\" OREGS \"0, %\" IREGS \"1\"\n+\t\t\t: \"=r\" (result) : \"w\" (x));\n+\t break;\n+\tcase FE_UPWARD:\n+\t asm volatile (\"fcvtps\" \"\\t%\" OREGS \"0, %\" IREGS \"1\"\n+\t\t\t: \"=r\" (result) : \"w\" (x));\n+\t break;\n+\tcase FE_DOWNWARD:\n+\t asm volatile (\"fcvtms\" \"\\t%\" OREGS \"0, %\" IREGS \"1\"\n+\t\t\t: \"=r\" (result) : \"w\" (x));\n+\t break;\n+\tcase FE_TOWARDZERO:\n+\tdefault:\n+\t asm volatile (\"fcvtzs\" \"\\t%\" OREGS \"0, %\" IREGS \"1\"\n+\t\t\t: \"=r\" (result) : \"w\" (x));\n+\t}\n+ return result;\n+ }\n+#endif\n asm ( \"frintx\" \"\\t%\" IREGS \"1, %\" IREGS \"2\\n\\t\"\n \"fcvtzs\" \"\\t%\" OREGS \"0, %\" IREGS \"1\"\n : \"=r\" (result), \"=w\" (temp) : \"w\" (x) );\ndiff --git a/sysdeps/aarch64/fpu/s_lrintf.c b/sysdeps/aarch64/fpu/s_lrintf.c\nindex a995e4b..2e73271 100644\n--- a/sysdeps/aarch64/fpu/s_lrintf.c\n+++ b/sysdeps/aarch64/fpu/s_lrintf.c\n@@ -18,5 +18,5 @@\n \n #define FUNC lrintf\n #define ITYPE float\n-#define IREGS \"s\"\n+#define IREG_SIZE 32\n #include <s_lrint.c>\ndiff --git a/sysdeps/aarch64/fpu/s_lround.c b/sysdeps/aarch64/fpu/s_lround.c\nindex 9be9e7f..1f77d82 100644\n--- a/sysdeps/aarch64/fpu/s_lround.c\n+++ b/sysdeps/aarch64/fpu/s_lround.c\n@@ -24,18 +24,37 @@\n \n #ifndef ITYPE\n # define ITYPE double\n-# define IREGS \"d\"\n+# define IREG_SIZE 64\n #else\n-# ifndef IREGS\n-# error IREGS not defined\n+# ifndef IREG_SIZE\n+# error IREG_SIZE not defined\n # endif\n #endif\n \n #ifndef OTYPE\n # define OTYPE long int\n+# ifdef __ILP32__\n+# define OREG_SIZE 32\n+# else\n+# define OREG_SIZE 64\n+# endif\n+#else\n+# ifndef OREG_SIZE\n+# error OREG_SIZE not defined\n+# endif\n+#endif\n+\n+#if IREG_SIZE == 32\n+# define IREGS \"s\"\n+#else\n+# define IREGS \"d\"\n #endif\n \n-#define OREGS \"x\"\n+#if OREG_SIZE == 32\n+# define OREGS \"w\"\n+#else\n+# define OREGS \"x\"\n+#endif\n \n #define __CONCATX(a,b) __CONCAT(a,b)\n \ndiff --git a/sysdeps/aarch64/fpu/s_lroundf.c b/sysdeps/aarch64/fpu/s_lroundf.c\nindex 4a066d4..b30ddb6 100644\n--- a/sysdeps/aarch64/fpu/s_lroundf.c\n+++ b/sysdeps/aarch64/fpu/s_lroundf.c\n@@ -18,5 +18,5 @@\n \n #define FUNC lroundf\n #define ITYPE float\n-#define IREGS \"s\"\n+#define IREG_SIZE 32\n #include <s_lround.c>\n", "prefixes": [ "AArch64" ] }