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GET /api/1.2/patches/807195/?format=api
{ "id": 807195, "url": "http://patchwork.ozlabs.org/api/1.2/patches/807195/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170829172326.1131-1-bobby.prani@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170829172326.1131-1-bobby.prani@gmail.com>", "list_archive_url": null, "date": "2017-08-29T17:23:26", "name": "tcg/softmmu: Increase size of TLB caches", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "35b6d01f4d6ab24968f85193d138feda91732d28", "submitter": { "id": 64653, "url": "http://patchwork.ozlabs.org/api/1.2/people/64653/?format=api", "name": "Pranith Kumar", "email": "bobby.prani@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170829172326.1131-1-bobby.prani@gmail.com/mbox/", "series": [ { "id": 420, "url": "http://patchwork.ozlabs.org/api/1.2/series/420/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=420", "date": "2017-08-29T17:23:26", "name": "tcg/softmmu: Increase size of TLB caches", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/420/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807195/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807195/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"MArLCQpP\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhb8f58lGz9t2Q\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 30 Aug 2017 03:24:00 +1000 (AEST)", "from localhost ([::1]:46252 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dmkF2-0007ra-R2\n\tfor incoming@patchwork.ozlabs.org; Tue, 29 Aug 2017 13:23:56 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:34718)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <bobby.prani@gmail.com>) id 1dmkEg-0007rT-BN\n\tfor qemu-devel@nongnu.org; Tue, 29 Aug 2017 13:23:35 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <bobby.prani@gmail.com>) id 1dmkEb-0001jK-DV\n\tfor qemu-devel@nongnu.org; Tue, 29 Aug 2017 13:23:34 -0400", "from mail-yw0-x242.google.com ([2607:f8b0:4002:c05::242]:34710)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <bobby.prani@gmail.com>)\n\tid 1dmkEb-0001jA-8H\n\tfor qemu-devel@nongnu.org; Tue, 29 Aug 2017 13:23:29 -0400", "by mail-yw0-x242.google.com with SMTP id h127so2482438ywf.1\n\tfor <qemu-devel@nongnu.org>; Tue, 29 Aug 2017 10:23:29 -0700 (PDT)", "from localhost.localdomain ([98.192.46.210])\n\tby smtp.gmail.com with ESMTPSA id\n\tb2sm1234175ywc.22.2017.08.29.10.23.27\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 29 Aug 2017 10:23:27 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id;\n\tbh=NHugTQalvIiKhOHZEznqII8p/AljMahZvf4lJhaQjFI=;\n\tb=MArLCQpPfmFxlGhTODeHF/C+pwcyye4Z166JxXwOo7JLuqYQbtG9QNvRYJJyHb43HV\n\tU4uBDGSGmKXUjzUTx6nzvtUu1dsmd7eULuAMW/URaMz82GYtm80Rqe7/J6Gou0k2cvq9\n\tXCByOeOlwMJ9r4cyc6+GWHwRJTns/ufLt9ziCymqLR/S7WBsNiWyHROGoDnnKEGWKhx7\n\tvjeMXgH/wnEMRdqEHmCJSXdTCrqOYSiWH6uBxXcexlDPGm65nVi9VHjdJyB3qR+OxKe0\n\tBTy5ekWfizHwqrNV9AjDQX+FLs5y/hd/2N9SCaCa2gAanHgrDatvEE2kV5YG1nmTY71h\n\tOYOQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id;\n\tbh=NHugTQalvIiKhOHZEznqII8p/AljMahZvf4lJhaQjFI=;\n\tb=QMw92W7np8SjF1wBrqlnJ2N1CJ2X8bHFhrOPiPv8zux682VaeB/lL6NYr8m7QO/ItU\n\tIsQ2Vwt7TACSvryA3+GrYE+EwgMTl9fDgDpc2wCDxcpwXxQc5OoOUO/cRkybj+SZpG9+\n\t1jFvatXcY1G4aWFR9+btKRriLmuTg3Z+v3abBdTcXKzcm4FRTutYDqUzdPth0/ItRgBL\n\txo2regLir0ucY4+/En6N/pa3dblane5rWXZN6TDqjOjvBjd7nCl7XRC9771gElpRbiyi\n\t4kzlZ8Ot4dVm+YjiWDEoC6yZjIBbD/jOxgJy1fS0nl5ao0GQdU4DrDB8rHd5dqJ8vhGX\n\tuDdw==", "X-Gm-Message-State": "AHYfb5hVnviSR/rKvueYcQbh/6ErCBnJ7BJEjQoYsOqvfwxSfc03X2Kx\n\tQVtBnk5d9t0ORw==", "X-Received": "by 10.129.179.202 with SMTP id r193mr987878ywh.253.1504027408512;\n\tTue, 29 Aug 2017 10:23:28 -0700 (PDT)", "From": "Pranith Kumar <bobby.prani@gmail.com>", "To": "alex.bennee@linaro.org", "Date": "Tue, 29 Aug 2017 13:23:26 -0400", "Message-Id": "<20170829172326.1131-1-bobby.prani@gmail.com>", "X-Mailer": "git-send-email 2.13.0", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:4002:c05::242", "Subject": "[Qemu-devel] [PATCH] tcg/softmmu: Increase size of TLB caches", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "qemu-devel@nongnu.org, rth@twiddle.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "This patch increases the number of entries cached in the TLB. I went\nover a few architectures to see if increasing it is problematic. Only\narmv6 seems to have a limitation that only 8 bits can be used for\nindexing these entries. For other architectures, the number of TLB\nentries is increased to a 4K-sized cache. The patch also doubles the\nnumber of victim TLB entries.\n\nSome statistics collected from a build benchmark for various cache\nsizes is listed below:\n\n| TLB bits\\vTLB entires | 8 | 16 | 32 |\n| 8 | 952.94(+0.0%) | 929.99(+2.4%) | 919.02(+3.6%) |\n| 10 | 898.92(+5.6%) | 886.13(+7.0%) | 887.03(+6.9%) |\n| 12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) |\n\nThe best combination for this workload came out to be 12 bits for the\nTLB and a 16 entry vTLB cache.\n\nSigned-off-by: Pranith Kumar <bobby.prani@gmail.com>\n---\n include/exec/cpu-defs.h | 6 +++---\n tcg/aarch64/tcg-target.h | 1 +\n tcg/arm/tcg-target.h | 1 +\n tcg/i386/tcg-target.h | 2 ++\n tcg/ia64/tcg-target.h | 1 +\n tcg/mips/tcg-target.h | 2 ++\n tcg/ppc/tcg-target.h | 1 +\n tcg/s390/tcg-target.h | 1 +\n tcg/sparc/tcg-target.h | 1 +\n tcg/tci/tcg-target.h | 1 +\n 10 files changed, 14 insertions(+), 3 deletions(-)", "diff": "diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h\nindex bc8e7f848d..1957e3f32c 100644\n--- a/include/exec/cpu-defs.h\n+++ b/include/exec/cpu-defs.h\n@@ -57,8 +57,8 @@ typedef uint64_t target_ulong;\n #endif\n \n #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)\n-/* use a fully associative victim tlb of 8 entries */\n-#define CPU_VTLB_SIZE 8\n+/* use a fully associative victim tlb of 16 entries */\n+#define CPU_VTLB_SIZE 16\n \n #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32\n #define CPU_TLB_ENTRY_BITS 4\n@@ -89,7 +89,7 @@ typedef uint64_t target_ulong;\n * of tlb_table inside env (which is non-trivial but not huge).\n */\n #define CPU_TLB_BITS \\\n- MIN(8, \\\n+ MIN(MIN(12, TCG_TARGET_TLB_MAX_INDEX_BITS), \\\n TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \\\n (NB_MMU_MODES <= 1 ? 0 : \\\n NB_MMU_MODES <= 2 ? 1 : \\\ndiff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h\nindex b41a248bee..9f4558cd83 100644\n--- a/tcg/aarch64/tcg-target.h\n+++ b/tcg/aarch64/tcg-target.h\n@@ -15,6 +15,7 @@\n \n #define TCG_TARGET_INSN_UNIT_SIZE 4\n #define TCG_TARGET_TLB_DISPLACEMENT_BITS 24\n+#define TCG_TARGET_TLB_MAX_INDEX_BITS 32\n #undef TCG_TARGET_STACK_GROWSUP\n \n typedef enum {\ndiff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h\nindex a38be15a39..ebe27991f3 100644\n--- a/tcg/arm/tcg-target.h\n+++ b/tcg/arm/tcg-target.h\n@@ -60,6 +60,7 @@ extern int arm_arch;\n #undef TCG_TARGET_STACK_GROWSUP\n #define TCG_TARGET_INSN_UNIT_SIZE 4\n #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16\n+#define TCG_TARGET_TLB_MAX_INDEX_BITS 8\n \n typedef enum {\n TCG_REG_R0 = 0,\ndiff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h\nindex 73a15f7e80..5279af6eb1 100644\n--- a/tcg/i386/tcg-target.h\n+++ b/tcg/i386/tcg-target.h\n@@ -162,6 +162,8 @@ extern bool have_popcnt;\n # define TCG_AREG0 TCG_REG_EBP\n #endif\n \n+#define TCG_TARGET_TLB_MAX_INDEX_BITS (32 - CPU_TLB_ENTRY_BITS)\n+\n static inline void flush_icache_range(uintptr_t start, uintptr_t stop)\n {\n }\ndiff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h\nindex 8f475fe742..35878e20c7 100644\n--- a/tcg/ia64/tcg-target.h\n+++ b/tcg/ia64/tcg-target.h\n@@ -28,6 +28,7 @@\n \n #define TCG_TARGET_INSN_UNIT_SIZE 16\n #define TCG_TARGET_TLB_DISPLACEMENT_BITS 21\n+#define TCG_TARGET_TLB_MAX_INDEX_BITS 32\n \n typedef struct {\n uint64_t lo __attribute__((aligned(16)));\ndiff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h\nindex e9558d15bc..1b60e53169 100644\n--- a/tcg/mips/tcg-target.h\n+++ b/tcg/mips/tcg-target.h\n@@ -39,6 +39,8 @@\n #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16\n #define TCG_TARGET_NB_REGS 32\n \n+#define TCG_TARGET_TLB_MAX_INDEX_BITS (16 - CPU_TLB_ENTRY_BITS)\n+\n typedef enum {\n TCG_REG_ZERO = 0,\n TCG_REG_AT,\ndiff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h\nindex 5a092b038a..82e10c9471 100644\n--- a/tcg/ppc/tcg-target.h\n+++ b/tcg/ppc/tcg-target.h\n@@ -34,6 +34,7 @@\n #define TCG_TARGET_NB_REGS 32\n #define TCG_TARGET_INSN_UNIT_SIZE 4\n #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16\n+#define TCG_TARGET_TLB_MAX_INDEX_BITS 32\n \n typedef enum {\n TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3,\ndiff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h\nindex dc0e59193c..57f0e22532 100644\n--- a/tcg/s390/tcg-target.h\n+++ b/tcg/s390/tcg-target.h\n@@ -27,6 +27,7 @@\n \n #define TCG_TARGET_INSN_UNIT_SIZE 2\n #define TCG_TARGET_TLB_DISPLACEMENT_BITS 19\n+#define TCG_TARGET_TLB_MAX_INDEX_BITS 32\n \n typedef enum TCGReg {\n TCG_REG_R0 = 0,\ndiff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h\nindex 4515c9ab48..378d218923 100644\n--- a/tcg/sparc/tcg-target.h\n+++ b/tcg/sparc/tcg-target.h\n@@ -29,6 +29,7 @@\n \n #define TCG_TARGET_INSN_UNIT_SIZE 4\n #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32\n+#define TCG_TARGET_TLB_MAX_INDEX_BITS 12\n #define TCG_TARGET_NB_REGS 32\n \n typedef enum {\ndiff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h\nindex 06963288dc..bb36e8197d 100644\n--- a/tcg/tci/tcg-target.h\n+++ b/tcg/tci/tcg-target.h\n@@ -43,6 +43,7 @@\n #define TCG_TARGET_INTERPRETER 1\n #define TCG_TARGET_INSN_UNIT_SIZE 1\n #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32\n+#define TCG_TARGET_TLB_MAX_INDEX_BITS 32\n \n #if UINTPTR_MAX == UINT32_MAX\n # define TCG_TARGET_REG_BITS 32\n", "prefixes": [] }