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GET /api/1.2/patches/806959/?format=api
{ "id": 806959, "url": "http://patchwork.ozlabs.org/api/1.2/patches/806959/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170829063313.10237-4-bobby.prani@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170829063313.10237-4-bobby.prani@gmail.com>", "list_archive_url": null, "date": "2017-08-29T06:33:12", "name": "[RFC,v3,4/5] mttcg: Implement implicit ordering semantics", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d7cc15bd3edaccdc9274836327ed48b3930ddb1e", "submitter": { "id": 64653, "url": "http://patchwork.ozlabs.org/api/1.2/people/64653/?format=api", "name": "Pranith Kumar", "email": "bobby.prani@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170829063313.10237-4-bobby.prani@gmail.com/mbox/", "series": [ { "id": 312, "url": "http://patchwork.ozlabs.org/api/1.2/series/312/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=312", "date": "2017-08-29T06:33:12", "name": null, "version": 3, "mbox": "http://patchwork.ozlabs.org/series/312/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806959/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806959/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"vY3KGb8l\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhJks5Cfrz9t2v\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 29 Aug 2017 16:34:12 +1000 (AEST)", "from localhost ([::1]:43059 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dma6D-0000Qr-OR\n\tfor incoming@patchwork.ozlabs.org; Tue, 29 Aug 2017 02:34:09 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:38860)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <bobby.prani@gmail.com>) id 1dma5R-0000P6-LF\n\tfor qemu-devel@nongnu.org; Tue, 29 Aug 2017 02:33:22 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <bobby.prani@gmail.com>) id 1dma5Q-00042Q-Ia\n\tfor qemu-devel@nongnu.org; Tue, 29 Aug 2017 02:33:21 -0400", "from mail-yw0-x242.google.com ([2607:f8b0:4002:c05::242]:34754)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <bobby.prani@gmail.com>)\n\tid 1dma5Q-00042L-Do\n\tfor qemu-devel@nongnu.org; Tue, 29 Aug 2017 02:33:20 -0400", "by mail-yw0-x242.google.com with SMTP id h127so1495652ywf.1\n\tfor <qemu-devel@nongnu.org>; Mon, 28 Aug 2017 23:33:20 -0700 (PDT)", "from localhost.localdomain ([98.192.46.210])\n\tby smtp.gmail.com with ESMTPSA id\n\tx4sm817923ywa.44.2017.08.28.23.33.18\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tMon, 28 Aug 2017 23:33:18 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=7jf5kKveFFHMo0yJcrJ1liN+nMs1p848URNjXj7SZxg=;\n\tb=vY3KGb8lNeYKpI45nYNSYVMl2ecsk703DU6vJXrfVB+YQiSPBQ7g+dh7tOoXn9hBXS\n\tGaI8erj7DchQLPtR3cJwZPvLMs85McgACY0aHO9I8KImu7b6Bw1YMvfHCHmh53Tp3p3c\n\tiXO+SG+egDCtNimfSea7YKjLOZ8wRfjyG6pisTn/M7WaU/q4rw4pdr2ly7O3OQl0SX1W\n\tQcwbeuY0TyB4skpFLecKrhTN8Ce0YXx6nTPBF/anamoZNmEenEWYW99rjxQTaorQBHYt\n\twldroo2aZ7RmN/wu3kHXLZfR1J4wM+JoChhjro04GBh8ByTLHL4osgxfuxGQUKp/Rpvp\n\tyaMg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=7jf5kKveFFHMo0yJcrJ1liN+nMs1p848URNjXj7SZxg=;\n\tb=Fds9VRClE8nt8E4XD312BXcnVQ0k0f1ILTaU16CS0NChRfuUyf4HpKLFwqKs0aFJEj\n\t6CXEgoQRfbRG5+W8CySzr1atwNHK/R4js4Ml0FImXuZRl2obv8Xn5W846h8EKzNExm3S\n\t6bd148fRzmalzmEBCgzpqYDOXdkzWFHoJAyhPl0Z/rfX+0lWVj9sfSxrPnWlrlAsCbFn\n\tpnuFnJuYjdbIlQZ30Yt3PmVb+3Jw0am2LHysxsU5ZGCuORabbGGnkPxgL3fDsXhLlMPI\n\tbDhEdD/y6fwvsKnatwF1uvvvMbkOBVg2O0Cc5FBkrYuSLK65VQcaZXctIi97oXZqQDUE\n\tHkcg==", "X-Gm-Message-State": "AHYfb5hcogdcQ6Z/TViZGpZIHFWK+4rwfs9whWlLXHXlX7uv0Q8y+GX6\n\t6XQLtZIqOcSX0Q==", "X-Received": "by 10.13.204.131 with SMTP id o125mr2509450ywd.388.1503988399722;\n\tMon, 28 Aug 2017 23:33:19 -0700 (PDT)", "From": "Pranith Kumar <bobby.prani@gmail.com>", "To": "alex.bennee@linaro.org, Richard Henderson <rth@twiddle.net>,\n\tqemu-devel@nongnu.org (open list:All patches CC here)", "Date": "Tue, 29 Aug 2017 02:33:12 -0400", "Message-Id": "<20170829063313.10237-4-bobby.prani@gmail.com>", "X-Mailer": "git-send-email 2.13.0", "In-Reply-To": "<20170829063313.10237-1-bobby.prani@gmail.com>", "References": "<20170829063313.10237-1-bobby.prani@gmail.com>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:4002:c05::242", "Subject": "[Qemu-devel] [RFC v3 PATCH 4/5] mttcg: Implement implicit ordering\n\tsemantics", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "pbonzini@redhat.com, qemu-devel@nongnu.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Currently, we cannot use mttcg for running strong memory model guests\non weak memory model hosts due to missing ordering semantics.\n\nWe implicitly generate fence instructions for stronger guests if an\nordering mismatch is detected. We generate fences only for the orders\nfor which fence instructions are necessary, for example a fence is not\nnecessary between a store and a subsequent load on x86 since its\nabsence in the guest binary tells that ordering need not be\nensured. Also note that if we find multiple subsequent fence\ninstructions in the generated IR, we combine them in the TCG\noptimization pass.\n\nThis patch allows us to boot an x86 guest on ARM64 hosts using mttcg.\n\nSigned-off-by: Pranith Kumar <bobby.prani@gmail.com>\n---\n tcg/tcg-op.c | 16 ++++++++++++++++\n 1 file changed, 16 insertions(+)", "diff": "diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c\nindex 87f673ef49..688d91755b 100644\n--- a/tcg/tcg-op.c\n+++ b/tcg/tcg-op.c\n@@ -28,6 +28,7 @@\n #include \"exec/exec-all.h\"\n #include \"tcg.h\"\n #include \"tcg-op.h\"\n+#include \"tcg-mo.h\"\n #include \"trace-tcg.h\"\n #include \"trace/mem.h\"\n \n@@ -2662,8 +2663,20 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr,\n #endif\n }\n \n+static void tcg_gen_req_mo(TCGBar type)\n+{\n+#ifdef TCG_GUEST_DEFAULT_MO\n+ type &= TCG_GUEST_DEFAULT_MO;\n+#endif\n+ type &= ~TCG_TARGET_DEFAULT_MO;\n+ if (type) {\n+ tcg_gen_mb(type | TCG_BAR_SC);\n+ }\n+}\n+\n void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n {\n+ tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);\n memop = tcg_canonicalize_memop(memop, 0, 0);\n trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,\n addr, trace_mem_get_info(memop, 0));\n@@ -2672,6 +2685,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n \n void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n {\n+ tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);\n memop = tcg_canonicalize_memop(memop, 0, 1);\n trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,\n addr, trace_mem_get_info(memop, 1));\n@@ -2680,6 +2694,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n \n void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n {\n+ tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);\n if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {\n tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);\n if (memop & MO_SIGN) {\n@@ -2698,6 +2713,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n \n void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n {\n+ tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);\n if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {\n tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop);\n return;\n", "prefixes": [ "RFC", "v3", "4/5" ] }