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GET /api/1.2/patches/805811/?format=api
{ "id": 805811, "url": "http://patchwork.ozlabs.org/api/1.2/patches/805811/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/1503654642-59977-1-git-send-email-liudongdong3@huawei.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.2/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1503654642-59977-1-git-send-email-liudongdong3@huawei.com>", "list_archive_url": null, "date": "2017-08-25T09:50:42", "name": "PCI/portdrv: Fix MSI/MSI-X bug for PCIe port service drivers", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "d0c7535e63387ce548af720bec4f3e08e1303e81", "submitter": { "id": 67753, "url": "http://patchwork.ozlabs.org/api/1.2/people/67753/?format=api", "name": "Dongdong Liu", "email": "liudongdong3@huawei.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/1503654642-59977-1-git-send-email-liudongdong3@huawei.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/805811/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/805811/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-pci-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xdwgn4MfMz9sNd\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 25 Aug 2017 19:23:17 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754877AbdHYJXQ (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 25 Aug 2017 05:23:16 -0400", "from szxga05-in.huawei.com ([45.249.212.191]:4572 \"EHLO\n\tszxga05-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1754859AbdHYJXP (ORCPT\n\t<rfc822; linux-pci@vger.kernel.org>); Fri, 25 Aug 2017 05:23:15 -0400", "from 172.30.72.59 (EHLO DGGEMS411-HUB.china.huawei.com)\n\t([172.30.72.59])\n\tby dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DFX98451; Fri, 25 Aug 2017 17:23:10 +0800 (CST)", "from linux-ioko.site (10.71.200.31) by\n\tDGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP\n\tServer id 14.3.301.0; Fri, 25 Aug 2017 17:23:01 +0800" ], "From": "Dongdong Liu <liudongdong3@huawei.com>", "To": "<helgaas@kernel.org>", "CC": "<linux-pci@vger.kernel.org>, <gabriele.paoloni@huawei.com>,\n\t<charles.chenxin@huawei.com>, <linuxarm@huawei.com>,\n\tDongdong Liu <liudongdong3@huawei.com>", "Subject": "[PATCH] PCI/portdrv: Fix MSI/MSI-X bug for PCIe port service drivers", "Date": "Fri, 25 Aug 2017 17:50:42 +0800", "Message-ID": "<1503654642-59977-1-git-send-email-liudongdong3@huawei.com>", "X-Mailer": "git-send-email 1.9.1", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.71.200.31]", "X-CFilter-Loop": "Reflected", "X-Mirapoint-Virus-RAPID-Raw": "score=unknown(0),\n\trefid=str=0001.0A020206.599FEC7E.004D, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32", "X-Mirapoint-Loop-Id": "7a9864070fdcf63a55c4c5655d2f5135", "Sender": "linux-pci-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pci.vger.kernel.org>", "X-Mailing-List": "linux-pci@vger.kernel.org" }, "content": "Current code is broken as calling pci_free_irq_vectors()\ninvalidates the IRQ numbers returned before by pci_irq_vectors();\nso we need to move all the assignment of the Linux IRQ numbers at\nthe bottom of the function.\n\nAfter removing and adding back the PCI root port device,\nwe see the PCIe port service drivers request irq failed.\n\nroot@(none)$ lspci -tv\n-[0000:00]-+-00.0-[01]----00.0 Device 19e5:0123\n \\-08.0-[02-03]--+-00.0 Device 8086:10fb\n \\-00.1 Device 8086:10fb\n\nroot@(none)$ echo 1 > /sys/devices/pci0000\\:00/0000\\:00\\:00.0/remove\niommu: Removing device 0000:00:00.0 from group 2\nroot@(none)$ echo 1 > /sys/devices/pci0000\\:00/pci_bus/0000\\:00/rescan\npci 0000:01:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it\nwith 'pcie_aspm=force'\npci 0000:00:00.0: BAR 14: assigned [mem 0xe0100000-0xe03fffff]\npci 0000:00:00.0: BAR 15: assigned [mem 0x80000e00000-0x80000ffffff 64bit\npref]\npci 0000:00:00.0: BAR 13: assigned [io 0x1000-0x1fff]\npci 0000:01:00.0: BAR 0: assigned [mem 0xe0100000-0xe013ffff 64bit]\npci 0000:01:00.0: BAR 6: assigned [mem 0xe0140000-0xe015ffff pref]\npci 0000:00:00.0: PCI bridge to [bus 01]\npci 0000:00:00.0: bridge window [io 0x1000-0x1fff]\npci 0000:00:00.0: bridge window [mem 0xe0100000-0xe03fffff]\npci 0000:00:00.0: bridge window [mem 0x80000e00000-0x80000ffffff 64bit\npref]\niommu: Adding device 0000:00:00.0 to group 2\npcie_pme: probe of 0000:00:00.0:pcie001 failed with error -22\naer: probe of 0000:00:00.0:pcie002 failed with error -22\npciehp 0000:00:00.0:pcie004: Slot #0 AttnBtn- PwrCtrl- MRL- AttnInd-\nPwrInd- HotPlug+ Surprise+ Interlock- NoCompl- LLActRep+\npciehp 0000:00:00.0:pcie004: Cannot get irq 20 for the hotplug controller\npciehp 0000:00:00.0:pcie004: Notification initialization failed (-1)\ndpc 0000:00:00.0:pcie010: request IRQ22 failed: -22\ndpc: probe of 0000:00:00.0:pcie010 failed with error -22\n\nSigned-off-by: Dongdong Liu <liudongdong3@huawei.com>\nSigned-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>\n---\n drivers/pci/pcie/portdrv_core.c | 41 ++++++++++++++++++++++++-----------------\n 1 file changed, 24 insertions(+), 17 deletions(-)", "diff": "diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c\nindex 313a21d..4cac558 100644\n--- a/drivers/pci/pcie/portdrv_core.c\n+++ b/drivers/pci/pcie/portdrv_core.c\n@@ -54,7 +54,10 @@ static void release_pcie_device(struct device *dev)\n */\n static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask)\n {\n-\tint nr_entries, entry, nvec = 0;\n+\tint nr_entries, nvec = 0;\n+\tint entry_hp = 0;\n+\tint entry_aer = 0;\n+\tint entry_dpc = 0;\n \n \t/*\n \t * Allocate as many entries as the port wants, so that we can check\n@@ -86,14 +89,11 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask)\n \t\t * interrupt message.\"\n \t\t */\n \t\tpcie_capability_read_word(dev, PCI_EXP_FLAGS, ®16);\n-\t\tentry = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9;\n-\t\tif (entry >= nr_entries)\n+\t\tentry_hp = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9;\n+\t\tif (entry_hp >= nr_entries)\n \t\t\tgoto out_free_irqs;\n \n-\t\tirqs[PCIE_PORT_SERVICE_PME_SHIFT] = pci_irq_vector(dev, entry);\n-\t\tirqs[PCIE_PORT_SERVICE_HP_SHIFT] = pci_irq_vector(dev, entry);\n-\n-\t\tnvec = max(nvec, entry + 1);\n+\t\tnvec = max(nvec, entry_hp + 1);\n \t}\n \n \tif (mask & PCIE_PORT_SERVICE_AER) {\n@@ -114,13 +114,11 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask)\n \t\t */\n \t\tpos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);\n \t\tpci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, ®32);\n-\t\tentry = reg32 >> 27;\n-\t\tif (entry >= nr_entries)\n+\t\tentry_aer = reg32 >> 27;\n+\t\tif (entry_aer >= nr_entries)\n \t\t\tgoto out_free_irqs;\n \n-\t\tirqs[PCIE_PORT_SERVICE_AER_SHIFT] = pci_irq_vector(dev, entry);\n-\n-\t\tnvec = max(nvec, entry + 1);\n+\t\tnvec = max(nvec, entry_aer + 1);\n \t}\n \n \tif (mask & PCIE_PORT_SERVICE_DPC) {\n@@ -141,13 +139,11 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask)\n \t\t */\n \t\tpos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC);\n \t\tpci_read_config_word(dev, pos + PCI_EXP_DPC_CAP, ®16);\n-\t\tentry = reg16 & 0x1f;\n-\t\tif (entry >= nr_entries)\n+\t\tentry_dpc = reg16 & 0x1f;\n+\t\tif (entry_dpc >= nr_entries)\n \t\t\tgoto out_free_irqs;\n \n-\t\tirqs[PCIE_PORT_SERVICE_DPC_SHIFT] = pci_irq_vector(dev, entry);\n-\n-\t\tnvec = max(nvec, entry + 1);\n+\t\tnvec = max(nvec, entry_dpc + 1);\n \t}\n \n \t/*\n@@ -166,6 +162,17 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask)\n \t\t\treturn nr_entries;\n \t}\n \n+\tif (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP)) {\n+\t\tirqs[PCIE_PORT_SERVICE_PME_SHIFT] = pci_irq_vector(dev, entry_hp);\n+\t\tirqs[PCIE_PORT_SERVICE_HP_SHIFT] = pci_irq_vector(dev, entry_hp);\n+\t}\n+\n+\tif (mask & PCIE_PORT_SERVICE_AER)\n+\t\tirqs[PCIE_PORT_SERVICE_AER_SHIFT] = pci_irq_vector(dev, entry_aer);\n+\n+\tif (mask & PCIE_PORT_SERVICE_DPC)\n+\t\tirqs[PCIE_PORT_SERVICE_DPC_SHIFT] = pci_irq_vector(dev, entry_dpc);\n+\n \treturn 0;\n \n out_free_irqs:\n", "prefixes": [] }