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GET /api/1.2/patches/805770/?format=api
{ "id": 805770, "url": "http://patchwork.ozlabs.org/api/1.2/patches/805770/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1503639722-19121-9-git-send-email-paulus@ozlabs.org/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/1.2/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1503639722-19121-9-git-send-email-paulus@ozlabs.org>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1503639722-19121-9-git-send-email-paulus@ozlabs.org/", "date": "2017-08-25T05:42:00", "name": "[v2,08/10] powerpc: Emulate load/store floating double pair instructions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "27030cc1799e0a87f3017da8c715477ab8e168f4", "submitter": { "id": 67079, "url": "http://patchwork.ozlabs.org/api/1.2/people/67079/?format=api", "name": "Paul Mackerras", "email": "paulus@ozlabs.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1503639722-19121-9-git-send-email-paulus@ozlabs.org/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/805770/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/805770/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org", "linuxppc-dev@ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xdrbM28TZz9s7h\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri, 25 Aug 2017 16:19:11 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xdrbL6QMpzDqR9\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri, 25 Aug 2017 16:19:10 +1000 (AEST)", "from ozlabs.org (bilbo.ozlabs.org [103.22.144.67])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xdrDW5Rv7zDqXy\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 25 Aug 2017 16:02:51 +1000 (AEST)", "by ozlabs.org (Postfix)\n\tid 3xdrDW42bWz9sRY; Fri, 25 Aug 2017 16:02:51 +1000 (AEST)", "from authenticated.ozlabs.org (localhost [127.0.0.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPSA id 3xdrDW2ltSz9sxR\n\tfor <linuxppc-dev@ozlabs.org>; Fri, 25 Aug 2017 16:02:51 +1000 (AEST)" ], "Authentication-Results": [ "ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"ll6WE/PG\";\n\tdkim-atps=neutral", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"ll6WE/PG\";\n\tdkim-atps=neutral", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"ll6WE/PG\"; \n\tdkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; \n\tt=1503640971; bh=IQfWecpQ90mggu8xVSXGS6DeQHYIkz7GmH0Pcg0gT8g=;\n\th=From:To:Subject:Date:In-Reply-To:References:From;\n\tb=ll6WE/PGHu4P+68YazEJOkU+DJBpo/1a2r4xoZ8bhLNY45ydS1ACG6/LTjCd+i3Gn\n\tFIrjI76HJnDYkDsbO+wv7WL3qKyFFpc5bR07DOW8r3Ql0IOuf+IQrIiGdVCJ2GqpGG\n\tYvljHvaKcsz/BcK7e2IbkCNaO4eDHVLyvGiwECflHKzV6S7i0pz/FjMSF5AbkClMLr\n\ta30zbieH1trUcewVVkTwblS5V3iiqPnnJo74zmgqFVDHQRSoMBr3MBpAPgvev4SXvy\n\t8BoPy/mDp9n1mvfYUjF7b+VrjlbzI0NVi2TngPYMl+MQv9NfDHahrpDODW8EfCwd7M\n\tJg2d8w2f7/Yjw==", "From": "Paul Mackerras <paulus@ozlabs.org>", "To": "linuxppc-dev@ozlabs.org", "Subject": "[PATCH v2 08/10] powerpc: Emulate load/store floating double pair\n\tinstructions", "Date": "Fri, 25 Aug 2017 15:42:00 +1000", "Message-Id": "<1503639722-19121-9-git-send-email-paulus@ozlabs.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1503639722-19121-1-git-send-email-paulus@ozlabs.org>", "References": "<1503639722-19121-1-git-send-email-paulus@ozlabs.org>", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "This adds lfdp[x] and stfdp[x] to the set of instructions that\nanalyse_instr() and emulate_step() understand.\n\nSigned-off-by: Paul Mackerras <paulus@ozlabs.org>\n---\n arch/powerpc/lib/sstep.c | 76 ++++++++++++++++++++++++++++++++++++++----------\n 1 file changed, 60 insertions(+), 16 deletions(-)", "diff": "diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c\nindex 82b1e69..4773055 100644\n--- a/arch/powerpc/lib/sstep.c\n+++ b/arch/powerpc/lib/sstep.c\n@@ -414,9 +414,9 @@ static int do_fp_load(int rn, unsigned long ea, int nb, struct pt_regs *regs)\n \tint err;\n \tunion {\n \t\tfloat f;\n-\t\tdouble d;\n-\t\tunsigned long l;\n-\t\tu8 b[sizeof(double)];\n+\t\tdouble d[2];\n+\t\tunsigned long l[2];\n+\t\tu8 b[2 * sizeof(double)];\n \t} u;\n \n \tif (!address_ok(regs, ea, nb))\n@@ -426,11 +426,19 @@ static int do_fp_load(int rn, unsigned long ea, int nb, struct pt_regs *regs)\n \t\treturn err;\n \tpreempt_disable();\n \tif (nb == 4)\n-\t\tconv_sp_to_dp(&u.f, &u.d);\n+\t\tconv_sp_to_dp(&u.f, &u.d[0]);\n \tif (regs->msr & MSR_FP)\n-\t\tput_fpr(rn, &u.d);\n+\t\tput_fpr(rn, &u.d[0]);\n \telse\n-\t\tcurrent->thread.TS_FPR(rn) = u.l;\n+\t\tcurrent->thread.TS_FPR(rn) = u.l[0];\n+\tif (nb == 16) {\n+\t\t/* lfdp */\n+\t\trn |= 1;\n+\t\tif (regs->msr & MSR_FP)\n+\t\t\tput_fpr(rn, &u.d[1]);\n+\t\telse\n+\t\t\tcurrent->thread.TS_FPR(rn) = u.l[1];\n+\t}\n \tpreempt_enable();\n \treturn 0;\n }\n@@ -440,20 +448,27 @@ static int do_fp_store(int rn, unsigned long ea, int nb, struct pt_regs *regs)\n {\n \tunion {\n \t\tfloat f;\n-\t\tdouble d;\n-\t\tunsigned long l;\n-\t\tu8 b[sizeof(double)];\n+\t\tdouble d[2];\n+\t\tunsigned long l[2];\n+\t\tu8 b[2 * sizeof(double)];\n \t} u;\n \n \tif (!address_ok(regs, ea, nb))\n \t\treturn -EFAULT;\n \tpreempt_disable();\n \tif (regs->msr & MSR_FP)\n-\t\tget_fpr(rn, &u.d);\n+\t\tget_fpr(rn, &u.d[0]);\n \telse\n-\t\tu.l = current->thread.TS_FPR(rn);\n+\t\tu.l[0] = current->thread.TS_FPR(rn);\n \tif (nb == 4)\n-\t\tconv_dp_to_sp(&u.d, &u.f);\n+\t\tconv_dp_to_sp(&u.d[0], &u.f);\n+\tif (nb == 16) {\n+\t\trn |= 1;\n+\t\tif (regs->msr & MSR_FP)\n+\t\t\tget_fpr(rn, &u.d[1]);\n+\t\telse\n+\t\t\tu.l[1] = current->thread.TS_FPR(rn);\n+\t}\n \tpreempt_enable();\n \treturn copy_mem_out(u.b, ea, nb);\n }\n@@ -1966,7 +1981,21 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n \t\t\t\tgoto fpunavail;\n \t\t\top->type = MKOP(STORE_FP, u, 8);\n \t\t\tbreak;\n-#endif\n+\n+#ifdef __powerpc64__\n+\t\tcase 791:\t/* lfdpx */\n+\t\t\tif (!(regs->msr & MSR_FP))\n+\t\t\t\tgoto fpunavail;\n+\t\t\top->type = MKOP(LOAD_FP, 0, 16);\n+\t\t\tbreak;\n+\n+\t\tcase 919:\t/* stfdpx */\n+\t\t\tif (!(regs->msr & MSR_FP))\n+\t\t\t\tgoto fpunavail;\n+\t\t\top->type = MKOP(STORE_FP, 0, 16);\n+\t\t\tbreak;\n+#endif /* __powerpc64 */\n+#endif /* CONFIG_PPC_FPU */\n \n #ifdef __powerpc64__\n \t\tcase 660:\t/* stdbrx */\n@@ -1984,7 +2013,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n \t\t\top->val = byterev_4(regs->gpr[rd]);\n \t\t\tbreak;\n \n-\t\tcase 725:\n+\t\tcase 725:\t/* stswi */\n \t\t\tif (rb == 0)\n \t\t\t\trb = 32;\t/* # bytes to store */\n \t\t\top->type = MKOP(STORE_MULTI, 0, rb);\n@@ -2368,9 +2397,16 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n #endif\n \n #ifdef CONFIG_VSX\n-\tcase 57:\t/* lxsd, lxssp */\n+\tcase 57:\t/* lfdp, lxsd, lxssp */\n \t\top->ea = dsform_ea(instr, regs);\n \t\tswitch (instr & 3) {\n+\t\tcase 0:\t\t/* lfdp */\n+\t\t\tif (!(regs->msr & MSR_FP))\n+\t\t\t\tgoto fpunavail;\n+\t\t\tif (rd & 1)\n+\t\t\t\tbreak;\t\t/* reg must be even */\n+\t\t\top->type = MKOP(LOAD_FP, 0, 16);\n+\t\t\tbreak;\n \t\tcase 2:\t\t/* lxsd */\n \t\t\tif (!(regs->msr & MSR_VSX))\n \t\t\t\tgoto vsxunavail;\n@@ -2408,8 +2444,16 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n #endif\n \n #ifdef CONFIG_VSX\n-\tcase 61:\t/* lxv, stxsd, stxssp, stxv */\n+\tcase 61:\t/* stfdp, lxv, stxsd, stxssp, stxv */\n \t\tswitch (instr & 7) {\n+\t\tcase 0:\t\t/* stfdp with LSB of DS field = 0 */\n+\t\tcase 4:\t\t/* stfdp with LSB of DS field = 1 */\n+\t\t\top->ea = dsform_ea(instr, regs);\n+\t\t\tif (!(regs->msr & MSR_FP))\n+\t\t\t\tgoto fpunavail;\n+\t\t\top->type = MKOP(STORE_FP, 0, 16);\n+\t\t\tbreak;\n+\n \t\tcase 1:\t\t/* lxv */\n \t\t\top->ea = dqform_ea(instr, regs);\n \t\t\tif (!(instr & 8)) {\n", "prefixes": [ "v2", "08/10" ] }