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GET /api/1.2/patches/805593/?format=api
{ "id": 805593, "url": "http://patchwork.ozlabs.org/api/1.2/patches/805593/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170824184321.19432-4-ard.biesheuvel@linaro.org/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.2/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170824184321.19432-4-ard.biesheuvel@linaro.org>", "list_archive_url": null, "date": "2017-08-24T18:43:21", "name": "[v2,3/3] dt-bindings: designware: add binding for Designware PCIe in ECAM mode", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "463b7295b73a8b95ac1fda7185698c62ab709019", "submitter": { "id": 26857, "url": "http://patchwork.ozlabs.org/api/1.2/people/26857/?format=api", "name": "Ard Biesheuvel", "email": "ard.biesheuvel@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170824184321.19432-4-ard.biesheuvel@linaro.org/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/805593/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/805593/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-pci-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"hUcVF6u3\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xdY961TL3z9sRq\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 25 Aug 2017 04:43:54 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752909AbdHXSnw (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tThu, 24 Aug 2017 14:43:52 -0400", "from mail-wm0-f50.google.com ([74.125.82.50]:35721 \"EHLO\n\tmail-wm0-f50.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1753021AbdHXSnv (ORCPT\n\t<rfc822; linux-pci@vger.kernel.org>); Thu, 24 Aug 2017 14:43:51 -0400", "by mail-wm0-f50.google.com with SMTP id b189so2146954wmd.0\n\tfor <linux-pci@vger.kernel.org>; Thu, 24 Aug 2017 11:43:51 -0700 (PDT)", "from localhost.localdomain ([196.71.110.206])\n\tby smtp.gmail.com with ESMTPSA id\n\te2sm3531945wrd.60.2017.08.24.11.43.48\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tThu, 24 Aug 2017 11:43:49 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=lt5Vc3jPFYX7xUzjTmciGyhW5aRa2RkJ69BPzFtj69g=;\n\tb=hUcVF6u3opREYgu+9N/xBPcFEwpdArsu5o/815B6kUZb5p8hNQNKwnY8dINnmwjzca\n\tSOG/Q4+KS78GnbXAjGLd7AXf5oElap0X1z7lW4z5ojeM3RIpG3BlIV/BzUKFdQfsSy2a\n\tAYHnDLp23ygdWJg0s012cEz1EAugkZIM6lpDU=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=lt5Vc3jPFYX7xUzjTmciGyhW5aRa2RkJ69BPzFtj69g=;\n\tb=lcFDW+o/76HixART7MYmkPjMO9U+76T6qUNWEQ0q9nV0GuleIl2317e2q/tnhs8cHS\n\tD6EV8tDzThS4Q82MDYMzelO+QsY+s7sUzg0vh3DAsrUX4wvmjEcch89YEq5CVRPUj1CO\n\tkkCUNrMYXwRHYkWiBetacswTEHRIbwQaGdZhG7J2nNdRCmX8AHet5ZBsbejgnDGeQbTy\n\tDvRHZkoGdgRAhMA//E4kP9Mh6YV10DF+fPA8mvq6WLmo8/BopziVsJ+MJxV/fG+lKoGP\n\tQ6yE1D2BFFt//NLnhJcbJsZ06JCnm7rjIm3E26LPtJEqhl3RbnYTO3xVrmZ58z3c0JFr\n\tHhXQ==", "X-Gm-Message-State": "AHYfb5hXO2XjW1HF66YTmucjRIwXIrKEnlq3JWYx9cEiSia5cnKQ4l90\n\tdaeaP5jyIRFwd8AINuU0hw==", "X-Received": "by 10.28.102.135 with SMTP id a129mr1716840wmc.44.1503600230289; \n\tThu, 24 Aug 2017 11:43:50 -0700 (PDT)", "From": "Ard Biesheuvel <ard.biesheuvel@linaro.org>", "To": "linux-pci@vger.kernel.org", "Cc": "mw@semihalf.com, Ard Biesheuvel <ard.biesheuvel@linaro.org>,\n\tLeif Lindholm <leif.lindholm@linaro.org>,\n\tGraeme Gregory <graeme.gregory@linaro.org>,\n\tBjorn Helgaas <bhelgaas@google.com>, Jingoo Han <jingoohan1@gmail.com>,\n\tJoao Pinto <Joao.Pinto@synopsys.com>,\n\tMarc Zyngier <marc.zyngier@arm.com>, Rob Herring <robh@kernel.org>", "Subject": "[PATCH v2 3/3] dt-bindings: designware: add binding for Designware\n\tPCIe in ECAM mode", "Date": "Thu, 24 Aug 2017 19:43:21 +0100", "Message-Id": "<20170824184321.19432-4-ard.biesheuvel@linaro.org>", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": "<20170824184321.19432-1-ard.biesheuvel@linaro.org>", "References": "<20170824184321.19432-1-ard.biesheuvel@linaro.org>", "Sender": "linux-pci-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pci.vger.kernel.org>", "X-Mailing-List": "linux-pci@vger.kernel.org" }, "content": "Describe the binding for firmware-configured instances of the Synopsys\nDesignware PCIe controller in RC mode.\n\nCc: Rob Herring <robh@kernel.org>\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\n---\n Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt | 56 ++++++++++++++++++++\n 1 file changed, 56 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt\nnew file mode 100644\nindex 000000000000..b8127b19c220\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt\n@@ -0,0 +1,56 @@\n+* Synopsys Designware PCIe root complex in ECAM mode\n+\n+In some cases, firmware may already have configured the Synopsys Designware\n+PCIe controller in RC mode with static ATU window mappings that cover all\n+config, MMIO and I/O spaces in a [mostly] ECAM compatible fashion.\n+In this case, there is no need for the OS to perform any low level setup\n+of clocks or device registers, nor is there any reason for the driver to\n+reconfigure ATU windows for config and/or IO space accesses at runtime.\n+\n+Such hardware configurations should be described as \"pci-host-ecam-generic\"\n+if they are truly ECAM compatible. Configurations that require no low-level\n+setup by the OS nor any ATU window reconfiguration at runtime, but do\n+require special handling for type 0 config TLPs may instead be described as\n+\"snps,dw-pcie-ecam\".\n+\n+Required properties:\n+- compatible: should contain \"snps,dw-pcie-ecam\".\n+\n+Please refer to the binding document of \"pci-host-ecam-generic\" in the\n+file host-generic-pci.txt for a description of the remaining required\n+and optional properties.\n+\n+\n+* MSI support for Synopsys Designware PCIe root complex in ECAM mode\n+\n+Platforms that elect to perform all configuration of the RC in firmware\n+and use the \"pci-host-ecam-generic\" or \"snps,dw-pcie-ecam\" binding to\n+describe it to the OS may include a separate description of the embedded\n+MSI controller in case no MSI support is available in the core interrupt\n+controller.\n+\n+Required properties:\n+- compatible: should contain \"snps,dw-pcie-msi\".\n+- reg: a single region describing the device registers.\n+- interrupts: interrupt specifier for the interrupt that is asserted when\n+ an MSI is received by the RC.\n+- msi-controller: empty property identifying this device as an MSI controller.\n+\n+Example for an implementation that routes all legacy INTx interrupts via SPI\n+#188 and all MSI interrupts via SPI #190:\n+\n+ pcie@20000000 {\n+ compatible = \"snps,dw-pcie-ecam\";\n+ device_type = \"pci\";\n+ msi-parent = <&msi0>;\n+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;\n+ interrupt-map = <0x0 0x0 0x0 0x0 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;\n+ ...\n+ };\n+\n+ msi0: msi@10000000 {\n+ compatible = \"snps,dw-pcie-msi\";\n+ reg = <0x0 0x10000000 0x0 0x10000>;\n+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;\n+ msi-controller;\n+ };\n", "prefixes": [ "v2", "3/3" ] }