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GET /api/1.2/patches/804519/?format=api
{ "id": 804519, "url": "http://patchwork.ozlabs.org/api/1.2/patches/804519/?format=api", "web_url": "http://patchwork.ozlabs.org/project/skiboot/patch/1503414811-15197-1-git-send-email-clombard@linux.vnet.ibm.com/", "project": { "id": 44, "url": "http://patchwork.ozlabs.org/api/1.2/projects/44/?format=api", "name": "skiboot firmware development", "link_name": "skiboot", "list_id": "skiboot.lists.ozlabs.org", "list_email": "skiboot@lists.ozlabs.org", "web_url": "http://github.com/open-power/skiboot", "scm_url": "http://github.com/open-power/skiboot", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1503414811-15197-1-git-send-email-clombard@linux.vnet.ibm.com>", "list_archive_url": null, "date": "2017-08-22T15:13:31", "name": "capi: POWER9 DD2 update", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "475b470aa13d11ddd8d82efc5abe898bc6271631", "submitter": { "id": 67351, "url": "http://patchwork.ozlabs.org/api/1.2/people/67351/?format=api", "name": "Christophe Lombard", "email": "clombard@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/skiboot/patch/1503414811-15197-1-git-send-email-clombard@linux.vnet.ibm.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/804519/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/804519/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xcDbh2yNqz9sNd\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 23 Aug 2017 01:13:52 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xcDbg6D1HzDrCv\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 23 Aug 2017 01:13:51 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xcDbT3XZZzDqBV\n\tfor <skiboot@lists.ozlabs.org>; Wed, 23 Aug 2017 01:13:40 +1000 (AEST)", "from pps.filterd (m0098410.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7MFBGwS007953\n\tfor <skiboot@lists.ozlabs.org>; Tue, 22 Aug 2017 11:13:38 -0400", "from e06smtp13.uk.ibm.com (e06smtp13.uk.ibm.com [195.75.94.109])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2cgjs04m13-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <skiboot@lists.ozlabs.org>; Tue, 22 Aug 2017 11:13:38 -0400", "from localhost\n\tby e06smtp13.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <skiboot@lists.ozlabs.org> from <clombard@linux.vnet.ibm.com>;\n\tTue, 22 Aug 2017 16:13:35 +0100", "from b06cxnps4075.portsmouth.uk.ibm.com (9.149.109.197)\n\tby e06smtp13.uk.ibm.com (192.168.101.143) with IBM ESMTP SMTP\n\tGateway: Authorized Use Only! Violators will be prosecuted; \n\tTue, 22 Aug 2017 16:13:32 +0100", "from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com\n\t[9.149.105.61])\n\tby b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v7MFDWq617039612; Tue, 22 Aug 2017 15:13:32 GMT", "from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 0BFC311C04C;\n\tTue, 22 Aug 2017 16:10:14 +0100 (BST)", "from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 657CA11C04A;\n\tTue, 22 Aug 2017 16:10:13 +0100 (BST)", "from lombard-w520.ibm.com (unknown [9.164.146.234])\n\tby d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP;\n\tTue, 22 Aug 2017 16:10:13 +0100 (BST)" ], "From": "Christophe Lombard <clombard@linux.vnet.ibm.com>", "To": "skiboot@lists.ozlabs.org, fbarrat@linux.vnet.ibm.com,\n\tvaibhav@linux.vnet.ibm.com, andrew.donnellan@au1.ibm.com", "Date": "Tue, 22 Aug 2017 17:13:31 +0200", "X-Mailer": "git-send-email 2.7.4", "MIME-Version": "1.0", "X-TM-AS-GCONF": "00", "x-cbid": "17082215-0012-0000-0000-000005718355", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17082215-0013-0000-0000-000018E95EF9", "Message-Id": "<1503414811-15197-1-git-send-email-clombard@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-22_06:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708220232", "Subject": "[Skiboot] [PATCH] capi: POWER9 DD2 update", "X-BeenThere": "skiboot@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Mailing list for skiboot development <skiboot.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/skiboot/>", "List-Post": "<mailto:skiboot@lists.ozlabs.org>", "List-Help": "<mailto:skiboot-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"Skiboot\"\n\t<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "The CAPI initialization sequence has been updated in DD2.\nThis patch adapts to the changes, retaining compatibility with DD1.\n\nTests performed on some of the new hardware.\n\nSigned-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>\n---\n hw/phb4.c | 190 +++++++++++++++++++++++++++++++++++-----------------\n include/phb4-regs.h | 4 ++\n 2 files changed, 134 insertions(+), 60 deletions(-)", "diff": "diff --git a/hw/phb4.c b/hw/phb4.c\nindex a49f9db..ef923d9 100644\n--- a/hw/phb4.c\n+++ b/hw/phb4.c\n@@ -3350,13 +3350,17 @@ static void phb4_init_capp_regs(struct phb4 *p)\n \n \toffset = PHB4_CAPP_REG_OFFSET(p);\n \n-\t/* Enable cresp examination by CAPP */\n+\t/* APC Master PowerBus Control Register */\n \txscom_read(p->chip_id, APC_MASTER_PB_CTRL + offset, ®);\n-\treg |= PPC_BIT(0);\n+\treg |= PPC_BIT(0); /* enable cResp exam */\n+\treg |= PPC_BIT(3); /* disable vg not sys */\n \tif (p->rev == PHB4_REV_NIMBUS_DD10) {\n \t\treg |= PPC_BIT(1);\n-\t\t/* disable vg not sys */\n-\t\treg |= PPC_BIT(3);\n+\t}\n+\tif (p->rev == PHB4_REV_NIMBUS_DD20) {\n+\t\treg |= PPC_BIT(2); /* disable nn rn */\n+\t\treg |= PPC_BIT(4); /* disable g */\n+\t\treg |= PPC_BIT(5); /* disable ln */\n \t}\n \txscom_write(p->chip_id, APC_MASTER_PB_CTRL + offset, reg);\n \n@@ -3368,37 +3372,50 @@ static void phb4_init_capp_regs(struct phb4 *p)\n \t/* Set snoop ttype decoding , dir size to 256k */\n \txscom_write(p->chip_id, SNOOP_CAPI_CONFIG + offset, 0xA000000000000000);\n \n-\t/* Use Read Epsilon Tier2 for all scopes, Address Pipeline Master\n-\t * Wait Count to highest(1023) and Number of rpt_hang.data to 3\n+\t/* Use Read Epsilon Tier2 for all scopes.\n+\t * Set Tier2 Read Epsilon.\n \t */\n-\txscom_write(p->chip_id, SNOOP_CONTROL + offset, 0x8000000010072000);\n+\txscom_read(p->chip_id, SNOOP_CONTROL + offset, ®);\n+\treg |= PPC_BIT(0);\n+\treg |= PPC_BIT(35);\n+\txscom_write(p->chip_id, SNOOP_CONTROL + offset, reg);\n \n-\t/* TLBI Hang Divider = 16. CI Store Buffer Threshold initialized\n-\t * to b’0101’ = use 6 buffers. X16 PCIe(14 buffers)\n-\t */\n+\t/* Transport Control Register */\n \txscom_read(p->chip_id, TRANSPORT_CONTROL + offset, ®);\n-\tif (!(reg & PPC_BIT(4))) {\n-\t\tif (p->index == CAPP0_PHB_INDEX)\n-\t\t\txscom_write(p->chip_id, TRANSPORT_CONTROL + offset,\n-\t\t\t\t 0x081400000000000A);\n+\tif (p->index == CAPP0_PHB_INDEX) {\n+\t\treg |= PPC_BIT(1); /* Send Packet Timer Value */\n+\t\treg |= PPC_BITMASK(10, 13); /* Send Packet Timer Value */\n+\t\treg &= ~PPC_BITMASK(18, 21); /* Set Max tlbi divider */\n+\t\treg |= PPC_BIT(62);\n+\t}\n+\tif (p->index == CAPP1_PHB_INDEX) {\n+\t\treg |= PPC_BIT(4); /* Send Packet Timer Value */\n+\t\treg |= PPC_BIT(11); /* Set CI Store Buffer Threshold=5 */\n+\t\treg |= PPC_BIT(13); /* Set CI Store Buffer Threshold=5 */\n+\t}\n+\treg &= ~PPC_BITMASK(14, 17); /* Set Max LPC CI store buffer to zeros */\n+\treg |= PPC_BIT(60); /* Set lowest CI Store buffer used bits */\n \n-\t\tif (p->index == CAPP1_PHB_INDEX)\n-\t\t\txscom_write(p->chip_id, TRANSPORT_CONTROL + offset,\n-\t\t\t\t 0x0814000000000008);\n+\txscom_write(p->chip_id, TRANSPORT_CONTROL + offset, reg);\n \n-\t\t/* Initialize CI Store Buffers */\n-\t\txscom_read(p->chip_id, TRANSPORT_CONTROL + offset, ®);\n-\t\treg |= PPC_BIT(63);\n-\t\txscom_write(p->chip_id, TRANSPORT_CONTROL + offset, reg);\n-\t}\n+\t/* Initialize CI Store Buffers */\n+\txscom_read(p->chip_id, TRANSPORT_CONTROL + offset, ®);\n+\treg |= PPC_BIT(63);\n+\txscom_write(p->chip_id, TRANSPORT_CONTROL + offset, reg);\n \n \t/* Enable epoch timer */\n \txscom_write(p->chip_id, EPOCH_RECOVERY_TIMERS_CTRL + offset,\n-\t\t 0xC0000000FFF0FFFE);\n+\t\t 0xC0000000FFF8FFE0);\n \n+\t/* Flush SUE State Map Register */\n \txscom_write(p->chip_id, FLUSH_SUE_STATE_MAP + offset,\n \t\t 0x1DCF5F6600000000);\n-\txscom_write(p->chip_id, FLUSH_SUE_UOP1 + offset, 0xE310280428000000);\n+\n+\tif (p->rev == PHB4_REV_NIMBUS_DD20) {\n+\t\t/* Flush SUE uOP1 Register */\n+\t\txscom_write(p->chip_id, FLUSH_SUE_UOP1 + offset,\n+\t\t\t 0xE310280428000000);\n+\t}\n \n \t/* capp owns PHB read buffers */\n \tif (p->index == CAPP0_PHB_INDEX) {\n@@ -3408,14 +3425,26 @@ static void phb4_init_capp_regs(struct phb4 *p)\n \t\t\t 0xFFFFFFFFFFFF0000);\n \t}\n \tif (p->index == CAPP1_PHB_INDEX) {\n+\t\t/* Set 30 Read machines for CAPP Minus 20-27 for DMA */\n \t\txscom_write(p->chip_id, APC_FSM_READ_MASK + offset,\n-\t\t\t 0xFFFFFFFE00000000);\n+\t\t\t 0xFFFFF00E00000000);\n \t\txscom_write(p->chip_id, XPT_FSM_RMM + offset,\n-\t\t\t 0xFFFFFFFE00000000);\n+\t\t\t 0xFFFFF00E00000000);\n \t}\n \n+\t/* CAPP FIR Action 0 */\n+\txscom_write(p->chip_id, CAPP_FIR_ACTION0 + offset, 0);\n+\n+\t/* CAPP FIR Action 1 */\n+\txscom_write(p->chip_id, CAPP_FIR_ACTION1 + offset, 0);\n+\n \t/* Deassert TLBI_FENCED and tlbi_psl_is_dead */\n \txscom_write(p->chip_id, CAPP_ERR_STATUS_CTRL + offset, 0);\n+\n+\t/* Mask the CAPP PSL Credit Timeout Register error */\n+\txscom_read(p->chip_id, CAPP_FIR_MASK + offset, ®);\n+\treg |= PPC_BIT(46);\n+\txscom_write(p->chip_id, CAPP_FIR_MASK + offset, reg);\n }\n \n /* override some inits with CAPI defaults */\n@@ -3442,6 +3471,9 @@ static void phb4_init_capp_errors(struct phb4 *p)\n * NestBase = 4010C00 for PEC0\n * 4011000 for PEC1\n * 4011400 for PEC2\n+ * PCIBase = D010800 for PE0\n+ * E010800 for PE1\n+ * F010800 for PE2\n *\n * Some registers are shared amongst all of the stacks and will only\n * have 1 copy. Other registers are implemented one per stack.\n@@ -3455,31 +3487,19 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,\n \t\t\t\tenum capi_dma_tvt dma_tvt)\n {\n \tuint64_t reg, start_addr, end_addr;\n-\tuint32_t offset;\n \tint i;\n \n-\txscom_read(p->chip_id, p->pe_xscom + 0x7, ®);\n-\tif (reg & PPC_BIT(0))\n+\t/* CAPP Control Register */\n+\txscom_read(p->chip_id, p->pe_xscom + XPEC_NEST_CAPP_CNTL, ®);\n+\tif (reg & PPC_BIT(0)) {\n \t\tPHBDBG(p, \"Already in CAPP mode\\n\");\n-\n-\t/* PEC Phase 3 (PBCQ) registers Init */\n-\t/* poll cqstat\n-\t * CAPP0 attached to PHB0(PEC0)\n-\t * CAPP1 attached to PHB3(PEC2)\n-\t */\n-\tif (p->index == 0) {\n-\t\t/* PEC 0 */\n-\t\toffset = 0x40;\n-\t} else if (p->index == 1 || p->index == 2) {\n-\t\t/* PEC 1 */\n-\t\toffset = 0x80;\n-\t} else {\n-\t\t/* PEC 2 */\n-\t\toffset = 0xC0;\n \t}\n \n \tfor (i = 0; i < 500000; i++) {\n-\t\txscom_read(p->chip_id, p->pe_xscom + offset + 0xC, ®);\n+\t\t/* PBCQ General Status Register */\n+\t\txscom_read(p->chip_id,\n+\t\t\t p->pe_stk_xscom + XPEC_NEST_STK_PBCQ_STAT,\n+\t\t\t ®);\n \t\tif (!(reg & 0xC000000000000000))\n \t\t\tbreak;\n \t\ttime_wait_us(10);\n@@ -3489,24 +3509,48 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,\n \t\treturn OPAL_HARDWARE;\n \t}\n \n-\t/* Enable CAPP Mode , Set 14 CI Store buffers for CAPP,\n-\t * Set 48 Read machines for CAPP.\n+\t/* CAPP Control Register. Enable CAPP Mode */\n+\tif (p->index == CAPP0_PHB_INDEX) {\n+\t\t/* PBCQ is operating as a x16 stack the maximum number\n+\t\t * of engines give to CAPP will be 14 and will be\n+\t\t * assigned in the order of STQ 15 to 2\n+\t\t */\n+\t\t/* PBCQ is operating as a x16 stack engines 0-47 are\n+\t\t * available for capp use.\n+\t\t * Set 48 Read machines for CAPP\n+\t\t */\n+\t\treg = 0x800EFFFFFFFFFFFFULL;\n+\t}\n+\tif (p->index == CAPP1_PHB_INDEX) {\n+\t\t/* PBCQ is operating as a x8 stack the maximum number of\n+\t\t * engines given to CAPP should be 6 and will be\n+\t\t * assigned in the order of 7 to 2.\n+\t\t */\n+\t\t/* PBCQ is operating as a x8 stack the only engines\n+\t\t * 0-30 are available for capp use.\n+\t\t * Set 30 Read machines, minus 20-27 for DMA\n+\t\t */\n+\t\treg = 0x8006FFFFF00E0000ULL;\n+\t}\n+\txscom_write(p->chip_id, p->pe_xscom + XPEC_NEST_CAPP_CNTL, reg);\n+\n+\t/* PCI to PB data movement ignores the PB init signal.\n+\t * Disable streaming.\n \t */\n+\txscom_read(p->chip_id, p->pe_xscom + XPEC_NEST_PBCQ_HW_CONFIG, ®);\n+\treg |= XPEC_NEST_PBCQ_HW_CONFIG_PBINIT;\n \tif (p->index == CAPP0_PHB_INDEX)\n-\t\treg = 0x800EFFFFFFFFFFFF;\n-\n-\tif (p->index == CAPP1_PHB_INDEX)\n-\t\treg = 0x8006FFFFFFFE0000;\n-\txscom_write(p->chip_id, p->pe_xscom + 0x7, reg);\n-\n-\tif (p->rev == PHB4_REV_NIMBUS_DD10) {\n-\t\t/* Ignores the PB init signal */\n-\t\txscom_read(p->chip_id, p->pe_xscom + 0x0, ®);\n-\t\treg |= PPC_BIT(12);\n-\t\txscom_write(p->chip_id, p->pe_xscom + 0x0, reg);\n-\t}\n+\t\treg &= ~XPEC_NEST_PBCQ_HW_CONFIG_CH_STR;\n+\txscom_write(p->chip_id, p->pe_xscom + XPEC_NEST_PBCQ_HW_CONFIG, reg);\n \n \t/* PEC Phase 4 (PHB) registers adjustment\n+\t * Inbound CAPP traffic: The CAPI can send both CAPP packets and\n+\t * I/O packets. A PCIe packet is indentified as a CAPP packet in\n+\t * the PHB if the PCIe address matches either the CAPI\n+\t * Compare/Mask register or its NBW Compare/Mask register.\n+\t */\n+\n+\t/*\n \t * Bit [0:7] XSL_DSNCTL[capiind]\n \t * Init_25 - CAPI Compare/Mask\n \t */\n@@ -3514,13 +3558,39 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,\n \t\t 0x0200FE0000000000Ull | PHB_CAPI_CMPM_ENABLE);\n \n \tif (!(p->rev == PHB4_REV_NIMBUS_DD10)) {\n-\t\t/* Init_123 : NBW Compare/Mask Register */\n+\t\t/* Init_123 : NBW Compare/Mask Register.\n+\t\t * If a CAPP packet is designated as NBW it will be\n+\t\t * guaranteed a non-blocking path through the PHB and\n+\t\t * PEC. This is done in the PEC by guaranteeing at least\n+\t\t * 1 of the DMA write buffers and controllers will be\n+\t\t * reserved for NBW.\n+\t\t */\n \t\tout_be64(p->regs + PHB_PBL_NBW_CMP_MASK,\n \t\t\t 0x0300FF0000000000Ull | PHB_PBL_NBW_MASK_ENABLE);\n \n \t\t/* Init_24 - ASN Compare/Mask */\n \t\tout_be64(p->regs + PHB_PBL_ASN_CMPM,\n \t\t\t 0x0400FF0000000000Ull | PHB_PBL_ASN_ENABLE);\n+\n+\t\t/* PBCQ Tunnel Bar Register\n+\t\t * Write Tunnel register to match PSL TNR register\n+\t\t */\n+\t\txscom_write(p->chip_id,\n+\t\t\t p->pe_stk_xscom + XPEC_NEST_STK_TUNNEL_BAR,\n+\t\t\t 0x020000E000000000);\n+\n+\t\t/* PB AIB Hardware Control Register\n+\t\t * Wait 32 PCI clocks for a credit to become available\n+\t\t * before rejecting.\n+\t\t */\n+\t\txscom_read(p->chip_id,\n+\t\t\t p->pci_xscom + XPEC_PCI_PBAIB_HW_CONFIG, ®);\n+\t\treg |= PPC_BITMASK(40, 42);\n+\t\tif (p->index == CAPP1_PHB_INDEX)\n+\t\t\treg |= PPC_BIT(30);\n+\t\txscom_write(p->chip_id,\n+\t\t\t p->pci_xscom + XPEC_PCI_PBAIB_HW_CONFIG,\n+\t\t\t reg);\n \t}\n \n \t/* non-translate/50-bit mode */\ndiff --git a/include/phb4-regs.h b/include/phb4-regs.h\nindex 59c308e..e83c8c3 100644\n--- a/include/phb4-regs.h\n+++ b/include/phb4-regs.h\n@@ -337,6 +337,9 @@\n \n /* Nest base registers */\n #define XPEC_NEST_PBCQ_HW_CONFIG\t\t0x0\n+#define XPEC_NEST_PBCQ_HW_CONFIG_PBINIT\tPPC_BIT(12)\n+#define XPEC_NEST_PBCQ_HW_CONFIG_CH_STR\tPPC_BIT(33)\n+#define XPEC_NEST_CAPP_CNTL\t\t\t0x7\n \n /* Nest base per-stack registers */\n #define XPEC_NEST_STK_PCI_NFIR\t\t\t0x0\n@@ -365,6 +368,7 @@\n #define XPEC_NEST_STK_BAR_EN_PHB\t\tPPC_BIT(2)\n #define XPEC_NEST_STK_BAR_EN_INT\t\tPPC_BIT(3)\n #define XPEC_NEST_STK_DATA_FREZ_TYPE\t\t0x15\n+#define XPEC_NEST_STK_TUNNEL_BAR\t\t0x16\n \n /* PCI base registers */\n #define XPEC_PCI_PBAIB_HW_CONFIG\t\t0x0\n", "prefixes": [] }