Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.2/patches/802868/?format=api
{ "id": 802868, "url": "http://patchwork.ozlabs.org/api/1.2/patches/802868/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170817185413.6324-5-mperttunen@nvidia.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/1.2/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170817185413.6324-5-mperttunen@nvidia.com>", "list_archive_url": null, "date": "2017-08-17T18:54:11", "name": "[4/6] dt-bindings: host1x: Fix and add Tegra186 information", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "2049b09f3b0e7513c77bf82d57d94d234fbb274c", "submitter": { "id": 26499, "url": "http://patchwork.ozlabs.org/api/1.2/people/26499/?format=api", "name": "Mikko Perttunen", "email": "mperttunen@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170817185413.6324-5-mperttunen@nvidia.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/802868/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/802868/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xYFr46zKPz9s4q\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tFri, 18 Aug 2017 04:59:16 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753516AbdHQS7D (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tThu, 17 Aug 2017 14:59:03 -0400", "from mail.kapsi.fi ([91.232.154.25]:41057 \"EHLO mail.kapsi.fi\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1752647AbdHQS5x (ORCPT <rfc822;devicetree@vger.kernel.org>);\n\tThu, 17 Aug 2017 14:57:53 -0400", "from dsl-hkibng41-567306-181.dhcp.inet.fi ([86.115.6.181]\n\thelo=localhost.localdomain) by mail.kapsi.fi with esmtpsa\n\t(TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n\t(Exim 4.84_2) (envelope-from <mperttunen@nvidia.com>)\n\tid 1diPzC-0003Fl-JC; Thu, 17 Aug 2017 21:57:42 +0300" ], "From": "Mikko Perttunen <mperttunen@nvidia.com>", "To": "thierry.reding@gmail.com, jonathanh@nvidia.com, robh+dt@kernel.org,\n\tmark.rutland@arm.com", "Cc": "digetx@gmail.com, amerilainen@nvidia.com, dnibade@nvidia.com,\n\tsgurrappadi@nvidia.com, dri-devel@lists.freedesktop.org,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tMikko Perttunen <mperttunen@nvidia.com>", "Subject": "[PATCH 4/6] dt-bindings: host1x: Fix and add Tegra186 information", "Date": "Thu, 17 Aug 2017 21:54:11 +0300", "Message-Id": "<20170817185413.6324-5-mperttunen@nvidia.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170817185413.6324-1-mperttunen@nvidia.com>", "References": "<20170817185413.6324-1-mperttunen@nvidia.com>", "X-SA-Exim-Connect-IP": "86.115.6.181", "X-SA-Exim-Mail-From": "mperttunen@nvidia.com", "X-SA-Exim-Scanned": "No (on mail.kapsi.fi); SAEximRunCond expanded to false", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "Add note that address/size-cells should be 2 on 64-bit systems,\nand add Tegra186-specific register range properties.\n\nSigned-off-by: Mikko Perttunen <mperttunen@nvidia.com>\n---\n .../devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt | 9 +++++++--\n 1 file changed, 7 insertions(+), 2 deletions(-)", "diff": "diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt\nindex 74e1e8add5a1..b3e785b47100 100644\n--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt\n+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt\n@@ -3,11 +3,16 @@ NVIDIA Tegra host1x\n Required properties:\n - compatible: \"nvidia,tegra<chip>-host1x\"\n - reg: Physical base address and length of the controller's registers.\n+ For pre-Tegra186, one entry describing the whole register area.\n+ For Tegra186, one entry for each entry in reg-names:\n+ \"vm\" - VM region assigned to Linux\n+ \"hypervisor\" - Hypervisor region (only if Linux acts as hypervisor)\n - interrupts: The interrupt outputs from the controller.\n - #address-cells: The number of cells used to represent physical base addresses\n- in the host1x address space. Should be 1.\n+ in the host1x address space. Should be 1 for 32-bit and 2 for 64-bit systems.\n - #size-cells: The number of cells used to represent the size of an address\n- range in the host1x address space. Should be 1.\n+ range in the host1x address space. Should be 1 for 32-bit and 2 for 64-bit\n+ systems.\n - ranges: The mapping of the host1x address space to the CPU address space.\n - clocks: Must contain one entry, for the module clock.\n See ../clocks/clock-bindings.txt for details.\n", "prefixes": [ "4/6" ] }