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Update a patch.
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Update a patch.
GET /api/1.2/patches/802398/?format=api
{ "id": 802398, "url": "http://patchwork.ozlabs.org/api/1.2/patches/802398/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1502955089-2049-3-git-send-email-ran.wang_1@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1502955089-2049-3-git-send-email-ran.wang_1@nxp.com>", "list_archive_url": null, "date": "2017-08-17T07:31:24", "name": "[U-Boot,v3,3/8] armv8: Add workaround for USB erratum A-008997", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "30965d1632a741ab89007119a8ffc85dcd053f56", "submitter": { "id": 71939, "url": "http://patchwork.ozlabs.org/api/1.2/people/71939/?format=api", "name": "Ran Wang", "email": "ran.wang_1@nxp.com" }, "delegate": { "id": 2666, "url": "http://patchwork.ozlabs.org/api/1.2/users/2666/?format=api", "username": "yorksun", "first_name": "York", "last_name": "Sun", "email": "yorksun@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1502955089-2049-3-git-send-email-ran.wang_1@nxp.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/802398/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/802398/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com;" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xXz3p6wkYz9t3D\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 17 Aug 2017 17:53:26 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid B8769C21EDF; Thu, 17 Aug 2017 07:53:24 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 0A532C21F48;\n\tThu, 17 Aug 2017 07:49:06 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid C46D0C21F4E; Thu, 17 Aug 2017 07:48:42 +0000 (UTC)", "from NAM01-BN3-obe.outbound.protection.outlook.com\n\t(mail-bn3nam01on0073.outbound.protection.outlook.com [104.47.33.73])\n\tby lists.denx.de (Postfix) with ESMTPS id 48B0AC21EC1\n\tfor <u-boot@lists.denx.de>; Thu, 17 Aug 2017 07:48:38 +0000 (UTC)", "from BN6PR03CA0066.namprd03.prod.outlook.com (10.173.137.28) by\n\tDM5PR03MB3323.namprd03.prod.outlook.com (10.174.241.144) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.1.1362.18; Thu, 17 Aug 2017 07:48:36 +0000", "from BN1AFFO11FD007.protection.gbl (2a01:111:f400:7c10::119) by\n\tBN6PR03CA0066.outlook.office365.com (2603:10b6:404:4c::28) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1362.18\n\tvia Frontend Transport; Thu, 17 Aug 2017 07:48:36 +0000", "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBN1AFFO11FD007.mail.protection.outlook.com (10.58.52.67) with\n\tMicrosoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1341.15\n\tvia Frontend Transport; Thu, 17 Aug 2017 07:48:35 +0000", "from titan.ap.freescale.net ([10.192.208.233])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv7H7mNcT022692; Thu, 17 Aug 2017 00:48:32 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=BAD_ENC_HEADER,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL,\n\tSPF_HELO_PASS\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "Ran Wang <ran.wang_1@nxp.com>", "To": "open list <u-boot@lists.denx.de>, Albert Aribaud\n\t<albert.u.boot@aribaud.net>, York Sun <york.sun@nxp.com>, Suresh Gupta\n\t<suresh.bhagat@nxp.com>, Sriram Dash <sriram.dash@nxp.com>", "Date": "Thu, 17 Aug 2017 15:31:24 +0800", "Message-ID": "<1502955089-2049-3-git-send-email-ran.wang_1@nxp.com>", "X-Mailer": "git-send-email 2.1.0.27.g96db324", "In-Reply-To": "<1502955089-2049-1-git-send-email-ran.wang_1@nxp.com>", "References": "<1502955089-2049-1-git-send-email-ran.wang_1@nxp.com>", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131474297160461426;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); 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BCL:0; PCL:0;\n\tRULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(300000503095)(300135400095)(2017052603031)(201703131430075)(201703131517081)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);\n\tSRVR:DM5PR03MB3323; ", "X-MS-TrafficTypeDiagnostic": "DM5PR03MB3323:", "X-Exchange-Antispam-Report-Test": "UriScan:(185117386973197);", "X-Microsoft-Antispam-PRVS": "<DM5PR03MB3323B6D6A6272F64D521B5DDF1830@DM5PR03MB3323.namprd03.prod.outlook.com>", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6095135)(601004)(2401047)(8121501046)(13016025)(5005006)(13018025)(3002001)(100000703101)(100105400095)(10201501046)(93006095)(93001095)(6055026)(6096035)(20161123561025)(20161123565025)(201703131430075)(201703131433075)(201703131448075)(201703161259150)(201703151042153)(20161123556025)(20161123559100)(20161123563025)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:DM5PR03MB3323; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:DM5PR03MB3323; ", "X-Forefront-PRVS": "0402872DA1", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "17 Aug 2017 07:48:35.8121\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM5PR03MB3323", "Cc": "Priyanka Jain <priyanka.jain@nxp.com>, ran.wang_1@nxp.com", "Subject": "[U-Boot] [PATCH v3 3/8] armv8: Add workaround for USB erratum\n\tA-008997", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential\nOutput Voltage Test Compliance fails using default transmitter\nsettings\n\nChange setting required for transmitter signal swings to pass\ncompliance tests.\n\nSigned-off-by: Sriram Dash <sriram.dash@nxp.com>\nSigned-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>\nSigned-off-by: Suresh Gupta <suresh.gupta@nxp.com>\nSigned-off-by: Ran Wang <ran.wang_1@nxp.com>\n---\nChange in v3:\n\tUse inline function to make code cleaner.\n\tCorrect typo of 'CONFIG_ARCH_LS1043A'.\n\nChange in v2:\n\tIn function erratum_a008997():\n\t1.Put a blank line after variable declaration.\n\n arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 +++++\n arch/arm/cpu/armv8/fsl-layerscape/soc.c | 26 ++++++++++++++++++++++\n .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 ++++\n 3 files changed, 36 insertions(+)", "diff": "diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\nindex 2dae539..a2de86b 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n@@ -24,6 +24,7 @@ config ARCH_LS1043A\n \tselect SYS_FSL_ERRATUM_A010539\n \tselect SYS_FSL_ERRATUM_A009008\n \tselect SYS_FSL_ERRATUM_A009798\n+\tselect SYS_FSL_ERRATUM_A008997\n \tselect SYS_FSL_HAS_DDR3\n \tselect SYS_FSL_HAS_DDR4\n \tselect ARCH_EARLY_INIT_R\n@@ -47,6 +48,7 @@ config ARCH_LS1046A\n \tselect SYS_FSL_ERRATUM_A010539\n \tselect SYS_FSL_ERRATUM_A009008\n \tselect SYS_FSL_ERRATUM_A009798\n+\tselect SYS_FSL_ERRATUM_A008997\n \tselect SYS_FSL_HAS_DDR4\n \tselect SYS_FSL_SRDS_2\n \tselect ARCH_EARLY_INIT_R\n@@ -85,6 +87,7 @@ config ARCH_LS2080A\n \tselect SYS_FSL_ERRATUM_A009203\n \tselect SYS_FSL_ERRATUM_A009008\n \tselect SYS_FSL_ERRATUM_A009798\n+\tselect SYS_FSL_ERRATUM_A008997\n \tselect ARCH_EARLY_INIT_R\n \tselect BOARD_EARLY_INIT_F\n \n@@ -234,6 +237,9 @@ config SYS_FSL_ERRATUM_A009008\n config SYS_FSL_ERRATUM_A009798\n \tbool \"Workaround for USB PHY erratum A009798\"\n \n+config SYS_FSL_ERRATUM_A008997\n+\tbool \"Workaround for USB PHY erratum A008997\"\n+\n config MAX_CPUS\n \tint \"Maximum number of CPUs permitted for Layerscape\"\n \tdefault 4 if ARCH_LS1043A\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\nindex dda19e0..f0dac99 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n@@ -100,6 +100,30 @@ static void erratum_a009798(void)\n #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */\n }\n \n+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)\n+static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)\n+{\n+\tu32 val;\n+\n+\tval = scfg_in32(scfg + offset / 4) & ~(0x7F << 9);\n+\tval |= (USB_PCSTXSWINGFULL << 9);\n+\tscfg_out32(scfg + offset / 4, val);\n+}\n+#endif\n+\n+static void erratum_a008997(void)\n+{\n+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997\n+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)\n+\tu32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;\n+\n+\tset_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);\n+\tset_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);\n+\tset_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);\n+#endif\n+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */\n+}\n+\n #if defined(CONFIG_FSL_LSCH3)\n /*\n * This erratum requires setting a value to eddrtqcr1 to\n@@ -248,6 +272,7 @@ void fsl_lsch3_early_init_f(void)\n \terratum_a008336();\n \terratum_a009008();\n \terratum_a009798();\n+\terratum_a008997();\n #ifdef CONFIG_CHAIN_OF_TRUST\n \t/* In case of Secure Boot, the IBR configures the SMMU\n \t* to allow only Secure transactions.\n@@ -525,6 +550,7 @@ void fsl_lsch2_early_init_f(void)\n \terratum_a010539();\n \terratum_a009008();\n \terratum_a009798();\n+\terratum_a008997();\n }\n #endif\n \ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\nindex 8bd40e8..2e52078 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\n@@ -339,10 +339,14 @@ struct ccsr_gur {\n \n #define SCFG_BASE\t\t\t0x01570000\n #define SCFG_USB3PRM1CR_USB1\t\t0x070\n+#define SCFG_USB3PRM2CR_USB1\t\t0x074\n #define SCFG_USB3PRM1CR_USB2\t\t0x07C\n+#define SCFG_USB3PRM2CR_USB2\t\t0x080\n #define SCFG_USB3PRM1CR_USB3\t\t0x088\n+#define SCFG_USB3PRM2CR_USB3\t\t0x08c\n #define USB_TXVREFTUNE\t\t\t0x9\n #define USB_SQRXTUNE\t\t\t0xFC7FFFFF\n+#define USB_PCSTXSWINGFULL\t\t0x47\n \n #define SCFG_SNPCNFGCR_SECRDSNP\t\t0x80000000\n #define SCFG_SNPCNFGCR_SECWRSNP\t\t0x40000000\n", "prefixes": [ "U-Boot", "v3", "3/8" ] }