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GET /api/1.2/patches/801898/?format=api
{ "id": 801898, "url": "http://patchwork.ozlabs.org/api/1.2/patches/801898/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1502862122-14771-10-git-send-email-bmeng.cn@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1502862122-14771-10-git-send-email-bmeng.cn@gmail.com>", "list_archive_url": null, "date": "2017-08-16T05:41:58", "name": "[U-Boot,09/13] x86: Add Intel Braswell SoC support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "dcf68b2250843e9ca05572e85d01e5d8bf89e366", "submitter": { "id": 64981, "url": "http://patchwork.ozlabs.org/api/1.2/people/64981/?format=api", "name": "Bin Meng", "email": "bmeng.cn@gmail.com" }, "delegate": { "id": 56520, "url": "http://patchwork.ozlabs.org/api/1.2/users/56520/?format=api", "username": "bmeng", "first_name": "Bin", "last_name": "Meng", "email": "bmeng.cn@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1502862122-14771-10-git-send-email-bmeng.cn@gmail.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/801898/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/801898/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"LZ3bgNQm\"; dkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xXJDb6hk4z9s78\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 16 Aug 2017 15:43:43 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 9BAECC21DB5; Wed, 16 Aug 2017 05:41:02 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 5578EC21E0C;\n\tWed, 16 Aug 2017 05:39:00 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 97CD5C21DA4; Wed, 16 Aug 2017 05:37:57 +0000 (UTC)", "from mail-io0-f194.google.com (mail-io0-f194.google.com\n\t[209.85.223.194])\n\tby lists.denx.de (Postfix) with ESMTPS id 8AF1CC21DA4\n\tfor <u-boot@lists.denx.de>; Wed, 16 Aug 2017 05:37:53 +0000 (UTC)", "by mail-io0-f194.google.com with SMTP id h70so1779711ioi.2\n\tfor <u-boot@lists.denx.de>; Tue, 15 Aug 2017 22:37:53 -0700 (PDT)", "from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com.\n\t[147.11.156.139])\n\tby smtp.gmail.com with ESMTPSA id g13sm30442ioi.0.2017.08.15.22.37.50\n\t(version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tTue, 15 Aug 2017 22:37:51 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=FREEMAIL_FROM,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,\n\tT_DKIM_INVALID autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:subject:date:message-id:in-reply-to:references;\n\tbh=t/uzUFYe46g2x03S4PraZCEkt200DW5sw8wlB30u9ZY=;\n\tb=LZ3bgNQm3L2xP5GAoF6/+Tdw1QdIkCEJeronzVFY6CTLBNmQTQtR8+bepMLGACg9n4\n\t3ewqfwJHkZZxxoFtWAmXV2hgqvrZ6STfwyZ/hDUKLtKHHLQ4tC2riT1bCZBHdMGbBGRN\n\tH+F8w9xkq3mik83fK15RWUtXPYLXxuUUpAS1AN26RElSKoBWVmCfngjM34Cs2sy6dkGU\n\tmoY5+pPlXcv8WhDE2N2Uj0x1+19Jnx6rR5tsSCKzLPME7r0NwQjRWAvofffD1foQc589\n\tK9gysJ+/iZgexisoOcuWpVq1o7FV8WZ8bx4Dp5cCTX47GnGODu2/+qwqCSKv9YWq5n9Y\n\tkLUA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=t/uzUFYe46g2x03S4PraZCEkt200DW5sw8wlB30u9ZY=;\n\tb=KDld+EvboOFzYFR5ThyKshnid+AsZK2fx7bq4Fhf1tlfzTQ3EEBNpOM30NE42zNcPS\n\tzZ43OmDumODkmHI5hOIUkYJt/RrAornCInV9fqFCxbZGfGGo3kGUrCuItVDQIse2iGO/\n\tj22nBzLmWMe8GMAi+lMOJWe+mujriGWZifTK2JuqNz2T3a7PIClKqLSCRHsHhVz+Onil\n\tNqVlpOSyabRwFj8ztdXxIKzQuqjvSMAHV+yOxux2NIDD8z1reMCJqCx1efvMN0c8PpQM\n\tr45yuv8bfm1B2wfe7cLSEF7pcYMycPyVEq865B1OjEijOhIG/OuxT0jPmozB2i/ZG0xA\n\tX5Pg==", "X-Gm-Message-State": "AHYfb5gzrR+VaNEn6G4JtvUqiPy9UykZvE82wb73XD7Cqx5AKUFrlxqj\n\tED4zx2jG7WQCSvPb", "X-Received": "by 10.107.146.213 with SMTP id u204mr511934iod.252.1502861872350;\n\tTue, 15 Aug 2017 22:37:52 -0700 (PDT)", "From": "Bin Meng <bmeng.cn@gmail.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tU-Boot Mailing List <u-boot@lists.denx.de>", "Date": "Tue, 15 Aug 2017 22:41:58 -0700", "Message-Id": "<1502862122-14771-10-git-send-email-bmeng.cn@gmail.com>", "X-Mailer": "git-send-email 1.7.9.5", "In-Reply-To": "<1502862122-14771-1-git-send-email-bmeng.cn@gmail.com>", "References": "<1502862122-14771-1-git-send-email-bmeng.cn@gmail.com>", "Subject": "[U-Boot] [PATCH 09/13] x86: Add Intel Braswell SoC support", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "This adds initial Intel Braswell SoC support. It uses Intel FSP\nto initialize the chipset.\n\nSimilar to its predecessor BayTrail, there are some work to do to\nenable the legacy UART integrated in the Braswell SoC.\n\nSigned-off-by: Bin Meng <bmeng.cn@gmail.com>\n---\n\n arch/x86/Kconfig | 1 +\n arch/x86/cpu/Makefile | 1 +\n arch/x86/cpu/braswell/Kconfig | 38 +++++++\n arch/x86/cpu/braswell/Makefile | 7 ++\n arch/x86/cpu/braswell/braswell.c | 36 ++++++\n arch/x86/cpu/braswell/cpu.c | 170 +++++++++++++++++++++++++++++\n arch/x86/cpu/braswell/early_uart.c | 86 +++++++++++++++\n arch/x86/include/asm/arch-braswell/iomap.h | 50 +++++++++\n 8 files changed, 389 insertions(+)\n create mode 100644 arch/x86/cpu/braswell/Kconfig\n create mode 100644 arch/x86/cpu/braswell/Makefile\n create mode 100644 arch/x86/cpu/braswell/braswell.c\n create mode 100644 arch/x86/cpu/braswell/cpu.c\n create mode 100644 arch/x86/cpu/braswell/early_uart.c\n create mode 100644 arch/x86/include/asm/arch-braswell/iomap.h", "diff": "diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig\nindex f72d307..9620764 100644\n--- a/arch/x86/Kconfig\n+++ b/arch/x86/Kconfig\n@@ -108,6 +108,7 @@ source \"board/intel/Kconfig\"\n \n # platform-specific options below\n source \"arch/x86/cpu/baytrail/Kconfig\"\n+source \"arch/x86/cpu/braswell/Kconfig\"\n source \"arch/x86/cpu/broadwell/Kconfig\"\n source \"arch/x86/cpu/coreboot/Kconfig\"\n source \"arch/x86/cpu/ivybridge/Kconfig\"\ndiff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile\nindex 999429e..94cdff1 100644\n--- a/arch/x86/cpu/Makefile\n+++ b/arch/x86/cpu/Makefile\n@@ -27,6 +27,7 @@ endif\n \n obj-y += intel_common/\n obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/\n+obj-$(CONFIG_INTEL_BRASWELL) += braswell/\n obj-$(CONFIG_INTEL_BROADWELL) += broadwell/\n obj-$(CONFIG_SYS_COREBOOT) += coreboot/\n obj-$(CONFIG_EFI_APP) += efi/\ndiff --git a/arch/x86/cpu/braswell/Kconfig b/arch/x86/cpu/braswell/Kconfig\nnew file mode 100644\nindex 0000000..c993889\n--- /dev/null\n+++ b/arch/x86/cpu/braswell/Kconfig\n@@ -0,0 +1,38 @@\n+#\n+# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+config INTEL_BRASWELL\n+\tbool\n+\tselect HAVE_FSP\n+\tselect ARCH_MISC_INIT\n+\timply HAVE_INTEL_ME\n+\timply HAVE_VBT\n+\timply ENABLE_MRC_CACHE\n+\timply ENV_IS_IN_SPI_FLASH\n+\timply AHCI_PCI\n+\timply ICH_SPI\n+\timply MMC\n+\timply MMC_PCI\n+\timply MMC_SDHCI\n+\timply MMC_SDHCI_SDMA\n+\timply SCSI\n+\timply SPI_FLASH\n+\timply SYS_NS16550\n+\timply USB\n+\timply USB_XHCI_HCD\n+\timply VIDEO_FSP\n+\n+if INTEL_BRASWELL\n+\n+config FSP_ADDR\n+\thex\n+\tdefault 0xfff20000\n+\n+config FSP_LOCKDOWN_SPI\n+\tbool\n+\tdefault y\n+\n+endif\ndiff --git a/arch/x86/cpu/braswell/Makefile b/arch/x86/cpu/braswell/Makefile\nnew file mode 100644\nindex 0000000..19bcee6\n--- /dev/null\n+++ b/arch/x86/cpu/braswell/Makefile\n@@ -0,0 +1,7 @@\n+#\n+# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+obj-y += braswell.o cpu.o early_uart.o\ndiff --git a/arch/x86/cpu/braswell/braswell.c b/arch/x86/cpu/braswell/braswell.c\nnew file mode 100644\nindex 0000000..37099aa\n--- /dev/null\n+++ b/arch/x86/cpu/braswell/braswell.c\n@@ -0,0 +1,36 @@\n+/*\n+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/mrccache.h>\n+#include <asm/post.h>\n+\n+int arch_cpu_init(void)\n+{\n+\tpost_code(POST_CPU_INIT);\n+\n+\treturn x86_cpu_init_f();\n+}\n+\n+int arch_misc_init(void)\n+{\n+#ifdef CONFIG_ENABLE_MRC_CACHE\n+\t/*\n+\t * We intend not to check any return value here, as even MRC cache\n+\t * is not saved successfully, it is not a severe error that will\n+\t * prevent system from continuing to boot.\n+\t */\n+\tmrccache_save();\n+#endif\n+\n+\treturn 0;\n+}\n+\n+void reset_cpu(ulong addr)\n+{\n+\t/* cold reset */\n+\tx86_full_reset();\n+}\ndiff --git a/arch/x86/cpu/braswell/cpu.c b/arch/x86/cpu/braswell/cpu.c\nnew file mode 100644\nindex 0000000..6ff9036\n--- /dev/null\n+++ b/arch/x86/cpu/braswell/cpu.c\n@@ -0,0 +1,170 @@\n+/*\n+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ *\n+ * Derived from arch/x86/cpu/baytrail/cpu.c\n+ */\n+\n+#include <common.h>\n+#include <cpu.h>\n+#include <dm.h>\n+#include <asm/cpu.h>\n+#include <asm/cpu_x86.h>\n+#include <asm/io.h>\n+#include <asm/lapic.h>\n+#include <asm/msr.h>\n+#include <asm/turbo.h>\n+\n+static const unsigned int braswell_bus_freq_table[] = {\n+\t83333333,\n+\t100000000,\n+\t133333333,\n+\t116666666,\n+\t80000000,\n+\t93333333,\n+\t90000000,\n+\t88900000,\n+\t87500000\n+};\n+\n+static unsigned int braswell_bus_freq(void)\n+{\n+\tmsr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL);\n+\n+\tif ((clk_info.lo & 0xf) < (ARRAY_SIZE(braswell_bus_freq_table)))\n+\t\treturn braswell_bus_freq_table[clk_info.lo & 0xf];\n+\n+\treturn 0;\n+}\n+\n+static unsigned long braswell_tsc_freq(void)\n+{\n+\tmsr_t platform_info;\n+\tulong bclk = braswell_bus_freq();\n+\n+\tif (!bclk)\n+\t\treturn 0;\n+\n+\tplatform_info = msr_read(MSR_PLATFORM_INFO);\n+\n+\treturn bclk * ((platform_info.lo >> 8) & 0xff);\n+}\n+\n+static int braswell_get_info(struct udevice *dev, struct cpu_info *info)\n+{\n+\tinfo->cpu_freq = braswell_tsc_freq();\n+\tinfo->features = (1 << CPU_FEAT_L1_CACHE) | (1 << CPU_FEAT_MMU);\n+\n+\treturn 0;\n+}\n+\n+static int braswell_get_count(struct udevice *dev)\n+{\n+\tint ecx = 0;\n+\n+\t/*\n+\t * Use the algorithm described in Intel 64 and IA-32 Architectures\n+\t * Software Developer's Manual Volume 3 (3A, 3B & 3C): System\n+\t * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping\n+\t * of CPUID Extended Topology Leaf.\n+\t */\n+\twhile (1) {\n+\t\tstruct cpuid_result leaf_b;\n+\n+\t\tleaf_b = cpuid_ext(0xb, ecx);\n+\n+\t\t/*\n+\t\t * Braswell doesn't have hyperthreading so just determine the\n+\t\t * number of cores by from level type (ecx[15:8] == * 2)\n+\t\t */\n+\t\tif ((leaf_b.ecx & 0xff00) == 0x0200)\n+\t\t\treturn leaf_b.ebx & 0xffff;\n+\n+\t\tecx++;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void braswell_set_max_freq(void)\n+{\n+\tmsr_t perf_ctl;\n+\tmsr_t msr;\n+\n+\t/* Enable speed step */\n+\tmsr = msr_read(MSR_IA32_MISC_ENABLES);\n+\tmsr.lo |= (1 << 16);\n+\tmsr_write(MSR_IA32_MISC_ENABLES, msr);\n+\n+\t/* Enable Burst Mode */\n+\tmsr = msr_read(MSR_IA32_MISC_ENABLES);\n+\tmsr.hi = 0;\n+\tmsr_write(MSR_IA32_MISC_ENABLES, msr);\n+\n+\t/*\n+\t * Set guaranteed ratio [21:16] from IACORE_TURBO_RATIOS to\n+\t * bits [15:8] of the PERF_CTL\n+\t */\n+\tmsr = msr_read(MSR_IACORE_TURBO_RATIOS);\n+\tperf_ctl.lo = (msr.lo & 0x3f0000) >> 8;\n+\n+\t/*\n+\t * Set guaranteed vid [22:16] from IACORE_TURBO_VIDS to\n+\t * bits [7:0] of the PERF_CTL\n+\t */\n+\tmsr = msr_read(MSR_IACORE_TURBO_VIDS);\n+\tperf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;\n+\n+\tperf_ctl.hi = 0;\n+\tmsr_write(MSR_IA32_PERF_CTL, perf_ctl);\n+}\n+\n+static int braswell_probe(struct udevice *dev)\n+{\n+\tdebug(\"Init Braswell core\\n\");\n+\n+\t/*\n+\t * On Braswell the turbo disable bit is actually scoped at the\n+\t * building-block level, not package. For non-BSP cores that are\n+\t * within a building block, enable turbo. The cores within the BSP's\n+\t * building block will just see it already enabled and move on.\n+\t */\n+\tif (lapicid())\n+\t\tturbo_enable();\n+\n+\t/* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */\n+\tmsr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f080f, 0xe0008),\n+\tmsr_clrsetbits_64(MSR_POWER_MISC,\n+\t\t\t ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK, 0);\n+\n+\t/* Disable C1E */\n+\tmsr_clrsetbits_64(MSR_POWER_CTL, 2, 0);\n+\tmsr_setbits_64(MSR_POWER_MISC, 0x44);\n+\n+\t/* Set this core to max frequency ratio */\n+\tbraswell_set_max_freq();\n+\n+\treturn 0;\n+}\n+\n+static const struct udevice_id braswell_ids[] = {\n+\t{ .compatible = \"intel,braswell-cpu\" },\n+\t{ }\n+};\n+\n+static const struct cpu_ops braswell_ops = {\n+\t.get_desc\t= cpu_x86_get_desc,\n+\t.get_info\t= braswell_get_info,\n+\t.get_count\t= braswell_get_count,\n+\t.get_vendor\t= cpu_x86_get_vendor,\n+};\n+\n+U_BOOT_DRIVER(cpu_x86_braswell_drv) = {\n+\t.name\t\t= \"cpu_x86_braswell\",\n+\t.id\t\t= UCLASS_CPU,\n+\t.of_match\t= braswell_ids,\n+\t.bind\t\t= cpu_x86_bind,\n+\t.probe\t\t= braswell_probe,\n+\t.ops\t\t= &braswell_ops,\n+};\ndiff --git a/arch/x86/cpu/braswell/early_uart.c b/arch/x86/cpu/braswell/early_uart.c\nnew file mode 100644\nindex 0000000..0300e13\n--- /dev/null\n+++ b/arch/x86/cpu/braswell/early_uart.c\n@@ -0,0 +1,86 @@\n+/*\n+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/io.h>\n+\n+#define PCI_DEV_CONFIG(segbus, dev, fn) ( \\\n+\t\t(((segbus) & 0xfff) << 20) | \\\n+\t\t(((dev) & 0x1f) << 15) | \\\n+\t\t(((fn) & 0x07) << 12))\n+\n+/* Platform Controller Unit */\n+#define LPC_DEV\t\t\t0x1f\n+#define LPC_FUNC\t\t0\n+\n+/* Enable UART */\n+#define UART_CONT\t\t0x80\n+\n+/* UART PAD definitions */\n+#define UART_RXD_COMMUITY\t1\n+#define UART_TXD_COMMUITY\t1\n+#define UART_RXD_FAMILY\t\t4\n+#define UART_TXD_FAMILY\t\t4\n+#define UART_RXD_PAD\t\t2\n+#define UART_TXD_PAD\t\t7\n+#define UART_RXD_FUNC\t\t3\n+#define UART_TXD_FUNC\t\t3\n+\n+/* IO Memory */\n+#define IO_BASE_ADDRESS\t\t0xfed80000\n+\n+static inline uint32_t gpio_pconf0(int community, int family, int pad)\n+{\n+\treturn IO_BASE_ADDRESS + community * 0x8000 + 0x4400 +\n+\t\tfamily * 0x400 + pad * 8;\n+}\n+\n+static void gpio_select_func(int community, int family, int pad, int func)\n+{\n+\tuint32_t reg;\n+\tuint32_t pconf0_addr = gpio_pconf0(community, family, pad);\n+\n+\treg = readl(pconf0_addr);\n+\treg &= ~(0xf << 16);\n+\treg |= (func << 16);\n+\twritel(reg, pconf0_addr);\n+}\n+\n+static void x86_pci_write_config32(int dev, unsigned int where, u32 value)\n+{\n+\tunsigned long addr;\n+\n+\taddr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);\n+\twritel(value, addr);\n+}\n+\n+/* This can be called after memory-mapped PCI is working */\n+int setup_internal_uart(int enable)\n+{\n+\t/* Enable or disable the legacy UART hardware */\n+\tx86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT,\n+\t\t\t enable);\n+\n+\t/* All done for the disable part, so just return */\n+\tif (!enable)\n+\t\treturn 0;\n+\n+\t/*\n+\t * Set up the pads to the UART function. This allows the signals to\n+\t * leave the chip\n+\t */\n+\tgpio_select_func(UART_RXD_COMMUITY, UART_RXD_FAMILY,\n+\t\t\t UART_RXD_PAD, UART_RXD_FUNC);\n+\tgpio_select_func(UART_TXD_COMMUITY, UART_TXD_FAMILY,\n+\t\t\t UART_TXD_PAD, UART_TXD_FUNC);\n+\n+\treturn 0;\n+}\n+\n+void board_debug_uart_init(void)\n+{\n+\tsetup_internal_uart(1);\n+}\ndiff --git a/arch/x86/include/asm/arch-braswell/iomap.h b/arch/x86/include/asm/arch-braswell/iomap.h\nnew file mode 100644\nindex 0000000..7df2dc5\n--- /dev/null\n+++ b/arch/x86/include/asm/arch-braswell/iomap.h\n@@ -0,0 +1,50 @@\n+/*\n+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef _BRASWELL_IOMAP_H_\n+#define _BRASWELL_IOMAP_H_\n+\n+/* Memory Mapped IO bases */\n+\n+/* Power Management Controller */\n+#define PMC_BASE_ADDRESS\t0xfed03000\n+#define PMC_BASE_SIZE\t\t0x400\n+\n+/* Power Management Unit */\n+#define PUNIT_BASE_ADDRESS\t0xfed05000\n+#define PUNIT_BASE_SIZE\t\t0x800\n+\n+/* Intel Legacy Block */\n+#define ILB_BASE_ADDRESS\t0xfed08000\n+#define ILB_BASE_SIZE\t\t0x400\n+\n+/* SPI Bus */\n+#define SPI_BASE_ADDRESS\t0xfed01000\n+#define SPI_BASE_SIZE\t\t0x400\n+\n+/* Root Complex Base Address */\n+#define RCBA_BASE_ADDRESS\t0xfed1c000\n+#define RCBA_BASE_SIZE\t\t0x400\n+\n+/* IO Memory */\n+#define IO_BASE_ADDRESS\t\t0xfed80000\n+#define IO_BASE_SIZE\t\t0x4000\n+\n+/* MODPHY */\n+#define MPHY_BASE_ADDRESS\t0xfef00000\n+#define MPHY_BASE_SIZE\t\t0x100000\n+\n+/* IO Port bases */\n+\n+#define ACPI_BASE_ADDRESS\t0x400\n+#define ACPI_BASE_SIZE\t\t0x80\n+\n+#define GPIO_BASE_ADDRESS\t0x500\n+#define GPIO_BASE_SIZE\t\t0x100\n+\n+#define SMBUS_BASE_ADDRESS\t0xefa0\n+\n+#endif /* _BRASWELL_IOMAP_H_ */\n", "prefixes": [ "U-Boot", "09/13" ] }