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GET /api/1.2/patches/742447/?format=api
{ "id": 742447, "url": "http://patchwork.ozlabs.org/api/1.2/patches/742447/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1490243163-19566-5-git-send-email-paulus@ozlabs.org/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/1.2/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1490243163-19566-5-git-send-email-paulus@ozlabs.org>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1490243163-19566-5-git-send-email-paulus@ozlabs.org/", "date": "2017-03-23T04:26:02", "name": "[4/5] KVM: PPC: Emulation for more integer loads and stores", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "15bcbb979d8238649c61e49027d7b4cede9011a7", "submitter": { "id": 67079, "url": "http://patchwork.ozlabs.org/api/1.2/people/67079/?format=api", "name": "Paul Mackerras", "email": "paulus@ozlabs.org" }, "delegate": { "id": 13, "url": "http://patchwork.ozlabs.org/api/1.2/users/13/?format=api", "username": "paulus", "first_name": "Paul", "last_name": "Mackerras", "email": "paulus@samba.org" }, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1490243163-19566-5-git-send-email-paulus@ozlabs.org/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/742447/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/742447/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org", "linuxppc-dev@ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3vpYY65XsJz9s82\n\tfor <patchwork-incoming@ozlabs.org>;\n\tThu, 23 Mar 2017 15:31:54 +1100 (AEDT)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3vpYY64pBrzDqw0\n\tfor <patchwork-incoming@ozlabs.org>;\n\tThu, 23 Mar 2017 15:31:54 +1100 (AEDT)", "from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3vpYQZ6Fm7zDq5g\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tThu, 23 Mar 2017 15:26:14 +1100 (AEDT)", "by ozlabs.org (Postfix)\n\tid 3vpYQZ5WMMz9s88; Thu, 23 Mar 2017 15:26:14 +1100 (AEDT)", "from authenticated.ozlabs.org (localhost [127.0.0.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPSA id 3vpYQZ3hrYz9s82;\n\tThu, 23 Mar 2017 15:26:14 +1100 (AEDT)" ], "From": "Paul Mackerras <paulus@ozlabs.org>", "To": "kvm@vger.kernel.org,\n\tlinuxppc-dev@ozlabs.org,\n\tkvm-ppc@vger.kernel.org", "Subject": "[PATCH 4/5] KVM: PPC: Emulation for more integer loads and stores", "Date": "Thu, 23 Mar 2017 15:26:02 +1100", "Message-Id": "<1490243163-19566-5-git-send-email-paulus@ozlabs.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1490243163-19566-1-git-send-email-paulus@ozlabs.org>", "References": "<1490243163-19566-1-git-send-email-paulus@ozlabs.org>", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "This adds emulation for the following integer loads and stores,\nthus enabling them to be used in a guest for accessing emulated\nMMIO locations.\n\n- lhaux\n- lwaux\n- lwzux\n- ldu\n- lwa\n- stdux\n- stwux\n- stdu\n- ldbrx\n- stdbrx\n\nPreviously, most of these would cause an emulation failure exit to\nuserspace, though ldu and lwa got treated incorrectly as ld, and\nstdu got treated incorrectly as std.\n\nThis also tidies up some of the formatting and updates the comment\nlisting instructions that still need to be implemented.\n\nWith this, all integer loads and stores that are defined in the Power\nISA v2.07 are emulated, except for those that are permitted to trap\nwhen used on cache-inhibited or write-through mappings (and which do\nin fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,\nlq/stq, and l[bhwdq]arx/st[bhwdq]cx.\n\nSigned-off-by: Paul Mackerras <paulus@ozlabs.org>\n---\n arch/powerpc/include/asm/ppc-opcode.h | 5 ++\n arch/powerpc/kvm/emulate_loadstore.c | 135 ++++++++++++++++++++++------------\n 2 files changed, 91 insertions(+), 49 deletions(-)", "diff": "diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h\nindex 94e7df2..738bac1 100644\n--- a/arch/powerpc/include/asm/ppc-opcode.h\n+++ b/arch/powerpc/include/asm/ppc-opcode.h\n@@ -96,6 +96,8 @@\n #define OP_31_XOP_LBZX 87\n #define OP_31_XOP_STDX 149\n #define OP_31_XOP_STWX 151\n+#define OP_31_XOP_STDUX 181\n+#define OP_31_XOP_STWUX 183\n #define OP_31_XOP_STBX 215\n #define OP_31_XOP_LBZUX 119\n #define OP_31_XOP_STBUX 247\n@@ -104,13 +106,16 @@\n #define OP_31_XOP_MFSPR 339\n #define OP_31_XOP_LWAX 341\n #define OP_31_XOP_LHAX 343\n+#define OP_31_XOP_LWAUX 373\n #define OP_31_XOP_LHAUX 375\n #define OP_31_XOP_STHX 407\n #define OP_31_XOP_STHUX 439\n #define OP_31_XOP_MTSPR 467\n #define OP_31_XOP_DCBI 470\n+#define OP_31_XOP_LDBRX 532\n #define OP_31_XOP_LWBRX 534\n #define OP_31_XOP_TLBSYNC 566\n+#define OP_31_XOP_STDBRX 660\n #define OP_31_XOP_STWBRX 662\n #define OP_31_XOP_STFSX\t 663\n #define OP_31_XOP_STFSUX 695\ndiff --git a/arch/powerpc/kvm/emulate_loadstore.c b/arch/powerpc/kvm/emulate_loadstore.c\nindex a0f27a3..f10ba0c 100644\n--- a/arch/powerpc/kvm/emulate_loadstore.c\n+++ b/arch/powerpc/kvm/emulate_loadstore.c\n@@ -58,18 +58,14 @@ static bool kvmppc_check_vsx_disabled(struct kvm_vcpu *vcpu)\n }\n #endif /* CONFIG_VSX */\n \n-/* XXX to do:\n- * lhax\n- * lhaux\n- * lswx\n- * lswi\n- * stswx\n- * stswi\n- * lha\n- * lhau\n- * lmw\n- * stmw\n+/*\n+ * XXX to do:\n+ * lfiwax, lfiwzx\n+ * vector loads and stores\n *\n+ * Instructions that trap when used on cache-inhibited mappings\n+ * are not emulated here: multiple and string instructions,\n+ * lq/stq, and the load-reserve/store-conditional instructions.\n */\n int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)\n {\n@@ -110,6 +106,11 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)\n \t\t\temulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);\n \t\t\tbreak;\n \n+\t\tcase OP_31_XOP_LWZUX:\n+\t\t\temulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);\n+\t\t\tkvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);\n+\t\t\tbreak;\n+\n \t\tcase OP_31_XOP_LBZX:\n \t\t\temulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);\n \t\t\tbreak;\n@@ -121,26 +122,34 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)\n \n \t\tcase OP_31_XOP_STDX:\n \t\t\temulated = kvmppc_handle_store(run, vcpu,\n-\t\t\t\t\t\t kvmppc_get_gpr(vcpu, rs),\n-\t\t\t\t\t\t\t8, 1);\n+\t\t\t\t\tkvmppc_get_gpr(vcpu, rs), 8, 1);\n+\t\t\tbreak;\n+\n+\t\tcase OP_31_XOP_STDUX:\n+\t\t\temulated = kvmppc_handle_store(run, vcpu,\n+\t\t\t\t\tkvmppc_get_gpr(vcpu, rs), 8, 1);\n+\t\t\tkvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);\n \t\t\tbreak;\n \n \t\tcase OP_31_XOP_STWX:\n \t\t\temulated = kvmppc_handle_store(run, vcpu,\n-\t\t\t\t\t\t kvmppc_get_gpr(vcpu, rs),\n-\t\t\t 4, 1);\n+\t\t\t\t\tkvmppc_get_gpr(vcpu, rs), 4, 1);\n+\t\t\tbreak;\n+\n+\t\tcase OP_31_XOP_STWUX:\n+\t\t\temulated = kvmppc_handle_store(run, vcpu,\n+\t\t\t\t\tkvmppc_get_gpr(vcpu, rs), 4, 1);\n+\t\t\tkvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);\n \t\t\tbreak;\n \n \t\tcase OP_31_XOP_STBX:\n \t\t\temulated = kvmppc_handle_store(run, vcpu,\n-\t\t\t\t\t\t kvmppc_get_gpr(vcpu, rs),\n-\t\t\t 1, 1);\n+\t\t\t\t\tkvmppc_get_gpr(vcpu, rs), 1, 1);\n \t\t\tbreak;\n \n \t\tcase OP_31_XOP_STBUX:\n \t\t\temulated = kvmppc_handle_store(run, vcpu,\n-\t\t\t\t\t\t kvmppc_get_gpr(vcpu, rs),\n-\t\t\t 1, 1);\n+\t\t\t\t\tkvmppc_get_gpr(vcpu, rs), 1, 1);\n \t\t\tkvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);\n \t\t\tbreak;\n \n@@ -148,6 +157,11 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)\n \t\t\temulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);\n \t\t\tbreak;\n \n+\t\tcase OP_31_XOP_LHAUX:\n+\t\t\temulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);\n+\t\t\tkvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);\n+\t\t\tbreak;\n+\n \t\tcase OP_31_XOP_LHZX:\n \t\t\temulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);\n \t\t\tbreak;\n@@ -159,14 +173,12 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)\n \n \t\tcase OP_31_XOP_STHX:\n \t\t\temulated = kvmppc_handle_store(run, vcpu,\n-\t\t\t\t\t\t kvmppc_get_gpr(vcpu, rs),\n-\t\t\t 2, 1);\n+\t\t\t\t\tkvmppc_get_gpr(vcpu, rs), 2, 1);\n \t\t\tbreak;\n \n \t\tcase OP_31_XOP_STHUX:\n \t\t\temulated = kvmppc_handle_store(run, vcpu,\n-\t\t\t\t\t\t kvmppc_get_gpr(vcpu, rs),\n-\t\t\t 2, 1);\n+\t\t\t\t\tkvmppc_get_gpr(vcpu, rs), 2, 1);\n \t\t\tkvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);\n \t\t\tbreak;\n \n@@ -186,8 +198,7 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)\n \n \t\tcase OP_31_XOP_STWBRX:\n \t\t\temulated = kvmppc_handle_store(run, vcpu,\n-\t\t\t\t\t\t kvmppc_get_gpr(vcpu, rs),\n-\t\t\t 4, 0);\n+\t\t\t\t\tkvmppc_get_gpr(vcpu, rs), 4, 0);\n \t\t\tbreak;\n \n \t\tcase OP_31_XOP_LHBRX:\n@@ -196,8 +207,16 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)\n \n \t\tcase OP_31_XOP_STHBRX:\n \t\t\temulated = kvmppc_handle_store(run, vcpu,\n-\t\t\t\t\t\t kvmppc_get_gpr(vcpu, rs),\n-\t\t\t 2, 0);\n+\t\t\t\t\tkvmppc_get_gpr(vcpu, rs), 2, 0);\n+\t\t\tbreak;\n+\n+\t\tcase OP_31_XOP_LDBRX:\n+\t\t\temulated = kvmppc_handle_load(run, vcpu, rt, 8, 0);\n+\t\t\tbreak;\n+\n+\t\tcase OP_31_XOP_STDBRX:\n+\t\t\temulated = kvmppc_handle_store(run, vcpu,\n+\t\t\t\t\tkvmppc_get_gpr(vcpu, rs), 8, 0);\n \t\t\tbreak;\n \n \t\tcase OP_31_XOP_LDX:\n@@ -213,6 +232,11 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)\n \t\t\temulated = kvmppc_handle_loads(run, vcpu, rt, 4, 1);\n \t\t\tbreak;\n \n+\t\tcase OP_31_XOP_LWAUX:\n+\t\t\temulated = kvmppc_handle_loads(run, vcpu, rt, 4, 1);\n+\t\t\tkvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);\n+\t\t\tbreak;\n+\n #ifdef CONFIG_PPC_FPU\n \t\tcase OP_31_XOP_LFSX:\n \t\t\tif (kvmppc_check_fp_disabled(vcpu))\n@@ -267,16 +291,14 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)\n \t\t\tif (kvmppc_check_fp_disabled(vcpu))\n \t\t\t\treturn EMULATE_DONE;\n \t\t\temulated = kvmppc_handle_store(run, vcpu,\n-\t\t\t\tVCPU_FPR(vcpu, rs),\n-\t\t 8, 1);\n+\t\t\t\tVCPU_FPR(vcpu, rs), 8, 1);\n \t\t\tbreak;\n \n \t\tcase OP_31_XOP_STFDUX:\n \t\t\tif (kvmppc_check_fp_disabled(vcpu))\n \t\t\t\treturn EMULATE_DONE;\n \t\t\temulated = kvmppc_handle_store(run, vcpu,\n-\t\t\t\tVCPU_FPR(vcpu, rs),\n-\t\t 8, 1);\n+\t\t\t\tVCPU_FPR(vcpu, rs), 8, 1);\n \t\t\tkvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);\n \t\t\tbreak;\n \n@@ -284,8 +306,7 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)\n \t\t\tif (kvmppc_check_fp_disabled(vcpu))\n \t\t\t\treturn EMULATE_DONE;\n \t\t\temulated = kvmppc_handle_store(run, vcpu,\n-\t\t\t\tVCPU_FPR(vcpu, rs),\n-\t\t 4, 1);\n+\t\t\t\tVCPU_FPR(vcpu, rs), 4, 1);\n \t\t\tbreak;\n #endif\n \n@@ -472,10 +493,22 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)\n \t\tbreak;\n #endif\n \n-\t/* TBD: Add support for other 64 bit load variants like ldu etc. */\n \tcase OP_LD:\n \t\trt = get_rt(inst);\n-\t\temulated = kvmppc_handle_load(run, vcpu, rt, 8, 1);\n+\t\tswitch (inst & 3) {\n+\t\tcase 0:\t/* ld */\n+\t\t\temulated = kvmppc_handle_load(run, vcpu, rt, 8, 1);\n+\t\t\tbreak;\n+\t\tcase 1: /* ldu */\n+\t\t\temulated = kvmppc_handle_load(run, vcpu, rt, 8, 1);\n+\t\t\tkvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);\n+\t\t\tbreak;\n+\t\tcase 2:\t/* lwa */\n+\t\t\temulated = kvmppc_handle_loads(run, vcpu, rt, 4, 1);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\temulated = EMULATE_FAIL;\n+\t\t}\n \t\tbreak;\n \n \tcase OP_LWZU:\n@@ -498,31 +531,37 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)\n \t\t 4, 1);\n \t\tbreak;\n \n-\t/* TBD: Add support for other 64 bit store variants like stdu, stdux, stdx etc. */\n \tcase OP_STD:\n \t\trs = get_rs(inst);\n-\t\temulated = kvmppc_handle_store(run, vcpu,\n-\t\t\t\t\t kvmppc_get_gpr(vcpu, rs),\n-\t\t 8, 1);\n+\t\tswitch (inst & 3) {\n+\t\tcase 0:\t/* std */\n+\t\t\temulated = kvmppc_handle_store(run, vcpu,\n+\t\t\t\tkvmppc_get_gpr(vcpu, rs), 8, 1);\n+\t\t\tbreak;\n+\t\tcase 1: /* stdu */\n+\t\t\temulated = kvmppc_handle_store(run, vcpu,\n+\t\t\t\tkvmppc_get_gpr(vcpu, rs), 8, 1);\n+\t\t\tkvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\temulated = EMULATE_FAIL;\n+\t\t}\n \t\tbreak;\n \n \tcase OP_STWU:\n \t\temulated = kvmppc_handle_store(run, vcpu,\n-\t\t\t\t\t kvmppc_get_gpr(vcpu, rs),\n-\t\t 4, 1);\n+\t\t\t\tkvmppc_get_gpr(vcpu, rs), 4, 1);\n \t\tkvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);\n \t\tbreak;\n \n \tcase OP_STB:\n \t\temulated = kvmppc_handle_store(run, vcpu,\n-\t\t\t\t\t kvmppc_get_gpr(vcpu, rs),\n-\t\t 1, 1);\n+\t\t\t\tkvmppc_get_gpr(vcpu, rs), 1, 1);\n \t\tbreak;\n \n \tcase OP_STBU:\n \t\temulated = kvmppc_handle_store(run, vcpu,\n-\t\t\t\t\t kvmppc_get_gpr(vcpu, rs),\n-\t\t 1, 1);\n+\t\t\t\tkvmppc_get_gpr(vcpu, rs), 1, 1);\n \t\tkvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);\n \t\tbreak;\n \n@@ -546,14 +585,12 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)\n \n \tcase OP_STH:\n \t\temulated = kvmppc_handle_store(run, vcpu,\n-\t\t\t\t\t kvmppc_get_gpr(vcpu, rs),\n-\t\t 2, 1);\n+\t\t\t\tkvmppc_get_gpr(vcpu, rs), 2, 1);\n \t\tbreak;\n \n \tcase OP_STHU:\n \t\temulated = kvmppc_handle_store(run, vcpu,\n-\t\t\t\t\t kvmppc_get_gpr(vcpu, rs),\n-\t\t 2, 1);\n+\t\t\t\tkvmppc_get_gpr(vcpu, rs), 2, 1);\n \t\tkvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);\n \t\tbreak;\n \n", "prefixes": [ "4/5" ] }