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GET /api/1.2/patches/2235220/?format=api
{ "id": 2235220, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2235220/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260508034912.4082520-3-rkannoth@marvell.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/1.2/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508034912.4082520-3-rkannoth@marvell.com>", "list_archive_url": null, "date": "2026-05-08T03:49:05", "name": "[v12,net-next,2/9] net/mlx5e: trim stack use in PCIe congestion threshold helper", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4a4799aedfd75c0a24424f685685359894edd6cc", "submitter": { "id": 86908, "url": "http://patchwork.ozlabs.org/api/1.2/people/86908/?format=api", "name": "Ratheesh Kannoth", "email": "rkannoth@marvell.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260508034912.4082520-3-rkannoth@marvell.com/mbox/", "series": [ { "id": 503453, "url": "http://patchwork.ozlabs.org/api/1.2/series/503453/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=503453", "date": "2026-05-08T03:49:12", "name": "octeontx2-af: npc: Enhancements.", "version": 12, "mbox": "http://patchwork.ozlabs.org/series/503453/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2235220/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2235220/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=qQ6amO3L;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::137; 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client-ip=67.231.148.174;\n helo=mx0b-0016f401.pphosted.com;\n envelope-from=prvs=65883a0750=rkannoth@marvell.com; receiver=<UNKNOWN>", "DMARC-Filter": "OpenDMARC Filter v1.4.2 smtp4.osuosl.org 96C43414E9", "From": "Ratheesh Kannoth <rkannoth@marvell.com>", "To": "<intel-wired-lan@lists.osuosl.org>, <linux-kernel@vger.kernel.org>,\n <linux-rdma@vger.kernel.org>, <netdev@vger.kernel.org>,\n <oss-drivers@corigine.com>", "CC": "<akiyano@amazon.com>, <andrew+netdev@lunn.ch>,\n <anthony.l.nguyen@intel.com>, <arkadiusz.kubalewski@intel.com>,\n <brett.creeley@amd.com>, <darinzon@amazon.com>, <davem@davemloft.net>,\n <donald.hunter@gmail.com>, <edumazet@google.com>, <horms@kernel.org>,\n <idosch@nvidia.com>, <ivecera@redhat.com>, <jiri@resnulli.us>,\n <kuba@kernel.org>, <leon@kernel.org>, <mbloch@nvidia.com>,\n <michael.chan@broadcom.com>, <pabeni@redhat.com>,\n <pavan.chebbi@broadcom.com>, <petrm@nvidia.com>,\n <Prathosh.Satish@microchip.com>, <przemyslaw.kitszel@intel.com>,\n <saeedm@nvidia.com>, <sgoutham@marvell.com>, <tariqt@nvidia.com>,\n <vadim.fedorenko@linux.dev>, Ratheesh Kannoth <rkannoth@marvell.com>", "Date": "Fri, 8 May 2026 09:19:05 +0530", "Message-ID": "<20260508034912.4082520-3-rkannoth@marvell.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260508034912.4082520-1-rkannoth@marvell.com>", "References": "<20260508034912.4082520-1-rkannoth@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "mIZUNbQgqFhIKvwAl1gsnIIP3dR0l610", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNTA4MDAzMyBTYWx0ZWRfXytgNrDRTptqJ\n nsux18mdiNswztiaGb87eN2rVJ4yMhSOyXZwu5m3YGwLJnCZsuVY1TuNnmXj+r2dc/VectyfntT\n Z6Zxon+0B7BAyihibK+74825huMoSVu+BHOonXL8O/kHj6a4Po5qfXRyColfGYqMW0NhAoBjpqw\n bXXTV/kPmvIdprpjFvpHGsoZljQLqARVCq4PJS2cRxeOUf/4bifLQgrfZQNXwqN57HD91QyIRAu\n seHOJ/VjNL0+ra1iFoH+SUPLcR5eZy/RgpBATC0ECJnKE8s9MELlDOxyiayYEnB6jAQlrOCIlg5\n LpNHINbDXGVlF/WrzvdtvKrBiJRoVaFDVVNqeVoNguwb6bpXQdZxUAgJvMykNvfwQ+iNKEar+8i\n 8CVOfnAUDd61U2u0knmUfGk2j9JU89Ed8jJ5mYfpaGwqkmJPxO75KKVdi30GG0KadNxPhzPGmGH\n pg0Ow8e5PRozoLc7mlQ==", "X-Proofpoint-GUID": "mIZUNbQgqFhIKvwAl1gsnIIP3dR0l610", "X-Authority-Analysis": "v=2.4 cv=WMBPmHsR c=1 sm=1 tr=0 ts=69fd5d60 cx=c_pps\n a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17\n a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22\n a=EAYMVhzMl8SCOHhVQcBL:22 a=M5GUcnROAAAA:8 a=YjTTaRMW2Sk_qnKZcsQA:9\n a=OBjm3rFKGHvpk9ecZwUJ:22", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-05-07_02,2026-05-06_01,2025-10-01_01", "X-Mailman-Approved-At": "Fri, 08 May 2026 22:09:04 +0000", "X-Mailman-Original-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=marvell.com; h=\n cc:content-transfer-encoding:content-type:date:from:in-reply-to\n :message-id:mime-version:references:subject:to; s=pfpt0220; bh=w\n NoyjCcOt9iCXEZtiOjB9y5jkpJj2m5Kh9tPG4kCON8=; b=gAy6wfkcAoXTC/bZs\n ied3LxcaJxjNTXdOMSJ5hachPCyZpZBUZF1jR2gU7Mp8cWmtEGlTeepZCdwUq98u\n b3/noflsIz0d/ihXC0BM/Jk88PjPV2gueqEFQSRUpyvvSGbB+dmVfRmuQVEMVFnY\n NRUYWTQGoEc4eZlfUVWkIbkZ6jCaG8wWIt3TFGZQq9vdxeKucohvvvVmNQuIrBht\n BM4E3ROFgNUKxtvNFVKYxLeckqxSa+op9l+Cr+TkPKAePJPDyr4oZev5f3dW7sr6\n n8Ghu3Fo4+1BHNP2fv86ABPp3cS0kDcSMGn72SetMQ5RQ7K1yy9dy5p0f7ocKqBB\n m0YEQ==", "X-Mailman-Original-Authentication-Results": [ "smtp4.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=marvell.com", "smtp4.osuosl.org;\n dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com\n header.a=rsa-sha256 header.s=pfpt0220 header.b=gAy6wfkc" ], "Subject": "[Intel-wired-lan] [PATCH v12 net-next 2/9] net/mlx5e: trim stack\n use in PCIe congestion threshold helper", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n <intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "union devlink_param_value grew when U64 array parameters were added.\nKeeping a four-element array of that union in\nmlx5e_pcie_cong_get_thresh_config() inflated the stack frame past the\n-Wframe-larger-than limit.\n\nRead each driverinit value into a single reused union, then store the\nfour u16 thresholds in struct mlx5e_pcie_cong_thresh field order via a\ntemporary u16 pointer to config.\n\nSigned-off-by: Ratheesh Kannoth <rkannoth@marvell.com>\n---\n .../mellanox/mlx5/core/en/pcie_cong_event.c | 34 +++++++++++--------\n 1 file changed, 19 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c b/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c\nindex 2eb666a46f39..88e76be3a73d 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c\n@@ -252,28 +252,32 @@ static int\n mlx5e_pcie_cong_get_thresh_config(struct mlx5_core_dev *dev,\n \t\t\t\t struct mlx5e_pcie_cong_thresh *config)\n {\n+\tenum {\n+\t\tINBOUND_HIGH,\n+\t\tINBOUND_LOW,\n+\t\tOUTBOUND_HIGH,\n+\t\tOUTBOUND_LOW,\n+\t};\n+\n \tu32 ids[4] = {\n-\t\tMLX5_DEVLINK_PARAM_ID_PCIE_CONG_IN_LOW,\n-\t\tMLX5_DEVLINK_PARAM_ID_PCIE_CONG_IN_HIGH,\n-\t\tMLX5_DEVLINK_PARAM_ID_PCIE_CONG_OUT_LOW,\n-\t\tMLX5_DEVLINK_PARAM_ID_PCIE_CONG_OUT_HIGH,\n+\t\t[INBOUND_LOW] = MLX5_DEVLINK_PARAM_ID_PCIE_CONG_IN_LOW,\n+\t\t[INBOUND_HIGH] = MLX5_DEVLINK_PARAM_ID_PCIE_CONG_IN_HIGH,\n+\t\t[OUTBOUND_LOW] = MLX5_DEVLINK_PARAM_ID_PCIE_CONG_OUT_LOW,\n+\t\t[OUTBOUND_HIGH] = MLX5_DEVLINK_PARAM_ID_PCIE_CONG_OUT_HIGH,\n \t};\n-\tstruct devlink *devlink = priv_to_devlink(dev);\n-\tunion devlink_param_value val[4];\n \n-\tfor (int i = 0; i < 4; i++) {\n-\t\tu32 id = ids[i];\n-\t\tint err;\n+\tstruct devlink *devlink = priv_to_devlink(dev);\n+\tunion devlink_param_value val;\n+\tu16 *dst = (u16 *)config;\n+\tint err;\n \n-\t\terr = devl_param_driverinit_value_get(devlink, id, &val[i]);\n+\tfor (int i = 0; i < ARRAY_SIZE(ids); i++) {\n+\t\terr = devl_param_driverinit_value_get(devlink, ids[i], &val);\n \t\tif (err)\n \t\t\treturn err;\n-\t}\n \n-\tconfig->inbound_low = val[0].vu16;\n-\tconfig->inbound_high = val[1].vu16;\n-\tconfig->outbound_low = val[2].vu16;\n-\tconfig->outbound_high = val[3].vu16;\n+\t\tdst[i] = val.vu16;\n+\t}\n \n \treturn 0;\n }\n", "prefixes": [ "v12", "net-next", "2/9" ] }