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GET /api/1.2/patches/2235218/?format=api
{ "id": 2235218, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2235218/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260508034912.4082520-7-rkannoth@marvell.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/1.2/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508034912.4082520-7-rkannoth@marvell.com>", "list_archive_url": null, "date": "2026-05-08T03:49:09", "name": "[v12,net-next,6/9] octeontx2: cn20k: Coordinate default rules with NIX LF lifecycle", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ca1f9abd49edcf84682602af4f6eebe5f86f50cb", "submitter": { "id": 86908, "url": "http://patchwork.ozlabs.org/api/1.2/people/86908/?format=api", "name": "Ratheesh Kannoth", "email": "rkannoth@marvell.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260508034912.4082520-7-rkannoth@marvell.com/mbox/", "series": [ { "id": 503453, "url": "http://patchwork.ozlabs.org/api/1.2/series/503453/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=503453", "date": "2026-05-08T03:49:12", "name": "octeontx2-af: npc: Enhancements.", "version": 12, "mbox": "http://patchwork.ozlabs.org/series/503453/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2235218/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2235218/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=AoA0KCxN;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=140.211.166.137; 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a=rsa-sha256; c=relaxed/relaxed;\n d=marvell.com; h=\n cc:content-transfer-encoding:content-type:date:from:in-reply-to\n :message-id:mime-version:references:subject:to; s=pfpt0220; bh=u\n /2SfLNb+fJ+6rKwBlULKSyHf9qoTM9K99IzOqrMHlM=; b=PI3oBwtFrV3ETUyBi\n Xr1O7RMMrbph+2UVhDjpAqlnwYSM1C2T3U6RTE7MW4L0H5VYtq9XstpZhNLRLlg4\n Kid7b1rw7my9ezt6N3DFcVS/kQVI06HtXm+jxIUtRMa6JgB8JPDOxkVgB6O0cLEc\n Ry5jk7yvvWnhcUIqNLNxCyATwCZq+OD2wywO1OBAv0TsPNmfKvnB5+Y65G2AYXK8\n c4nnS7JsAujLmM5PQtoYBBfhWOR/RG8jVHzkLFt/CbIldrHpErMmDAn1qGwcHyQB\n GoBoilbe/q5pr6mBZoTDvTBowJagvSA3tT5Ulu+nY0WumrmLtXVysY8uRWKgbVzO\n OeLxQ==", "X-Mailman-Original-Authentication-Results": [ "smtp2.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=marvell.com", "smtp2.osuosl.org;\n dkim=pass (2048-bit key,\n unprotected) header.d=marvell.com header.i=@marvell.com header.a=rsa-sha256\n header.s=pfpt0220 header.b=PI3oBwtF" ], "Subject": "[Intel-wired-lan] [PATCH v12 net-next 6/9] octeontx2: cn20k:\n Coordinate default rules with NIX LF lifecycle", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n <intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Add NIX_LF_DONT_FREE_DFT_IDXS so the PF can send NIX LF free during hw\nreinit or teardown without the AF freeing CN20K default NPC rule indexes\nwhile the driver still owns that state (otx2_init_hw_resources and\notx2_free_hw_resources).\n\nOn CN20K, allocate default NPC rules from NIX LF alloc before\nnix_interface_init, roll back with npc_cn20k_dft_rules_free on failure,\nand free from NIX LF free when the new flag is not set. Tighten\nrvu_mbox_handler_nix_lf_alloc error handling: use a single rc, propagate\nqmem_alloc and other errors, and set -ENOMEM only when kcalloc fails\n(remove the blanket -ENOMEM at the free_mem path).\n\nSigned-off-by: Ratheesh Kannoth <rkannoth@marvell.com>\n---\n .../net/ethernet/marvell/octeontx2/af/mbox.h | 1 +\n .../ethernet/marvell/octeontx2/af/rvu_nix.c | 69 ++++++++++++-------\n .../ethernet/marvell/octeontx2/af/rvu_npc.c | 22 ++++--\n .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 6 +-\n 4 files changed, 62 insertions(+), 36 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h\nindex dc42c81c0942..e07fbf842b94 100644\n--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h\n+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h\n@@ -1009,6 +1009,7 @@ struct nix_lf_free_req {\n \tstruct mbox_msghdr hdr;\n #define NIX_LF_DISABLE_FLOWS\t\tBIT_ULL(0)\n #define NIX_LF_DONT_FREE_TX_VTAG\tBIT_ULL(1)\n+#define NIX_LF_DONT_FREE_DFT_IDXS\tBIT_ULL(2)\n \tu64 flags;\n };\n \ndiff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c\nindex f977734ae712..7df256a9e01c 100644\n--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c\n+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c\n@@ -16,6 +16,7 @@\n #include \"cgx.h\"\n #include \"lmac_common.h\"\n #include \"rvu_npc_hash.h\"\n+#include \"cn20k/npc.h\"\n \n static void nix_free_tx_vtag_entries(struct rvu *rvu, u16 pcifunc);\n static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req,\n@@ -1499,7 +1500,7 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu,\n \t\t\t\t struct nix_lf_alloc_req *req,\n \t\t\t\t struct nix_lf_alloc_rsp *rsp)\n {\n-\tint nixlf, qints, hwctx_size, intf, err, rc = 0;\n+\tint nixlf, qints, hwctx_size, intf, rc = 0;\n \tstruct rvu_hwinfo *hw = rvu->hw;\n \tu16 pcifunc = req->hdr.pcifunc;\n \tstruct rvu_block *block;\n@@ -1555,8 +1556,8 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu,\n \t\treturn NIX_AF_ERR_RSS_GRPS_INVALID;\n \n \t/* Reset this NIX LF */\n-\terr = rvu_lf_reset(rvu, block, nixlf);\n-\tif (err) {\n+\trc = rvu_lf_reset(rvu, block, nixlf);\n+\tif (rc) {\n \t\tdev_err(rvu->dev, \"Failed to reset NIX%d LF%d\\n\",\n \t\t\tblock->addr - BLKADDR_NIX0, nixlf);\n \t\treturn NIX_AF_ERR_LF_RESET;\n@@ -1566,13 +1567,15 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu,\n \n \t/* Alloc NIX RQ HW context memory and config the base */\n \thwctx_size = 1UL << ((ctx_cfg >> 4) & 0xF);\n-\terr = qmem_alloc(rvu->dev, &pfvf->rq_ctx, req->rq_cnt, hwctx_size);\n-\tif (err)\n+\trc = qmem_alloc(rvu->dev, &pfvf->rq_ctx, req->rq_cnt, hwctx_size);\n+\tif (rc)\n \t\tgoto free_mem;\n \n \tpfvf->rq_bmap = kcalloc(req->rq_cnt, sizeof(long), GFP_KERNEL);\n-\tif (!pfvf->rq_bmap)\n+\tif (!pfvf->rq_bmap) {\n+\t\trc = -ENOMEM;\n \t\tgoto free_mem;\n+\t}\n \n \trvu_write64(rvu, blkaddr, NIX_AF_LFX_RQS_BASE(nixlf),\n \t\t (u64)pfvf->rq_ctx->iova);\n@@ -1583,13 +1586,15 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu,\n \n \t/* Alloc NIX SQ HW context memory and config the base */\n \thwctx_size = 1UL << (ctx_cfg & 0xF);\n-\terr = qmem_alloc(rvu->dev, &pfvf->sq_ctx, req->sq_cnt, hwctx_size);\n-\tif (err)\n+\trc = qmem_alloc(rvu->dev, &pfvf->sq_ctx, req->sq_cnt, hwctx_size);\n+\tif (rc)\n \t\tgoto free_mem;\n \n \tpfvf->sq_bmap = kcalloc(req->sq_cnt, sizeof(long), GFP_KERNEL);\n-\tif (!pfvf->sq_bmap)\n+\tif (!pfvf->sq_bmap) {\n+\t\trc = -ENOMEM;\n \t\tgoto free_mem;\n+\t}\n \n \trvu_write64(rvu, blkaddr, NIX_AF_LFX_SQS_BASE(nixlf),\n \t\t (u64)pfvf->sq_ctx->iova);\n@@ -1599,13 +1604,15 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu,\n \n \t/* Alloc NIX CQ HW context memory and config the base */\n \thwctx_size = 1UL << ((ctx_cfg >> 8) & 0xF);\n-\terr = qmem_alloc(rvu->dev, &pfvf->cq_ctx, req->cq_cnt, hwctx_size);\n-\tif (err)\n+\trc = qmem_alloc(rvu->dev, &pfvf->cq_ctx, req->cq_cnt, hwctx_size);\n+\tif (rc)\n \t\tgoto free_mem;\n \n \tpfvf->cq_bmap = kcalloc(req->cq_cnt, sizeof(long), GFP_KERNEL);\n-\tif (!pfvf->cq_bmap)\n+\tif (!pfvf->cq_bmap) {\n+\t\trc = -ENOMEM;\n \t\tgoto free_mem;\n+\t}\n \n \trvu_write64(rvu, blkaddr, NIX_AF_LFX_CQS_BASE(nixlf),\n \t\t (u64)pfvf->cq_ctx->iova);\n@@ -1615,18 +1622,18 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu,\n \n \t/* Initialize receive side scaling (RSS) */\n \thwctx_size = 1UL << ((ctx_cfg >> 12) & 0xF);\n-\terr = nixlf_rss_ctx_init(rvu, blkaddr, pfvf, nixlf, req->rss_sz,\n-\t\t\t\t req->rss_grps, hwctx_size, req->way_mask,\n-\t\t\t\t !!(req->flags & NIX_LF_RSS_TAG_LSB_AS_ADDER));\n-\tif (err)\n+\trc = nixlf_rss_ctx_init(rvu, blkaddr, pfvf, nixlf, req->rss_sz,\n+\t\t\t\treq->rss_grps, hwctx_size, req->way_mask,\n+\t\t\t\t!!(req->flags & NIX_LF_RSS_TAG_LSB_AS_ADDER));\n+\tif (rc)\n \t\tgoto free_mem;\n \n \t/* Alloc memory for CQINT's HW contexts */\n \tcfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2);\n \tqints = (cfg >> 24) & 0xFFF;\n \thwctx_size = 1UL << ((ctx_cfg >> 24) & 0xF);\n-\terr = qmem_alloc(rvu->dev, &pfvf->cq_ints_ctx, qints, hwctx_size);\n-\tif (err)\n+\trc = qmem_alloc(rvu->dev, &pfvf->cq_ints_ctx, qints, hwctx_size);\n+\tif (rc)\n \t\tgoto free_mem;\n \n \trvu_write64(rvu, blkaddr, NIX_AF_LFX_CINTS_BASE(nixlf),\n@@ -1639,8 +1646,8 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu,\n \tcfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2);\n \tqints = (cfg >> 12) & 0xFFF;\n \thwctx_size = 1UL << ((ctx_cfg >> 20) & 0xF);\n-\terr = qmem_alloc(rvu->dev, &pfvf->nix_qints_ctx, qints, hwctx_size);\n-\tif (err)\n+\trc = qmem_alloc(rvu->dev, &pfvf->nix_qints_ctx, qints, hwctx_size);\n+\tif (rc)\n \t\tgoto free_mem;\n \n \trvu_write64(rvu, blkaddr, NIX_AF_LFX_QINTS_BASE(nixlf),\n@@ -1684,10 +1691,16 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu,\n \tif (is_sdp_pfvf(rvu, pcifunc))\n \t\tintf = NIX_INTF_TYPE_SDP;\n \n-\terr = nix_interface_init(rvu, pcifunc, intf, nixlf, rsp,\n-\t\t\t\t !!(req->flags & NIX_LF_LBK_BLK_SEL));\n-\tif (err)\n-\t\tgoto free_mem;\n+\tif (is_cn20k(rvu->pdev)) {\n+\t\trc = npc_cn20k_dft_rules_alloc(rvu, pcifunc);\n+\t\tif (rc)\n+\t\t\tgoto free_mem;\n+\t}\n+\n+\trc = nix_interface_init(rvu, pcifunc, intf, nixlf, rsp,\n+\t\t\t\t!!(req->flags & NIX_LF_LBK_BLK_SEL));\n+\tif (rc)\n+\t\tgoto free_dft;\n \n \t/* Disable NPC entries as NIXLF's contexts are not initialized yet */\n \trvu_npc_disable_default_entries(rvu, pcifunc, nixlf);\n@@ -1699,9 +1712,12 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu,\n \n \tgoto exit;\n \n+free_dft:\n+\tif (is_cn20k(rvu->pdev))\n+\t\tnpc_cn20k_dft_rules_free(rvu, pcifunc);\n+\n free_mem:\n \tnix_ctx_free(rvu, pfvf);\n-\trc = -ENOMEM;\n \n exit:\n \t/* Set macaddr of this PF/VF */\n@@ -1775,6 +1791,9 @@ int rvu_mbox_handler_nix_lf_free(struct rvu *rvu, struct nix_lf_free_req *req,\n \n \tnix_ctx_free(rvu, pfvf);\n \n+\tif (is_cn20k(rvu->pdev) && !(req->flags & NIX_LF_DONT_FREE_DFT_IDXS))\n+\t\tnpc_cn20k_dft_rules_free(rvu, pcifunc);\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c\nindex 3c814d157ab9..5fa9e1c7ae9f 100644\n--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c\n+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c\n@@ -990,7 +990,7 @@ void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,\n \tu16 vf_func;\n \n \t/* Only CGX PF/VF can add allmulticast entry */\n-\tif (is_lbk_vf(rvu, pcifunc) && is_sdp_vf(rvu, pcifunc))\n+\tif (is_lbk_vf(rvu, pcifunc) || is_sdp_vf(rvu, pcifunc))\n \t\treturn;\n \n \tblkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);\n@@ -1285,11 +1285,18 @@ void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc,\n \tstruct nix_mce_list *mce_list;\n \tint index, blkaddr, mce_idx;\n \tstruct rvu_pfvf *pfvf;\n+\tu16 ptr[4];\n \n \t/* multicast pkt replication is not enabled for AF's VFs & SDP links */\n \tif (is_lbk_vf(rvu, pcifunc) || is_sdp_pfvf(rvu, pcifunc))\n \t\treturn;\n \n+\t/* In cn20k, only CGX mapped devices have default MCAST entry */\n+\tif (is_cn20k(rvu->pdev) &&\n+\t npc_cn20k_dft_rules_idx_get(rvu, pcifunc, &ptr[0], &ptr[1],\n+\t\t\t\t\t&ptr[2], &ptr[3]))\n+\t\treturn;\n+\n \tblkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);\n \tif (blkaddr < 0)\n \t\treturn;\n@@ -1329,9 +1336,12 @@ static void npc_enadis_default_entries(struct rvu *rvu, u16 pcifunc,\n \tstruct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);\n \tstruct npc_mcam *mcam = &rvu->hw->mcam;\n \tint index, blkaddr;\n+\tu16 ptr[4];\n \n \t/* only CGX or LBK interfaces have default entries */\n-\tif (is_cn20k(rvu->pdev) && !npc_is_cgx_or_lbk(rvu, pcifunc))\n+\tif (is_cn20k(rvu->pdev) &&\n+\t npc_cn20k_dft_rules_idx_get(rvu, pcifunc, &ptr[0], &ptr[1],\n+\t\t\t\t\t&ptr[2], &ptr[3]))\n \t\treturn;\n \n \tblkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);\n@@ -4085,12 +4095,10 @@ void rvu_npc_clear_ucast_entry(struct rvu *rvu, int pcifunc, int nixlf)\n \n \tucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc,\n \t\t\t\t\t nixlf, NIXLF_UCAST_ENTRY);\n-\tif (ucast_idx < 0) {\n-\t\tdev_err(rvu->dev,\n-\t\t\t\"%s: Error to get ucast entry for pcifunc=%#x\\n\",\n-\t\t\t__func__, pcifunc);\n+\n+\t/* In cn20k, default rules are freed before detach rsrc */\n+\tif (ucast_idx < 0)\n \t\treturn;\n-\t}\n \n \tnpc_enable_mcam_entry(rvu, mcam, blkaddr, ucast_idx, false);\n \ndiff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c\nindex ee623476e5ff..81b088f5a016 100644\n--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c\n+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c\n@@ -1053,7 +1053,6 @@ irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq)\n \t/* Clear the IRQ */\n \totx2_write64(pf, RVU_PF_INT, BIT_ULL(0));\n \n-\n \tmbox_data = otx2_read64(pf, RVU_PF_PFAF_MBOX0);\n \n \tif (mbox_data & MBOX_UP_MSG) {\n@@ -1729,7 +1728,7 @@ int otx2_init_hw_resources(struct otx2_nic *pf)\n \tmutex_lock(&mbox->lock);\n \tfree_req = otx2_mbox_alloc_msg_nix_lf_free(mbox);\n \tif (free_req) {\n-\t\tfree_req->flags = NIX_LF_DISABLE_FLOWS;\n+\t\tfree_req->flags = NIX_LF_DISABLE_FLOWS | NIX_LF_DONT_FREE_DFT_IDXS;\n \t\tif (otx2_sync_mbox_msg(mbox))\n \t\t\tdev_err(pf->dev, \"%s failed to free nixlf\\n\", __func__);\n \t}\n@@ -1803,7 +1802,7 @@ void otx2_free_hw_resources(struct otx2_nic *pf)\n \t/* Reset NIX LF */\n \tfree_req = otx2_mbox_alloc_msg_nix_lf_free(mbox);\n \tif (free_req) {\n-\t\tfree_req->flags = NIX_LF_DISABLE_FLOWS;\n+\t\tfree_req->flags = NIX_LF_DISABLE_FLOWS | NIX_LF_DONT_FREE_DFT_IDXS;\n \t\tif (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN))\n \t\t\tfree_req->flags |= NIX_LF_DONT_FREE_TX_VTAG;\n \t\tif (otx2_sync_mbox_msg(mbox))\n@@ -1926,7 +1925,6 @@ int otx2_alloc_queue_mem(struct otx2_nic *pf)\n \tstruct otx2_qset *qset = &pf->qset;\n \tstruct otx2_cq_poll *cq_poll;\n \n-\n \t/* RQ and SQs are mapped to different CQs,\n \t * so find out max CQ IRQs (i.e CINTs) needed.\n \t */\n", "prefixes": [ "v12", "net-next", "6/9" ] }