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GET /api/1.2/patches/2235216/?format=api
{ "id": 2235216, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2235216/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260508034912.4082520-6-rkannoth@marvell.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/1.2/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508034912.4082520-6-rkannoth@marvell.com>", "list_archive_url": null, "date": "2026-05-08T03:49:08", "name": "[v12,net-next,5/9] octeontx2-af: npc: cn20k: add subbank search order control", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5538cde3a148bb1d8b5790a76ead00ac9d9f3e58", "submitter": { "id": 86908, "url": "http://patchwork.ozlabs.org/api/1.2/people/86908/?format=api", "name": "Ratheesh Kannoth", "email": "rkannoth@marvell.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260508034912.4082520-6-rkannoth@marvell.com/mbox/", "series": [ { "id": 503453, "url": "http://patchwork.ozlabs.org/api/1.2/series/503453/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=503453", "date": "2026-05-08T03:49:12", "name": "octeontx2-af: npc: Enhancements.", "version": 12, "mbox": "http://patchwork.ozlabs.org/series/503453/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2235216/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2235216/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=h42SN7Az;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::137; 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client-ip=67.231.148.174;\n helo=mx0a-0016f401.pphosted.com;\n envelope-from=prvs=65883a0750=rkannoth@marvell.com; receiver=<UNKNOWN>", "DMARC-Filter": "OpenDMARC Filter v1.4.2 smtp4.osuosl.org 9E9EE41348", "From": "Ratheesh Kannoth <rkannoth@marvell.com>", "To": "<intel-wired-lan@lists.osuosl.org>, <linux-kernel@vger.kernel.org>,\n <linux-rdma@vger.kernel.org>, <netdev@vger.kernel.org>,\n <oss-drivers@corigine.com>", "CC": "<akiyano@amazon.com>, <andrew+netdev@lunn.ch>,\n <anthony.l.nguyen@intel.com>, <arkadiusz.kubalewski@intel.com>,\n <brett.creeley@amd.com>, <darinzon@amazon.com>, <davem@davemloft.net>,\n <donald.hunter@gmail.com>, <edumazet@google.com>, <horms@kernel.org>,\n <idosch@nvidia.com>, <ivecera@redhat.com>, <jiri@resnulli.us>,\n <kuba@kernel.org>, <leon@kernel.org>, <mbloch@nvidia.com>,\n <michael.chan@broadcom.com>, <pabeni@redhat.com>,\n <pavan.chebbi@broadcom.com>, <petrm@nvidia.com>,\n <Prathosh.Satish@microchip.com>, <przemyslaw.kitszel@intel.com>,\n <saeedm@nvidia.com>, <sgoutham@marvell.com>, <tariqt@nvidia.com>,\n <vadim.fedorenko@linux.dev>, Ratheesh Kannoth <rkannoth@marvell.com>", "Date": "Fri, 8 May 2026 09:19:08 +0530", "Message-ID": "<20260508034912.4082520-6-rkannoth@marvell.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260508034912.4082520-1-rkannoth@marvell.com>", "References": "<20260508034912.4082520-1-rkannoth@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "QxzE9-pM_VCAzKUWZH4o4R-9NCG46ze8", "X-Proofpoint-GUID": "QxzE9-pM_VCAzKUWZH4o4R-9NCG46ze8", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNTA4MDAzNCBTYWx0ZWRfX5HVTGcv5bUlU\n +euyHdjph9FDIwsjb9ytgfgAhqubp47sHxAziBRX3UBP7iwZy4PFZdKvf1YJnfP41STlpty1Znc\n kX1BYTUfKTrYugL8xHUhfCVWkUBfZrRdTME/uiYxQ/UOyRn2XDUPr01WkDfCmFAoXHWpeSeXa2Y\n hfNKoNlwicUaQusRe8v5RSgjr6Xulw0/A73vtYr1o7t+Q63SEb7v72EUQRGUgRU/4q94UqkUTjC\n EBlg3A4pMMDoKRJOvOgqc7jrPdNBGz7NLHyFDjxqeRJipcKIBhu7GwtNafJ7khbmSrQCxJeE9PB\n OHXydusEZxFivD59yhCPsnQdJqbKjAVBXUuWW9v2qpeQjzD7M5tCO3kuOS+wd/2JIPrDe0H28AA\n 2q6a+AkmcupeVGMHLENuWG6OXFePZ4ftU3vOYKc+k5/jxvHKOfG566tEyOYmz5Vo+TATVkhVD4Z\n 23NLy2oKPMbndxoAyqw==", "X-Authority-Analysis": "v=2.4 cv=WZ48rUhX c=1 sm=1 tr=0 ts=69fd5d82 cx=c_pps\n a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17\n a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22\n a=TtqV-g6YmW1Jfm2GSLaY:22 a=M5GUcnROAAAA:8 a=PAjbinj206NiyaaJ5nAA:9\n a=OBjm3rFKGHvpk9ecZwUJ:22", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-05-07_02,2026-05-06_01,2025-10-01_01", "X-Mailman-Approved-At": "Fri, 08 May 2026 22:09:04 +0000", "X-Mailman-Original-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=marvell.com; h=\n cc:content-transfer-encoding:content-type:date:from:in-reply-to\n :message-id:mime-version:references:subject:to; s=pfpt0220; bh=Z\n t5R2E5boZnsPUPuNF47EKAupoojwaBV2uiIYLG2j7k=; b=W8xjLeZ2f6Ydt/3/u\n D+SQdS/PBfQ+B0lFj2IcTPt8QROV+re21XHeTv2pP6Q1EM0Ha1BqLjOdISwe4eGD\n njMQNrcTk8FSCx//LMrt3B/BngjSIsHxSPBCrxEHVsryMo8Mq1J10R2MKKsSePy6\n uyGLcHOnSNXpaTWmkDZ+esia0GamrurOT0LeuK2rbkTPmh1wsZwKPrnORAknqmNx\n 5E8fKFVU2ZUKynDWFsyVEHC1DSFb48d0nI+ZBAt6LmNVCTryOEh5v9eQcOtszpEm\n dAtijC+Fr6bwQD2OfAxZkdZRgazeTb4uRj3PEsRSoqb7mDFr2rJn3X6RP83D0E1n\n QVFXw==", "X-Mailman-Original-Authentication-Results": [ "smtp4.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=marvell.com", "smtp4.osuosl.org;\n dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com\n header.a=rsa-sha256 header.s=pfpt0220 header.b=W8xjLeZ2" ], "Subject": "[Intel-wired-lan] [PATCH v12 net-next 5/9] octeontx2-af: npc:\n cn20k: add subbank search order control", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n <intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "CN20K NPC MCAM is split into 32 subbanks that are searched in a\npredefined order during allocation. Lower-numbered subbanks have\nhigher priority than higher-numbered ones.\n\nAdd a runtime \"srch_order\" to control the order in which\nsubbanks are searched during MCAM allocation.\n\nSigned-off-by: Ratheesh Kannoth <rkannoth@marvell.com>\n---\n .../ethernet/marvell/octeontx2/af/cn20k/npc.c | 54 ++++++++++-\n .../ethernet/marvell/octeontx2/af/cn20k/npc.h | 3 +\n .../marvell/octeontx2/af/rvu_devlink.c | 92 +++++++++++++++++--\n 3 files changed, 137 insertions(+), 12 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c\nindex e9aad0ad3fa6..6f8f42234b06 100644\n--- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c\n+++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c\n@@ -3376,7 +3376,7 @@ rvu_mbox_handler_npc_cn20k_get_kex_cfg(struct rvu *rvu,\n \treturn 0;\n }\n \n-static int *subbank_srch_order;\n+static u32 *subbank_srch_order;\n \n static void npc_populate_restricted_idxs(int num_subbanks)\n {\n@@ -3388,7 +3388,7 @@ static int npc_create_srch_order(int cnt)\n {\n \tint val = 0;\n \n-\tsubbank_srch_order = kcalloc(cnt, sizeof(int),\n+\tsubbank_srch_order = kcalloc(cnt, sizeof(u32),\n \t\t\t\t GFP_KERNEL);\n \tif (!subbank_srch_order)\n \t\treturn -ENOMEM;\n@@ -3906,6 +3906,56 @@ static void npc_unlock_all_subbank(void)\n \t\tmutex_unlock(&npc_priv.sb[i].lock);\n }\n \n+int npc_cn20k_search_order_set(struct rvu *rvu,\n+\t\t\t u64 narr[MAX_NUM_SUB_BANKS], int cnt)\n+{\n+\tstruct npc_mcam *mcam = &rvu->hw->mcam;\n+\tstruct npc_subbank *sb;\n+\tstruct xarray *xa;\n+\tint sb_idx, rc;\n+\n+\tif (cnt != npc_priv.num_subbanks) {\n+\t\tdev_err(rvu->dev, \"Number of entries(%u) != %u\\n\",\n+\t\t\tcnt, npc_priv.num_subbanks);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmutex_lock(&mcam->lock);\n+\tnpc_lock_all_subbank();\n+\trestrict_valid = false;\n+\n+\tfor (sb_idx = 0; sb_idx < cnt; sb_idx++) {\n+\t\tsb = &npc_priv.sb[sb_idx];\n+\n+\t\txa = &npc_priv.xa_sb_free;\n+\t\tif (sb->flags & NPC_SUBBANK_FLAG_USED)\n+\t\t\txa = &npc_priv.xa_sb_used;\n+\n+\t\tsb->arr_idx = narr[sb_idx];\n+\n+\t\trc = xa_err(xa_store(xa, sb->arr_idx,\n+\t\t\t\t xa_mk_value(sb_idx), GFP_KERNEL));\n+\t\tif (rc)\n+\t\t\tgoto fail;\n+\t}\n+\n+\tfor (int i = 0; i < cnt; i++)\n+\t\tsubbank_srch_order[i] = (u32)narr[i];\n+\n+fail:\n+\tnpc_unlock_all_subbank();\n+\tmutex_unlock(&mcam->lock);\n+\n+\treturn rc;\n+}\n+\n+const u32 *npc_cn20k_search_order_get(bool *restricted_order, u32 *sz)\n+{\n+\t*restricted_order = restrict_valid;\n+\t*sz = npc_priv.num_subbanks;\n+\treturn subbank_srch_order;\n+}\n+\n /* Only non-ref non-contigous mcam indexes\n * are picked for defrag process\n */\ndiff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h\nindex 9567a2d80b58..bf030e40fbf9 100644\n--- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h\n+++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h\n@@ -343,5 +343,8 @@ bool npc_is_cgx_or_lbk(struct rvu *rvu, u16 pcifunc);\n int npc_mcam_idx_2_subbank_idx(struct rvu *rvu, u16 mcam_idx,\n \t\t\t struct npc_subbank **sb,\n \t\t\t int *sb_off);\n+const u32 *npc_cn20k_search_order_get(bool *restricted_order, u32 *sz);\n+int npc_cn20k_search_order_set(struct rvu *rvu, u64 narr[MAX_NUM_SUB_BANKS],\n+\t\t\t int cnt);\n \n #endif /* NPC_CN20K_H */\ndiff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c\nindex a42404e6db7c..aa3ecab5ebd8 100644\n--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c\n+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c\n@@ -1258,6 +1258,7 @@ enum rvu_af_dl_param_id {\n \tRVU_AF_DEVLINK_PARAM_ID_NPC_EXACT_FEATURE_DISABLE,\n \tRVU_AF_DEVLINK_PARAM_ID_NPC_DEF_RULE_CNTR_ENABLE,\n \tRVU_AF_DEVLINK_PARAM_ID_NPC_DEFRAG,\n+\tRVU_AF_DEVLINK_PARAM_ID_NPC_SRCH_ORDER,\n \tRVU_AF_DEVLINK_PARAM_ID_NIX_MAXLF,\n };\n \n@@ -1619,12 +1620,83 @@ static int rvu_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,\n \treturn 0;\n }\n \n+static int rvu_af_dl_npc_srch_order_set(struct devlink *devlink, u32 id,\n+\t\t\t\t\tstruct devlink_param_gset_ctx *ctx,\n+\t\t\t\t\tstruct netlink_ext_ack *extack)\n+{\n+\tstruct rvu_devlink *rvu_dl = devlink_priv(devlink);\n+\tstruct rvu *rvu = rvu_dl->rvu;\n+\n+\treturn npc_cn20k_search_order_set(rvu,\n+\t\t\t\t\t ctx->val.u64arr.val,\n+\t\t\t\t\t ctx->val.u64arr.size);\n+}\n+\n+static int rvu_af_dl_npc_srch_order_get(struct devlink *devlink, u32 id,\n+\t\t\t\t\tstruct devlink_param_gset_ctx *ctx,\n+\t\t\t\t\tstruct netlink_ext_ack *extack)\n+{\n+\tbool restricted_order;\n+\tconst u32 *order;\n+\tu32 sz;\n+\n+\torder = npc_cn20k_search_order_get(&restricted_order, &sz);\n+\tctx->val.u64arr.size = sz;\n+\tfor (int i = 0; i < sz; i++)\n+\t\tctx->val.u64arr.val[i] = order[i];\n+\n+\treturn 0;\n+}\n+\n+static int rvu_af_dl_npc_srch_order_validate(struct devlink *devlink, u32 id,\n+\t\t\t\t\t union devlink_param_value *val,\n+\t\t\t\t\t struct netlink_ext_ack *extack)\n+{\n+\tstruct rvu_devlink *rvu_dl = devlink_priv(devlink);\n+\tstruct rvu *rvu = rvu_dl->rvu;\n+\tbool restricted_order;\n+\tunsigned long w = 0;\n+\tu64 *arr;\n+\tu32 sz;\n+\n+\tnpc_cn20k_search_order_get(&restricted_order, &sz);\n+\tif (sz != val->u64arr.size) {\n+\t\tdev_err(rvu->dev,\n+\t\t\t\"Wrong size %llu, should be %u\\n\",\n+\t\t\tval->u64arr.size, sz);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tarr = val->u64arr.val;\n+\tfor (int i = 0; i < sz; i++) {\n+\t\tif (arr[i] >= sz)\n+\t\t\treturn -EINVAL;\n+\n+\t\tw |= BIT_ULL(arr[i]);\n+\t}\n+\n+\tif (bitmap_weight(&w, sz) != sz) {\n+\t\tdev_err(rvu->dev,\n+\t\t\t\"Duplicate or out-of-range subbank index. %lu\\n\",\n+\t\t\tfind_first_zero_bit(&w, sz));\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static const struct devlink_ops rvu_devlink_ops = {\n \t.eswitch_mode_get = rvu_devlink_eswitch_mode_get,\n \t.eswitch_mode_set = rvu_devlink_eswitch_mode_set,\n };\n \n-static const struct devlink_param rvu_af_dl_param_defrag[] = {\n+static const struct devlink_param rvu_af_dl_cn20k_params[] = {\n+\tDEVLINK_PARAM_DRIVER(RVU_AF_DEVLINK_PARAM_ID_NPC_SRCH_ORDER,\n+\t\t\t \"npc_srch_order\", DEVLINK_PARAM_TYPE_U64_ARRAY,\n+\t\t\t BIT(DEVLINK_PARAM_CMODE_RUNTIME),\n+\t\t\t rvu_af_dl_npc_srch_order_get,\n+\t\t\t rvu_af_dl_npc_srch_order_set,\n+\t\t\t rvu_af_dl_npc_srch_order_validate),\n \tDEVLINK_PARAM_DRIVER(RVU_AF_DEVLINK_PARAM_ID_NPC_DEFRAG,\n \t\t\t \"npc_defrag\", DEVLINK_PARAM_TYPE_STRING,\n \t\t\t BIT(DEVLINK_PARAM_CMODE_RUNTIME),\n@@ -1666,13 +1738,13 @@ int rvu_register_dl(struct rvu *rvu)\n \t}\n \n \tif (is_cn20k(rvu->pdev)) {\n-\t\terr = devlink_params_register(dl, rvu_af_dl_param_defrag,\n-\t\t\t\t\t ARRAY_SIZE(rvu_af_dl_param_defrag));\n+\t\terr = devlink_params_register(dl, rvu_af_dl_cn20k_params,\n+\t\t\t\t\t ARRAY_SIZE(rvu_af_dl_cn20k_params));\n \t\tif (err) {\n \t\t\tdev_err(rvu->dev,\n-\t\t\t\t\"devlink defrag params register failed with error %d\",\n+\t\t\t\t\"devlink cn20k params register failed with error %d\",\n \t\t\t\terr);\n-\t\t\tgoto err_dl_defrag;\n+\t\t\tgoto err_dl_cn20k_params;\n \t\t}\n \t}\n \n@@ -1695,10 +1767,10 @@ int rvu_register_dl(struct rvu *rvu)\n \n err_dl_exact_match:\n \tif (is_cn20k(rvu->pdev))\n-\t\tdevlink_params_unregister(dl, rvu_af_dl_param_defrag,\n-\t\t\t\t\t ARRAY_SIZE(rvu_af_dl_param_defrag));\n+\t\tdevlink_params_unregister(dl, rvu_af_dl_cn20k_params,\n+\t\t\t\t\t ARRAY_SIZE(rvu_af_dl_cn20k_params));\n \n-err_dl_defrag:\n+err_dl_cn20k_params:\n \tdevlink_params_unregister(dl, rvu_af_dl_params, ARRAY_SIZE(rvu_af_dl_params));\n \n err_dl_health:\n@@ -1717,8 +1789,8 @@ void rvu_unregister_dl(struct rvu *rvu)\n \tdevlink_params_unregister(dl, rvu_af_dl_params, ARRAY_SIZE(rvu_af_dl_params));\n \n \tif (is_cn20k(rvu->pdev))\n-\t\tdevlink_params_unregister(dl, rvu_af_dl_param_defrag,\n-\t\t\t\t\t ARRAY_SIZE(rvu_af_dl_param_defrag));\n+\t\tdevlink_params_unregister(dl, rvu_af_dl_cn20k_params,\n+\t\t\t\t\t ARRAY_SIZE(rvu_af_dl_cn20k_params));\n \n \t/* Unregister exact match devlink only for CN10K-B */\n \tif (rvu_npc_exact_has_match_table(rvu))\n", "prefixes": [ "v12", "net-next", "5/9" ] }