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GET /api/1.2/patches/2235171/?format=api
{ "id": 2235171, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2235171/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508183717.193630-8-tdave@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508183717.193630-8-tdave@nvidia.com>", "list_archive_url": null, "date": "2026-05-08T18:37:16", "name": "[RFC,7/8] hw/arm/virt: add pcie-mmio-window machine property", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9f2477a581f8b8ad1f42bacfcc7de8065ebb1d53", "submitter": { "id": 89928, "url": "http://patchwork.ozlabs.org/api/1.2/people/89928/?format=api", "name": "Tushar Dave", "email": "tdave@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508183717.193630-8-tdave@nvidia.com/mbox/", "series": [ { "id": 503429, "url": "http://patchwork.ozlabs.org/api/1.2/series/503429/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503429", "date": "2026-05-08T18:37:09", "name": "hw/arm/virt, hw/pci: PCI pre-enumeration and fixed BAR allocation", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/503429/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2235171/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2235171/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=feqEb2E1;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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The default aperture may be too small\nor not cover the required range.\n\nThis property allows the aperture to be resized or repositioned\nso that all fixed BAR addresses are accessible to the guest.\n\nSigned-off-by: Tushar Dave <tdave@nvidia.com>\n---\n hw/arm/virt.c | 87 ++++++++++++++++++++++++++++++++++++++++++-\n include/hw/arm/virt.h | 2 +\n 2 files changed, 87 insertions(+), 2 deletions(-)", "diff": "diff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex ec0d8475ca..55f41c7e46 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -1915,8 +1915,31 @@ static void virt_set_high_memmap(VirtMachineState *vms,\n \n for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {\n region_enabled = virt_get_high_memmap_enabled(vms, i);\n- region_base = ROUND_UP(base, extended_memmap[i].size);\n- region_size = extended_memmap[i].size;\n+\n+ if (i == VIRT_HIGH_PCIE_MMIO && vms->override_pcie_mmio_size) {\n+ region_base = vms->override_pcie_mmio_base;\n+ region_size = vms->override_pcie_mmio_size;\n+\n+ /* Check for overlap with prior high regions */\n+ if (region_base < base) {\n+ error_report(\"pcie-mmio-window base 0x%\" PRIx64 \" overlaps \"\n+ \"high memory layout (must be >= 0x%\" PRIx64 \")\",\n+ (uint64_t)region_base, (uint64_t)base);\n+ exit(1);\n+ }\n+ /* Must not exceed the PA space */\n+ if (region_base + region_size > BIT_ULL(pa_bits)) {\n+ error_report(\"pcie-mmio-window [0x%\" PRIx64 \", 0x%\" PRIx64 \") \"\n+ \"exceeds %d-bit PA space\",\n+ (uint64_t)region_base,\n+ (uint64_t)(region_base + region_size),\n+ pa_bits);\n+ exit(1);\n+ }\n+ } else {\n+ region_base = ROUND_UP(base, extended_memmap[i].size);\n+ region_size = extended_memmap[i].size;\n+ }\n \n vms->memmap[i].base = region_base;\n vms->memmap[i].size = region_size;\n@@ -3004,6 +3027,60 @@ static void virt_set_gic_version(Object *obj, const char *value, Error **errp)\n }\n }\n \n+static char *virt_get_pcie_mmio_window(Object *obj, Error **errp)\n+{\n+ VirtMachineState *vms = VIRT_MACHINE(obj);\n+\n+ if (!vms->override_pcie_mmio_size) {\n+ return g_strdup(\"\");\n+ }\n+ return g_strdup_printf(\"0x%\" PRIx64 \":0x%\" PRIx64,\n+ (uint64_t)vms->override_pcie_mmio_base,\n+ (uint64_t)vms->override_pcie_mmio_size);\n+}\n+\n+static void virt_set_pcie_mmio_window(Object *obj, const char *value, Error **errp)\n+{\n+ VirtMachineState *vms = VIRT_MACHINE(obj);\n+ uint64_t base = 0, size = 0;\n+ const char *endptr;\n+ int ret;\n+\n+ if (!value || !*value) {\n+ return;\n+ }\n+\n+ ret = qemu_strtou64(value, &endptr, 0, &base);\n+ if (ret || base == 0) {\n+ error_setg(errp, \"pcie-mmio-window base must be a positive number\");\n+ return;\n+ }\n+ if (*endptr != ':' || !*(endptr + 1)) {\n+ error_setg(errp, \"pcie-mmio-window expects BASE:SIZE\");\n+ return;\n+ }\n+\n+ ret = qemu_strtou64(endptr + 1, NULL, 0, &size);\n+ if (ret || size == 0) {\n+ error_setg(errp, \"pcie-mmio-window size must be a positive number\");\n+ return;\n+ }\n+\n+ if (!is_power_of_2(size)) {\n+ error_setg(errp, \"pcie-mmio-window size 0x%\" PRIx64 \" must be a power of 2\",\n+ (uint64_t)size);\n+ return;\n+ }\n+ if (base % size != 0) {\n+ error_setg(errp, \"pcie-mmio-window base 0x%\" PRIx64 \" must be aligned to size 0x%\" PRIx64,\n+ (uint64_t)base, (uint64_t)size);\n+ return;\n+ }\n+\n+ vms->override_pcie_mmio_base = base;\n+ vms->override_pcie_mmio_size = size;\n+}\n+\n static char *virt_get_iommu(Object *obj, Error **errp)\n {\n VirtMachineState *vms = VIRT_MACHINE(obj);\n@@ -3582,6 +3659,12 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)\n \"Set the IOMMU type. \"\n \"Valid values are none and smmuv3\");\n \n+ object_class_property_add_str(oc, \"pcie-mmio-window\",\n+ virt_get_pcie_mmio_window,\n+ virt_set_pcie_mmio_window);\n+ object_class_property_set_description(oc, \"pcie-mmio-window\",\n+ \"Override the high PCIe MMIO window as BASE:SIZE\");\n+\n object_class_property_add_bool(oc, \"default-bus-bypass-iommu\",\n virt_get_default_bus_bypass_iommu,\n virt_set_default_bus_bypass_iommu);\ndiff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h\nindex 5fcbd1c76f..410df857c7 100644\n--- a/include/hw/arm/virt.h\n+++ b/include/hw/arm/virt.h\n@@ -187,6 +187,8 @@ struct VirtMachineState {\n MemoryRegion *sysmem;\n MemoryRegion *secure_sysmem;\n bool pci_preserve_config;\n+ hwaddr override_pcie_mmio_base;\n+ hwaddr override_pcie_mmio_size;\n };\n \n #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)\n", "prefixes": [ "RFC", "7/8" ] }