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GET /api/1.2/patches/2235170/?format=api
{ "id": 2235170, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2235170/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508183717.193630-9-tdave@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508183717.193630-9-tdave@nvidia.com>", "list_archive_url": null, "date": "2026-05-08T18:37:17", "name": "[RFC,8/8] hw/arm/virt: add pci-pre-enum machine property", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bed6ae240ccad6723accba4e8fe01d44b69ecae1", "submitter": { "id": 89928, "url": "http://patchwork.ozlabs.org/api/1.2/people/89928/?format=api", "name": "Tushar Dave", "email": "tdave@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508183717.193630-9-tdave@nvidia.com/mbox/", "series": [ { "id": 503429, "url": "http://patchwork.ozlabs.org/api/1.2/series/503429/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503429", "date": "2026-05-08T18:37:09", "name": "hw/arm/virt, hw/pci: PCI pre-enumeration and fixed BAR allocation", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/503429/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2235170/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2235170/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=mQtH6eN9;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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When enabled, QEMU\nperforms PCI enumeration and programs BARs before handing control to\nfirmware.\n\nThis is intended for use with the \"fixed-bars\" property, where the\nuser assigns fixed BAR addresses and expects firmware to preserve the\nconfiguration.\n\npci-pre-enum is exposed as a separate machine property rather than\nbeing implied by the presence of fixed-bars. This allows QEMU's PCI\nenumeration path to be exercised independently (for example, to\nverify that QEMU produces the same device enumeration as EDK2)\nwithout requiring any device to specify fixed BARs.\n\nWhen enabled, a \"pci-enum-done\" property is added to the PCI node in\nthe device tree to indicate to firmware (e.g. EDK2) that PCI\nenumeration has already been performed.\n\nWhen disabled (default), behavior is unchanged.\n\nSigned-off-by: Tushar Dave <tdave@nvidia.com>\n---\n hw/arm/virt.c | 70 +++++++++++++++++++++++++++++++++++++++++--\n include/hw/arm/virt.h | 1 +\n 2 files changed, 68 insertions(+), 3 deletions(-)", "diff": "diff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex 55f41c7e46..7d41bfc457 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -52,6 +52,7 @@\n #include \"system/whpx.h\"\n #include \"system/qtest.h\"\n #include \"system/system.h\"\n+#include \"system/reset.h\"\n #include \"hw/core/loader.h\"\n #include \"qapi/error.h\"\n #include \"qemu/bitops.h\"\n@@ -94,6 +95,8 @@\n #include \"hw/cxl/cxl.h\"\n #include \"hw/cxl/cxl_host.h\"\n #include \"qemu/guest-random.h\"\n+#include \"hw/pci/pci-resource.h\"\n+#include \"hw/pci/pci-enumerate.h\"\n \n static GlobalProperty arm_virt_compat_defaults[] = {\n { TYPE_VIRTIO_IOMMU_PCI, \"aw-bits\", \"48\" },\n@@ -1697,6 +1700,10 @@ static void create_pcie(VirtMachineState *vms)\n qemu_fdt_setprop_cell(ms->fdt, nodename, \"#interrupt-cells\", 1);\n create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);\n \n+ if (vms->pci_pre_enum) {\n+ qemu_fdt_setprop_cell(ms->fdt, nodename, \"pci-enum-done\", 1);\n+ }\n+\n if (vms->iommu) {\n vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);\n \n@@ -1832,6 +1839,20 @@ static void virt_build_smbios(VirtMachineState *vms)\n }\n }\n \n+static void virt_pci_apply_fix_bar_after_reset(void *opaque)\n+{\n+ VirtMachineState *vms = opaque;\n+ PciFixedBarMmioParams mmio = {\n+ .mmio32_base = vms->memmap[VIRT_PCIE_MMIO].base,\n+ .mmio32_size = vms->memmap[VIRT_PCIE_MMIO].size,\n+ .mmio64_base = vms->memmap[VIRT_HIGH_PCIE_MMIO].base,\n+ .mmio64_size = vms->memmap[VIRT_HIGH_PCIE_MMIO].size,\n+ };\n+\n+ pci_enumerate_bus(vms->bus);\n+ pci_fixed_bar_allocator(vms->bus, &mmio);\n+}\n+\n static\n void virt_machine_done(Notifier *notifier, void *data)\n {\n@@ -1864,11 +1885,30 @@ void virt_machine_done(Notifier *notifier, void *data)\n if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms, cpu) < 0) {\n exit(1);\n }\n-\n- pci_bus_add_fw_cfg_extra_pci_roots(vms->fw_cfg, vms->bus,\n- &error_abort);\n+ /*\n+ * In pci-pre-enum mode, EDK2 does not perform PCI enumeration or\n+ * resource assignment (PcdPciDisableBusEnumeration = TRUE). All root\n+ * bridges are marked ResourceAssigned, meaning the topology and\n+ * MMIO/MMIO64 apertures provided by QEMU are treated as final.\n+ *\n+ * In this mode, each root bridge is consumed as an independent resource\n+ * domain. Exposing additional root bridges (e.g. PXB extra roots) that\n+ * share identical MMIO/MMIO64 apertures creates duplicate resource domains\n+ * with overlapping address spaces, which is invalid in this mode.\n+ *\n+ * Therefore, extra root bridges are not exposed in pre-enumeration mode.\n+ */\n+ if (!vms->pci_pre_enum) {\n+ pci_bus_add_fw_cfg_extra_pci_roots(vms->fw_cfg, vms->bus,\n+ &error_abort);\n+ }\n \n virt_acpi_setup(vms);\n+\n+ if (vms->pci_pre_enum) {\n+ qemu_register_reset(virt_pci_apply_fix_bar_after_reset, vms);\n+ }\n+\n virt_build_smbios(vms);\n }\n \n@@ -2988,6 +3028,20 @@ static void virt_set_mte(Object *obj, bool value, Error **errp)\n vms->mte = value;\n }\n \n+static bool virt_get_pci_pre_enum(Object *obj, Error **errp)\n+{\n+ VirtMachineState *vms = VIRT_MACHINE(obj);\n+\n+ return vms->pci_pre_enum;\n+}\n+\n+static void virt_set_pci_pre_enum(Object *obj, bool value, Error **errp)\n+{\n+ VirtMachineState *vms = VIRT_MACHINE(obj);\n+\n+ vms->pci_pre_enum = value;\n+}\n+\n static char *virt_get_gic_version(Object *obj, Error **errp)\n {\n VirtMachineState *vms = VIRT_MACHINE(obj);\n@@ -3726,6 +3780,13 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)\n \"in ACPI table header.\"\n \"The string may be up to 8 bytes in size\");\n \n+ object_class_property_add_bool(oc, \"pci-pre-enum\",\n+ virt_get_pci_pre_enum,\n+ virt_set_pci_pre_enum);\n+ object_class_property_set_description(oc, \"pci-pre-enum\",\n+ \"Set on/off to enable/disable PCI enumeration and resource assignment\"\n+ \" in QEMU. When enabled, QEMU programs BARs (including fixed-bars\"\n+ \" addresses) before handing control to firmware.\");\n }\n \n static void virt_instance_init(Object *obj)\n@@ -3768,6 +3829,9 @@ static void virt_instance_init(Object *obj)\n /* MTE is disabled by default. */\n vms->mte = false;\n \n+ /* PCI pre-enumeration disabled by default */\n+ vms->pci_pre_enum = false;\n+\n /* Supply kaslr-seed and rng-seed by default */\n vms->dtb_randomness = true;\n \ndiff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h\nindex 410df857c7..0786f4a4fc 100644\n--- a/include/hw/arm/virt.h\n+++ b/include/hw/arm/virt.h\n@@ -187,6 +187,7 @@ struct VirtMachineState {\n MemoryRegion *sysmem;\n MemoryRegion *secure_sysmem;\n bool pci_preserve_config;\n+ bool pci_pre_enum;\n hwaddr override_pcie_mmio_base;\n hwaddr override_pcie_mmio_size;\n };\n", "prefixes": [ "RFC", "8/8" ] }