get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/1.2/patches/2235168/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2235168,
    "url": "http://patchwork.ozlabs.org/api/1.2/patches/2235168/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508183717.193630-2-tdave@nvidia.com/",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
        "list_email": "qemu-devel@nongnu.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260508183717.193630-2-tdave@nvidia.com>",
    "list_archive_url": null,
    "date": "2026-05-08T18:37:10",
    "name": "[RFC,1/8] hw/pci: add fixed-bars property to allow fixed BAR addresses",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "1e2fc4e6e8b1ee9fbd916c0e1f6afef61beb3816",
    "submitter": {
        "id": 89928,
        "url": "http://patchwork.ozlabs.org/api/1.2/people/89928/?format=api",
        "name": "Tushar Dave",
        "email": "tdave@nvidia.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508183717.193630-2-tdave@nvidia.com/mbox/",
    "series": [
        {
            "id": 503429,
            "url": "http://patchwork.ozlabs.org/api/1.2/series/503429/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503429",
            "date": "2026-05-08T18:37:09",
            "name": "hw/arm/virt, hw/pci: PCI pre-enumeration and fixed BAR allocation",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/503429/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2235168/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2235168/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@legolas.ozlabs.org",
        "Authentication-Results": [
            "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=gszBdSVT;\n\tdkim-atps=neutral",
            "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)",
            "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nvidia.com;"
        ],
        "Received": [
            "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gByZB09cLz1yCg\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 09 May 2026 04:38:58 +1000 (AEST)",
            "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wLQ5K-0006fF-Gb; Fri, 08 May 2026 14:38:02 -0400",
            "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <tdave@nvidia.com>)\n id 1wLQ5E-0006eZ-AE; Fri, 08 May 2026 14:37:56 -0400",
            "from mail-centralusazlp170100005.outbound.protection.outlook.com\n ([2a01:111:f403:c111::5] helo=DM1PR04CU001.outbound.protection.outlook.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <tdave@nvidia.com>)\n id 1wLQ5C-0002Yg-KO; Fri, 08 May 2026 14:37:56 -0400",
            "from BY5PR12MB4179.namprd12.prod.outlook.com (2603:10b6:a03:211::8)\n by CH3PR12MB8482.namprd12.prod.outlook.com (2603:10b6:610:15b::8)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9891.20; Fri, 8 May\n 2026 18:37:44 +0000",
            "from BY5PR12MB4179.namprd12.prod.outlook.com\n ([fe80::2036:e8b:9b3:f325]) by BY5PR12MB4179.namprd12.prod.outlook.com\n ([fe80::2036:e8b:9b3:f325%4]) with mapi id 15.20.9891.019; Fri, 8 May 2026\n 18:37:44 +0000"
        ],
        "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=xxKkGqmuuIs63zltx+H8jpj467ES8n7KOtXzXPIwM02/dd1mEI1MBXBT8s+WezDQnHMMyNuqu562eBqBXVqNOMW5jJhhPB7rn4QS6pQU4bMuW0kRp674LkGgD0YQxjj1gSGThHorCXr3pSoZo5oyUoBf7NTSm8CgYuxUcEt/qINEivYsL2ZEXgXD9lHmhwEfczFn560/O8hKlN89SFhwDuJdKET/fS+Kyp7djfYOLyaD5jnW2+C77P9qCmEXz3VCSzUFNARwDXurCrJn8gQowPUJfqWeXppPWD/J/rdMStrwRjOT/Lay+WYC1H7lDfKB+UnUON9VOGe/v6QlXvo5mw==",
        "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=wzeKAO+rXcuLDHgcb16pHML/zJ2nWk54OrooHG4hgVA=;\n b=Or9KA3WQ6FMsrXolc7Pj/AxJkQMbBeUESYatqwg4KYveKDz66cuLOTWgo9+YBFa47KRPW9vhOR2nH9tGiONCk46zfCBNijXG3qpU8gqJpX04hJzF5bDDWBncAXmC9iat4uQGtWV/Cb17f8tX+4ZT7CFiVu9cvyAmQXe58WJRvL9CHvywXwMvhFCUJredf9sDJf4lFXwkctI6+Th1C2MNITOKMVCKChsfyRC7cF6WOszt8Kf9N4Hjhc5RS7gaKLWV8bPDhrI0GKztaOTwRJHz7TlugQDiId/B5yy1hCWY4InbdIIUsfBDeUcDlFqHMsydsZrOLoZfQ/+O4w/itPaIRg==",
        "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=wzeKAO+rXcuLDHgcb16pHML/zJ2nWk54OrooHG4hgVA=;\n b=gszBdSVTpMaxoxdwTiSq6obN3yvUfnJgL0y5yfBQa2TLLjxpGyFZjnOzStycrK6u1WQY33atEqA1WCtGJKA19PJDXWRuZmfokJh+wMZq/KgDPMUGUNH8SJlgMoh5aXKNfEGzEwvtehNyuZHx88ohFHdAvscnL6MPYiSr2ijYanykyOuL4bk6gFoPj8f5kSePtKDeq12PayE64jmd6B7k37DxwOt3erxq/y2JUAWCIdRvgvQpa7892e/Z65F1A4KTD3w4eTjaVAV4jRy6WjtBXA+6MHDdm7uFFrjhD3JMOUZ6eCfE1WUlV46CayNd65gA/K0u2TDqIdUNZW1rn/zMsA==",
        "From": "Tushar Dave <tdave@nvidia.com>",
        "To": "qemu-devel@nongnu.org",
        "Cc": "alwilliamson@nvidia.com, jgg@nvidia.com, skolothumtho@nvidia.com,\n qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com,\n marcel.apfelbaum@gmail.com, devel@edk2.groups.io",
        "Subject": "[RFC PATCH 1/8] hw/pci: add fixed-bars property to allow fixed BAR\n addresses",
        "Date": "Fri,  8 May 2026 13:37:10 -0500",
        "Message-Id": "<20260508183717.193630-2-tdave@nvidia.com>",
        "X-Mailer": "git-send-email 2.34.1",
        "In-Reply-To": "<20260508183717.193630-1-tdave@nvidia.com>",
        "References": "<20260508183717.193630-1-tdave@nvidia.com>",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-ClientProxiedBy": "MN0PR04CA0029.namprd04.prod.outlook.com\n (2603:10b6:208:52d::34) To BY5PR12MB4179.namprd12.prod.outlook.com\n (2603:10b6:a03:211::8)",
        "MIME-Version": "1.0",
        "X-MS-PublicTrafficType": "Email",
        "X-MS-TrafficTypeDiagnostic": "BY5PR12MB4179:EE_|CH3PR12MB8482:EE_",
        "X-MS-Office365-Filtering-Correlation-Id": "367e1f7f-9c98-4194-e3b4-08dead30e349",
        "X-MS-Exchange-SenderADCheck": "1",
        "X-MS-Exchange-AntiSpam-Relay": "0",
        "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|366016|376014|1800799024|18002099003|56012099003|22082099003;",
        "X-Microsoft-Antispam-Message-Info": "\n 0pb1G/CMYMLLce3OgjPr7PH4yHgqHV2y3ELixEVaSgl1O22hP0GXcz/ESaWd8bEMxRg5P2vjABtOKcMYabBgatwmiUij+IRPLB8G/8/L578h/S5CcNdXjCPFug1NlF1OuE3DKp6n3m0Rm3X5ijiX/CDxaUsDhUyv01ek7YoDzJjdOoeOmGdW8lZItkucuiIUdikGnBoqad5qDQs5m8UwJ/+BckEGviJ0IDZSl0PAfgHw+8YY+iSAqn6pT3iV6tLjGHOjg4w/JwTKxOSLDYXN1NxVZTe76WX3VWgOfXA1NNgTtpFZxqolrdZqFQDaiK4yQhK/KdT1f2mrn0qFShG3gZ4MsQ3Xfvzo/RcRpj4Jy3vCSZRpsd4qvp23GZZSTg9VCetjC6upCvpsROq6VJ1sPOR6yfJJ4hgIdS/sEnX69kSeeITU0eVh04HxSsWuRz8gLIG+bF1vOKTgP8cy0HFMtP8dK3ptezFpklw3R69X8khdPKuQR3ybmrSxjSOJ/Y66+qB8VW4g1FHz3eJJ31tlt5zTHJdH5j1np0vSFQKS607p76RH2ZmsWk6W4YQXUVVOAB9vNyqTmgUjufUxNkhn8XyGHnXGtLlvnCrgAJe6mmP/tIbPSMaj97w1FqLhTInMckyCypmdNtce30fYTFP2C4U6SI9H6+q8JuWFzSTLgo2dTK3xMYx/rBkjwbL6vzg9",
        "X-Forefront-Antispam-Report": "CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:BY5PR12MB4179.namprd12.prod.outlook.com; PTR:; CAT:NONE;\n SFS:(13230040)(366016)(376014)(1800799024)(18002099003)(56012099003)(22082099003);\n DIR:OUT; SFP:1101;",
        "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1",
        "X-MS-Exchange-AntiSpam-MessageData-0": "\n Ry/S1oklQYrbDDv5qYtbAmtRiRwsF6EF+zzV4UVIr9/+N56+bWSM9hphlYp0bHj8MkEEdXbQG117itWj42LRxBBA9k0zzL95ZmfeIaL/8Y33qbK3tcHieCBM1ja4H74ftJBp52QETZ18RafcS2NzcB+EslQvOAv62Xxlt+DsmTlfNBsw0HVjSn4jhEsfdODQ0IcQvd/Or6CtkSmk5+if7g8kE+a3lt6vRnGjCHEiq/MeKTWjHfkfSgy349HwqQmyRn+ST8WSKpey/3GXD5c38kOiOmmQ/Pahze/gEqJGbEHBNmIC22M4NgZmRaUwj5fS+ahHtDst9TJqzPdBUVakAsmwYh1FaZWZUS9eEpBxs+4egGspg0BsO7a7ykp47wV03O9lDsRtYr40+wqV0rAsNuEYPMFA10L+IOpjh662b/OC/ipXYEj0DEuIydHd9JbFVrckDYOnT1C842vioXcx0PVcBgECvvG1F+Q0Z7bJQ19Q5bPHdNOQKiyTGh2ixaa16WjYcsuZ4FGznRgxQZkn3AGNTVrV4nHVO02/q0M10+VYaaoj8chjhkOQLjqsCqjESrpeic0TG7UA8pGr5nJYRkHhO38vb9hVv7scmWM7RgSIir26ReQhNOyDElu0IlZI7m8kNDsI25E2lAYqaeL7bWIjjiLj1bJeptZBwH8c6guzXrKYyh2WR7LeSJuGODwGyFr0KQmFdoP4yAl9pM28ifTnKVeA5zmuAvrx2X6hkJnD93t7YNhjOO3gVDoEI1wpuAx6l7n7G0fgU3Am8cOcWj3eJIG0Ro3X0bk68E0YQiTsjzQKpVINO7ES92ADueo9KTQjDeuqYRNLxBMNxcXckGbqllObz4U8dcDCXuUFpbQOFnEyc4jjwG80GleVykHDqMjCeRGqSpE0PWWh/QDzbsfBupp1tLC50JXLxGHoGqn6LehXixwuoNnpIMM10x6jQmogR2UUkzHmGvx7PJa82i114AYz0vy6XqNmLOox9tdyvaIRQRbEXX/4BesKDOQqeyeHkWW7Bu1UckjHwPR1FMxBrF8F3iiNrr5NUTUepuCoS+O/2yHy2rENCs64MvxiGjOS0JWP/OkAyx8kATRi2wQnt5E1s7jPgeW4V6twgvXkylWO45etjfiSspINMvyxMgCw/OyRzGaWLrEe9kunFvpXdhjIJlNTLeYCS6iM1PIpMyghF4OkUvlg3K8e7Pp8nZHExnz3b8aEZFaa2xS7ifzaDfo9jvhAMNFznpDW5O8KbvP/wzbJNXYds92pyOpMgvhu6bTsScYpq4dPNRPs1BJ2aVrfQWeksGxS7e6qOJPoxNtuezXV/l8qcOM4Q402MxsIy64rtMm3QNO/qyglfV8s5ZCvNqgEsztsXig+u2+9PXZ90mnPBVBUuYwKEnJxB8Vwj9drX7QPKVNOsrnJjCbgYY9nbnox2u3JnkJzAFLGq6ZcJBFwA0nxXtkWTMpL2XtJCNkviYpDw5ScU79BCEc5oXjvUU4bWEbDJXLr6ZAqFmk7jqgffbOrKk/jEHn962hc/Hxhqm/Dpqs6EpAar/l5C23Sj8rLCF7DuBMYFmBSOpIekohNIrKUf8VnBQa9ZYySoQ7m40f0MMWAuN6r+T4ka7WnTKocueIhlgX+PnRJXFhu6tw9C4KOhl9atkobJ/nxzBv1A+0iybcQnwj6/G5KwNozGm1aUFn/2B+r0ld3C2qT7Jcg7hF1sZiwrfm7iJIDeB1gE3MMbyNhFppPQQ==",
        "X-OriginatorOrg": "Nvidia.com",
        "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 367e1f7f-9c98-4194-e3b4-08dead30e349",
        "X-MS-Exchange-CrossTenant-AuthSource": "BY5PR12MB4179.namprd12.prod.outlook.com",
        "X-MS-Exchange-CrossTenant-AuthAs": "Internal",
        "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 May 2026 18:37:41.7928 (UTC)",
        "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted",
        "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a",
        "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED",
        "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n mdjBOkoyMNRU2udJg+30J4MYTBrDMQ+ORe98hlReOP7hXjEt4lJRB58m0U3kyfHGzxGxy9qeMzI3oNsDjwVbgw==",
        "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR12MB8482",
        "Received-SPF": "permerror client-ip=2a01:111:f403:c111::5;\n envelope-from=tdave@nvidia.com;\n helo=DM1PR04CU001.outbound.protection.outlook.com",
        "X-Spam_score_int": "-14",
        "X-Spam_score": "-1.5",
        "X-Spam_bar": "-",
        "X-Spam_report": "(-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.44,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no",
        "X-Spam_action": "no action",
        "X-BeenThere": "qemu-devel@nongnu.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "qemu development <qemu-devel.nongnu.org>",
        "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>",
        "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>",
        "List-Post": "<mailto:qemu-devel@nongnu.org>",
        "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>",
        "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>",
        "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org",
        "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"
    },
    "content": "Introduce a per-device fixed-bars property that allows users to provide\nfixed PCI BAR addresses for PCI endpoint devices.\n\nThe fixed-bars property cannot be supported on hot-plugged PCI devices.\nPCI BARs for the hot-plugged device are programmed by the guest at the\ntime the device appears.\n\nProperty format:\n- Comma-separated list of BAR entries, each as:\n  barN@<addr>[,barM@<addr>]*\n\n- Example:\n  -device vfio-pci,...,fixed-bars=bar2@0x6b8000000000\n\n- Multiple BARs:\n  -device vfio-pci,host=...,id=dev0\n  -set dev0.fixed-bars=bar0@0x400000000000,bar4@0x410000000000\n\nSigned-off-by: Tushar Dave <tdave@nvidia.com>\n---\n hw/pci/pci.c                | 108 ++++++++++++++++++++++++++++++++++++\n include/hw/pci/pci_device.h |  10 ++++\n 2 files changed, 118 insertions(+)",
    "diff": "diff --git a/hw/pci/pci.c b/hw/pci/pci.c\nindex 2c3657d00d..054fc2c0fa 100644\n--- a/hw/pci/pci.c\n+++ b/hw/pci/pci.c\n@@ -50,6 +50,7 @@\n #include \"hw/core/boards.h\"\n #include \"hw/nvram/fw_cfg.h\"\n #include \"qapi/error.h\"\n+#include \"qapi/util.h\"\n #include \"qemu/cutils.h\"\n #include \"pci-internal.h\"\n \n@@ -81,6 +82,7 @@ static const Property pci_props[] = {\n     DEFINE_PROP_STRING(\"romfile\", PCIDevice, romfile),\n     DEFINE_PROP_UINT32(\"romsize\", PCIDevice, romsize, UINT32_MAX),\n     DEFINE_PROP_INT32(\"rombar\",  PCIDevice, rom_bar, -1),\n+    DEFINE_PROP_STRING(\"fixed-bars\", PCIDevice, fixed_bars),\n     DEFINE_PROP_BIT(\"multifunction\", PCIDevice, cap_present,\n                     QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),\n     DEFINE_PROP_BIT(\"x-pcie-lnksta-dllla\", PCIDevice, cap_present,\n@@ -218,6 +220,103 @@ static void pci_bus_unrealize(BusState *qbus)\n     vmstate_unregister(NULL, &vmstate_pcibus, bus);\n }\n \n+#define FIXED_BARS_ERR \"fixed-bars: expected barN@<addr>[,barM@<addr>]*; \"\n+\n+static int pci_parse_bar_token(const char *tok, Error **errp)\n+{\n+    int v = qapi_enum_parse(&OffAutoPCIBAR_lookup, tok, -1, errp);\n+\n+    if (v < 0) {\n+        return -1;\n+    }\n+    if (v < OFF_AUTO_PCIBAR_BAR0) {\n+        error_setg(errp, FIXED_BARS_ERR \"invalid BAR '%s', expected bar0..bar5\", tok);\n+        return -1;\n+    }\n+    return v - OFF_AUTO_PCIBAR_BAR0;\n+}\n+\n+/*\n+ * Parse fixed-bars=barN@<addr>[,barM@<addr>]*\n+ * BAR type, size, and alignment validation is deferred to the allocator,\n+ * which has the full device context needed to perform those checks.\n+ * On error, sets *@errp.\n+ */\n+static void pci_parse_fixed_bars(PCIDevice *pci_dev, Error **errp)\n+{\n+    Error *local_err = NULL;\n+    char **entries = NULL;\n+    char **parts = NULL;\n+    const char *endp;\n+    char **e;\n+    uint64_t bar_addr;\n+    int index;\n+    int i, ret;\n+\n+    if (!pci_dev->fixed_bars || !*pci_dev->fixed_bars) {\n+        return;\n+    }\n+    if (DEVICE(pci_dev)->hotplugged) {\n+        error_setg(&local_err,\n+                   \"fixed-bars is not supported on hot-plugged PCI devices\");\n+        goto out;\n+    }\n+\n+    entries = g_strsplit(pci_dev->fixed_bars, \",\", -1);\n+    for (e = entries; e && *e; e++) {\n+        const char *entry = g_strstrip(*e);\n+        if (*entry == '\\0') {\n+            error_setg(&local_err, FIXED_BARS_ERR \"empty field in list\");\n+            goto out;\n+        }\n+\n+        parts = g_strsplit(entry, \"@\", 2);\n+        if (!parts[0] || !parts[1]) {\n+            error_setg(&local_err, FIXED_BARS_ERR \"not '%s'\", entry);\n+            goto out;\n+        }\n+\n+        index = pci_parse_bar_token(parts[0], &local_err);\n+        if (index < 0) {\n+            goto out;\n+        }\n+\n+        ret = qemu_strtou64(parts[1], &endp, 0, &bar_addr);\n+        if (ret) {\n+            error_setg(&local_err, FIXED_BARS_ERR \"unparseable address in '%s'\",\n+                       entry);\n+            goto out;\n+        }\n+        if (*endp != '\\0') {\n+            error_setg(&local_err, FIXED_BARS_ERR \"trailing data after address in '%s'\",\n+                       entry);\n+            goto out;\n+        }\n+        g_clear_pointer(&parts, g_strfreev);\n+\n+        if (!pci_dev->fixed_bar_addrs) {\n+            pci_dev->fixed_bar_addrs = g_new(pcibus_t, PCI_NUM_REGIONS - 1);\n+            for (i = 0; i < PCI_NUM_REGIONS - 1; i++) {\n+                pci_dev->fixed_bar_addrs[i] = PCI_BAR_UNMAPPED;\n+            }\n+        }\n+        if (pci_dev->fixed_bar_addrs[index] != PCI_BAR_UNMAPPED) {\n+            error_setg(&local_err, FIXED_BARS_ERR \"bar%d specified more than once\",\n+                       index);\n+            goto out;\n+        }\n+        pci_dev->fixed_bar_addrs[index] = (pcibus_t)bar_addr;\n+    }\n+\n+out:\n+    g_clear_pointer(&parts, g_strfreev);\n+    g_strfreev(entries);\n+    if (local_err) {\n+        g_clear_pointer(&pci_dev->fixed_bar_addrs, g_free);\n+        error_propagate(errp, local_err);\n+    }\n+}\n+\n static int pcibus_num(PCIBus *bus)\n {\n     if (pci_bus_is_root(bus)) {\n@@ -1473,6 +1572,8 @@ static void pci_qdev_unrealize(DeviceState *dev)\n     pci_del_option_rom(pci_dev);\n     pcie_sriov_unregister_device(pci_dev);\n \n+    g_clear_pointer(&pci_dev->fixed_bar_addrs, g_free);\n+\n     if (pc->exit) {\n         pc->exit(pci_dev);\n     }\n@@ -2369,6 +2470,13 @@ static void pci_qdev_realize(DeviceState *qdev, Error **errp)\n         is_default_rom = true;\n     }\n \n+    pci_parse_fixed_bars(pci_dev, &local_err);\n+    if (local_err) {\n+        error_propagate(errp, local_err);\n+        pci_qdev_unrealize(DEVICE(pci_dev));\n+        return;\n+    }\n+\n     pci_add_option_rom(pci_dev, is_default_rom, &local_err);\n     if (local_err) {\n         error_propagate(errp, local_err);\ndiff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h\nindex 5cac6e1688..3e46876985 100644\n--- a/include/hw/pci/pci_device.h\n+++ b/include/hw/pci/pci_device.h\n@@ -179,6 +179,16 @@ struct PCIDevice {\n     char *failover_pair_id;\n     uint32_t acpi_index;\n \n+    /*\n+     * When fixed-bars property is in use, fixed_bar_addrs is non-NULL\n+     * and has PCI_NUM_REGIONS - 1 elements (bar0..bar5); each slot is\n+     * either PCI_BAR_UNMAPPED (no fixed address for that BAR) or the\n+     * fixed address for that BAR.  NULL if the property is unused/empty\n+     * or the map is not yet allocated.\n+     */\n+    char *fixed_bars;\n+    pcibus_t *fixed_bar_addrs;\n+\n     /*\n      * Indirect DMA region bounce buffer size as configured for the device. This\n      * is a configuration parameter that is reflected into bus_master_as when\n",
    "prefixes": [
        "RFC",
        "1/8"
    ]
}